1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "qemu-common.h" 32 #include "cpu.h" 33 #include "hw/boards.h" 34 #include "hw/irq.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/sysbus.h" 37 #include "migration/vmstate.h" 38 #include "strongarm.h" 39 #include "qemu/error-report.h" 40 #include "hw/arm/boot.h" 41 #include "chardev/char-fe.h" 42 #include "chardev/char-serial.h" 43 #include "sysemu/sysemu.h" 44 #include "hw/ssi/ssi.h" 45 #include "qapi/error.h" 46 #include "qemu/cutils.h" 47 #include "qemu/log.h" 48 #include "qom/object.h" 49 50 //#define DEBUG 51 52 /* 53 TODO 54 - Implement cp15, c14 ? 55 - Implement cp15, c15 !!! (idle used in L) 56 - Implement idle mode handling/DIM 57 - Implement sleep mode/Wake sources 58 - Implement reset control 59 - Implement memory control regs 60 - PCMCIA handling 61 - Maybe support MBGNT/MBREQ 62 - DMA channels 63 - GPCLK 64 - IrDA 65 - MCP 66 - Enhance UART with modem signals 67 */ 68 69 #ifdef DEBUG 70 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 71 #else 72 # define DPRINTF(format, ...) do { } while (0) 73 #endif 74 75 static struct { 76 hwaddr io_base; 77 int irq; 78 } sa_serial[] = { 79 { 0x80010000, SA_PIC_UART1 }, 80 { 0x80030000, SA_PIC_UART2 }, 81 { 0x80050000, SA_PIC_UART3 }, 82 { 0, 0 } 83 }; 84 85 /* Interrupt Controller */ 86 87 #define TYPE_STRONGARM_PIC "strongarm_pic" 88 typedef struct StrongARMPICState StrongARMPICState; 89 DECLARE_INSTANCE_CHECKER(StrongARMPICState, STRONGARM_PIC, 90 TYPE_STRONGARM_PIC) 91 92 struct StrongARMPICState { 93 SysBusDevice parent_obj; 94 95 MemoryRegion iomem; 96 qemu_irq irq; 97 qemu_irq fiq; 98 99 uint32_t pending; 100 uint32_t enabled; 101 uint32_t is_fiq; 102 uint32_t int_idle; 103 }; 104 105 #define ICIP 0x00 106 #define ICMR 0x04 107 #define ICLR 0x08 108 #define ICFP 0x10 109 #define ICPR 0x20 110 #define ICCR 0x0c 111 112 #define SA_PIC_SRCS 32 113 114 115 static void strongarm_pic_update(void *opaque) 116 { 117 StrongARMPICState *s = opaque; 118 119 /* FIXME: reflect DIM */ 120 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 121 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 122 } 123 124 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 125 { 126 StrongARMPICState *s = opaque; 127 128 if (level) { 129 s->pending |= 1 << irq; 130 } else { 131 s->pending &= ~(1 << irq); 132 } 133 134 strongarm_pic_update(s); 135 } 136 137 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 138 unsigned size) 139 { 140 StrongARMPICState *s = opaque; 141 142 switch (offset) { 143 case ICIP: 144 return s->pending & ~s->is_fiq & s->enabled; 145 case ICMR: 146 return s->enabled; 147 case ICLR: 148 return s->is_fiq; 149 case ICCR: 150 return s->int_idle == 0; 151 case ICFP: 152 return s->pending & s->is_fiq & s->enabled; 153 case ICPR: 154 return s->pending; 155 default: 156 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 157 __func__, offset); 158 return 0; 159 } 160 } 161 162 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 163 uint64_t value, unsigned size) 164 { 165 StrongARMPICState *s = opaque; 166 167 switch (offset) { 168 case ICMR: 169 s->enabled = value; 170 break; 171 case ICLR: 172 s->is_fiq = value; 173 break; 174 case ICCR: 175 s->int_idle = (value & 1) ? 0 : ~0; 176 break; 177 default: 178 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 179 __func__, offset); 180 break; 181 } 182 strongarm_pic_update(s); 183 } 184 185 static const MemoryRegionOps strongarm_pic_ops = { 186 .read = strongarm_pic_mem_read, 187 .write = strongarm_pic_mem_write, 188 .endianness = DEVICE_NATIVE_ENDIAN, 189 }; 190 191 static void strongarm_pic_initfn(Object *obj) 192 { 193 DeviceState *dev = DEVICE(obj); 194 StrongARMPICState *s = STRONGARM_PIC(obj); 195 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 196 197 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 198 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, 199 "pic", 0x1000); 200 sysbus_init_mmio(sbd, &s->iomem); 201 sysbus_init_irq(sbd, &s->irq); 202 sysbus_init_irq(sbd, &s->fiq); 203 } 204 205 static int strongarm_pic_post_load(void *opaque, int version_id) 206 { 207 strongarm_pic_update(opaque); 208 return 0; 209 } 210 211 static VMStateDescription vmstate_strongarm_pic_regs = { 212 .name = "strongarm_pic", 213 .version_id = 0, 214 .minimum_version_id = 0, 215 .post_load = strongarm_pic_post_load, 216 .fields = (VMStateField[]) { 217 VMSTATE_UINT32(pending, StrongARMPICState), 218 VMSTATE_UINT32(enabled, StrongARMPICState), 219 VMSTATE_UINT32(is_fiq, StrongARMPICState), 220 VMSTATE_UINT32(int_idle, StrongARMPICState), 221 VMSTATE_END_OF_LIST(), 222 }, 223 }; 224 225 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 226 { 227 DeviceClass *dc = DEVICE_CLASS(klass); 228 229 dc->desc = "StrongARM PIC"; 230 dc->vmsd = &vmstate_strongarm_pic_regs; 231 } 232 233 static const TypeInfo strongarm_pic_info = { 234 .name = TYPE_STRONGARM_PIC, 235 .parent = TYPE_SYS_BUS_DEVICE, 236 .instance_size = sizeof(StrongARMPICState), 237 .instance_init = strongarm_pic_initfn, 238 .class_init = strongarm_pic_class_init, 239 }; 240 241 /* Real-Time Clock */ 242 #define RTAR 0x00 /* RTC Alarm register */ 243 #define RCNR 0x04 /* RTC Counter register */ 244 #define RTTR 0x08 /* RTC Timer Trim register */ 245 #define RTSR 0x10 /* RTC Status register */ 246 247 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 248 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 249 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 250 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 251 252 /* 16 LSB of RTTR are clockdiv for internal trim logic, 253 * trim delete isn't emulated, so 254 * f = 32 768 / (RTTR_trim + 1) */ 255 256 #define TYPE_STRONGARM_RTC "strongarm-rtc" 257 typedef struct StrongARMRTCState StrongARMRTCState; 258 DECLARE_INSTANCE_CHECKER(StrongARMRTCState, STRONGARM_RTC, 259 TYPE_STRONGARM_RTC) 260 261 struct StrongARMRTCState { 262 SysBusDevice parent_obj; 263 264 MemoryRegion iomem; 265 uint32_t rttr; 266 uint32_t rtsr; 267 uint32_t rtar; 268 uint32_t last_rcnr; 269 int64_t last_hz; 270 QEMUTimer *rtc_alarm; 271 QEMUTimer *rtc_hz; 272 qemu_irq rtc_irq; 273 qemu_irq rtc_hz_irq; 274 }; 275 276 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 277 { 278 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 279 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 280 } 281 282 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 283 { 284 int64_t rt = qemu_clock_get_ms(rtc_clock); 285 s->last_rcnr += ((rt - s->last_hz) << 15) / 286 (1000 * ((s->rttr & 0xffff) + 1)); 287 s->last_hz = rt; 288 } 289 290 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 291 { 292 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 293 timer_mod(s->rtc_hz, s->last_hz + 1000); 294 } else { 295 timer_del(s->rtc_hz); 296 } 297 298 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 299 timer_mod(s->rtc_alarm, s->last_hz + 300 (((s->rtar - s->last_rcnr) * 1000 * 301 ((s->rttr & 0xffff) + 1)) >> 15)); 302 } else { 303 timer_del(s->rtc_alarm); 304 } 305 } 306 307 static inline void strongarm_rtc_alarm_tick(void *opaque) 308 { 309 StrongARMRTCState *s = opaque; 310 s->rtsr |= RTSR_AL; 311 strongarm_rtc_timer_update(s); 312 strongarm_rtc_int_update(s); 313 } 314 315 static inline void strongarm_rtc_hz_tick(void *opaque) 316 { 317 StrongARMRTCState *s = opaque; 318 s->rtsr |= RTSR_HZ; 319 strongarm_rtc_timer_update(s); 320 strongarm_rtc_int_update(s); 321 } 322 323 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 324 unsigned size) 325 { 326 StrongARMRTCState *s = opaque; 327 328 switch (addr) { 329 case RTTR: 330 return s->rttr; 331 case RTSR: 332 return s->rtsr; 333 case RTAR: 334 return s->rtar; 335 case RCNR: 336 return s->last_rcnr + 337 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 338 (1000 * ((s->rttr & 0xffff) + 1)); 339 default: 340 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 341 return 0; 342 } 343 } 344 345 static void strongarm_rtc_write(void *opaque, hwaddr addr, 346 uint64_t value, unsigned size) 347 { 348 StrongARMRTCState *s = opaque; 349 uint32_t old_rtsr; 350 351 switch (addr) { 352 case RTTR: 353 strongarm_rtc_hzupdate(s); 354 s->rttr = value; 355 strongarm_rtc_timer_update(s); 356 break; 357 358 case RTSR: 359 old_rtsr = s->rtsr; 360 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 361 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 362 363 if (s->rtsr != old_rtsr) { 364 strongarm_rtc_timer_update(s); 365 } 366 367 strongarm_rtc_int_update(s); 368 break; 369 370 case RTAR: 371 s->rtar = value; 372 strongarm_rtc_timer_update(s); 373 break; 374 375 case RCNR: 376 strongarm_rtc_hzupdate(s); 377 s->last_rcnr = value; 378 strongarm_rtc_timer_update(s); 379 break; 380 381 default: 382 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 383 } 384 } 385 386 static const MemoryRegionOps strongarm_rtc_ops = { 387 .read = strongarm_rtc_read, 388 .write = strongarm_rtc_write, 389 .endianness = DEVICE_NATIVE_ENDIAN, 390 }; 391 392 static void strongarm_rtc_init(Object *obj) 393 { 394 StrongARMRTCState *s = STRONGARM_RTC(obj); 395 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 396 struct tm tm; 397 398 s->rttr = 0x0; 399 s->rtsr = 0; 400 401 qemu_get_timedate(&tm, 0); 402 403 s->last_rcnr = (uint32_t) mktimegm(&tm); 404 s->last_hz = qemu_clock_get_ms(rtc_clock); 405 406 sysbus_init_irq(dev, &s->rtc_irq); 407 sysbus_init_irq(dev, &s->rtc_hz_irq); 408 409 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, 410 "rtc", 0x10000); 411 sysbus_init_mmio(dev, &s->iomem); 412 } 413 414 static void strongarm_rtc_realize(DeviceState *dev, Error **errp) 415 { 416 StrongARMRTCState *s = STRONGARM_RTC(dev); 417 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 418 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 419 } 420 421 static int strongarm_rtc_pre_save(void *opaque) 422 { 423 StrongARMRTCState *s = opaque; 424 425 strongarm_rtc_hzupdate(s); 426 427 return 0; 428 } 429 430 static int strongarm_rtc_post_load(void *opaque, int version_id) 431 { 432 StrongARMRTCState *s = opaque; 433 434 strongarm_rtc_timer_update(s); 435 strongarm_rtc_int_update(s); 436 437 return 0; 438 } 439 440 static const VMStateDescription vmstate_strongarm_rtc_regs = { 441 .name = "strongarm-rtc", 442 .version_id = 0, 443 .minimum_version_id = 0, 444 .pre_save = strongarm_rtc_pre_save, 445 .post_load = strongarm_rtc_post_load, 446 .fields = (VMStateField[]) { 447 VMSTATE_UINT32(rttr, StrongARMRTCState), 448 VMSTATE_UINT32(rtsr, StrongARMRTCState), 449 VMSTATE_UINT32(rtar, StrongARMRTCState), 450 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 451 VMSTATE_INT64(last_hz, StrongARMRTCState), 452 VMSTATE_END_OF_LIST(), 453 }, 454 }; 455 456 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 457 { 458 DeviceClass *dc = DEVICE_CLASS(klass); 459 460 dc->desc = "StrongARM RTC Controller"; 461 dc->vmsd = &vmstate_strongarm_rtc_regs; 462 dc->realize = strongarm_rtc_realize; 463 } 464 465 static const TypeInfo strongarm_rtc_sysbus_info = { 466 .name = TYPE_STRONGARM_RTC, 467 .parent = TYPE_SYS_BUS_DEVICE, 468 .instance_size = sizeof(StrongARMRTCState), 469 .instance_init = strongarm_rtc_init, 470 .class_init = strongarm_rtc_sysbus_class_init, 471 }; 472 473 /* GPIO */ 474 #define GPLR 0x00 475 #define GPDR 0x04 476 #define GPSR 0x08 477 #define GPCR 0x0c 478 #define GRER 0x10 479 #define GFER 0x14 480 #define GEDR 0x18 481 #define GAFR 0x1c 482 483 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 484 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 485 DECLARE_INSTANCE_CHECKER(StrongARMGPIOInfo, STRONGARM_GPIO, 486 TYPE_STRONGARM_GPIO) 487 488 struct StrongARMGPIOInfo { 489 SysBusDevice busdev; 490 MemoryRegion iomem; 491 qemu_irq handler[28]; 492 qemu_irq irqs[11]; 493 qemu_irq irqX; 494 495 uint32_t ilevel; 496 uint32_t olevel; 497 uint32_t dir; 498 uint32_t rising; 499 uint32_t falling; 500 uint32_t status; 501 uint32_t gafr; 502 503 uint32_t prev_level; 504 }; 505 506 507 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 508 { 509 int i; 510 for (i = 0; i < 11; i++) { 511 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 512 } 513 514 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 515 } 516 517 static void strongarm_gpio_set(void *opaque, int line, int level) 518 { 519 StrongARMGPIOInfo *s = opaque; 520 uint32_t mask; 521 522 mask = 1 << line; 523 524 if (level) { 525 s->status |= s->rising & mask & 526 ~s->ilevel & ~s->dir; 527 s->ilevel |= mask; 528 } else { 529 s->status |= s->falling & mask & 530 s->ilevel & ~s->dir; 531 s->ilevel &= ~mask; 532 } 533 534 if (s->status & mask) { 535 strongarm_gpio_irq_update(s); 536 } 537 } 538 539 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 540 { 541 uint32_t level, diff; 542 int bit; 543 544 level = s->olevel & s->dir; 545 546 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 547 bit = ctz32(diff); 548 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 549 } 550 551 s->prev_level = level; 552 } 553 554 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 555 unsigned size) 556 { 557 StrongARMGPIOInfo *s = opaque; 558 559 switch (offset) { 560 case GPDR: /* GPIO Pin-Direction registers */ 561 return s->dir; 562 563 case GPSR: /* GPIO Pin-Output Set registers */ 564 qemu_log_mask(LOG_GUEST_ERROR, 565 "strongarm GPIO: read from write only register GPSR\n"); 566 return 0; 567 568 case GPCR: /* GPIO Pin-Output Clear registers */ 569 qemu_log_mask(LOG_GUEST_ERROR, 570 "strongarm GPIO: read from write only register GPCR\n"); 571 return 0; 572 573 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 574 return s->rising; 575 576 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 577 return s->falling; 578 579 case GAFR: /* GPIO Alternate Function registers */ 580 return s->gafr; 581 582 case GPLR: /* GPIO Pin-Level registers */ 583 return (s->olevel & s->dir) | 584 (s->ilevel & ~s->dir); 585 586 case GEDR: /* GPIO Edge Detect Status registers */ 587 return s->status; 588 589 default: 590 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 591 } 592 593 return 0; 594 } 595 596 static void strongarm_gpio_write(void *opaque, hwaddr offset, 597 uint64_t value, unsigned size) 598 { 599 StrongARMGPIOInfo *s = opaque; 600 601 switch (offset) { 602 case GPDR: /* GPIO Pin-Direction registers */ 603 s->dir = value & 0x0fffffff; 604 strongarm_gpio_handler_update(s); 605 break; 606 607 case GPSR: /* GPIO Pin-Output Set registers */ 608 s->olevel |= value & 0x0fffffff; 609 strongarm_gpio_handler_update(s); 610 break; 611 612 case GPCR: /* GPIO Pin-Output Clear registers */ 613 s->olevel &= ~value; 614 strongarm_gpio_handler_update(s); 615 break; 616 617 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 618 s->rising = value; 619 break; 620 621 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 622 s->falling = value; 623 break; 624 625 case GAFR: /* GPIO Alternate Function registers */ 626 s->gafr = value; 627 break; 628 629 case GEDR: /* GPIO Edge Detect Status registers */ 630 s->status &= ~value; 631 strongarm_gpio_irq_update(s); 632 break; 633 634 default: 635 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 636 } 637 } 638 639 static const MemoryRegionOps strongarm_gpio_ops = { 640 .read = strongarm_gpio_read, 641 .write = strongarm_gpio_write, 642 .endianness = DEVICE_NATIVE_ENDIAN, 643 }; 644 645 static DeviceState *strongarm_gpio_init(hwaddr base, 646 DeviceState *pic) 647 { 648 DeviceState *dev; 649 int i; 650 651 dev = qdev_new(TYPE_STRONGARM_GPIO); 652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 653 654 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 655 for (i = 0; i < 12; i++) 656 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 657 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 658 659 return dev; 660 } 661 662 static void strongarm_gpio_initfn(Object *obj) 663 { 664 DeviceState *dev = DEVICE(obj); 665 StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); 666 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 667 int i; 668 669 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 670 qdev_init_gpio_out(dev, s->handler, 28); 671 672 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, 673 "gpio", 0x1000); 674 675 sysbus_init_mmio(sbd, &s->iomem); 676 for (i = 0; i < 11; i++) { 677 sysbus_init_irq(sbd, &s->irqs[i]); 678 } 679 sysbus_init_irq(sbd, &s->irqX); 680 } 681 682 static const VMStateDescription vmstate_strongarm_gpio_regs = { 683 .name = "strongarm-gpio", 684 .version_id = 0, 685 .minimum_version_id = 0, 686 .fields = (VMStateField[]) { 687 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 688 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 689 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 690 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 691 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 692 VMSTATE_UINT32(status, StrongARMGPIOInfo), 693 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 694 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), 695 VMSTATE_END_OF_LIST(), 696 }, 697 }; 698 699 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 700 { 701 DeviceClass *dc = DEVICE_CLASS(klass); 702 703 dc->desc = "StrongARM GPIO controller"; 704 dc->vmsd = &vmstate_strongarm_gpio_regs; 705 } 706 707 static const TypeInfo strongarm_gpio_info = { 708 .name = TYPE_STRONGARM_GPIO, 709 .parent = TYPE_SYS_BUS_DEVICE, 710 .instance_size = sizeof(StrongARMGPIOInfo), 711 .instance_init = strongarm_gpio_initfn, 712 .class_init = strongarm_gpio_class_init, 713 }; 714 715 /* Peripheral Pin Controller */ 716 #define PPDR 0x00 717 #define PPSR 0x04 718 #define PPAR 0x08 719 #define PSDR 0x0c 720 #define PPFR 0x10 721 722 #define TYPE_STRONGARM_PPC "strongarm-ppc" 723 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 724 DECLARE_INSTANCE_CHECKER(StrongARMPPCInfo, STRONGARM_PPC, 725 TYPE_STRONGARM_PPC) 726 727 struct StrongARMPPCInfo { 728 SysBusDevice parent_obj; 729 730 MemoryRegion iomem; 731 qemu_irq handler[28]; 732 733 uint32_t ilevel; 734 uint32_t olevel; 735 uint32_t dir; 736 uint32_t ppar; 737 uint32_t psdr; 738 uint32_t ppfr; 739 740 uint32_t prev_level; 741 }; 742 743 static void strongarm_ppc_set(void *opaque, int line, int level) 744 { 745 StrongARMPPCInfo *s = opaque; 746 747 if (level) { 748 s->ilevel |= 1 << line; 749 } else { 750 s->ilevel &= ~(1 << line); 751 } 752 } 753 754 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 755 { 756 uint32_t level, diff; 757 int bit; 758 759 level = s->olevel & s->dir; 760 761 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 762 bit = ctz32(diff); 763 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 764 } 765 766 s->prev_level = level; 767 } 768 769 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 770 unsigned size) 771 { 772 StrongARMPPCInfo *s = opaque; 773 774 switch (offset) { 775 case PPDR: /* PPC Pin Direction registers */ 776 return s->dir | ~0x3fffff; 777 778 case PPSR: /* PPC Pin State registers */ 779 return (s->olevel & s->dir) | 780 (s->ilevel & ~s->dir) | 781 ~0x3fffff; 782 783 case PPAR: 784 return s->ppar | ~0x41000; 785 786 case PSDR: 787 return s->psdr; 788 789 case PPFR: 790 return s->ppfr | ~0x7f001; 791 792 default: 793 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 794 } 795 796 return 0; 797 } 798 799 static void strongarm_ppc_write(void *opaque, hwaddr offset, 800 uint64_t value, unsigned size) 801 { 802 StrongARMPPCInfo *s = opaque; 803 804 switch (offset) { 805 case PPDR: /* PPC Pin Direction registers */ 806 s->dir = value & 0x3fffff; 807 strongarm_ppc_handler_update(s); 808 break; 809 810 case PPSR: /* PPC Pin State registers */ 811 s->olevel = value & s->dir & 0x3fffff; 812 strongarm_ppc_handler_update(s); 813 break; 814 815 case PPAR: 816 s->ppar = value & 0x41000; 817 break; 818 819 case PSDR: 820 s->psdr = value & 0x3fffff; 821 break; 822 823 case PPFR: 824 s->ppfr = value & 0x7f001; 825 break; 826 827 default: 828 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 829 } 830 } 831 832 static const MemoryRegionOps strongarm_ppc_ops = { 833 .read = strongarm_ppc_read, 834 .write = strongarm_ppc_write, 835 .endianness = DEVICE_NATIVE_ENDIAN, 836 }; 837 838 static void strongarm_ppc_init(Object *obj) 839 { 840 DeviceState *dev = DEVICE(obj); 841 StrongARMPPCInfo *s = STRONGARM_PPC(obj); 842 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 843 844 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 845 qdev_init_gpio_out(dev, s->handler, 22); 846 847 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, 848 "ppc", 0x1000); 849 850 sysbus_init_mmio(sbd, &s->iomem); 851 } 852 853 static const VMStateDescription vmstate_strongarm_ppc_regs = { 854 .name = "strongarm-ppc", 855 .version_id = 0, 856 .minimum_version_id = 0, 857 .fields = (VMStateField[]) { 858 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 859 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 860 VMSTATE_UINT32(dir, StrongARMPPCInfo), 861 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 862 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 863 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 864 VMSTATE_UINT32(prev_level, StrongARMPPCInfo), 865 VMSTATE_END_OF_LIST(), 866 }, 867 }; 868 869 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 870 { 871 DeviceClass *dc = DEVICE_CLASS(klass); 872 873 dc->desc = "StrongARM PPC controller"; 874 dc->vmsd = &vmstate_strongarm_ppc_regs; 875 } 876 877 static const TypeInfo strongarm_ppc_info = { 878 .name = TYPE_STRONGARM_PPC, 879 .parent = TYPE_SYS_BUS_DEVICE, 880 .instance_size = sizeof(StrongARMPPCInfo), 881 .instance_init = strongarm_ppc_init, 882 .class_init = strongarm_ppc_class_init, 883 }; 884 885 /* UART Ports */ 886 #define UTCR0 0x00 887 #define UTCR1 0x04 888 #define UTCR2 0x08 889 #define UTCR3 0x0c 890 #define UTDR 0x14 891 #define UTSR0 0x1c 892 #define UTSR1 0x20 893 894 #define UTCR0_PE (1 << 0) /* Parity enable */ 895 #define UTCR0_OES (1 << 1) /* Even parity */ 896 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 897 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 898 899 #define UTCR3_RXE (1 << 0) /* Rx enable */ 900 #define UTCR3_TXE (1 << 1) /* Tx enable */ 901 #define UTCR3_BRK (1 << 2) /* Force Break */ 902 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 903 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 904 #define UTCR3_LBM (1 << 5) /* Loopback */ 905 906 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 907 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 908 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 909 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 910 #define UTSR0_REB (1 << 4) /* Receiver end break */ 911 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 912 913 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 914 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 915 #define UTSR1_PRE (1 << 3) /* Parity error */ 916 #define UTSR1_FRE (1 << 4) /* Frame error */ 917 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 918 919 #define RX_FIFO_PRE (1 << 8) 920 #define RX_FIFO_FRE (1 << 9) 921 #define RX_FIFO_ROR (1 << 10) 922 923 #define TYPE_STRONGARM_UART "strongarm-uart" 924 typedef struct StrongARMUARTState StrongARMUARTState; 925 DECLARE_INSTANCE_CHECKER(StrongARMUARTState, STRONGARM_UART, 926 TYPE_STRONGARM_UART) 927 928 struct StrongARMUARTState { 929 SysBusDevice parent_obj; 930 931 MemoryRegion iomem; 932 CharBackend chr; 933 qemu_irq irq; 934 935 uint8_t utcr0; 936 uint16_t brd; 937 uint8_t utcr3; 938 uint8_t utsr0; 939 uint8_t utsr1; 940 941 uint8_t tx_fifo[8]; 942 uint8_t tx_start; 943 uint8_t tx_len; 944 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 945 uint8_t rx_start; 946 uint8_t rx_len; 947 948 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 949 bool wait_break_end; 950 QEMUTimer *rx_timeout_timer; 951 QEMUTimer *tx_timer; 952 }; 953 954 static void strongarm_uart_update_status(StrongARMUARTState *s) 955 { 956 uint16_t utsr1 = 0; 957 958 if (s->tx_len != 8) { 959 utsr1 |= UTSR1_TNF; 960 } 961 962 if (s->rx_len != 0) { 963 uint16_t ent = s->rx_fifo[s->rx_start]; 964 965 utsr1 |= UTSR1_RNE; 966 if (ent & RX_FIFO_PRE) { 967 s->utsr1 |= UTSR1_PRE; 968 } 969 if (ent & RX_FIFO_FRE) { 970 s->utsr1 |= UTSR1_FRE; 971 } 972 if (ent & RX_FIFO_ROR) { 973 s->utsr1 |= UTSR1_ROR; 974 } 975 } 976 977 s->utsr1 = utsr1; 978 } 979 980 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 981 { 982 uint16_t utsr0 = s->utsr0 & 983 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 984 int i; 985 986 if ((s->utcr3 & UTCR3_TXE) && 987 (s->utcr3 & UTCR3_TIE) && 988 s->tx_len <= 4) { 989 utsr0 |= UTSR0_TFS; 990 } 991 992 if ((s->utcr3 & UTCR3_RXE) && 993 (s->utcr3 & UTCR3_RIE) && 994 s->rx_len > 4) { 995 utsr0 |= UTSR0_RFS; 996 } 997 998 for (i = 0; i < s->rx_len && i < 4; i++) 999 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 1000 utsr0 |= UTSR0_EIF; 1001 break; 1002 } 1003 1004 s->utsr0 = utsr0; 1005 qemu_set_irq(s->irq, utsr0); 1006 } 1007 1008 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 1009 { 1010 int speed, parity, data_bits, stop_bits, frame_size; 1011 QEMUSerialSetParams ssp; 1012 1013 /* Start bit. */ 1014 frame_size = 1; 1015 if (s->utcr0 & UTCR0_PE) { 1016 /* Parity bit. */ 1017 frame_size++; 1018 if (s->utcr0 & UTCR0_OES) { 1019 parity = 'E'; 1020 } else { 1021 parity = 'O'; 1022 } 1023 } else { 1024 parity = 'N'; 1025 } 1026 if (s->utcr0 & UTCR0_SBS) { 1027 stop_bits = 2; 1028 } else { 1029 stop_bits = 1; 1030 } 1031 1032 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1033 frame_size += data_bits + stop_bits; 1034 speed = 3686400 / 16 / (s->brd + 1); 1035 ssp.speed = speed; 1036 ssp.parity = parity; 1037 ssp.data_bits = data_bits; 1038 ssp.stop_bits = stop_bits; 1039 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; 1040 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1041 1042 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1043 speed, parity, data_bits, stop_bits); 1044 } 1045 1046 static void strongarm_uart_rx_to(void *opaque) 1047 { 1048 StrongARMUARTState *s = opaque; 1049 1050 if (s->rx_len) { 1051 s->utsr0 |= UTSR0_RID; 1052 strongarm_uart_update_int_status(s); 1053 } 1054 } 1055 1056 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1057 { 1058 if ((s->utcr3 & UTCR3_RXE) == 0) { 1059 /* rx disabled */ 1060 return; 1061 } 1062 1063 if (s->wait_break_end) { 1064 s->utsr0 |= UTSR0_REB; 1065 s->wait_break_end = false; 1066 } 1067 1068 if (s->rx_len < 12) { 1069 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1070 s->rx_len++; 1071 } else 1072 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1073 } 1074 1075 static int strongarm_uart_can_receive(void *opaque) 1076 { 1077 StrongARMUARTState *s = opaque; 1078 1079 if (s->rx_len == 12) { 1080 return 0; 1081 } 1082 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1083 if (s->rx_len < 8) { 1084 return 8 - s->rx_len; 1085 } 1086 return 1; 1087 } 1088 1089 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1090 { 1091 StrongARMUARTState *s = opaque; 1092 int i; 1093 1094 for (i = 0; i < size; i++) { 1095 strongarm_uart_rx_push(s, buf[i]); 1096 } 1097 1098 /* call the timeout receive callback in 3 char transmit time */ 1099 timer_mod(s->rx_timeout_timer, 1100 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1101 1102 strongarm_uart_update_status(s); 1103 strongarm_uart_update_int_status(s); 1104 } 1105 1106 static void strongarm_uart_event(void *opaque, QEMUChrEvent event) 1107 { 1108 StrongARMUARTState *s = opaque; 1109 if (event == CHR_EVENT_BREAK) { 1110 s->utsr0 |= UTSR0_RBB; 1111 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1112 s->wait_break_end = true; 1113 strongarm_uart_update_status(s); 1114 strongarm_uart_update_int_status(s); 1115 } 1116 } 1117 1118 static void strongarm_uart_tx(void *opaque) 1119 { 1120 StrongARMUARTState *s = opaque; 1121 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1122 1123 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1124 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1125 } else if (qemu_chr_fe_backend_connected(&s->chr)) { 1126 /* XXX this blocks entire thread. Rewrite to use 1127 * qemu_chr_fe_write and background I/O callbacks */ 1128 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); 1129 } 1130 1131 s->tx_start = (s->tx_start + 1) % 8; 1132 s->tx_len--; 1133 if (s->tx_len) { 1134 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1135 } 1136 strongarm_uart_update_status(s); 1137 strongarm_uart_update_int_status(s); 1138 } 1139 1140 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1141 unsigned size) 1142 { 1143 StrongARMUARTState *s = opaque; 1144 uint16_t ret; 1145 1146 switch (addr) { 1147 case UTCR0: 1148 return s->utcr0; 1149 1150 case UTCR1: 1151 return s->brd >> 8; 1152 1153 case UTCR2: 1154 return s->brd & 0xff; 1155 1156 case UTCR3: 1157 return s->utcr3; 1158 1159 case UTDR: 1160 if (s->rx_len != 0) { 1161 ret = s->rx_fifo[s->rx_start]; 1162 s->rx_start = (s->rx_start + 1) % 12; 1163 s->rx_len--; 1164 strongarm_uart_update_status(s); 1165 strongarm_uart_update_int_status(s); 1166 return ret; 1167 } 1168 return 0; 1169 1170 case UTSR0: 1171 return s->utsr0; 1172 1173 case UTSR1: 1174 return s->utsr1; 1175 1176 default: 1177 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1178 return 0; 1179 } 1180 } 1181 1182 static void strongarm_uart_write(void *opaque, hwaddr addr, 1183 uint64_t value, unsigned size) 1184 { 1185 StrongARMUARTState *s = opaque; 1186 1187 switch (addr) { 1188 case UTCR0: 1189 s->utcr0 = value & 0x7f; 1190 strongarm_uart_update_parameters(s); 1191 break; 1192 1193 case UTCR1: 1194 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1195 strongarm_uart_update_parameters(s); 1196 break; 1197 1198 case UTCR2: 1199 s->brd = (s->brd & 0xf00) | (value & 0xff); 1200 strongarm_uart_update_parameters(s); 1201 break; 1202 1203 case UTCR3: 1204 s->utcr3 = value & 0x3f; 1205 if ((s->utcr3 & UTCR3_RXE) == 0) { 1206 s->rx_len = 0; 1207 } 1208 if ((s->utcr3 & UTCR3_TXE) == 0) { 1209 s->tx_len = 0; 1210 } 1211 strongarm_uart_update_status(s); 1212 strongarm_uart_update_int_status(s); 1213 break; 1214 1215 case UTDR: 1216 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1217 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1218 s->tx_len++; 1219 strongarm_uart_update_status(s); 1220 strongarm_uart_update_int_status(s); 1221 if (s->tx_len == 1) { 1222 strongarm_uart_tx(s); 1223 } 1224 } 1225 break; 1226 1227 case UTSR0: 1228 s->utsr0 = s->utsr0 & ~(value & 1229 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1230 strongarm_uart_update_int_status(s); 1231 break; 1232 1233 default: 1234 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1235 } 1236 } 1237 1238 static const MemoryRegionOps strongarm_uart_ops = { 1239 .read = strongarm_uart_read, 1240 .write = strongarm_uart_write, 1241 .endianness = DEVICE_NATIVE_ENDIAN, 1242 }; 1243 1244 static void strongarm_uart_init(Object *obj) 1245 { 1246 StrongARMUARTState *s = STRONGARM_UART(obj); 1247 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1248 1249 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, 1250 "uart", 0x10000); 1251 sysbus_init_mmio(dev, &s->iomem); 1252 sysbus_init_irq(dev, &s->irq); 1253 } 1254 1255 static void strongarm_uart_realize(DeviceState *dev, Error **errp) 1256 { 1257 StrongARMUARTState *s = STRONGARM_UART(dev); 1258 1259 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1260 strongarm_uart_rx_to, 1261 s); 1262 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1263 qemu_chr_fe_set_handlers(&s->chr, 1264 strongarm_uart_can_receive, 1265 strongarm_uart_receive, 1266 strongarm_uart_event, 1267 NULL, s, NULL, true); 1268 } 1269 1270 static void strongarm_uart_reset(DeviceState *dev) 1271 { 1272 StrongARMUARTState *s = STRONGARM_UART(dev); 1273 1274 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1275 s->brd = 23; /* 9600 */ 1276 /* enable send & recv - this actually violates spec */ 1277 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1278 1279 s->rx_len = s->tx_len = 0; 1280 1281 strongarm_uart_update_parameters(s); 1282 strongarm_uart_update_status(s); 1283 strongarm_uart_update_int_status(s); 1284 } 1285 1286 static int strongarm_uart_post_load(void *opaque, int version_id) 1287 { 1288 StrongARMUARTState *s = opaque; 1289 1290 strongarm_uart_update_parameters(s); 1291 strongarm_uart_update_status(s); 1292 strongarm_uart_update_int_status(s); 1293 1294 /* tx and restart timer */ 1295 if (s->tx_len) { 1296 strongarm_uart_tx(s); 1297 } 1298 1299 /* restart rx timeout timer */ 1300 if (s->rx_len) { 1301 timer_mod(s->rx_timeout_timer, 1302 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1303 } 1304 1305 return 0; 1306 } 1307 1308 static const VMStateDescription vmstate_strongarm_uart_regs = { 1309 .name = "strongarm-uart", 1310 .version_id = 0, 1311 .minimum_version_id = 0, 1312 .post_load = strongarm_uart_post_load, 1313 .fields = (VMStateField[]) { 1314 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1315 VMSTATE_UINT16(brd, StrongARMUARTState), 1316 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1317 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1318 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1319 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1320 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1321 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1322 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1323 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1324 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1325 VMSTATE_END_OF_LIST(), 1326 }, 1327 }; 1328 1329 static Property strongarm_uart_properties[] = { 1330 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1331 DEFINE_PROP_END_OF_LIST(), 1332 }; 1333 1334 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1335 { 1336 DeviceClass *dc = DEVICE_CLASS(klass); 1337 1338 dc->desc = "StrongARM UART controller"; 1339 dc->reset = strongarm_uart_reset; 1340 dc->vmsd = &vmstate_strongarm_uart_regs; 1341 device_class_set_props(dc, strongarm_uart_properties); 1342 dc->realize = strongarm_uart_realize; 1343 } 1344 1345 static const TypeInfo strongarm_uart_info = { 1346 .name = TYPE_STRONGARM_UART, 1347 .parent = TYPE_SYS_BUS_DEVICE, 1348 .instance_size = sizeof(StrongARMUARTState), 1349 .instance_init = strongarm_uart_init, 1350 .class_init = strongarm_uart_class_init, 1351 }; 1352 1353 /* Synchronous Serial Ports */ 1354 1355 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1356 typedef struct StrongARMSSPState StrongARMSSPState; 1357 DECLARE_INSTANCE_CHECKER(StrongARMSSPState, STRONGARM_SSP, 1358 TYPE_STRONGARM_SSP) 1359 1360 struct StrongARMSSPState { 1361 SysBusDevice parent_obj; 1362 1363 MemoryRegion iomem; 1364 qemu_irq irq; 1365 SSIBus *bus; 1366 1367 uint16_t sscr[2]; 1368 uint16_t sssr; 1369 1370 uint16_t rx_fifo[8]; 1371 uint8_t rx_level; 1372 uint8_t rx_start; 1373 }; 1374 1375 #define SSCR0 0x60 /* SSP Control register 0 */ 1376 #define SSCR1 0x64 /* SSP Control register 1 */ 1377 #define SSDR 0x6c /* SSP Data register */ 1378 #define SSSR 0x74 /* SSP Status register */ 1379 1380 /* Bitfields for above registers */ 1381 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1382 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1383 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1384 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1385 #define SSCR0_SSE (1 << 7) 1386 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1387 #define SSCR1_RIE (1 << 0) 1388 #define SSCR1_TIE (1 << 1) 1389 #define SSCR1_LBM (1 << 2) 1390 #define SSSR_TNF (1 << 2) 1391 #define SSSR_RNE (1 << 3) 1392 #define SSSR_TFS (1 << 5) 1393 #define SSSR_RFS (1 << 6) 1394 #define SSSR_ROR (1 << 7) 1395 #define SSSR_RW 0x0080 1396 1397 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1398 { 1399 int level = 0; 1400 1401 level |= (s->sssr & SSSR_ROR); 1402 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1403 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1404 qemu_set_irq(s->irq, level); 1405 } 1406 1407 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1408 { 1409 s->sssr &= ~SSSR_TFS; 1410 s->sssr &= ~SSSR_TNF; 1411 if (s->sscr[0] & SSCR0_SSE) { 1412 if (s->rx_level >= 4) { 1413 s->sssr |= SSSR_RFS; 1414 } else { 1415 s->sssr &= ~SSSR_RFS; 1416 } 1417 if (s->rx_level) { 1418 s->sssr |= SSSR_RNE; 1419 } else { 1420 s->sssr &= ~SSSR_RNE; 1421 } 1422 /* TX FIFO is never filled, so it is always in underrun 1423 condition if SSP is enabled */ 1424 s->sssr |= SSSR_TFS; 1425 s->sssr |= SSSR_TNF; 1426 } 1427 1428 strongarm_ssp_int_update(s); 1429 } 1430 1431 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1432 unsigned size) 1433 { 1434 StrongARMSSPState *s = opaque; 1435 uint32_t retval; 1436 1437 switch (addr) { 1438 case SSCR0: 1439 return s->sscr[0]; 1440 case SSCR1: 1441 return s->sscr[1]; 1442 case SSSR: 1443 return s->sssr; 1444 case SSDR: 1445 if (~s->sscr[0] & SSCR0_SSE) { 1446 return 0xffffffff; 1447 } 1448 if (s->rx_level < 1) { 1449 printf("%s: SSP Rx Underrun\n", __func__); 1450 return 0xffffffff; 1451 } 1452 s->rx_level--; 1453 retval = s->rx_fifo[s->rx_start++]; 1454 s->rx_start &= 0x7; 1455 strongarm_ssp_fifo_update(s); 1456 return retval; 1457 default: 1458 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1459 break; 1460 } 1461 return 0; 1462 } 1463 1464 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1465 uint64_t value, unsigned size) 1466 { 1467 StrongARMSSPState *s = opaque; 1468 1469 switch (addr) { 1470 case SSCR0: 1471 s->sscr[0] = value & 0xffbf; 1472 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1473 printf("%s: Wrong data size: %i bits\n", __func__, 1474 (int)SSCR0_DSS(value)); 1475 } 1476 if (!(value & SSCR0_SSE)) { 1477 s->sssr = 0; 1478 s->rx_level = 0; 1479 } 1480 strongarm_ssp_fifo_update(s); 1481 break; 1482 1483 case SSCR1: 1484 s->sscr[1] = value & 0x2f; 1485 if (value & SSCR1_LBM) { 1486 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1487 } 1488 strongarm_ssp_fifo_update(s); 1489 break; 1490 1491 case SSSR: 1492 s->sssr &= ~(value & SSSR_RW); 1493 strongarm_ssp_int_update(s); 1494 break; 1495 1496 case SSDR: 1497 if (SSCR0_UWIRE(s->sscr[0])) { 1498 value &= 0xff; 1499 } else 1500 /* Note how 32bits overflow does no harm here */ 1501 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1502 1503 /* Data goes from here to the Tx FIFO and is shifted out from 1504 * there directly to the slave, no need to buffer it. 1505 */ 1506 if (s->sscr[0] & SSCR0_SSE) { 1507 uint32_t readval; 1508 if (s->sscr[1] & SSCR1_LBM) { 1509 readval = value; 1510 } else { 1511 readval = ssi_transfer(s->bus, value); 1512 } 1513 1514 if (s->rx_level < 0x08) { 1515 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1516 } else { 1517 s->sssr |= SSSR_ROR; 1518 } 1519 } 1520 strongarm_ssp_fifo_update(s); 1521 break; 1522 1523 default: 1524 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1525 break; 1526 } 1527 } 1528 1529 static const MemoryRegionOps strongarm_ssp_ops = { 1530 .read = strongarm_ssp_read, 1531 .write = strongarm_ssp_write, 1532 .endianness = DEVICE_NATIVE_ENDIAN, 1533 }; 1534 1535 static int strongarm_ssp_post_load(void *opaque, int version_id) 1536 { 1537 StrongARMSSPState *s = opaque; 1538 1539 strongarm_ssp_fifo_update(s); 1540 1541 return 0; 1542 } 1543 1544 static void strongarm_ssp_init(Object *obj) 1545 { 1546 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1547 DeviceState *dev = DEVICE(sbd); 1548 StrongARMSSPState *s = STRONGARM_SSP(dev); 1549 1550 sysbus_init_irq(sbd, &s->irq); 1551 1552 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, 1553 "ssp", 0x1000); 1554 sysbus_init_mmio(sbd, &s->iomem); 1555 1556 s->bus = ssi_create_bus(dev, "ssi"); 1557 } 1558 1559 static void strongarm_ssp_reset(DeviceState *dev) 1560 { 1561 StrongARMSSPState *s = STRONGARM_SSP(dev); 1562 1563 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1564 s->rx_start = 0; 1565 s->rx_level = 0; 1566 } 1567 1568 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1569 .name = "strongarm-ssp", 1570 .version_id = 0, 1571 .minimum_version_id = 0, 1572 .post_load = strongarm_ssp_post_load, 1573 .fields = (VMStateField[]) { 1574 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1575 VMSTATE_UINT16(sssr, StrongARMSSPState), 1576 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1577 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1578 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1579 VMSTATE_END_OF_LIST(), 1580 }, 1581 }; 1582 1583 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1584 { 1585 DeviceClass *dc = DEVICE_CLASS(klass); 1586 1587 dc->desc = "StrongARM SSP controller"; 1588 dc->reset = strongarm_ssp_reset; 1589 dc->vmsd = &vmstate_strongarm_ssp_regs; 1590 } 1591 1592 static const TypeInfo strongarm_ssp_info = { 1593 .name = TYPE_STRONGARM_SSP, 1594 .parent = TYPE_SYS_BUS_DEVICE, 1595 .instance_size = sizeof(StrongARMSSPState), 1596 .instance_init = strongarm_ssp_init, 1597 .class_init = strongarm_ssp_class_init, 1598 }; 1599 1600 /* Main CPU functions */ 1601 StrongARMState *sa1110_init(const char *cpu_type) 1602 { 1603 StrongARMState *s; 1604 int i; 1605 1606 s = g_new0(StrongARMState, 1); 1607 1608 if (strncmp(cpu_type, "sa1110", 6)) { 1609 error_report("Machine requires a SA1110 processor."); 1610 exit(1); 1611 } 1612 1613 s->cpu = ARM_CPU(cpu_create(cpu_type)); 1614 1615 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1616 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1617 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1618 NULL); 1619 1620 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1621 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1622 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1623 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1624 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1625 NULL); 1626 1627 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1628 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1629 1630 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1631 1632 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1633 1634 for (i = 0; sa_serial[i].io_base; i++) { 1635 DeviceState *dev = qdev_new(TYPE_STRONGARM_UART); 1636 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1637 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1638 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1639 sa_serial[i].io_base); 1640 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1641 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1642 } 1643 1644 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1645 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1646 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1647 1648 return s; 1649 } 1650 1651 static void strongarm_register_types(void) 1652 { 1653 type_register_static(&strongarm_pic_info); 1654 type_register_static(&strongarm_rtc_sysbus_info); 1655 type_register_static(&strongarm_gpio_info); 1656 type_register_static(&strongarm_ppc_info); 1657 type_register_static(&strongarm_uart_info); 1658 type_register_static(&strongarm_ssp_info); 1659 } 1660 1661 type_init(strongarm_register_types) 1662