1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/arm.h" 12 #include "hw/devices.h" 13 #include "net/net.h" 14 #include "sysemu/sysemu.h" 15 #include "hw/pci/pci.h" 16 #include "hw/i2c/i2c.h" 17 #include "hw/boards.h" 18 #include "sysemu/block-backend.h" 19 #include "exec/address-spaces.h" 20 #include "hw/block/flash.h" 21 22 #define VERSATILE_FLASH_ADDR 0x34000000 23 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 24 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 25 26 /* Primary interrupt controller. */ 27 28 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" 29 #define VERSATILE_PB_SIC(obj) \ 30 OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC) 31 32 typedef struct vpb_sic_state { 33 SysBusDevice parent_obj; 34 35 MemoryRegion iomem; 36 uint32_t level; 37 uint32_t mask; 38 uint32_t pic_enable; 39 qemu_irq parent[32]; 40 int irq; 41 } vpb_sic_state; 42 43 static const VMStateDescription vmstate_vpb_sic = { 44 .name = "versatilepb_sic", 45 .version_id = 1, 46 .minimum_version_id = 1, 47 .fields = (VMStateField[]) { 48 VMSTATE_UINT32(level, vpb_sic_state), 49 VMSTATE_UINT32(mask, vpb_sic_state), 50 VMSTATE_UINT32(pic_enable, vpb_sic_state), 51 VMSTATE_END_OF_LIST() 52 } 53 }; 54 55 static void vpb_sic_update(vpb_sic_state *s) 56 { 57 uint32_t flags; 58 59 flags = s->level & s->mask; 60 qemu_set_irq(s->parent[s->irq], flags != 0); 61 } 62 63 static void vpb_sic_update_pic(vpb_sic_state *s) 64 { 65 int i; 66 uint32_t mask; 67 68 for (i = 21; i <= 30; i++) { 69 mask = 1u << i; 70 if (!(s->pic_enable & mask)) 71 continue; 72 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 73 } 74 } 75 76 static void vpb_sic_set_irq(void *opaque, int irq, int level) 77 { 78 vpb_sic_state *s = (vpb_sic_state *)opaque; 79 if (level) 80 s->level |= 1u << irq; 81 else 82 s->level &= ~(1u << irq); 83 if (s->pic_enable & (1u << irq)) 84 qemu_set_irq(s->parent[irq], level); 85 vpb_sic_update(s); 86 } 87 88 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 89 unsigned size) 90 { 91 vpb_sic_state *s = (vpb_sic_state *)opaque; 92 93 switch (offset >> 2) { 94 case 0: /* STATUS */ 95 return s->level & s->mask; 96 case 1: /* RAWSTAT */ 97 return s->level; 98 case 2: /* ENABLE */ 99 return s->mask; 100 case 4: /* SOFTINT */ 101 return s->level & 1; 102 case 8: /* PICENABLE */ 103 return s->pic_enable; 104 default: 105 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 106 return 0; 107 } 108 } 109 110 static void vpb_sic_write(void *opaque, hwaddr offset, 111 uint64_t value, unsigned size) 112 { 113 vpb_sic_state *s = (vpb_sic_state *)opaque; 114 115 switch (offset >> 2) { 116 case 2: /* ENSET */ 117 s->mask |= value; 118 break; 119 case 3: /* ENCLR */ 120 s->mask &= ~value; 121 break; 122 case 4: /* SOFTINTSET */ 123 if (value) 124 s->mask |= 1; 125 break; 126 case 5: /* SOFTINTCLR */ 127 if (value) 128 s->mask &= ~1u; 129 break; 130 case 8: /* PICENSET */ 131 s->pic_enable |= (value & 0x7fe00000); 132 vpb_sic_update_pic(s); 133 break; 134 case 9: /* PICENCLR */ 135 s->pic_enable &= ~value; 136 vpb_sic_update_pic(s); 137 break; 138 default: 139 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 140 return; 141 } 142 vpb_sic_update(s); 143 } 144 145 static const MemoryRegionOps vpb_sic_ops = { 146 .read = vpb_sic_read, 147 .write = vpb_sic_write, 148 .endianness = DEVICE_NATIVE_ENDIAN, 149 }; 150 151 static int vpb_sic_init(SysBusDevice *sbd) 152 { 153 DeviceState *dev = DEVICE(sbd); 154 vpb_sic_state *s = VERSATILE_PB_SIC(dev); 155 int i; 156 157 qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); 158 for (i = 0; i < 32; i++) { 159 sysbus_init_irq(sbd, &s->parent[i]); 160 } 161 s->irq = 31; 162 memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s, 163 "vpb-sic", 0x1000); 164 sysbus_init_mmio(sbd, &s->iomem); 165 return 0; 166 } 167 168 /* Board init. */ 169 170 /* The AB and PB boards both use the same core, just with different 171 peripherals and expansion busses. For now we emulate a subset of the 172 PB peripherals and just change the board ID. */ 173 174 static struct arm_boot_info versatile_binfo; 175 176 static void versatile_init(MachineState *machine, int board_id) 177 { 178 ARMCPU *cpu; 179 MemoryRegion *sysmem = get_system_memory(); 180 MemoryRegion *ram = g_new(MemoryRegion, 1); 181 qemu_irq pic[32]; 182 qemu_irq sic[32]; 183 DeviceState *dev, *sysctl; 184 SysBusDevice *busdev; 185 DeviceState *pl041; 186 PCIBus *pci_bus; 187 NICInfo *nd; 188 I2CBus *i2c; 189 int n; 190 int done_smc = 0; 191 DriveInfo *dinfo; 192 193 if (!machine->cpu_model) { 194 machine->cpu_model = "arm926"; 195 } 196 cpu = cpu_arm_init(machine->cpu_model); 197 if (!cpu) { 198 fprintf(stderr, "Unable to find CPU definition\n"); 199 exit(1); 200 } 201 memory_region_init_ram(ram, NULL, "versatile.ram", machine->ram_size, 202 &error_abort); 203 vmstate_register_ram_global(ram); 204 /* ??? RAM should repeat to fill physical memory space. */ 205 /* SDRAM at address zero. */ 206 memory_region_add_subregion(sysmem, 0, ram); 207 208 sysctl = qdev_create(NULL, "realview_sysctl"); 209 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 210 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 211 qdev_init_nofail(sysctl); 212 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 213 214 dev = sysbus_create_varargs("pl190", 0x10140000, 215 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 216 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 217 NULL); 218 for (n = 0; n < 32; n++) { 219 pic[n] = qdev_get_gpio_in(dev, n); 220 } 221 dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); 222 for (n = 0; n < 32; n++) { 223 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 224 sic[n] = qdev_get_gpio_in(dev, n); 225 } 226 227 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 228 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 229 230 dev = qdev_create(NULL, "versatile_pci"); 231 busdev = SYS_BUS_DEVICE(dev); 232 qdev_init_nofail(dev); 233 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 234 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 235 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ 236 sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ 237 sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ 238 sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ 239 sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ 240 sysbus_connect_irq(busdev, 0, sic[27]); 241 sysbus_connect_irq(busdev, 1, sic[28]); 242 sysbus_connect_irq(busdev, 2, sic[29]); 243 sysbus_connect_irq(busdev, 3, sic[30]); 244 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 245 246 for(n = 0; n < nb_nics; n++) { 247 nd = &nd_table[n]; 248 249 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { 250 smc91c111_init(nd, 0x10010000, sic[25]); 251 done_smc = 1; 252 } else { 253 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 254 } 255 } 256 if (usb_enabled(false)) { 257 pci_create_simple(pci_bus, -1, "pci-ohci"); 258 } 259 n = drive_get_max_bus(IF_SCSI); 260 while (n >= 0) { 261 pci_create_simple(pci_bus, -1, "lsi53c895a"); 262 n--; 263 } 264 265 sysbus_create_simple("pl011", 0x101f1000, pic[12]); 266 sysbus_create_simple("pl011", 0x101f2000, pic[13]); 267 sysbus_create_simple("pl011", 0x101f3000, pic[14]); 268 sysbus_create_simple("pl011", 0x10009000, sic[6]); 269 270 sysbus_create_simple("pl080", 0x10130000, pic[17]); 271 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 272 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 273 274 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 275 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 276 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 277 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 278 279 /* The versatile/PB actually has a modified Color LCD controller 280 that includes hardware cursor support from the PL111. */ 281 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); 282 /* Wire up the mux control signals from the SYS_CLCD register */ 283 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 284 285 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 286 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 287 288 /* Add PL031 Real Time Clock. */ 289 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 290 291 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 292 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 293 i2c_create_slave(i2c, "ds1338", 0x68); 294 295 /* Add PL041 AACI Interface to the LM4549 codec */ 296 pl041 = qdev_create(NULL, "pl041"); 297 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 298 qdev_init_nofail(pl041); 299 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 300 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 301 302 /* Memory map for Versatile/PB: */ 303 /* 0x10000000 System registers. */ 304 /* 0x10001000 PCI controller config registers. */ 305 /* 0x10002000 Serial bus interface. */ 306 /* 0x10003000 Secondary interrupt controller. */ 307 /* 0x10004000 AACI (audio). */ 308 /* 0x10005000 MMCI0. */ 309 /* 0x10006000 KMI0 (keyboard). */ 310 /* 0x10007000 KMI1 (mouse). */ 311 /* 0x10008000 Character LCD Interface. */ 312 /* 0x10009000 UART3. */ 313 /* 0x1000a000 Smart card 1. */ 314 /* 0x1000b000 MMCI1. */ 315 /* 0x10010000 Ethernet. */ 316 /* 0x10020000 USB. */ 317 /* 0x10100000 SSMC. */ 318 /* 0x10110000 MPMC. */ 319 /* 0x10120000 CLCD Controller. */ 320 /* 0x10130000 DMA Controller. */ 321 /* 0x10140000 Vectored interrupt controller. */ 322 /* 0x101d0000 AHB Monitor Interface. */ 323 /* 0x101e0000 System Controller. */ 324 /* 0x101e1000 Watchdog Interface. */ 325 /* 0x101e2000 Timer 0/1. */ 326 /* 0x101e3000 Timer 2/3. */ 327 /* 0x101e4000 GPIO port 0. */ 328 /* 0x101e5000 GPIO port 1. */ 329 /* 0x101e6000 GPIO port 2. */ 330 /* 0x101e7000 GPIO port 3. */ 331 /* 0x101e8000 RTC. */ 332 /* 0x101f0000 Smart card 0. */ 333 /* 0x101f1000 UART0. */ 334 /* 0x101f2000 UART1. */ 335 /* 0x101f3000 UART2. */ 336 /* 0x101f4000 SSPI. */ 337 /* 0x34000000 NOR Flash */ 338 339 dinfo = drive_get(IF_PFLASH, 0, 0); 340 if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash", 341 VERSATILE_FLASH_SIZE, 342 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 343 VERSATILE_FLASH_SECT_SIZE, 344 VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE, 345 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { 346 fprintf(stderr, "qemu: Error registering flash memory.\n"); 347 } 348 349 versatile_binfo.ram_size = machine->ram_size; 350 versatile_binfo.kernel_filename = machine->kernel_filename; 351 versatile_binfo.kernel_cmdline = machine->kernel_cmdline; 352 versatile_binfo.initrd_filename = machine->initrd_filename; 353 versatile_binfo.board_id = board_id; 354 arm_load_kernel(cpu, &versatile_binfo); 355 } 356 357 static void vpb_init(MachineState *machine) 358 { 359 versatile_init(machine, 0x183); 360 } 361 362 static void vab_init(MachineState *machine) 363 { 364 versatile_init(machine, 0x25e); 365 } 366 367 static QEMUMachine versatilepb_machine = { 368 .name = "versatilepb", 369 .desc = "ARM Versatile/PB (ARM926EJ-S)", 370 .init = vpb_init, 371 .block_default_type = IF_SCSI, 372 }; 373 374 static QEMUMachine versatileab_machine = { 375 .name = "versatileab", 376 .desc = "ARM Versatile/AB (ARM926EJ-S)", 377 .init = vab_init, 378 .block_default_type = IF_SCSI, 379 }; 380 381 static void versatile_machine_init(void) 382 { 383 qemu_register_machine(&versatilepb_machine); 384 qemu_register_machine(&versatileab_machine); 385 } 386 387 machine_init(versatile_machine_init); 388 389 static void vpb_sic_class_init(ObjectClass *klass, void *data) 390 { 391 DeviceClass *dc = DEVICE_CLASS(klass); 392 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 393 394 k->init = vpb_sic_init; 395 dc->vmsd = &vmstate_vpb_sic; 396 } 397 398 static const TypeInfo vpb_sic_info = { 399 .name = TYPE_VERSATILE_PB_SIC, 400 .parent = TYPE_SYS_BUS_DEVICE, 401 .instance_size = sizeof(vpb_sic_state), 402 .class_init = vpb_sic_class_init, 403 }; 404 405 static void versatilepb_register_types(void) 406 { 407 type_register_static(&vpb_sic_info); 408 } 409 410 type_init(versatilepb_register_types) 411