1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm-misc.h" 12 #include "hw/devices.h" 13 #include "net/net.h" 14 #include "sysemu/sysemu.h" 15 #include "hw/pci/pci.h" 16 #include "hw/i2c.h" 17 #include "hw/boards.h" 18 #include "sysemu/blockdev.h" 19 #include "exec/address-spaces.h" 20 #include "hw/flash.h" 21 22 #define VERSATILE_FLASH_ADDR 0x34000000 23 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 24 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 25 26 /* Primary interrupt controller. */ 27 28 typedef struct vpb_sic_state 29 { 30 SysBusDevice busdev; 31 MemoryRegion iomem; 32 uint32_t level; 33 uint32_t mask; 34 uint32_t pic_enable; 35 qemu_irq parent[32]; 36 int irq; 37 } vpb_sic_state; 38 39 static const VMStateDescription vmstate_vpb_sic = { 40 .name = "versatilepb_sic", 41 .version_id = 1, 42 .minimum_version_id = 1, 43 .fields = (VMStateField[]) { 44 VMSTATE_UINT32(level, vpb_sic_state), 45 VMSTATE_UINT32(mask, vpb_sic_state), 46 VMSTATE_UINT32(pic_enable, vpb_sic_state), 47 VMSTATE_END_OF_LIST() 48 } 49 }; 50 51 static void vpb_sic_update(vpb_sic_state *s) 52 { 53 uint32_t flags; 54 55 flags = s->level & s->mask; 56 qemu_set_irq(s->parent[s->irq], flags != 0); 57 } 58 59 static void vpb_sic_update_pic(vpb_sic_state *s) 60 { 61 int i; 62 uint32_t mask; 63 64 for (i = 21; i <= 30; i++) { 65 mask = 1u << i; 66 if (!(s->pic_enable & mask)) 67 continue; 68 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 69 } 70 } 71 72 static void vpb_sic_set_irq(void *opaque, int irq, int level) 73 { 74 vpb_sic_state *s = (vpb_sic_state *)opaque; 75 if (level) 76 s->level |= 1u << irq; 77 else 78 s->level &= ~(1u << irq); 79 if (s->pic_enable & (1u << irq)) 80 qemu_set_irq(s->parent[irq], level); 81 vpb_sic_update(s); 82 } 83 84 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 85 unsigned size) 86 { 87 vpb_sic_state *s = (vpb_sic_state *)opaque; 88 89 switch (offset >> 2) { 90 case 0: /* STATUS */ 91 return s->level & s->mask; 92 case 1: /* RAWSTAT */ 93 return s->level; 94 case 2: /* ENABLE */ 95 return s->mask; 96 case 4: /* SOFTINT */ 97 return s->level & 1; 98 case 8: /* PICENABLE */ 99 return s->pic_enable; 100 default: 101 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 102 return 0; 103 } 104 } 105 106 static void vpb_sic_write(void *opaque, hwaddr offset, 107 uint64_t value, unsigned size) 108 { 109 vpb_sic_state *s = (vpb_sic_state *)opaque; 110 111 switch (offset >> 2) { 112 case 2: /* ENSET */ 113 s->mask |= value; 114 break; 115 case 3: /* ENCLR */ 116 s->mask &= ~value; 117 break; 118 case 4: /* SOFTINTSET */ 119 if (value) 120 s->mask |= 1; 121 break; 122 case 5: /* SOFTINTCLR */ 123 if (value) 124 s->mask &= ~1u; 125 break; 126 case 8: /* PICENSET */ 127 s->pic_enable |= (value & 0x7fe00000); 128 vpb_sic_update_pic(s); 129 break; 130 case 9: /* PICENCLR */ 131 s->pic_enable &= ~value; 132 vpb_sic_update_pic(s); 133 break; 134 default: 135 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 136 return; 137 } 138 vpb_sic_update(s); 139 } 140 141 static const MemoryRegionOps vpb_sic_ops = { 142 .read = vpb_sic_read, 143 .write = vpb_sic_write, 144 .endianness = DEVICE_NATIVE_ENDIAN, 145 }; 146 147 static int vpb_sic_init(SysBusDevice *dev) 148 { 149 vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev); 150 int i; 151 152 qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32); 153 for (i = 0; i < 32; i++) { 154 sysbus_init_irq(dev, &s->parent[i]); 155 } 156 s->irq = 31; 157 memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000); 158 sysbus_init_mmio(dev, &s->iomem); 159 return 0; 160 } 161 162 /* Board init. */ 163 164 /* The AB and PB boards both use the same core, just with different 165 peripherals and expansion busses. For now we emulate a subset of the 166 PB peripherals and just change the board ID. */ 167 168 static struct arm_boot_info versatile_binfo; 169 170 static void versatile_init(QEMUMachineInitArgs *args, int board_id) 171 { 172 ARMCPU *cpu; 173 MemoryRegion *sysmem = get_system_memory(); 174 MemoryRegion *ram = g_new(MemoryRegion, 1); 175 qemu_irq *cpu_pic; 176 qemu_irq pic[32]; 177 qemu_irq sic[32]; 178 DeviceState *dev, *sysctl; 179 SysBusDevice *busdev; 180 DeviceState *pl041; 181 PCIBus *pci_bus; 182 NICInfo *nd; 183 i2c_bus *i2c; 184 int n; 185 int done_smc = 0; 186 DriveInfo *dinfo; 187 188 if (!args->cpu_model) { 189 args->cpu_model = "arm926"; 190 } 191 cpu = cpu_arm_init(args->cpu_model); 192 if (!cpu) { 193 fprintf(stderr, "Unable to find CPU definition\n"); 194 exit(1); 195 } 196 memory_region_init_ram(ram, "versatile.ram", args->ram_size); 197 vmstate_register_ram_global(ram); 198 /* ??? RAM should repeat to fill physical memory space. */ 199 /* SDRAM at address zero. */ 200 memory_region_add_subregion(sysmem, 0, ram); 201 202 sysctl = qdev_create(NULL, "realview_sysctl"); 203 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 204 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 205 qdev_init_nofail(sysctl); 206 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 207 208 cpu_pic = arm_pic_init_cpu(cpu); 209 dev = sysbus_create_varargs("pl190", 0x10140000, 210 cpu_pic[ARM_PIC_CPU_IRQ], 211 cpu_pic[ARM_PIC_CPU_FIQ], NULL); 212 for (n = 0; n < 32; n++) { 213 pic[n] = qdev_get_gpio_in(dev, n); 214 } 215 dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); 216 for (n = 0; n < 32; n++) { 217 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 218 sic[n] = qdev_get_gpio_in(dev, n); 219 } 220 221 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 222 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 223 224 dev = qdev_create(NULL, "versatile_pci"); 225 busdev = SYS_BUS_DEVICE(dev); 226 qdev_init_nofail(dev); 227 sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */ 228 sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */ 229 sysbus_connect_irq(busdev, 0, sic[27]); 230 sysbus_connect_irq(busdev, 1, sic[28]); 231 sysbus_connect_irq(busdev, 2, sic[29]); 232 sysbus_connect_irq(busdev, 3, sic[30]); 233 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 234 235 /* The Versatile PCI bridge does not provide access to PCI IO space, 236 so many of the qemu PCI devices are not useable. */ 237 for(n = 0; n < nb_nics; n++) { 238 nd = &nd_table[n]; 239 240 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { 241 smc91c111_init(nd, 0x10010000, sic[25]); 242 done_smc = 1; 243 } else { 244 pci_nic_init_nofail(nd, "rtl8139", NULL); 245 } 246 } 247 if (usb_enabled(false)) { 248 pci_create_simple(pci_bus, -1, "pci-ohci"); 249 } 250 n = drive_get_max_bus(IF_SCSI); 251 while (n >= 0) { 252 pci_create_simple(pci_bus, -1, "lsi53c895a"); 253 n--; 254 } 255 256 sysbus_create_simple("pl011", 0x101f1000, pic[12]); 257 sysbus_create_simple("pl011", 0x101f2000, pic[13]); 258 sysbus_create_simple("pl011", 0x101f3000, pic[14]); 259 sysbus_create_simple("pl011", 0x10009000, sic[6]); 260 261 sysbus_create_simple("pl080", 0x10130000, pic[17]); 262 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 263 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 264 265 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 266 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 267 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 268 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 269 270 /* The versatile/PB actually has a modified Color LCD controller 271 that includes hardware cursor support from the PL111. */ 272 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); 273 /* Wire up the mux control signals from the SYS_CLCD register */ 274 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 275 276 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 277 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 278 279 /* Add PL031 Real Time Clock. */ 280 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 281 282 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 283 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); 284 i2c_create_slave(i2c, "ds1338", 0x68); 285 286 /* Add PL041 AACI Interface to the LM4549 codec */ 287 pl041 = qdev_create(NULL, "pl041"); 288 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 289 qdev_init_nofail(pl041); 290 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 291 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 292 293 /* Memory map for Versatile/PB: */ 294 /* 0x10000000 System registers. */ 295 /* 0x10001000 PCI controller config registers. */ 296 /* 0x10002000 Serial bus interface. */ 297 /* 0x10003000 Secondary interrupt controller. */ 298 /* 0x10004000 AACI (audio). */ 299 /* 0x10005000 MMCI0. */ 300 /* 0x10006000 KMI0 (keyboard). */ 301 /* 0x10007000 KMI1 (mouse). */ 302 /* 0x10008000 Character LCD Interface. */ 303 /* 0x10009000 UART3. */ 304 /* 0x1000a000 Smart card 1. */ 305 /* 0x1000b000 MMCI1. */ 306 /* 0x10010000 Ethernet. */ 307 /* 0x10020000 USB. */ 308 /* 0x10100000 SSMC. */ 309 /* 0x10110000 MPMC. */ 310 /* 0x10120000 CLCD Controller. */ 311 /* 0x10130000 DMA Controller. */ 312 /* 0x10140000 Vectored interrupt controller. */ 313 /* 0x101d0000 AHB Monitor Interface. */ 314 /* 0x101e0000 System Controller. */ 315 /* 0x101e1000 Watchdog Interface. */ 316 /* 0x101e2000 Timer 0/1. */ 317 /* 0x101e3000 Timer 2/3. */ 318 /* 0x101e4000 GPIO port 0. */ 319 /* 0x101e5000 GPIO port 1. */ 320 /* 0x101e6000 GPIO port 2. */ 321 /* 0x101e7000 GPIO port 3. */ 322 /* 0x101e8000 RTC. */ 323 /* 0x101f0000 Smart card 0. */ 324 /* 0x101f1000 UART0. */ 325 /* 0x101f2000 UART1. */ 326 /* 0x101f3000 UART2. */ 327 /* 0x101f4000 SSPI. */ 328 /* 0x34000000 NOR Flash */ 329 330 dinfo = drive_get(IF_PFLASH, 0, 0); 331 if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash", 332 VERSATILE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, 333 VERSATILE_FLASH_SECT_SIZE, 334 VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE, 335 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { 336 fprintf(stderr, "qemu: Error registering flash memory.\n"); 337 } 338 339 versatile_binfo.ram_size = args->ram_size; 340 versatile_binfo.kernel_filename = args->kernel_filename; 341 versatile_binfo.kernel_cmdline = args->kernel_cmdline; 342 versatile_binfo.initrd_filename = args->initrd_filename; 343 versatile_binfo.board_id = board_id; 344 arm_load_kernel(cpu, &versatile_binfo); 345 } 346 347 static void vpb_init(QEMUMachineInitArgs *args) 348 { 349 versatile_init(args, 0x183); 350 } 351 352 static void vab_init(QEMUMachineInitArgs *args) 353 { 354 versatile_init(args, 0x25e); 355 } 356 357 static QEMUMachine versatilepb_machine = { 358 .name = "versatilepb", 359 .desc = "ARM Versatile/PB (ARM926EJ-S)", 360 .init = vpb_init, 361 .block_default_type = IF_SCSI, 362 DEFAULT_MACHINE_OPTIONS, 363 }; 364 365 static QEMUMachine versatileab_machine = { 366 .name = "versatileab", 367 .desc = "ARM Versatile/AB (ARM926EJ-S)", 368 .init = vab_init, 369 .block_default_type = IF_SCSI, 370 DEFAULT_MACHINE_OPTIONS, 371 }; 372 373 static void versatile_machine_init(void) 374 { 375 qemu_register_machine(&versatilepb_machine); 376 qemu_register_machine(&versatileab_machine); 377 } 378 379 machine_init(versatile_machine_init); 380 381 static void vpb_sic_class_init(ObjectClass *klass, void *data) 382 { 383 DeviceClass *dc = DEVICE_CLASS(klass); 384 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 385 386 k->init = vpb_sic_init; 387 dc->no_user = 1; 388 dc->vmsd = &vmstate_vpb_sic; 389 } 390 391 static const TypeInfo vpb_sic_info = { 392 .name = "versatilepb_sic", 393 .parent = TYPE_SYS_BUS_DEVICE, 394 .instance_size = sizeof(vpb_sic_state), 395 .class_init = vpb_sic_class_init, 396 }; 397 398 static void versatilepb_register_types(void) 399 { 400 type_register_static(&vpb_sic_info); 401 } 402 403 type_init(versatilepb_register_types) 404