1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/datadir.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/boot.h" 30 #include "hw/arm/primecell.h" 31 #include "hw/net/lan9118.h" 32 #include "hw/i2c/i2c.h" 33 #include "net/net.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "hw/block/flash.h" 38 #include "sysemu/device_tree.h" 39 #include "qemu/error-report.h" 40 #include <libfdt.h> 41 #include "hw/char/pl011.h" 42 #include "hw/cpu/a9mpcore.h" 43 #include "hw/cpu/a15mpcore.h" 44 #include "hw/i2c/arm_sbcon_i2c.h" 45 #include "hw/sd/sd.h" 46 #include "qom/object.h" 47 #include "audio/audio.h" 48 49 #define VEXPRESS_BOARD_ID 0x8e0 50 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 51 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 52 53 /* Number of virtio transports to create (0..8; limited by 54 * number of available IRQ lines). 55 */ 56 #define NUM_VIRTIO_TRANSPORTS 4 57 58 /* Address maps for peripherals: 59 * the Versatile Express motherboard has two possible maps, 60 * the "legacy" one (used for A9) and the "Cortex-A Series" 61 * map (used for newer cores). 62 * Individual daughterboards can also have different maps for 63 * their peripherals. 64 */ 65 66 enum { 67 VE_SYSREGS, 68 VE_SP810, 69 VE_SERIALPCI, 70 VE_PL041, 71 VE_MMCI, 72 VE_KMI0, 73 VE_KMI1, 74 VE_UART0, 75 VE_UART1, 76 VE_UART2, 77 VE_UART3, 78 VE_WDT, 79 VE_TIMER01, 80 VE_TIMER23, 81 VE_SERIALDVI, 82 VE_RTC, 83 VE_COMPACTFLASH, 84 VE_CLCD, 85 VE_NORFLASH0, 86 VE_NORFLASH1, 87 VE_NORFLASHALIAS, 88 VE_SRAM, 89 VE_VIDEORAM, 90 VE_ETHERNET, 91 VE_USB, 92 VE_DAPROM, 93 VE_VIRTIO, 94 }; 95 96 static hwaddr motherboard_legacy_map[] = { 97 [VE_NORFLASHALIAS] = 0, 98 /* CS7: 0x10000000 .. 0x10020000 */ 99 [VE_SYSREGS] = 0x10000000, 100 [VE_SP810] = 0x10001000, 101 [VE_SERIALPCI] = 0x10002000, 102 [VE_PL041] = 0x10004000, 103 [VE_MMCI] = 0x10005000, 104 [VE_KMI0] = 0x10006000, 105 [VE_KMI1] = 0x10007000, 106 [VE_UART0] = 0x10009000, 107 [VE_UART1] = 0x1000a000, 108 [VE_UART2] = 0x1000b000, 109 [VE_UART3] = 0x1000c000, 110 [VE_WDT] = 0x1000f000, 111 [VE_TIMER01] = 0x10011000, 112 [VE_TIMER23] = 0x10012000, 113 [VE_VIRTIO] = 0x10013000, 114 [VE_SERIALDVI] = 0x10016000, 115 [VE_RTC] = 0x10017000, 116 [VE_COMPACTFLASH] = 0x1001a000, 117 [VE_CLCD] = 0x1001f000, 118 /* CS0: 0x40000000 .. 0x44000000 */ 119 [VE_NORFLASH0] = 0x40000000, 120 /* CS1: 0x44000000 .. 0x48000000 */ 121 [VE_NORFLASH1] = 0x44000000, 122 /* CS2: 0x48000000 .. 0x4a000000 */ 123 [VE_SRAM] = 0x48000000, 124 /* CS3: 0x4c000000 .. 0x50000000 */ 125 [VE_VIDEORAM] = 0x4c000000, 126 [VE_ETHERNET] = 0x4e000000, 127 [VE_USB] = 0x4f000000, 128 }; 129 130 static hwaddr motherboard_aseries_map[] = { 131 [VE_NORFLASHALIAS] = 0, 132 /* CS0: 0x08000000 .. 0x0c000000 */ 133 [VE_NORFLASH0] = 0x08000000, 134 /* CS4: 0x0c000000 .. 0x10000000 */ 135 [VE_NORFLASH1] = 0x0c000000, 136 /* CS5: 0x10000000 .. 0x14000000 */ 137 /* CS1: 0x14000000 .. 0x18000000 */ 138 [VE_SRAM] = 0x14000000, 139 /* CS2: 0x18000000 .. 0x1c000000 */ 140 [VE_VIDEORAM] = 0x18000000, 141 [VE_ETHERNET] = 0x1a000000, 142 [VE_USB] = 0x1b000000, 143 /* CS3: 0x1c000000 .. 0x20000000 */ 144 [VE_DAPROM] = 0x1c000000, 145 [VE_SYSREGS] = 0x1c010000, 146 [VE_SP810] = 0x1c020000, 147 [VE_SERIALPCI] = 0x1c030000, 148 [VE_PL041] = 0x1c040000, 149 [VE_MMCI] = 0x1c050000, 150 [VE_KMI0] = 0x1c060000, 151 [VE_KMI1] = 0x1c070000, 152 [VE_UART0] = 0x1c090000, 153 [VE_UART1] = 0x1c0a0000, 154 [VE_UART2] = 0x1c0b0000, 155 [VE_UART3] = 0x1c0c0000, 156 [VE_WDT] = 0x1c0f0000, 157 [VE_TIMER01] = 0x1c110000, 158 [VE_TIMER23] = 0x1c120000, 159 [VE_VIRTIO] = 0x1c130000, 160 [VE_SERIALDVI] = 0x1c160000, 161 [VE_RTC] = 0x1c170000, 162 [VE_COMPACTFLASH] = 0x1c1a0000, 163 [VE_CLCD] = 0x1c1f0000, 164 }; 165 166 /* Structure defining the peculiarities of a specific daughterboard */ 167 168 typedef struct VEDBoardInfo VEDBoardInfo; 169 170 struct VexpressMachineClass { 171 MachineClass parent; 172 VEDBoardInfo *daughterboard; 173 }; 174 175 struct VexpressMachineState { 176 MachineState parent; 177 MemoryRegion vram; 178 MemoryRegion sram; 179 MemoryRegion flashalias; 180 MemoryRegion a15sram; 181 bool secure; 182 bool virt; 183 }; 184 185 #define TYPE_VEXPRESS_MACHINE "vexpress" 186 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 187 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 188 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) 189 190 typedef void DBoardInitFn(VexpressMachineState *machine, 191 ram_addr_t ram_size, 192 const char *cpu_type, 193 qemu_irq *pic); 194 195 struct VEDBoardInfo { 196 struct arm_boot_info bootinfo; 197 const hwaddr *motherboard_map; 198 hwaddr loader_start; 199 const hwaddr gic_cpu_if_addr; 200 uint32_t proc_id; 201 uint32_t num_voltage_sensors; 202 const uint32_t *voltages; 203 uint32_t num_clocks; 204 const uint32_t *clocks; 205 DBoardInitFn *init; 206 }; 207 208 static void init_cpus(MachineState *ms, const char *cpu_type, 209 const char *privdev, hwaddr periphbase, 210 qemu_irq *pic, bool secure, bool virt) 211 { 212 DeviceState *dev; 213 SysBusDevice *busdev; 214 int n; 215 unsigned int smp_cpus = ms->smp.cpus; 216 217 /* Create the actual CPUs */ 218 for (n = 0; n < smp_cpus; n++) { 219 Object *cpuobj = object_new(cpu_type); 220 221 if (!secure) { 222 object_property_set_bool(cpuobj, "has_el3", false, NULL); 223 } 224 if (!virt) { 225 if (object_property_find(cpuobj, "has_el2")) { 226 object_property_set_bool(cpuobj, "has_el2", false, NULL); 227 } 228 } 229 230 if (object_property_find(cpuobj, "reset-cbar")) { 231 object_property_set_int(cpuobj, "reset-cbar", periphbase, 232 &error_abort); 233 } 234 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 235 } 236 237 /* Create the private peripheral devices (including the GIC); 238 * this must happen after the CPUs are created because a15mpcore_priv 239 * wires itself up to the CPU's generic_timer gpio out lines. 240 */ 241 dev = qdev_new(privdev); 242 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 243 busdev = SYS_BUS_DEVICE(dev); 244 sysbus_realize_and_unref(busdev, &error_fatal); 245 sysbus_mmio_map(busdev, 0, periphbase); 246 247 /* Interrupts [42:0] are from the motherboard; 248 * [47:43] are reserved; [63:48] are daughterboard 249 * peripherals. Note that some documentation numbers 250 * external interrupts starting from 32 (because there 251 * are internal interrupts 0..31). 252 */ 253 for (n = 0; n < 64; n++) { 254 pic[n] = qdev_get_gpio_in(dev, n); 255 } 256 257 /* Connect the CPUs to the GIC */ 258 for (n = 0; n < smp_cpus; n++) { 259 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 260 261 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 262 sysbus_connect_irq(busdev, n + smp_cpus, 263 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 264 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 265 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 266 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 267 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 268 } 269 } 270 271 static void a9_daughterboard_init(VexpressMachineState *vms, 272 ram_addr_t ram_size, 273 const char *cpu_type, 274 qemu_irq *pic) 275 { 276 MachineState *machine = MACHINE(vms); 277 MemoryRegion *sysmem = get_system_memory(); 278 279 if (ram_size > 0x40000000) { 280 /* 1GB is the maximum the address space permits */ 281 error_report("vexpress-a9: cannot model more than 1GB RAM"); 282 exit(1); 283 } 284 285 /* 286 * RAM is from 0x60000000 upwards. The bottom 64MB of the 287 * address space should in theory be remappable to various 288 * things including ROM or RAM; we always map the flash there. 289 */ 290 memory_region_add_subregion(sysmem, 0x60000000, machine->ram); 291 292 /* 0x1e000000 A9MPCore (SCU) private memory region */ 293 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, 294 vms->secure, vms->virt); 295 296 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 297 298 /* 0x10020000 PL111 CLCD (daughterboard) */ 299 sysbus_create_simple("pl111", 0x10020000, pic[44]); 300 301 /* 0x10060000 AXI RAM */ 302 /* 0x100e0000 PL341 Dynamic Memory Controller */ 303 /* 0x100e1000 PL354 Static Memory Controller */ 304 /* 0x100e2000 System Configuration Controller */ 305 306 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 307 /* 0x100e5000 SP805 Watchdog module */ 308 /* 0x100e6000 BP147 TrustZone Protection Controller */ 309 /* 0x100e9000 PL301 'Fast' AXI matrix */ 310 /* 0x100ea000 PL301 'Slow' AXI matrix */ 311 /* 0x100ec000 TrustZone Address Space Controller */ 312 /* 0x10200000 CoreSight debug APB */ 313 /* 0x1e00a000 PL310 L2 Cache Controller */ 314 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 315 } 316 317 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 318 * values are in microvolts. 319 */ 320 static const uint32_t a9_voltages[] = { 321 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 322 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 323 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 324 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 325 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 326 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 327 }; 328 329 /* Reset values for daughterboard oscillators (in Hz) */ 330 static const uint32_t a9_clocks[] = { 331 45000000, /* AMBA AXI ACLK: 45MHz */ 332 23750000, /* daughterboard CLCD clock: 23.75MHz */ 333 66670000, /* Test chip reference clock: 66.67MHz */ 334 }; 335 336 static VEDBoardInfo a9_daughterboard = { 337 .motherboard_map = motherboard_legacy_map, 338 .loader_start = 0x60000000, 339 .gic_cpu_if_addr = 0x1e000100, 340 .proc_id = 0x0c000191, 341 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 342 .voltages = a9_voltages, 343 .num_clocks = ARRAY_SIZE(a9_clocks), 344 .clocks = a9_clocks, 345 .init = a9_daughterboard_init, 346 }; 347 348 static void a15_daughterboard_init(VexpressMachineState *vms, 349 ram_addr_t ram_size, 350 const char *cpu_type, 351 qemu_irq *pic) 352 { 353 MachineState *machine = MACHINE(vms); 354 MemoryRegion *sysmem = get_system_memory(); 355 356 { 357 /* We have to use a separate 64 bit variable here to avoid the gcc 358 * "comparison is always false due to limited range of data type" 359 * warning if we are on a host where ram_addr_t is 32 bits. 360 */ 361 uint64_t rsz = ram_size; 362 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 363 error_report("vexpress-a15: cannot model more than 30GB RAM"); 364 exit(1); 365 } 366 } 367 368 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 369 memory_region_add_subregion(sysmem, 0x80000000, machine->ram); 370 371 /* 0x2c000000 A15MPCore private memory region (GIC) */ 372 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, 373 0x2c000000, pic, vms->secure, vms->virt); 374 375 /* A15 daughterboard peripherals: */ 376 377 /* 0x20000000: CoreSight interfaces: not modelled */ 378 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 379 /* 0x2a420000: SCC: not modelled */ 380 /* 0x2a430000: system counter: not modelled */ 381 /* 0x2b000000: HDLCD controller: not modelled */ 382 /* 0x2b060000: SP805 watchdog: not modelled */ 383 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 384 /* 0x2e000000: system SRAM */ 385 memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, 386 &error_fatal); 387 memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); 388 389 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 390 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 391 } 392 393 static const uint32_t a15_voltages[] = { 394 900000, /* Vcore: 0.9V : CPU core voltage */ 395 }; 396 397 static const uint32_t a15_clocks[] = { 398 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 399 0, /* OSCCLK1: reserved */ 400 0, /* OSCCLK2: reserved */ 401 0, /* OSCCLK3: reserved */ 402 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 403 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 404 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 405 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 406 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 407 }; 408 409 static VEDBoardInfo a15_daughterboard = { 410 .motherboard_map = motherboard_aseries_map, 411 .loader_start = 0x80000000, 412 .gic_cpu_if_addr = 0x2c002000, 413 .proc_id = 0x14000237, 414 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 415 .voltages = a15_voltages, 416 .num_clocks = ARRAY_SIZE(a15_clocks), 417 .clocks = a15_clocks, 418 .init = a15_daughterboard_init, 419 }; 420 421 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 422 hwaddr addr, hwaddr size, uint32_t intc, 423 int irq) 424 { 425 /* Add a virtio_mmio node to the device tree blob: 426 * virtio_mmio@ADDRESS { 427 * compatible = "virtio,mmio"; 428 * reg = <ADDRESS, SIZE>; 429 * interrupt-parent = <&intc>; 430 * interrupts = <0, irq, 1>; 431 * } 432 * (Note that the format of the interrupts property is dependent on the 433 * interrupt controller that interrupt-parent points to; these are for 434 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 435 */ 436 int rc; 437 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 438 439 rc = qemu_fdt_add_subnode(fdt, nodename); 440 rc |= qemu_fdt_setprop_string(fdt, nodename, 441 "compatible", "virtio,mmio"); 442 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 443 acells, addr, scells, size); 444 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 445 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 446 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 447 g_free(nodename); 448 if (rc) { 449 return -1; 450 } 451 return 0; 452 } 453 454 static uint32_t find_int_controller(void *fdt) 455 { 456 /* Find the FDT node corresponding to the interrupt controller 457 * for virtio-mmio devices. We do this by scanning the fdt for 458 * a node with the right compatibility, since we know there is 459 * only one GIC on a vexpress board. 460 * We return the phandle of the node, or 0 if none was found. 461 */ 462 const char *compat = "arm,cortex-a9-gic"; 463 int offset; 464 465 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 466 if (offset >= 0) { 467 return fdt_get_phandle(fdt, offset); 468 } 469 return 0; 470 } 471 472 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 473 { 474 uint32_t acells, scells, intc; 475 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 476 477 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 478 NULL, &error_fatal); 479 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 480 NULL, &error_fatal); 481 intc = find_int_controller(fdt); 482 if (!intc) { 483 /* Not fatal, we just won't provide virtio. This will 484 * happen with older device tree blobs. 485 */ 486 warn_report("couldn't find interrupt controller in " 487 "dtb; will not include virtio-mmio devices in the dtb"); 488 } else { 489 int i; 490 const hwaddr *map = daughterboard->motherboard_map; 491 492 /* We iterate backwards here because adding nodes 493 * to the dtb puts them in last-first. 494 */ 495 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 496 add_virtio_mmio_node(fdt, acells, scells, 497 map[VE_VIRTIO] + 0x200 * i, 498 0x200, intc, 40 + i); 499 } 500 } 501 } 502 503 504 /* Open code a private version of pflash registration since we 505 * need to set non-default device width for VExpress platform. 506 */ 507 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 508 DriveInfo *di) 509 { 510 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 511 512 if (di) { 513 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); 514 } 515 516 qdev_prop_set_uint32(dev, "num-blocks", 517 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 518 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 519 qdev_prop_set_uint8(dev, "width", 4); 520 qdev_prop_set_uint8(dev, "device-width", 2); 521 qdev_prop_set_bit(dev, "big-endian", false); 522 qdev_prop_set_uint16(dev, "id0", 0x89); 523 qdev_prop_set_uint16(dev, "id1", 0x18); 524 qdev_prop_set_uint16(dev, "id2", 0x00); 525 qdev_prop_set_uint16(dev, "id3", 0x00); 526 qdev_prop_set_string(dev, "name", name); 527 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 528 529 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 530 return PFLASH_CFI01(dev); 531 } 532 533 static void vexpress_common_init(MachineState *machine) 534 { 535 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 536 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 537 VEDBoardInfo *daughterboard = vmc->daughterboard; 538 DeviceState *dev, *sysctl, *pl041; 539 qemu_irq pic[64]; 540 uint32_t sys_id; 541 DriveInfo *dinfo; 542 PFlashCFI01 *pflash0; 543 I2CBus *i2c; 544 ram_addr_t vram_size, sram_size; 545 MemoryRegion *sysmem = get_system_memory(); 546 const hwaddr *map = daughterboard->motherboard_map; 547 int i; 548 549 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 550 551 /* 552 * If a bios file was provided, attempt to map it into memory 553 */ 554 if (machine->firmware) { 555 char *fn; 556 int image_size; 557 558 if (drive_get(IF_PFLASH, 0, 0)) { 559 error_report("The contents of the first flash device may be " 560 "specified with -bios or with -drive if=pflash... " 561 "but you cannot use both options at once"); 562 exit(1); 563 } 564 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 565 if (!fn) { 566 error_report("Could not find ROM image '%s'", machine->firmware); 567 exit(1); 568 } 569 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 570 VEXPRESS_FLASH_SIZE); 571 g_free(fn); 572 if (image_size < 0) { 573 error_report("Could not load ROM image '%s'", machine->firmware); 574 exit(1); 575 } 576 } 577 578 /* Motherboard peripherals: the wiring is the same but the 579 * addresses vary between the legacy and A-Series memory maps. 580 */ 581 582 sys_id = 0x1190f500; 583 584 sysctl = qdev_new("realview_sysctl"); 585 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 586 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 587 qdev_prop_set_uint32(sysctl, "len-db-voltage", 588 daughterboard->num_voltage_sensors); 589 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 590 char *propname = g_strdup_printf("db-voltage[%d]", i); 591 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 592 g_free(propname); 593 } 594 qdev_prop_set_uint32(sysctl, "len-db-clock", 595 daughterboard->num_clocks); 596 for (i = 0; i < daughterboard->num_clocks; i++) { 597 char *propname = g_strdup_printf("db-clock[%d]", i); 598 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 599 g_free(propname); 600 } 601 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 602 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 603 604 /* VE_SP810: not modelled */ 605 /* VE_SERIALPCI: not modelled */ 606 607 pl041 = qdev_new("pl041"); 608 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 609 if (machine->audiodev) { 610 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); 611 } 612 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 613 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 614 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 615 616 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 617 /* Wire up MMC card detect and read-only signals */ 618 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 619 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 620 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 621 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 622 dinfo = drive_get(IF_SD, 0, 0); 623 if (dinfo) { 624 DeviceState *card; 625 626 card = qdev_new(TYPE_SD_CARD); 627 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 628 &error_fatal); 629 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 630 &error_fatal); 631 } 632 633 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 634 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 635 636 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 637 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 638 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 639 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 640 641 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 642 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 643 644 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL); 645 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 646 i2c_slave_create_simple(i2c, "sii9022", 0x39); 647 648 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 649 650 /* VE_COMPACTFLASH: not modelled */ 651 652 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 653 654 dinfo = drive_get(IF_PFLASH, 0, 0); 655 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 656 dinfo); 657 658 if (map[VE_NORFLASHALIAS] != -1) { 659 /* Map flash 0 as an alias into low memory */ 660 MemoryRegion *flash0mem; 661 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 662 memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", 663 flash0mem, 0, VEXPRESS_FLASH_SIZE); 664 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); 665 } 666 667 dinfo = drive_get(IF_PFLASH, 0, 1); 668 ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); 669 670 sram_size = 0x2000000; 671 memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, 672 &error_fatal); 673 memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); 674 675 vram_size = 0x800000; 676 memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, 677 &error_fatal); 678 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); 679 680 /* 0x4e000000 LAN9118 Ethernet */ 681 if (nd_table[0].used) { 682 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 683 } 684 685 /* VE_USB: not modelled */ 686 687 /* VE_DAPROM: not modelled */ 688 689 /* Create mmio transports, so the user can create virtio backends 690 * (which will be automatically plugged in to the transports). If 691 * no backend is created the transport will just sit harmlessly idle. 692 */ 693 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 694 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 695 pic[40 + i]); 696 } 697 698 daughterboard->bootinfo.ram_size = machine->ram_size; 699 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 700 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 701 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 702 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 703 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 704 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 705 /* When booting Linux we should be in secure state if the CPU has one. */ 706 daughterboard->bootinfo.secure_boot = vms->secure; 707 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); 708 } 709 710 static bool vexpress_get_secure(Object *obj, Error **errp) 711 { 712 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 713 714 return vms->secure; 715 } 716 717 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 718 { 719 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 720 721 vms->secure = value; 722 } 723 724 static bool vexpress_get_virt(Object *obj, Error **errp) 725 { 726 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 727 728 return vms->virt; 729 } 730 731 static void vexpress_set_virt(Object *obj, bool value, Error **errp) 732 { 733 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 734 735 vms->virt = value; 736 } 737 738 static void vexpress_instance_init(Object *obj) 739 { 740 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 741 742 /* EL3 is enabled by default on vexpress */ 743 vms->secure = true; 744 } 745 746 static void vexpress_a15_instance_init(Object *obj) 747 { 748 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 749 750 /* 751 * For the vexpress-a15, EL2 is by default enabled if EL3 is, 752 * but can also be specifically set to on or off. 753 */ 754 vms->virt = true; 755 } 756 757 static void vexpress_a9_instance_init(Object *obj) 758 { 759 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 760 761 /* The A9 doesn't have the virt extensions */ 762 vms->virt = false; 763 } 764 765 static void vexpress_class_init(ObjectClass *oc, void *data) 766 { 767 MachineClass *mc = MACHINE_CLASS(oc); 768 769 mc->desc = "ARM Versatile Express"; 770 mc->init = vexpress_common_init; 771 mc->max_cpus = 4; 772 mc->ignore_memory_transaction_failures = true; 773 mc->default_ram_id = "vexpress.highmem"; 774 775 machine_add_audiodev_property(mc); 776 object_class_property_add_bool(oc, "secure", vexpress_get_secure, 777 vexpress_set_secure); 778 object_class_property_set_description(oc, "secure", 779 "Set on/off to enable/disable the ARM " 780 "Security Extensions (TrustZone)"); 781 } 782 783 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 784 { 785 MachineClass *mc = MACHINE_CLASS(oc); 786 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 787 788 mc->desc = "ARM Versatile Express for Cortex-A9"; 789 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 790 791 vmc->daughterboard = &a9_daughterboard; 792 } 793 794 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 795 { 796 MachineClass *mc = MACHINE_CLASS(oc); 797 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 798 799 mc->desc = "ARM Versatile Express for Cortex-A15"; 800 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 801 802 vmc->daughterboard = &a15_daughterboard; 803 804 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt, 805 vexpress_set_virt); 806 object_class_property_set_description(oc, "virtualization", 807 "Set on/off to enable/disable the ARM " 808 "Virtualization Extensions " 809 "(defaults to same as 'secure')"); 810 811 } 812 813 static const TypeInfo vexpress_info = { 814 .name = TYPE_VEXPRESS_MACHINE, 815 .parent = TYPE_MACHINE, 816 .abstract = true, 817 .instance_size = sizeof(VexpressMachineState), 818 .instance_init = vexpress_instance_init, 819 .class_size = sizeof(VexpressMachineClass), 820 .class_init = vexpress_class_init, 821 }; 822 823 static const TypeInfo vexpress_a9_info = { 824 .name = TYPE_VEXPRESS_A9_MACHINE, 825 .parent = TYPE_VEXPRESS_MACHINE, 826 .class_init = vexpress_a9_class_init, 827 .instance_init = vexpress_a9_instance_init, 828 }; 829 830 static const TypeInfo vexpress_a15_info = { 831 .name = TYPE_VEXPRESS_A15_MACHINE, 832 .parent = TYPE_VEXPRESS_MACHINE, 833 .class_init = vexpress_a15_class_init, 834 .instance_init = vexpress_a15_instance_init, 835 }; 836 837 static void vexpress_machine_init(void) 838 { 839 type_register_static(&vexpress_info); 840 type_register_static(&vexpress_a9_info); 841 type_register_static(&vexpress_a15_info); 842 } 843 844 type_init(vexpress_machine_init); 845