1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/arm.h" 30 #include "hw/arm/primecell.h" 31 #include "hw/devices.h" 32 #include "hw/i2c/i2c.h" 33 #include "net/net.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "hw/block/flash.h" 39 #include "sysemu/device_tree.h" 40 #include "qemu/error-report.h" 41 #include <libfdt.h> 42 #include "hw/char/pl011.h" 43 #include "hw/cpu/a9mpcore.h" 44 #include "hw/cpu/a15mpcore.h" 45 46 #define VEXPRESS_BOARD_ID 0x8e0 47 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 48 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 49 50 /* Number of virtio transports to create (0..8; limited by 51 * number of available IRQ lines). 52 */ 53 #define NUM_VIRTIO_TRANSPORTS 4 54 55 /* Address maps for peripherals: 56 * the Versatile Express motherboard has two possible maps, 57 * the "legacy" one (used for A9) and the "Cortex-A Series" 58 * map (used for newer cores). 59 * Individual daughterboards can also have different maps for 60 * their peripherals. 61 */ 62 63 enum { 64 VE_SYSREGS, 65 VE_SP810, 66 VE_SERIALPCI, 67 VE_PL041, 68 VE_MMCI, 69 VE_KMI0, 70 VE_KMI1, 71 VE_UART0, 72 VE_UART1, 73 VE_UART2, 74 VE_UART3, 75 VE_WDT, 76 VE_TIMER01, 77 VE_TIMER23, 78 VE_SERIALDVI, 79 VE_RTC, 80 VE_COMPACTFLASH, 81 VE_CLCD, 82 VE_NORFLASH0, 83 VE_NORFLASH1, 84 VE_NORFLASHALIAS, 85 VE_SRAM, 86 VE_VIDEORAM, 87 VE_ETHERNET, 88 VE_USB, 89 VE_DAPROM, 90 VE_VIRTIO, 91 }; 92 93 static hwaddr motherboard_legacy_map[] = { 94 [VE_NORFLASHALIAS] = 0, 95 /* CS7: 0x10000000 .. 0x10020000 */ 96 [VE_SYSREGS] = 0x10000000, 97 [VE_SP810] = 0x10001000, 98 [VE_SERIALPCI] = 0x10002000, 99 [VE_PL041] = 0x10004000, 100 [VE_MMCI] = 0x10005000, 101 [VE_KMI0] = 0x10006000, 102 [VE_KMI1] = 0x10007000, 103 [VE_UART0] = 0x10009000, 104 [VE_UART1] = 0x1000a000, 105 [VE_UART2] = 0x1000b000, 106 [VE_UART3] = 0x1000c000, 107 [VE_WDT] = 0x1000f000, 108 [VE_TIMER01] = 0x10011000, 109 [VE_TIMER23] = 0x10012000, 110 [VE_VIRTIO] = 0x10013000, 111 [VE_SERIALDVI] = 0x10016000, 112 [VE_RTC] = 0x10017000, 113 [VE_COMPACTFLASH] = 0x1001a000, 114 [VE_CLCD] = 0x1001f000, 115 /* CS0: 0x40000000 .. 0x44000000 */ 116 [VE_NORFLASH0] = 0x40000000, 117 /* CS1: 0x44000000 .. 0x48000000 */ 118 [VE_NORFLASH1] = 0x44000000, 119 /* CS2: 0x48000000 .. 0x4a000000 */ 120 [VE_SRAM] = 0x48000000, 121 /* CS3: 0x4c000000 .. 0x50000000 */ 122 [VE_VIDEORAM] = 0x4c000000, 123 [VE_ETHERNET] = 0x4e000000, 124 [VE_USB] = 0x4f000000, 125 }; 126 127 static hwaddr motherboard_aseries_map[] = { 128 [VE_NORFLASHALIAS] = 0, 129 /* CS0: 0x08000000 .. 0x0c000000 */ 130 [VE_NORFLASH0] = 0x08000000, 131 /* CS4: 0x0c000000 .. 0x10000000 */ 132 [VE_NORFLASH1] = 0x0c000000, 133 /* CS5: 0x10000000 .. 0x14000000 */ 134 /* CS1: 0x14000000 .. 0x18000000 */ 135 [VE_SRAM] = 0x14000000, 136 /* CS2: 0x18000000 .. 0x1c000000 */ 137 [VE_VIDEORAM] = 0x18000000, 138 [VE_ETHERNET] = 0x1a000000, 139 [VE_USB] = 0x1b000000, 140 /* CS3: 0x1c000000 .. 0x20000000 */ 141 [VE_DAPROM] = 0x1c000000, 142 [VE_SYSREGS] = 0x1c010000, 143 [VE_SP810] = 0x1c020000, 144 [VE_SERIALPCI] = 0x1c030000, 145 [VE_PL041] = 0x1c040000, 146 [VE_MMCI] = 0x1c050000, 147 [VE_KMI0] = 0x1c060000, 148 [VE_KMI1] = 0x1c070000, 149 [VE_UART0] = 0x1c090000, 150 [VE_UART1] = 0x1c0a0000, 151 [VE_UART2] = 0x1c0b0000, 152 [VE_UART3] = 0x1c0c0000, 153 [VE_WDT] = 0x1c0f0000, 154 [VE_TIMER01] = 0x1c110000, 155 [VE_TIMER23] = 0x1c120000, 156 [VE_VIRTIO] = 0x1c130000, 157 [VE_SERIALDVI] = 0x1c160000, 158 [VE_RTC] = 0x1c170000, 159 [VE_COMPACTFLASH] = 0x1c1a0000, 160 [VE_CLCD] = 0x1c1f0000, 161 }; 162 163 /* Structure defining the peculiarities of a specific daughterboard */ 164 165 typedef struct VEDBoardInfo VEDBoardInfo; 166 167 typedef struct { 168 MachineClass parent; 169 VEDBoardInfo *daughterboard; 170 } VexpressMachineClass; 171 172 typedef struct { 173 MachineState parent; 174 bool secure; 175 bool virt; 176 } VexpressMachineState; 177 178 #define TYPE_VEXPRESS_MACHINE "vexpress" 179 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 180 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 181 #define VEXPRESS_MACHINE(obj) \ 182 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 183 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 184 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 185 #define VEXPRESS_MACHINE_CLASS(klass) \ 186 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 187 188 typedef void DBoardInitFn(const VexpressMachineState *machine, 189 ram_addr_t ram_size, 190 const char *cpu_type, 191 qemu_irq *pic); 192 193 struct VEDBoardInfo { 194 struct arm_boot_info bootinfo; 195 const hwaddr *motherboard_map; 196 hwaddr loader_start; 197 const hwaddr gic_cpu_if_addr; 198 uint32_t proc_id; 199 uint32_t num_voltage_sensors; 200 const uint32_t *voltages; 201 uint32_t num_clocks; 202 const uint32_t *clocks; 203 DBoardInitFn *init; 204 }; 205 206 static void init_cpus(const char *cpu_type, const char *privdev, 207 hwaddr periphbase, qemu_irq *pic, bool secure, bool virt) 208 { 209 DeviceState *dev; 210 SysBusDevice *busdev; 211 int n; 212 213 /* Create the actual CPUs */ 214 for (n = 0; n < smp_cpus; n++) { 215 Object *cpuobj = object_new(cpu_type); 216 217 if (!secure) { 218 object_property_set_bool(cpuobj, false, "has_el3", NULL); 219 } 220 if (!virt) { 221 if (object_property_find(cpuobj, "has_el2", NULL)) { 222 object_property_set_bool(cpuobj, false, "has_el2", NULL); 223 } 224 } 225 226 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 227 object_property_set_int(cpuobj, periphbase, 228 "reset-cbar", &error_abort); 229 } 230 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 231 } 232 233 /* Create the private peripheral devices (including the GIC); 234 * this must happen after the CPUs are created because a15mpcore_priv 235 * wires itself up to the CPU's generic_timer gpio out lines. 236 */ 237 dev = qdev_create(NULL, privdev); 238 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 239 qdev_init_nofail(dev); 240 busdev = SYS_BUS_DEVICE(dev); 241 sysbus_mmio_map(busdev, 0, periphbase); 242 243 /* Interrupts [42:0] are from the motherboard; 244 * [47:43] are reserved; [63:48] are daughterboard 245 * peripherals. Note that some documentation numbers 246 * external interrupts starting from 32 (because there 247 * are internal interrupts 0..31). 248 */ 249 for (n = 0; n < 64; n++) { 250 pic[n] = qdev_get_gpio_in(dev, n); 251 } 252 253 /* Connect the CPUs to the GIC */ 254 for (n = 0; n < smp_cpus; n++) { 255 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 256 257 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 258 sysbus_connect_irq(busdev, n + smp_cpus, 259 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 260 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 261 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 262 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 263 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 264 } 265 } 266 267 static void a9_daughterboard_init(const VexpressMachineState *vms, 268 ram_addr_t ram_size, 269 const char *cpu_type, 270 qemu_irq *pic) 271 { 272 MemoryRegion *sysmem = get_system_memory(); 273 MemoryRegion *ram = g_new(MemoryRegion, 1); 274 MemoryRegion *lowram = g_new(MemoryRegion, 1); 275 ram_addr_t low_ram_size; 276 277 if (ram_size > 0x40000000) { 278 /* 1GB is the maximum the address space permits */ 279 error_report("vexpress-a9: cannot model more than 1GB RAM"); 280 exit(1); 281 } 282 283 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 284 ram_size); 285 low_ram_size = ram_size; 286 if (low_ram_size > 0x4000000) { 287 low_ram_size = 0x4000000; 288 } 289 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 290 * address space should in theory be remappable to various 291 * things including ROM or RAM; we always map the RAM there. 292 */ 293 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 294 memory_region_add_subregion(sysmem, 0x0, lowram); 295 memory_region_add_subregion(sysmem, 0x60000000, ram); 296 297 /* 0x1e000000 A9MPCore (SCU) private memory region */ 298 init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, 299 vms->secure, vms->virt); 300 301 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 302 303 /* 0x10020000 PL111 CLCD (daughterboard) */ 304 sysbus_create_simple("pl111", 0x10020000, pic[44]); 305 306 /* 0x10060000 AXI RAM */ 307 /* 0x100e0000 PL341 Dynamic Memory Controller */ 308 /* 0x100e1000 PL354 Static Memory Controller */ 309 /* 0x100e2000 System Configuration Controller */ 310 311 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 312 /* 0x100e5000 SP805 Watchdog module */ 313 /* 0x100e6000 BP147 TrustZone Protection Controller */ 314 /* 0x100e9000 PL301 'Fast' AXI matrix */ 315 /* 0x100ea000 PL301 'Slow' AXI matrix */ 316 /* 0x100ec000 TrustZone Address Space Controller */ 317 /* 0x10200000 CoreSight debug APB */ 318 /* 0x1e00a000 PL310 L2 Cache Controller */ 319 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 320 } 321 322 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 323 * values are in microvolts. 324 */ 325 static const uint32_t a9_voltages[] = { 326 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 327 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 328 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 329 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 330 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 331 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 332 }; 333 334 /* Reset values for daughterboard oscillators (in Hz) */ 335 static const uint32_t a9_clocks[] = { 336 45000000, /* AMBA AXI ACLK: 45MHz */ 337 23750000, /* daughterboard CLCD clock: 23.75MHz */ 338 66670000, /* Test chip reference clock: 66.67MHz */ 339 }; 340 341 static VEDBoardInfo a9_daughterboard = { 342 .motherboard_map = motherboard_legacy_map, 343 .loader_start = 0x60000000, 344 .gic_cpu_if_addr = 0x1e000100, 345 .proc_id = 0x0c000191, 346 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 347 .voltages = a9_voltages, 348 .num_clocks = ARRAY_SIZE(a9_clocks), 349 .clocks = a9_clocks, 350 .init = a9_daughterboard_init, 351 }; 352 353 static void a15_daughterboard_init(const VexpressMachineState *vms, 354 ram_addr_t ram_size, 355 const char *cpu_type, 356 qemu_irq *pic) 357 { 358 MemoryRegion *sysmem = get_system_memory(); 359 MemoryRegion *ram = g_new(MemoryRegion, 1); 360 MemoryRegion *sram = g_new(MemoryRegion, 1); 361 362 { 363 /* We have to use a separate 64 bit variable here to avoid the gcc 364 * "comparison is always false due to limited range of data type" 365 * warning if we are on a host where ram_addr_t is 32 bits. 366 */ 367 uint64_t rsz = ram_size; 368 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 369 error_report("vexpress-a15: cannot model more than 30GB RAM"); 370 exit(1); 371 } 372 } 373 374 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 375 ram_size); 376 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 377 memory_region_add_subregion(sysmem, 0x80000000, ram); 378 379 /* 0x2c000000 A15MPCore private memory region (GIC) */ 380 init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure, 381 vms->virt); 382 383 /* A15 daughterboard peripherals: */ 384 385 /* 0x20000000: CoreSight interfaces: not modelled */ 386 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 387 /* 0x2a420000: SCC: not modelled */ 388 /* 0x2a430000: system counter: not modelled */ 389 /* 0x2b000000: HDLCD controller: not modelled */ 390 /* 0x2b060000: SP805 watchdog: not modelled */ 391 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 392 /* 0x2e000000: system SRAM */ 393 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 394 &error_fatal); 395 memory_region_add_subregion(sysmem, 0x2e000000, sram); 396 397 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 398 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 399 } 400 401 static const uint32_t a15_voltages[] = { 402 900000, /* Vcore: 0.9V : CPU core voltage */ 403 }; 404 405 static const uint32_t a15_clocks[] = { 406 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 407 0, /* OSCCLK1: reserved */ 408 0, /* OSCCLK2: reserved */ 409 0, /* OSCCLK3: reserved */ 410 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 411 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 412 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 413 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 414 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 415 }; 416 417 static VEDBoardInfo a15_daughterboard = { 418 .motherboard_map = motherboard_aseries_map, 419 .loader_start = 0x80000000, 420 .gic_cpu_if_addr = 0x2c002000, 421 .proc_id = 0x14000237, 422 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 423 .voltages = a15_voltages, 424 .num_clocks = ARRAY_SIZE(a15_clocks), 425 .clocks = a15_clocks, 426 .init = a15_daughterboard_init, 427 }; 428 429 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 430 hwaddr addr, hwaddr size, uint32_t intc, 431 int irq) 432 { 433 /* Add a virtio_mmio node to the device tree blob: 434 * virtio_mmio@ADDRESS { 435 * compatible = "virtio,mmio"; 436 * reg = <ADDRESS, SIZE>; 437 * interrupt-parent = <&intc>; 438 * interrupts = <0, irq, 1>; 439 * } 440 * (Note that the format of the interrupts property is dependent on the 441 * interrupt controller that interrupt-parent points to; these are for 442 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 443 */ 444 int rc; 445 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 446 447 rc = qemu_fdt_add_subnode(fdt, nodename); 448 rc |= qemu_fdt_setprop_string(fdt, nodename, 449 "compatible", "virtio,mmio"); 450 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 451 acells, addr, scells, size); 452 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 453 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 454 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 455 g_free(nodename); 456 if (rc) { 457 return -1; 458 } 459 return 0; 460 } 461 462 static uint32_t find_int_controller(void *fdt) 463 { 464 /* Find the FDT node corresponding to the interrupt controller 465 * for virtio-mmio devices. We do this by scanning the fdt for 466 * a node with the right compatibility, since we know there is 467 * only one GIC on a vexpress board. 468 * We return the phandle of the node, or 0 if none was found. 469 */ 470 const char *compat = "arm,cortex-a9-gic"; 471 int offset; 472 473 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 474 if (offset >= 0) { 475 return fdt_get_phandle(fdt, offset); 476 } 477 return 0; 478 } 479 480 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 481 { 482 uint32_t acells, scells, intc; 483 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 484 485 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 486 NULL, &error_fatal); 487 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 488 NULL, &error_fatal); 489 intc = find_int_controller(fdt); 490 if (!intc) { 491 /* Not fatal, we just won't provide virtio. This will 492 * happen with older device tree blobs. 493 */ 494 warn_report("couldn't find interrupt controller in " 495 "dtb; will not include virtio-mmio devices in the dtb"); 496 } else { 497 int i; 498 const hwaddr *map = daughterboard->motherboard_map; 499 500 /* We iterate backwards here because adding nodes 501 * to the dtb puts them in last-first. 502 */ 503 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 504 add_virtio_mmio_node(fdt, acells, scells, 505 map[VE_VIRTIO] + 0x200 * i, 506 0x200, intc, 40 + i); 507 } 508 } 509 } 510 511 512 /* Open code a private version of pflash registration since we 513 * need to set non-default device width for VExpress platform. 514 */ 515 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 516 DriveInfo *di) 517 { 518 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 519 520 if (di) { 521 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di), 522 &error_abort); 523 } 524 525 qdev_prop_set_uint32(dev, "num-blocks", 526 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 527 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 528 qdev_prop_set_uint8(dev, "width", 4); 529 qdev_prop_set_uint8(dev, "device-width", 2); 530 qdev_prop_set_bit(dev, "big-endian", false); 531 qdev_prop_set_uint16(dev, "id0", 0x89); 532 qdev_prop_set_uint16(dev, "id1", 0x18); 533 qdev_prop_set_uint16(dev, "id2", 0x00); 534 qdev_prop_set_uint16(dev, "id3", 0x00); 535 qdev_prop_set_string(dev, "name", name); 536 qdev_init_nofail(dev); 537 538 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 539 return PFLASH_CFI01(dev); 540 } 541 542 static void vexpress_common_init(MachineState *machine) 543 { 544 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 545 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 546 VEDBoardInfo *daughterboard = vmc->daughterboard; 547 DeviceState *dev, *sysctl, *pl041; 548 qemu_irq pic[64]; 549 uint32_t sys_id; 550 DriveInfo *dinfo; 551 PFlashCFI01 *pflash0; 552 I2CBus *i2c; 553 ram_addr_t vram_size, sram_size; 554 MemoryRegion *sysmem = get_system_memory(); 555 MemoryRegion *vram = g_new(MemoryRegion, 1); 556 MemoryRegion *sram = g_new(MemoryRegion, 1); 557 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 558 MemoryRegion *flash0mem; 559 const hwaddr *map = daughterboard->motherboard_map; 560 int i; 561 562 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 563 564 /* 565 * If a bios file was provided, attempt to map it into memory 566 */ 567 if (bios_name) { 568 char *fn; 569 int image_size; 570 571 if (drive_get(IF_PFLASH, 0, 0)) { 572 error_report("The contents of the first flash device may be " 573 "specified with -bios or with -drive if=pflash... " 574 "but you cannot use both options at once"); 575 exit(1); 576 } 577 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 578 if (!fn) { 579 error_report("Could not find ROM image '%s'", bios_name); 580 exit(1); 581 } 582 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 583 VEXPRESS_FLASH_SIZE); 584 g_free(fn); 585 if (image_size < 0) { 586 error_report("Could not load ROM image '%s'", bios_name); 587 exit(1); 588 } 589 } 590 591 /* Motherboard peripherals: the wiring is the same but the 592 * addresses vary between the legacy and A-Series memory maps. 593 */ 594 595 sys_id = 0x1190f500; 596 597 sysctl = qdev_create(NULL, "realview_sysctl"); 598 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 599 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 600 qdev_prop_set_uint32(sysctl, "len-db-voltage", 601 daughterboard->num_voltage_sensors); 602 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 603 char *propname = g_strdup_printf("db-voltage[%d]", i); 604 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 605 g_free(propname); 606 } 607 qdev_prop_set_uint32(sysctl, "len-db-clock", 608 daughterboard->num_clocks); 609 for (i = 0; i < daughterboard->num_clocks; i++) { 610 char *propname = g_strdup_printf("db-clock[%d]", i); 611 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 612 g_free(propname); 613 } 614 qdev_init_nofail(sysctl); 615 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 616 617 /* VE_SP810: not modelled */ 618 /* VE_SERIALPCI: not modelled */ 619 620 pl041 = qdev_create(NULL, "pl041"); 621 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 622 qdev_init_nofail(pl041); 623 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 624 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 625 626 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 627 /* Wire up MMC card detect and read-only signals */ 628 qdev_connect_gpio_out(dev, 0, 629 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 630 qdev_connect_gpio_out(dev, 1, 631 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 632 633 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 634 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 635 636 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 637 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 638 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 639 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 640 641 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 642 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 643 644 dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL); 645 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 646 i2c_create_slave(i2c, "sii9022", 0x39); 647 648 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 649 650 /* VE_COMPACTFLASH: not modelled */ 651 652 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 653 654 dinfo = drive_get_next(IF_PFLASH); 655 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 656 dinfo); 657 if (!pflash0) { 658 error_report("vexpress: error registering flash 0"); 659 exit(1); 660 } 661 662 if (map[VE_NORFLASHALIAS] != -1) { 663 /* Map flash 0 as an alias into low memory */ 664 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 665 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 666 flash0mem, 0, VEXPRESS_FLASH_SIZE); 667 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 668 } 669 670 dinfo = drive_get_next(IF_PFLASH); 671 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 672 dinfo)) { 673 error_report("vexpress: error registering flash 1"); 674 exit(1); 675 } 676 677 sram_size = 0x2000000; 678 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 679 &error_fatal); 680 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 681 682 vram_size = 0x800000; 683 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 684 &error_fatal); 685 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 686 687 /* 0x4e000000 LAN9118 Ethernet */ 688 if (nd_table[0].used) { 689 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 690 } 691 692 /* VE_USB: not modelled */ 693 694 /* VE_DAPROM: not modelled */ 695 696 /* Create mmio transports, so the user can create virtio backends 697 * (which will be automatically plugged in to the transports). If 698 * no backend is created the transport will just sit harmlessly idle. 699 */ 700 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 701 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 702 pic[40 + i]); 703 } 704 705 daughterboard->bootinfo.ram_size = machine->ram_size; 706 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 707 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 708 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 709 daughterboard->bootinfo.nb_cpus = smp_cpus; 710 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 711 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 712 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 713 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 714 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 715 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 716 /* When booting Linux we should be in secure state if the CPU has one. */ 717 daughterboard->bootinfo.secure_boot = vms->secure; 718 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 719 } 720 721 static bool vexpress_get_secure(Object *obj, Error **errp) 722 { 723 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 724 725 return vms->secure; 726 } 727 728 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 729 { 730 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 731 732 vms->secure = value; 733 } 734 735 static bool vexpress_get_virt(Object *obj, Error **errp) 736 { 737 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 738 739 return vms->virt; 740 } 741 742 static void vexpress_set_virt(Object *obj, bool value, Error **errp) 743 { 744 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 745 746 vms->virt = value; 747 } 748 749 static void vexpress_instance_init(Object *obj) 750 { 751 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 752 753 /* EL3 is enabled by default on vexpress */ 754 vms->secure = true; 755 object_property_add_bool(obj, "secure", vexpress_get_secure, 756 vexpress_set_secure, NULL); 757 object_property_set_description(obj, "secure", 758 "Set on/off to enable/disable the ARM " 759 "Security Extensions (TrustZone)", 760 NULL); 761 } 762 763 static void vexpress_a15_instance_init(Object *obj) 764 { 765 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 766 767 /* 768 * For the vexpress-a15, EL2 is by default enabled if EL3 is, 769 * but can also be specifically set to on or off. 770 */ 771 vms->virt = true; 772 object_property_add_bool(obj, "virtualization", vexpress_get_virt, 773 vexpress_set_virt, NULL); 774 object_property_set_description(obj, "virtualization", 775 "Set on/off to enable/disable the ARM " 776 "Virtualization Extensions " 777 "(defaults to same as 'secure')", 778 NULL); 779 } 780 781 static void vexpress_a9_instance_init(Object *obj) 782 { 783 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 784 785 /* The A9 doesn't have the virt extensions */ 786 vms->virt = false; 787 } 788 789 static void vexpress_class_init(ObjectClass *oc, void *data) 790 { 791 MachineClass *mc = MACHINE_CLASS(oc); 792 793 mc->desc = "ARM Versatile Express"; 794 mc->init = vexpress_common_init; 795 mc->max_cpus = 4; 796 mc->ignore_memory_transaction_failures = true; 797 } 798 799 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 800 { 801 MachineClass *mc = MACHINE_CLASS(oc); 802 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 803 804 mc->desc = "ARM Versatile Express for Cortex-A9"; 805 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 806 807 vmc->daughterboard = &a9_daughterboard; 808 } 809 810 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 811 { 812 MachineClass *mc = MACHINE_CLASS(oc); 813 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 814 815 mc->desc = "ARM Versatile Express for Cortex-A15"; 816 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 817 818 vmc->daughterboard = &a15_daughterboard; 819 } 820 821 static const TypeInfo vexpress_info = { 822 .name = TYPE_VEXPRESS_MACHINE, 823 .parent = TYPE_MACHINE, 824 .abstract = true, 825 .instance_size = sizeof(VexpressMachineState), 826 .instance_init = vexpress_instance_init, 827 .class_size = sizeof(VexpressMachineClass), 828 .class_init = vexpress_class_init, 829 }; 830 831 static const TypeInfo vexpress_a9_info = { 832 .name = TYPE_VEXPRESS_A9_MACHINE, 833 .parent = TYPE_VEXPRESS_MACHINE, 834 .class_init = vexpress_a9_class_init, 835 .instance_init = vexpress_a9_instance_init, 836 }; 837 838 static const TypeInfo vexpress_a15_info = { 839 .name = TYPE_VEXPRESS_A15_MACHINE, 840 .parent = TYPE_VEXPRESS_MACHINE, 841 .class_init = vexpress_a15_class_init, 842 .instance_init = vexpress_a15_instance_init, 843 }; 844 845 static void vexpress_machine_init(void) 846 { 847 type_register_static(&vexpress_info); 848 type_register_static(&vexpress_a9_info); 849 type_register_static(&vexpress_a15_info); 850 } 851 852 type_init(vexpress_machine_init); 853