1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "hw/sysbus.h" 25 #include "hw/arm/arm.h" 26 #include "hw/arm/primecell.h" 27 #include "hw/devices.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/blockdev.h" 34 #include "hw/block/flash.h" 35 #include "sysemu/device_tree.h" 36 #include "qemu/error-report.h" 37 #include <libfdt.h> 38 39 #define VEXPRESS_BOARD_ID 0x8e0 40 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 41 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 42 43 /* Number of virtio transports to create (0..8; limited by 44 * number of available IRQ lines). 45 */ 46 #define NUM_VIRTIO_TRANSPORTS 4 47 48 /* Address maps for peripherals: 49 * the Versatile Express motherboard has two possible maps, 50 * the "legacy" one (used for A9) and the "Cortex-A Series" 51 * map (used for newer cores). 52 * Individual daughterboards can also have different maps for 53 * their peripherals. 54 */ 55 56 enum { 57 VE_SYSREGS, 58 VE_SP810, 59 VE_SERIALPCI, 60 VE_PL041, 61 VE_MMCI, 62 VE_KMI0, 63 VE_KMI1, 64 VE_UART0, 65 VE_UART1, 66 VE_UART2, 67 VE_UART3, 68 VE_WDT, 69 VE_TIMER01, 70 VE_TIMER23, 71 VE_SERIALDVI, 72 VE_RTC, 73 VE_COMPACTFLASH, 74 VE_CLCD, 75 VE_NORFLASH0, 76 VE_NORFLASH1, 77 VE_NORFLASHALIAS, 78 VE_SRAM, 79 VE_VIDEORAM, 80 VE_ETHERNET, 81 VE_USB, 82 VE_DAPROM, 83 VE_VIRTIO, 84 }; 85 86 static hwaddr motherboard_legacy_map[] = { 87 [VE_NORFLASHALIAS] = 0, 88 /* CS7: 0x10000000 .. 0x10020000 */ 89 [VE_SYSREGS] = 0x10000000, 90 [VE_SP810] = 0x10001000, 91 [VE_SERIALPCI] = 0x10002000, 92 [VE_PL041] = 0x10004000, 93 [VE_MMCI] = 0x10005000, 94 [VE_KMI0] = 0x10006000, 95 [VE_KMI1] = 0x10007000, 96 [VE_UART0] = 0x10009000, 97 [VE_UART1] = 0x1000a000, 98 [VE_UART2] = 0x1000b000, 99 [VE_UART3] = 0x1000c000, 100 [VE_WDT] = 0x1000f000, 101 [VE_TIMER01] = 0x10011000, 102 [VE_TIMER23] = 0x10012000, 103 [VE_VIRTIO] = 0x10013000, 104 [VE_SERIALDVI] = 0x10016000, 105 [VE_RTC] = 0x10017000, 106 [VE_COMPACTFLASH] = 0x1001a000, 107 [VE_CLCD] = 0x1001f000, 108 /* CS0: 0x40000000 .. 0x44000000 */ 109 [VE_NORFLASH0] = 0x40000000, 110 /* CS1: 0x44000000 .. 0x48000000 */ 111 [VE_NORFLASH1] = 0x44000000, 112 /* CS2: 0x48000000 .. 0x4a000000 */ 113 [VE_SRAM] = 0x48000000, 114 /* CS3: 0x4c000000 .. 0x50000000 */ 115 [VE_VIDEORAM] = 0x4c000000, 116 [VE_ETHERNET] = 0x4e000000, 117 [VE_USB] = 0x4f000000, 118 }; 119 120 static hwaddr motherboard_aseries_map[] = { 121 [VE_NORFLASHALIAS] = 0, 122 /* CS0: 0x08000000 .. 0x0c000000 */ 123 [VE_NORFLASH0] = 0x08000000, 124 /* CS4: 0x0c000000 .. 0x10000000 */ 125 [VE_NORFLASH1] = 0x0c000000, 126 /* CS5: 0x10000000 .. 0x14000000 */ 127 /* CS1: 0x14000000 .. 0x18000000 */ 128 [VE_SRAM] = 0x14000000, 129 /* CS2: 0x18000000 .. 0x1c000000 */ 130 [VE_VIDEORAM] = 0x18000000, 131 [VE_ETHERNET] = 0x1a000000, 132 [VE_USB] = 0x1b000000, 133 /* CS3: 0x1c000000 .. 0x20000000 */ 134 [VE_DAPROM] = 0x1c000000, 135 [VE_SYSREGS] = 0x1c010000, 136 [VE_SP810] = 0x1c020000, 137 [VE_SERIALPCI] = 0x1c030000, 138 [VE_PL041] = 0x1c040000, 139 [VE_MMCI] = 0x1c050000, 140 [VE_KMI0] = 0x1c060000, 141 [VE_KMI1] = 0x1c070000, 142 [VE_UART0] = 0x1c090000, 143 [VE_UART1] = 0x1c0a0000, 144 [VE_UART2] = 0x1c0b0000, 145 [VE_UART3] = 0x1c0c0000, 146 [VE_WDT] = 0x1c0f0000, 147 [VE_TIMER01] = 0x1c110000, 148 [VE_TIMER23] = 0x1c120000, 149 [VE_VIRTIO] = 0x1c130000, 150 [VE_SERIALDVI] = 0x1c160000, 151 [VE_RTC] = 0x1c170000, 152 [VE_COMPACTFLASH] = 0x1c1a0000, 153 [VE_CLCD] = 0x1c1f0000, 154 }; 155 156 /* Structure defining the peculiarities of a specific daughterboard */ 157 158 typedef struct VEDBoardInfo VEDBoardInfo; 159 160 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, 161 ram_addr_t ram_size, 162 const char *cpu_model, 163 qemu_irq *pic); 164 165 struct VEDBoardInfo { 166 struct arm_boot_info bootinfo; 167 const hwaddr *motherboard_map; 168 hwaddr loader_start; 169 const hwaddr gic_cpu_if_addr; 170 uint32_t proc_id; 171 uint32_t num_voltage_sensors; 172 const uint32_t *voltages; 173 uint32_t num_clocks; 174 const uint32_t *clocks; 175 DBoardInitFn *init; 176 }; 177 178 static void init_cpus(const char *cpu_model, const char *privdev, 179 hwaddr periphbase, qemu_irq *pic) 180 { 181 ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 182 DeviceState *dev; 183 SysBusDevice *busdev; 184 int n; 185 186 if (!cpu_oc) { 187 fprintf(stderr, "Unable to find CPU definition\n"); 188 exit(1); 189 } 190 191 /* Create the actual CPUs */ 192 for (n = 0; n < smp_cpus; n++) { 193 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 194 Error *err = NULL; 195 196 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 197 object_property_set_int(cpuobj, periphbase, 198 "reset-cbar", &error_abort); 199 } 200 object_property_set_bool(cpuobj, true, "realized", &err); 201 if (err) { 202 error_report("%s", error_get_pretty(err)); 203 exit(1); 204 } 205 } 206 207 /* Create the private peripheral devices (including the GIC); 208 * this must happen after the CPUs are created because a15mpcore_priv 209 * wires itself up to the CPU's generic_timer gpio out lines. 210 */ 211 dev = qdev_create(NULL, privdev); 212 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 213 qdev_init_nofail(dev); 214 busdev = SYS_BUS_DEVICE(dev); 215 sysbus_mmio_map(busdev, 0, periphbase); 216 217 /* Interrupts [42:0] are from the motherboard; 218 * [47:43] are reserved; [63:48] are daughterboard 219 * peripherals. Note that some documentation numbers 220 * external interrupts starting from 32 (because there 221 * are internal interrupts 0..31). 222 */ 223 for (n = 0; n < 64; n++) { 224 pic[n] = qdev_get_gpio_in(dev, n); 225 } 226 227 /* Connect the CPUs to the GIC */ 228 for (n = 0; n < smp_cpus; n++) { 229 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 230 231 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 232 } 233 } 234 235 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, 236 ram_addr_t ram_size, 237 const char *cpu_model, 238 qemu_irq *pic) 239 { 240 MemoryRegion *sysmem = get_system_memory(); 241 MemoryRegion *ram = g_new(MemoryRegion, 1); 242 MemoryRegion *lowram = g_new(MemoryRegion, 1); 243 ram_addr_t low_ram_size; 244 245 if (!cpu_model) { 246 cpu_model = "cortex-a9"; 247 } 248 249 if (ram_size > 0x40000000) { 250 /* 1GB is the maximum the address space permits */ 251 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 252 exit(1); 253 } 254 255 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); 256 vmstate_register_ram_global(ram); 257 low_ram_size = ram_size; 258 if (low_ram_size > 0x4000000) { 259 low_ram_size = 0x4000000; 260 } 261 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 262 * address space should in theory be remappable to various 263 * things including ROM or RAM; we always map the RAM there. 264 */ 265 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 266 memory_region_add_subregion(sysmem, 0x0, lowram); 267 memory_region_add_subregion(sysmem, 0x60000000, ram); 268 269 /* 0x1e000000 A9MPCore (SCU) private memory region */ 270 init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); 271 272 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 273 274 /* 0x10020000 PL111 CLCD (daughterboard) */ 275 sysbus_create_simple("pl111", 0x10020000, pic[44]); 276 277 /* 0x10060000 AXI RAM */ 278 /* 0x100e0000 PL341 Dynamic Memory Controller */ 279 /* 0x100e1000 PL354 Static Memory Controller */ 280 /* 0x100e2000 System Configuration Controller */ 281 282 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 283 /* 0x100e5000 SP805 Watchdog module */ 284 /* 0x100e6000 BP147 TrustZone Protection Controller */ 285 /* 0x100e9000 PL301 'Fast' AXI matrix */ 286 /* 0x100ea000 PL301 'Slow' AXI matrix */ 287 /* 0x100ec000 TrustZone Address Space Controller */ 288 /* 0x10200000 CoreSight debug APB */ 289 /* 0x1e00a000 PL310 L2 Cache Controller */ 290 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 291 } 292 293 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 294 * values are in microvolts. 295 */ 296 static const uint32_t a9_voltages[] = { 297 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 298 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 299 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 300 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 301 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 302 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 303 }; 304 305 /* Reset values for daughterboard oscillators (in Hz) */ 306 static const uint32_t a9_clocks[] = { 307 45000000, /* AMBA AXI ACLK: 45MHz */ 308 23750000, /* daughterboard CLCD clock: 23.75MHz */ 309 66670000, /* Test chip reference clock: 66.67MHz */ 310 }; 311 312 static VEDBoardInfo a9_daughterboard = { 313 .motherboard_map = motherboard_legacy_map, 314 .loader_start = 0x60000000, 315 .gic_cpu_if_addr = 0x1e000100, 316 .proc_id = 0x0c000191, 317 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 318 .voltages = a9_voltages, 319 .num_clocks = ARRAY_SIZE(a9_clocks), 320 .clocks = a9_clocks, 321 .init = a9_daughterboard_init, 322 }; 323 324 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, 325 ram_addr_t ram_size, 326 const char *cpu_model, 327 qemu_irq *pic) 328 { 329 MemoryRegion *sysmem = get_system_memory(); 330 MemoryRegion *ram = g_new(MemoryRegion, 1); 331 MemoryRegion *sram = g_new(MemoryRegion, 1); 332 333 if (!cpu_model) { 334 cpu_model = "cortex-a15"; 335 } 336 337 { 338 /* We have to use a separate 64 bit variable here to avoid the gcc 339 * "comparison is always false due to limited range of data type" 340 * warning if we are on a host where ram_addr_t is 32 bits. 341 */ 342 uint64_t rsz = ram_size; 343 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 344 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 345 exit(1); 346 } 347 } 348 349 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); 350 vmstate_register_ram_global(ram); 351 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 352 memory_region_add_subregion(sysmem, 0x80000000, ram); 353 354 /* 0x2c000000 A15MPCore private memory region (GIC) */ 355 init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); 356 357 /* A15 daughterboard peripherals: */ 358 359 /* 0x20000000: CoreSight interfaces: not modelled */ 360 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 361 /* 0x2a420000: SCC: not modelled */ 362 /* 0x2a430000: system counter: not modelled */ 363 /* 0x2b000000: HDLCD controller: not modelled */ 364 /* 0x2b060000: SP805 watchdog: not modelled */ 365 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 366 /* 0x2e000000: system SRAM */ 367 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000); 368 vmstate_register_ram_global(sram); 369 memory_region_add_subregion(sysmem, 0x2e000000, sram); 370 371 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 372 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 373 } 374 375 static const uint32_t a15_voltages[] = { 376 900000, /* Vcore: 0.9V : CPU core voltage */ 377 }; 378 379 static const uint32_t a15_clocks[] = { 380 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 381 0, /* OSCCLK1: reserved */ 382 0, /* OSCCLK2: reserved */ 383 0, /* OSCCLK3: reserved */ 384 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 385 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 386 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 387 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 388 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 389 }; 390 391 static VEDBoardInfo a15_daughterboard = { 392 .motherboard_map = motherboard_aseries_map, 393 .loader_start = 0x80000000, 394 .gic_cpu_if_addr = 0x2c002000, 395 .proc_id = 0x14000237, 396 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 397 .voltages = a15_voltages, 398 .num_clocks = ARRAY_SIZE(a15_clocks), 399 .clocks = a15_clocks, 400 .init = a15_daughterboard_init, 401 }; 402 403 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 404 hwaddr addr, hwaddr size, uint32_t intc, 405 int irq) 406 { 407 /* Add a virtio_mmio node to the device tree blob: 408 * virtio_mmio@ADDRESS { 409 * compatible = "virtio,mmio"; 410 * reg = <ADDRESS, SIZE>; 411 * interrupt-parent = <&intc>; 412 * interrupts = <0, irq, 1>; 413 * } 414 * (Note that the format of the interrupts property is dependent on the 415 * interrupt controller that interrupt-parent points to; these are for 416 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 417 */ 418 int rc; 419 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 420 421 rc = qemu_fdt_add_subnode(fdt, nodename); 422 rc |= qemu_fdt_setprop_string(fdt, nodename, 423 "compatible", "virtio,mmio"); 424 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 425 acells, addr, scells, size); 426 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 427 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 428 g_free(nodename); 429 if (rc) { 430 return -1; 431 } 432 return 0; 433 } 434 435 static uint32_t find_int_controller(void *fdt) 436 { 437 /* Find the FDT node corresponding to the interrupt controller 438 * for virtio-mmio devices. We do this by scanning the fdt for 439 * a node with the right compatibility, since we know there is 440 * only one GIC on a vexpress board. 441 * We return the phandle of the node, or 0 if none was found. 442 */ 443 const char *compat = "arm,cortex-a9-gic"; 444 int offset; 445 446 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 447 if (offset >= 0) { 448 return fdt_get_phandle(fdt, offset); 449 } 450 return 0; 451 } 452 453 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 454 { 455 uint32_t acells, scells, intc; 456 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 457 458 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells"); 459 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells"); 460 intc = find_int_controller(fdt); 461 if (!intc) { 462 /* Not fatal, we just won't provide virtio. This will 463 * happen with older device tree blobs. 464 */ 465 fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 466 "dtb; will not include virtio-mmio devices in the dtb.\n"); 467 } else { 468 int i; 469 const hwaddr *map = daughterboard->motherboard_map; 470 471 /* We iterate backwards here because adding nodes 472 * to the dtb puts them in last-first. 473 */ 474 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 475 add_virtio_mmio_node(fdt, acells, scells, 476 map[VE_VIRTIO] + 0x200 * i, 477 0x200, intc, 40 + i); 478 } 479 } 480 } 481 482 483 /* Open code a private version of pflash registration since we 484 * need to set non-default device width for VExpress platform. 485 */ 486 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 487 DriveInfo *di) 488 { 489 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 490 491 if (di && qdev_prop_set_drive(dev, "drive", di->bdrv)) { 492 abort(); 493 } 494 495 qdev_prop_set_uint32(dev, "num-blocks", 496 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 497 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 498 qdev_prop_set_uint8(dev, "width", 4); 499 qdev_prop_set_uint8(dev, "device-width", 2); 500 qdev_prop_set_uint8(dev, "big-endian", 0); 501 qdev_prop_set_uint16(dev, "id0", 0x89); 502 qdev_prop_set_uint16(dev, "id1", 0x18); 503 qdev_prop_set_uint16(dev, "id2", 0x00); 504 qdev_prop_set_uint16(dev, "id3", 0x00); 505 qdev_prop_set_string(dev, "name", name); 506 qdev_init_nofail(dev); 507 508 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 509 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 510 } 511 512 static void vexpress_common_init(VEDBoardInfo *daughterboard, 513 MachineState *machine) 514 { 515 DeviceState *dev, *sysctl, *pl041; 516 qemu_irq pic[64]; 517 uint32_t sys_id; 518 DriveInfo *dinfo; 519 pflash_t *pflash0; 520 ram_addr_t vram_size, sram_size; 521 MemoryRegion *sysmem = get_system_memory(); 522 MemoryRegion *vram = g_new(MemoryRegion, 1); 523 MemoryRegion *sram = g_new(MemoryRegion, 1); 524 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 525 MemoryRegion *flash0mem; 526 const hwaddr *map = daughterboard->motherboard_map; 527 int i; 528 529 daughterboard->init(daughterboard, machine->ram_size, machine->cpu_model, 530 pic); 531 532 /* 533 * If a bios file was provided, attempt to map it into memory 534 */ 535 if (bios_name) { 536 const char *fn; 537 538 if (drive_get(IF_PFLASH, 0, 0)) { 539 error_report("The contents of the first flash device may be " 540 "specified with -bios or with -drive if=pflash... " 541 "but you cannot use both options at once"); 542 exit(1); 543 } 544 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 545 if (!fn || load_image_targphys(fn, map[VE_NORFLASH0], 546 VEXPRESS_FLASH_SIZE) < 0) { 547 error_report("Could not load ROM image '%s'", bios_name); 548 exit(1); 549 } 550 } 551 552 /* Motherboard peripherals: the wiring is the same but the 553 * addresses vary between the legacy and A-Series memory maps. 554 */ 555 556 sys_id = 0x1190f500; 557 558 sysctl = qdev_create(NULL, "realview_sysctl"); 559 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 560 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 561 qdev_prop_set_uint32(sysctl, "len-db-voltage", 562 daughterboard->num_voltage_sensors); 563 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 564 char *propname = g_strdup_printf("db-voltage[%d]", i); 565 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 566 g_free(propname); 567 } 568 qdev_prop_set_uint32(sysctl, "len-db-clock", 569 daughterboard->num_clocks); 570 for (i = 0; i < daughterboard->num_clocks; i++) { 571 char *propname = g_strdup_printf("db-clock[%d]", i); 572 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 573 g_free(propname); 574 } 575 qdev_init_nofail(sysctl); 576 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 577 578 /* VE_SP810: not modelled */ 579 /* VE_SERIALPCI: not modelled */ 580 581 pl041 = qdev_create(NULL, "pl041"); 582 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 583 qdev_init_nofail(pl041); 584 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 585 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 586 587 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 588 /* Wire up MMC card detect and read-only signals */ 589 qdev_connect_gpio_out(dev, 0, 590 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 591 qdev_connect_gpio_out(dev, 1, 592 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 593 594 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 595 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 596 597 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 598 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 599 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 600 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 601 602 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 603 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 604 605 /* VE_SERIALDVI: not modelled */ 606 607 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 608 609 /* VE_COMPACTFLASH: not modelled */ 610 611 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 612 613 dinfo = drive_get_next(IF_PFLASH); 614 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 615 dinfo); 616 if (!pflash0) { 617 fprintf(stderr, "vexpress: error registering flash 0.\n"); 618 exit(1); 619 } 620 621 if (map[VE_NORFLASHALIAS] != -1) { 622 /* Map flash 0 as an alias into low memory */ 623 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 624 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 625 flash0mem, 0, VEXPRESS_FLASH_SIZE); 626 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 627 } 628 629 dinfo = drive_get_next(IF_PFLASH); 630 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 631 dinfo)) { 632 fprintf(stderr, "vexpress: error registering flash 1.\n"); 633 exit(1); 634 } 635 636 sram_size = 0x2000000; 637 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size); 638 vmstate_register_ram_global(sram); 639 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 640 641 vram_size = 0x800000; 642 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size); 643 vmstate_register_ram_global(vram); 644 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 645 646 /* 0x4e000000 LAN9118 Ethernet */ 647 if (nd_table[0].used) { 648 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 649 } 650 651 /* VE_USB: not modelled */ 652 653 /* VE_DAPROM: not modelled */ 654 655 /* Create mmio transports, so the user can create virtio backends 656 * (which will be automatically plugged in to the transports). If 657 * no backend is created the transport will just sit harmlessly idle. 658 */ 659 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 660 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 661 pic[40 + i]); 662 } 663 664 daughterboard->bootinfo.ram_size = machine->ram_size; 665 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 666 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 667 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 668 daughterboard->bootinfo.nb_cpus = smp_cpus; 669 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 670 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 671 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 672 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 673 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 674 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 675 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 676 } 677 678 static void vexpress_a9_init(MachineState *machine) 679 { 680 vexpress_common_init(&a9_daughterboard, machine); 681 } 682 683 static void vexpress_a15_init(MachineState *machine) 684 { 685 vexpress_common_init(&a15_daughterboard, machine); 686 } 687 688 static QEMUMachine vexpress_a9_machine = { 689 .name = "vexpress-a9", 690 .desc = "ARM Versatile Express for Cortex-A9", 691 .init = vexpress_a9_init, 692 .block_default_type = IF_SCSI, 693 .max_cpus = 4, 694 }; 695 696 static QEMUMachine vexpress_a15_machine = { 697 .name = "vexpress-a15", 698 .desc = "ARM Versatile Express for Cortex-A15", 699 .init = vexpress_a15_init, 700 .block_default_type = IF_SCSI, 701 .max_cpus = 4, 702 }; 703 704 static void vexpress_machine_init(void) 705 { 706 qemu_register_machine(&vexpress_a9_machine); 707 qemu_register_machine(&vexpress_a15_machine); 708 } 709 710 machine_init(vexpress_machine_init); 711