1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu-common.h" 32 #include "qemu/bitmap.h" 33 #include "trace.h" 34 #include "qom/cpu.h" 35 #include "target/arm/cpu.h" 36 #include "hw/acpi/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/loader.h" 41 #include "hw/hw.h" 42 #include "hw/acpi/aml-build.h" 43 #include "hw/pci/pcie_host.h" 44 #include "hw/pci/pci.h" 45 #include "hw/arm/virt.h" 46 #include "sysemu/numa.h" 47 #include "kvm_arm.h" 48 49 #define ARM_SPI_BASE 32 50 #define ACPI_POWER_BUTTON_DEVICE "PWRB" 51 52 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 53 { 54 uint16_t i; 55 56 for (i = 0; i < smp_cpus; i++) { 57 Aml *dev = aml_device("C%.03X", i); 58 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 59 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 60 aml_append(scope, dev); 61 } 62 } 63 64 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 65 uint32_t uart_irq) 66 { 67 Aml *dev = aml_device("COM0"); 68 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 69 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 70 71 Aml *crs = aml_resource_template(); 72 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 73 uart_memmap->size, AML_READ_WRITE)); 74 aml_append(crs, 75 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 76 AML_EXCLUSIVE, &uart_irq, 1)); 77 aml_append(dev, aml_name_decl("_CRS", crs)); 78 79 /* The _ADR entry is used to link this device to the UART described 80 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 81 */ 82 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 83 84 aml_append(scope, dev); 85 } 86 87 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 88 { 89 Aml *dev = aml_device("FWCF"); 90 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 91 /* device present, functioning, decoding, not shown in UI */ 92 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 93 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 94 95 Aml *crs = aml_resource_template(); 96 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 97 fw_cfg_memmap->size, AML_READ_WRITE)); 98 aml_append(dev, aml_name_decl("_CRS", crs)); 99 aml_append(scope, dev); 100 } 101 102 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 103 { 104 Aml *dev, *crs; 105 hwaddr base = flash_memmap->base; 106 hwaddr size = flash_memmap->size / 2; 107 108 dev = aml_device("FLS0"); 109 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 110 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 111 112 crs = aml_resource_template(); 113 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 114 aml_append(dev, aml_name_decl("_CRS", crs)); 115 aml_append(scope, dev); 116 117 dev = aml_device("FLS1"); 118 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 119 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 120 crs = aml_resource_template(); 121 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 122 aml_append(dev, aml_name_decl("_CRS", crs)); 123 aml_append(scope, dev); 124 } 125 126 static void acpi_dsdt_add_virtio(Aml *scope, 127 const MemMapEntry *virtio_mmio_memmap, 128 uint32_t mmio_irq, int num) 129 { 130 hwaddr base = virtio_mmio_memmap->base; 131 hwaddr size = virtio_mmio_memmap->size; 132 int i; 133 134 for (i = 0; i < num; i++) { 135 uint32_t irq = mmio_irq + i; 136 Aml *dev = aml_device("VR%02u", i); 137 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 138 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 139 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 140 141 Aml *crs = aml_resource_template(); 142 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 143 aml_append(crs, 144 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 145 AML_EXCLUSIVE, &irq, 1)); 146 aml_append(dev, aml_name_decl("_CRS", crs)); 147 aml_append(scope, dev); 148 base += size; 149 } 150 } 151 152 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 153 uint32_t irq, bool use_highmem) 154 { 155 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 156 int i, bus_no; 157 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 158 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 159 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 160 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 161 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 162 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 163 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 164 165 Aml *dev = aml_device("%s", "PCI0"); 166 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 167 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 168 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 169 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 170 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 171 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 172 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 173 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 174 175 /* Declare the PCI Routing Table. */ 176 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 177 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 178 for (i = 0; i < PCI_NUM_PINS; i++) { 179 int gsi = (i + bus_no) % PCI_NUM_PINS; 180 Aml *pkg = aml_package(4); 181 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 182 aml_append(pkg, aml_int(i)); 183 aml_append(pkg, aml_name("GSI%d", gsi)); 184 aml_append(pkg, aml_int(0)); 185 aml_append(rt_pkg, pkg); 186 } 187 } 188 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 189 190 /* Create GSI link device */ 191 for (i = 0; i < PCI_NUM_PINS; i++) { 192 uint32_t irqs = irq + i; 193 Aml *dev_gsi = aml_device("GSI%d", i); 194 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 195 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 196 crs = aml_resource_template(); 197 aml_append(crs, 198 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 199 AML_EXCLUSIVE, &irqs, 1)); 200 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 201 crs = aml_resource_template(); 202 aml_append(crs, 203 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 204 AML_EXCLUSIVE, &irqs, 1)); 205 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 206 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 207 aml_append(dev_gsi, method); 208 aml_append(dev, dev_gsi); 209 } 210 211 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 212 aml_append(method, aml_return(aml_int(base_ecam))); 213 aml_append(dev, method); 214 215 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 216 Aml *rbuf = aml_resource_template(); 217 aml_append(rbuf, 218 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 219 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 220 nr_pcie_buses)); 221 aml_append(rbuf, 222 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 223 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 224 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 225 aml_append(rbuf, 226 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 227 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 228 size_pio)); 229 230 if (use_highmem) { 231 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 232 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 233 234 aml_append(rbuf, 235 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 236 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 237 base_mmio_high, 238 base_mmio_high + size_mmio_high - 1, 0x0000, 239 size_mmio_high)); 240 } 241 242 aml_append(method, aml_name_decl("RBUF", rbuf)); 243 aml_append(method, aml_return(rbuf)); 244 aml_append(dev, method); 245 246 /* Declare an _OSC (OS Control Handoff) method */ 247 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 248 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 249 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 250 aml_append(method, 251 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 252 253 /* PCI Firmware Specification 3.0 254 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 255 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 256 * identified by the Universal Unique IDentifier (UUID) 257 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 258 */ 259 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 260 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 261 aml_append(ifctx, 262 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 263 aml_append(ifctx, 264 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 265 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 266 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 267 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), 268 aml_name("CTRL"))); 269 270 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 271 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), 272 aml_name("CDW1"))); 273 aml_append(ifctx, ifctx1); 274 275 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 276 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), 277 aml_name("CDW1"))); 278 aml_append(ifctx, ifctx1); 279 280 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 281 aml_append(ifctx, aml_return(aml_arg(3))); 282 aml_append(method, ifctx); 283 284 elsectx = aml_else(); 285 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), 286 aml_name("CDW1"))); 287 aml_append(elsectx, aml_return(aml_arg(3))); 288 aml_append(method, elsectx); 289 aml_append(dev, method); 290 291 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 292 293 /* PCI Firmware Specification 3.0 294 * 4.6.1. _DSM for PCI Express Slot Information 295 * The UUID in _DSM in this context is 296 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 297 */ 298 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 299 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 300 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 301 uint8_t byte_list[1] = {1}; 302 buf = aml_buffer(1, byte_list); 303 aml_append(ifctx1, aml_return(buf)); 304 aml_append(ifctx, ifctx1); 305 aml_append(method, ifctx); 306 307 byte_list[0] = 0; 308 buf = aml_buffer(1, byte_list); 309 aml_append(method, aml_return(buf)); 310 aml_append(dev, method); 311 312 Aml *dev_rp0 = aml_device("%s", "RP0"); 313 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 314 aml_append(dev, dev_rp0); 315 316 Aml *dev_res0 = aml_device("%s", "RES0"); 317 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 318 crs = aml_resource_template(); 319 aml_append(crs, aml_memory32_fixed(base_ecam, size_ecam, AML_READ_WRITE)); 320 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 321 aml_append(dev, dev_res0); 322 aml_append(scope, dev); 323 } 324 325 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 326 uint32_t gpio_irq) 327 { 328 Aml *dev = aml_device("GPO0"); 329 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 330 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 331 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 332 333 Aml *crs = aml_resource_template(); 334 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 335 AML_READ_WRITE)); 336 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 337 AML_EXCLUSIVE, &gpio_irq, 1)); 338 aml_append(dev, aml_name_decl("_CRS", crs)); 339 340 Aml *aei = aml_resource_template(); 341 /* Pin 3 for power button */ 342 const uint32_t pin_list[1] = {3}; 343 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 344 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 345 "GPO0", NULL, 0)); 346 aml_append(dev, aml_name_decl("_AEI", aei)); 347 348 /* _E03 is handle for power button */ 349 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 350 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 351 aml_int(0x80))); 352 aml_append(dev, method); 353 aml_append(scope, dev); 354 } 355 356 static void acpi_dsdt_add_power_button(Aml *scope) 357 { 358 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 359 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 360 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 361 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 362 aml_append(scope, dev); 363 } 364 365 /* RSDP */ 366 static GArray * 367 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned xsdt_tbl_offset) 368 { 369 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 370 unsigned xsdt_pa_size = sizeof(rsdp->xsdt_physical_address); 371 unsigned xsdt_pa_offset = 372 (char *)&rsdp->xsdt_physical_address - rsdp_table->data; 373 374 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16, 375 true /* fseg memory */); 376 377 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 378 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 379 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 380 rsdp->revision = 0x02; 381 382 /* Address to be filled by Guest linker */ 383 bios_linker_loader_add_pointer(linker, 384 ACPI_BUILD_RSDP_FILE, xsdt_pa_offset, xsdt_pa_size, 385 ACPI_BUILD_TABLE_FILE, xsdt_tbl_offset); 386 387 /* Checksum to be filled by Guest linker */ 388 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 389 (char *)rsdp - rsdp_table->data, sizeof *rsdp, 390 (char *)&rsdp->checksum - rsdp_table->data); 391 392 return rsdp_table; 393 } 394 395 static void 396 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 397 { 398 int nb_nodes, iort_start = table_data->len; 399 AcpiIortIdMapping *idmap; 400 AcpiIortItsGroup *its; 401 AcpiIortTable *iort; 402 AcpiIortSmmu3 *smmu; 403 size_t node_size, iort_length, smmu_offset = 0; 404 AcpiIortRC *rc; 405 406 iort = acpi_data_push(table_data, sizeof(*iort)); 407 408 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 409 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 410 } else { 411 nb_nodes = 2; /* RC, ITS */ 412 } 413 414 iort_length = sizeof(*iort); 415 iort->node_count = cpu_to_le32(nb_nodes); 416 iort->node_offset = cpu_to_le32(sizeof(*iort)); 417 418 /* ITS group node */ 419 node_size = sizeof(*its) + sizeof(uint32_t); 420 iort_length += node_size; 421 its = acpi_data_push(table_data, node_size); 422 423 its->type = ACPI_IORT_NODE_ITS_GROUP; 424 its->length = cpu_to_le16(node_size); 425 its->its_count = cpu_to_le32(1); 426 its->identifiers[0] = 0; /* MADT translation_id */ 427 428 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 429 int irq = vms->irqmap[VIRT_SMMU]; 430 431 /* SMMUv3 node */ 432 smmu_offset = iort->node_offset + node_size; 433 node_size = sizeof(*smmu) + sizeof(*idmap); 434 iort_length += node_size; 435 smmu = acpi_data_push(table_data, node_size); 436 437 smmu->type = ACPI_IORT_NODE_SMMU_V3; 438 smmu->length = cpu_to_le16(node_size); 439 smmu->mapping_count = cpu_to_le32(1); 440 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 441 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 442 smmu->event_gsiv = cpu_to_le32(irq); 443 smmu->pri_gsiv = cpu_to_le32(irq + 1); 444 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 445 smmu->sync_gsiv = cpu_to_le32(irq + 3); 446 447 /* Identity RID mapping covering the whole input RID range */ 448 idmap = &smmu->id_mapping_array[0]; 449 idmap->input_base = 0; 450 idmap->id_count = cpu_to_le32(0xFFFF); 451 idmap->output_base = 0; 452 /* output IORT node is the ITS group node (the first node) */ 453 idmap->output_reference = cpu_to_le32(iort->node_offset); 454 } 455 456 /* Root Complex Node */ 457 node_size = sizeof(*rc) + sizeof(*idmap); 458 iort_length += node_size; 459 rc = acpi_data_push(table_data, node_size); 460 461 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 462 rc->length = cpu_to_le16(node_size); 463 rc->mapping_count = cpu_to_le32(1); 464 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 465 466 /* fully coherent device */ 467 rc->memory_properties.cache_coherency = cpu_to_le32(1); 468 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 469 rc->pci_segment_number = 0; /* MCFG pci_segment */ 470 471 /* Identity RID mapping covering the whole input RID range */ 472 idmap = &rc->id_mapping_array[0]; 473 idmap->input_base = 0; 474 idmap->id_count = cpu_to_le32(0xFFFF); 475 idmap->output_base = 0; 476 477 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 478 /* output IORT node is the smmuv3 node */ 479 idmap->output_reference = cpu_to_le32(smmu_offset); 480 } else { 481 /* output IORT node is the ITS group node (the first node) */ 482 idmap->output_reference = cpu_to_le32(iort->node_offset); 483 } 484 485 iort->length = cpu_to_le32(iort_length); 486 487 build_header(linker, table_data, (void *)(table_data->data + iort_start), 488 "IORT", table_data->len - iort_start, 0, NULL, NULL); 489 } 490 491 static void 492 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 493 { 494 AcpiSerialPortConsoleRedirection *spcr; 495 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 496 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 497 int spcr_start = table_data->len; 498 499 spcr = acpi_data_push(table_data, sizeof(*spcr)); 500 501 spcr->interface_type = 0x3; /* ARM PL011 UART */ 502 503 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 504 spcr->base_address.bit_width = 8; 505 spcr->base_address.bit_offset = 0; 506 spcr->base_address.access_width = 1; 507 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 508 509 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 510 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 511 512 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 513 spcr->parity = 0; /* No Parity */ 514 spcr->stopbits = 1; /* 1 Stop bit */ 515 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 516 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 517 518 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 519 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 520 521 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 522 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 523 } 524 525 static void 526 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 527 { 528 AcpiSystemResourceAffinityTable *srat; 529 AcpiSratProcessorGiccAffinity *core; 530 AcpiSratMemoryAffinity *numamem; 531 int i, srat_start; 532 uint64_t mem_base; 533 MachineClass *mc = MACHINE_GET_CLASS(vms); 534 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(MACHINE(vms)); 535 536 srat_start = table_data->len; 537 srat = acpi_data_push(table_data, sizeof(*srat)); 538 srat->reserved1 = cpu_to_le32(1); 539 540 for (i = 0; i < cpu_list->len; ++i) { 541 core = acpi_data_push(table_data, sizeof(*core)); 542 core->type = ACPI_SRAT_PROCESSOR_GICC; 543 core->length = sizeof(*core); 544 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 545 core->acpi_processor_uid = cpu_to_le32(i); 546 core->flags = cpu_to_le32(1); 547 } 548 549 mem_base = vms->memmap[VIRT_MEM].base; 550 for (i = 0; i < nb_numa_nodes; ++i) { 551 numamem = acpi_data_push(table_data, sizeof(*numamem)); 552 build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i, 553 MEM_AFFINITY_ENABLED); 554 mem_base += numa_info[i].node_mem; 555 } 556 557 build_header(linker, table_data, (void *)(table_data->data + srat_start), 558 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 559 } 560 561 static void 562 build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 563 { 564 AcpiTableMcfg *mcfg; 565 const MemMapEntry *memmap = vms->memmap; 566 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 567 int mcfg_start = table_data->len; 568 569 mcfg = acpi_data_push(table_data, len); 570 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 571 572 /* Only a single allocation so no need to play with segments */ 573 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 574 mcfg->allocation[0].start_bus_number = 0; 575 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 576 / PCIE_MMCFG_SIZE_MIN) - 1; 577 578 build_header(linker, table_data, (void *)(table_data->data + mcfg_start), 579 "MCFG", table_data->len - mcfg_start, 1, NULL, NULL); 580 } 581 582 /* GTDT */ 583 static void 584 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 585 { 586 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 587 int gtdt_start = table_data->len; 588 AcpiGenericTimerTable *gtdt; 589 uint32_t irqflags; 590 591 if (vmc->claim_edge_triggered_timers) { 592 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 593 } else { 594 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 595 } 596 597 gtdt = acpi_data_push(table_data, sizeof *gtdt); 598 /* The interrupt values are the same with the device tree when adding 16 */ 599 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 600 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 601 602 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 603 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 604 ACPI_GTDT_CAP_ALWAYS_ON); 605 606 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 607 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 608 609 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 610 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 611 612 build_header(linker, table_data, 613 (void *)(table_data->data + gtdt_start), "GTDT", 614 table_data->len - gtdt_start, 2, NULL, NULL); 615 } 616 617 /* MADT */ 618 static void 619 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 620 { 621 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 622 int madt_start = table_data->len; 623 const MemMapEntry *memmap = vms->memmap; 624 const int *irqmap = vms->irqmap; 625 AcpiMultipleApicTable *madt; 626 AcpiMadtGenericDistributor *gicd; 627 AcpiMadtGenericMsiFrame *gic_msi; 628 int i; 629 630 madt = acpi_data_push(table_data, sizeof *madt); 631 632 gicd = acpi_data_push(table_data, sizeof *gicd); 633 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 634 gicd->length = sizeof(*gicd); 635 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 636 gicd->version = vms->gic_version; 637 638 for (i = 0; i < vms->smp_cpus; i++) { 639 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 640 sizeof(*gicc)); 641 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 642 643 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 644 gicc->length = sizeof(*gicc); 645 if (vms->gic_version == 2) { 646 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 647 } 648 gicc->cpu_interface_number = cpu_to_le32(i); 649 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 650 gicc->uid = cpu_to_le32(i); 651 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 652 653 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 654 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 655 } 656 if (vms->virt && vms->gic_version == 3) { 657 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ)); 658 } 659 } 660 661 if (vms->gic_version == 3) { 662 AcpiMadtGenericTranslator *gic_its; 663 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 664 sizeof *gicr); 665 666 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 667 gicr->length = sizeof(*gicr); 668 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 669 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 670 671 if (its_class_name() && !vmc->no_its) { 672 gic_its = acpi_data_push(table_data, sizeof *gic_its); 673 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 674 gic_its->length = sizeof(*gic_its); 675 gic_its->translation_id = 0; 676 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 677 } 678 } else { 679 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 680 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 681 gic_msi->length = sizeof(*gic_msi); 682 gic_msi->gic_msi_frame_id = 0; 683 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 684 gic_msi->flags = cpu_to_le32(1); 685 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 686 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 687 } 688 689 build_header(linker, table_data, 690 (void *)(table_data->data + madt_start), "APIC", 691 table_data->len - madt_start, 3, NULL, NULL); 692 } 693 694 /* FADT */ 695 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 696 VirtMachineState *vms, unsigned dsdt_tbl_offset) 697 { 698 /* ACPI v5.1 */ 699 AcpiFadtData fadt = { 700 .rev = 5, 701 .minor_ver = 1, 702 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 703 .xdsdt_tbl_offset = &dsdt_tbl_offset, 704 }; 705 706 switch (vms->psci_conduit) { 707 case QEMU_PSCI_CONDUIT_DISABLED: 708 fadt.arm_boot_arch = 0; 709 break; 710 case QEMU_PSCI_CONDUIT_HVC: 711 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 712 ACPI_FADT_ARM_PSCI_USE_HVC; 713 break; 714 case QEMU_PSCI_CONDUIT_SMC: 715 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 716 break; 717 default: 718 g_assert_not_reached(); 719 } 720 721 build_fadt(table_data, linker, &fadt, NULL, NULL); 722 } 723 724 /* DSDT */ 725 static void 726 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 727 { 728 Aml *scope, *dsdt; 729 const MemMapEntry *memmap = vms->memmap; 730 const int *irqmap = vms->irqmap; 731 732 dsdt = init_aml_allocator(); 733 /* Reserve space for header */ 734 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 735 736 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 737 * While UEFI can use libfdt to disable the RTC device node in the DTB that 738 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 739 * the RTC ACPI device at all when using UEFI. 740 */ 741 scope = aml_scope("\\_SB"); 742 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 743 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 744 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 745 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 746 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 747 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 748 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 749 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 750 vms->highmem); 751 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 752 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 753 acpi_dsdt_add_power_button(scope); 754 755 aml_append(dsdt, scope); 756 757 /* copy AML table into ACPI tables blob and patch header there */ 758 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 759 build_header(linker, table_data, 760 (void *)(table_data->data + table_data->len - dsdt->buf->len), 761 "DSDT", dsdt->buf->len, 2, NULL, NULL); 762 free_aml_allocator(); 763 } 764 765 typedef 766 struct AcpiBuildState { 767 /* Copy of table in RAM (for patching). */ 768 MemoryRegion *table_mr; 769 MemoryRegion *rsdp_mr; 770 MemoryRegion *linker_mr; 771 /* Is table patched? */ 772 bool patched; 773 } AcpiBuildState; 774 775 static 776 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 777 { 778 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 779 GArray *table_offsets; 780 unsigned dsdt, xsdt; 781 GArray *tables_blob = tables->table_data; 782 783 table_offsets = g_array_new(false, true /* clear */, 784 sizeof(uint32_t)); 785 786 bios_linker_loader_alloc(tables->linker, 787 ACPI_BUILD_TABLE_FILE, tables_blob, 788 64, false /* high memory */); 789 790 /* DSDT is pointed to by FADT */ 791 dsdt = tables_blob->len; 792 build_dsdt(tables_blob, tables->linker, vms); 793 794 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 795 acpi_add_table(table_offsets, tables_blob); 796 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 797 798 acpi_add_table(table_offsets, tables_blob); 799 build_madt(tables_blob, tables->linker, vms); 800 801 acpi_add_table(table_offsets, tables_blob); 802 build_gtdt(tables_blob, tables->linker, vms); 803 804 acpi_add_table(table_offsets, tables_blob); 805 build_mcfg(tables_blob, tables->linker, vms); 806 807 acpi_add_table(table_offsets, tables_blob); 808 build_spcr(tables_blob, tables->linker, vms); 809 810 if (nb_numa_nodes > 0) { 811 acpi_add_table(table_offsets, tables_blob); 812 build_srat(tables_blob, tables->linker, vms); 813 if (have_numa_distance) { 814 acpi_add_table(table_offsets, tables_blob); 815 build_slit(tables_blob, tables->linker); 816 } 817 } 818 819 if (its_class_name() && !vmc->no_its) { 820 acpi_add_table(table_offsets, tables_blob); 821 build_iort(tables_blob, tables->linker, vms); 822 } 823 824 /* XSDT is pointed to by RSDP */ 825 xsdt = tables_blob->len; 826 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 827 828 /* RSDP is in FSEG memory, so allocate it separately */ 829 build_rsdp(tables->rsdp, tables->linker, xsdt); 830 831 /* Cleanup memory that's no longer used. */ 832 g_array_free(table_offsets, true); 833 } 834 835 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 836 { 837 uint32_t size = acpi_data_len(data); 838 839 /* Make sure RAM size is correct - in case it got changed 840 * e.g. by migration */ 841 memory_region_ram_resize(mr, size, &error_abort); 842 843 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 844 memory_region_set_dirty(mr, 0, size); 845 } 846 847 static void virt_acpi_build_update(void *build_opaque) 848 { 849 AcpiBuildState *build_state = build_opaque; 850 AcpiBuildTables tables; 851 852 /* No state to update or already patched? Nothing to do. */ 853 if (!build_state || build_state->patched) { 854 return; 855 } 856 build_state->patched = true; 857 858 acpi_build_tables_init(&tables); 859 860 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 861 862 acpi_ram_update(build_state->table_mr, tables.table_data); 863 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 864 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 865 866 acpi_build_tables_cleanup(&tables, true); 867 } 868 869 static void virt_acpi_build_reset(void *build_opaque) 870 { 871 AcpiBuildState *build_state = build_opaque; 872 build_state->patched = false; 873 } 874 875 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 876 GArray *blob, const char *name, 877 uint64_t max_size) 878 { 879 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 880 name, virt_acpi_build_update, build_state, NULL, true); 881 } 882 883 static const VMStateDescription vmstate_virt_acpi_build = { 884 .name = "virt_acpi_build", 885 .version_id = 1, 886 .minimum_version_id = 1, 887 .fields = (VMStateField[]) { 888 VMSTATE_BOOL(patched, AcpiBuildState), 889 VMSTATE_END_OF_LIST() 890 }, 891 }; 892 893 void virt_acpi_setup(VirtMachineState *vms) 894 { 895 AcpiBuildTables tables; 896 AcpiBuildState *build_state; 897 898 if (!vms->fw_cfg) { 899 trace_virt_acpi_setup(); 900 return; 901 } 902 903 if (!acpi_enabled) { 904 trace_virt_acpi_setup(); 905 return; 906 } 907 908 build_state = g_malloc0(sizeof *build_state); 909 910 acpi_build_tables_init(&tables); 911 virt_acpi_build(vms, &tables); 912 913 /* Now expose it all to Guest */ 914 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 915 ACPI_BUILD_TABLE_FILE, 916 ACPI_BUILD_TABLE_MAX_SIZE); 917 assert(build_state->table_mr != NULL); 918 919 build_state->linker_mr = 920 acpi_add_rom_blob(build_state, tables.linker->cmd_blob, 921 "etc/table-loader", 0); 922 923 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 924 acpi_data_len(tables.tcpalog)); 925 926 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 927 ACPI_BUILD_RSDP_FILE, 0); 928 929 qemu_register_reset(virt_acpi_build_reset, build_state); 930 virt_acpi_build_reset(build_state); 931 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 932 933 /* Cleanup tables but don't free the memory: we track it 934 * in build_state. 935 */ 936 acpi_build_tables_cleanup(&tables, false); 937 } 938