1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/boards.h" 39 #include "hw/arm/boot.h" 40 #include "hw/arm/primecell.h" 41 #include "hw/arm/virt.h" 42 #include "hw/block/flash.h" 43 #include "hw/vfio/vfio-calxeda-xgmac.h" 44 #include "hw/vfio/vfio-amd-xgbe.h" 45 #include "hw/display/ramfb.h" 46 #include "net/net.h" 47 #include "sysemu/device_tree.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "sysemu/tpm.h" 52 #include "sysemu/kvm.h" 53 #include "hw/loader.h" 54 #include "exec/address-spaces.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/arm/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/irq.h" 67 #include "kvm_arm.h" 68 #include "hw/firmware/smbios.h" 69 #include "qapi/visitor.h" 70 #include "qapi/qapi-visit-common.h" 71 #include "standard-headers/linux/input.h" 72 #include "hw/arm/smmuv3.h" 73 #include "hw/acpi/acpi.h" 74 #include "target/arm/internals.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-iommu.h" 79 #include "hw/char/pl011.h" 80 81 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 82 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 83 void *data) \ 84 { \ 85 MachineClass *mc = MACHINE_CLASS(oc); \ 86 virt_machine_##major##_##minor##_options(mc); \ 87 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 88 if (latest) { \ 89 mc->alias = "virt"; \ 90 } \ 91 } \ 92 static const TypeInfo machvirt_##major##_##minor##_info = { \ 93 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 94 .parent = TYPE_VIRT_MACHINE, \ 95 .class_init = virt_##major##_##minor##_class_init, \ 96 }; \ 97 static void machvirt_machine_##major##_##minor##_init(void) \ 98 { \ 99 type_register_static(&machvirt_##major##_##minor##_info); \ 100 } \ 101 type_init(machvirt_machine_##major##_##minor##_init); 102 103 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 104 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 105 #define DEFINE_VIRT_MACHINE(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 107 108 109 /* Number of external interrupt lines to configure the GIC with */ 110 #define NUM_IRQS 256 111 112 #define PLATFORM_BUS_NUM_IRQS 64 113 114 /* Legacy RAM limit in GB (< version 4.0) */ 115 #define LEGACY_RAMLIMIT_GB 255 116 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 117 118 /* Addresses and sizes of our components. 119 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 120 * 128MB..256MB is used for miscellaneous device I/O. 121 * 256MB..1GB is reserved for possible future PCI support (ie where the 122 * PCI memory window will go if we add a PCI host controller). 123 * 1GB and up is RAM (which may happily spill over into the 124 * high memory region beyond 4GB). 125 * This represents a compromise between how much RAM can be given to 126 * a 32 bit VM and leaving space for expansion and in particular for PCI. 127 * Note that devices should generally be placed at multiples of 0x10000, 128 * to accommodate guests using 64K pages. 129 */ 130 static const MemMapEntry base_memmap[] = { 131 /* Space up to 0x8000000 is reserved for a boot ROM */ 132 [VIRT_FLASH] = { 0, 0x08000000 }, 133 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 134 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 135 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 136 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 137 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 138 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 139 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 140 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 141 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 142 /* This redistributor space allows up to 2*64kB*123 CPUs */ 143 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 144 [VIRT_UART] = { 0x09000000, 0x00001000 }, 145 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 146 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 147 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 148 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 149 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 150 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 151 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 152 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 153 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 154 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 155 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 156 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 157 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 158 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 159 /* Actual RAM size depends on initial RAM and device memory settings */ 160 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 161 }; 162 163 /* 164 * Highmem IO Regions: This memory map is floating, located after the RAM. 165 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 166 * top of the RAM, so that its base get the same alignment as the size, 167 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 168 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 169 * Note the extended_memmap is sized so that it eventually also includes the 170 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 171 * index of base_memmap). 172 */ 173 static MemMapEntry extended_memmap[] = { 174 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 175 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 176 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 177 /* Second PCIe window */ 178 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 179 }; 180 181 static const int a15irqmap[] = { 182 [VIRT_UART] = 1, 183 [VIRT_RTC] = 2, 184 [VIRT_PCIE] = 3, /* ... to 6 */ 185 [VIRT_GPIO] = 7, 186 [VIRT_SECURE_UART] = 8, 187 [VIRT_ACPI_GED] = 9, 188 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 189 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 190 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 191 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 192 }; 193 194 static const char *valid_cpus[] = { 195 ARM_CPU_TYPE_NAME("cortex-a7"), 196 ARM_CPU_TYPE_NAME("cortex-a15"), 197 ARM_CPU_TYPE_NAME("cortex-a53"), 198 ARM_CPU_TYPE_NAME("cortex-a57"), 199 ARM_CPU_TYPE_NAME("cortex-a72"), 200 ARM_CPU_TYPE_NAME("host"), 201 ARM_CPU_TYPE_NAME("max"), 202 }; 203 204 static bool cpu_type_valid(const char *cpu) 205 { 206 int i; 207 208 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 209 if (strcmp(cpu, valid_cpus[i]) == 0) { 210 return true; 211 } 212 } 213 return false; 214 } 215 216 static void create_fdt(VirtMachineState *vms) 217 { 218 MachineState *ms = MACHINE(vms); 219 int nb_numa_nodes = ms->numa_state->num_nodes; 220 void *fdt = create_device_tree(&vms->fdt_size); 221 222 if (!fdt) { 223 error_report("create_device_tree() failed"); 224 exit(1); 225 } 226 227 vms->fdt = fdt; 228 229 /* Header */ 230 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 231 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 232 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 233 234 /* /chosen must exist for load_dtb to fill in necessary properties later */ 235 qemu_fdt_add_subnode(fdt, "/chosen"); 236 237 /* Clock node, for the benefit of the UART. The kernel device tree 238 * binding documentation claims the PL011 node clock properties are 239 * optional but in practice if you omit them the kernel refuses to 240 * probe for the device. 241 */ 242 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 243 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 244 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 245 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 246 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 247 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 248 "clk24mhz"); 249 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 250 251 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 252 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 253 uint32_t *matrix = g_malloc0(size); 254 int idx, i, j; 255 256 for (i = 0; i < nb_numa_nodes; i++) { 257 for (j = 0; j < nb_numa_nodes; j++) { 258 idx = (i * nb_numa_nodes + j) * 3; 259 matrix[idx + 0] = cpu_to_be32(i); 260 matrix[idx + 1] = cpu_to_be32(j); 261 matrix[idx + 2] = 262 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 263 } 264 } 265 266 qemu_fdt_add_subnode(fdt, "/distance-map"); 267 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 268 "numa-distance-map-v1"); 269 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 270 matrix, size); 271 g_free(matrix); 272 } 273 } 274 275 static void fdt_add_timer_nodes(const VirtMachineState *vms) 276 { 277 /* On real hardware these interrupts are level-triggered. 278 * On KVM they were edge-triggered before host kernel version 4.4, 279 * and level-triggered afterwards. 280 * On emulated QEMU they are level-triggered. 281 * 282 * Getting the DTB info about them wrong is awkward for some 283 * guest kernels: 284 * pre-4.8 ignore the DT and leave the interrupt configured 285 * with whatever the GIC reset value (or the bootloader) left it at 286 * 4.8 before rc6 honour the incorrect data by programming it back 287 * into the GIC, causing problems 288 * 4.8rc6 and later ignore the DT and always write "level triggered" 289 * into the GIC 290 * 291 * For backwards-compatibility, virt-2.8 and earlier will continue 292 * to say these are edge-triggered, but later machines will report 293 * the correct information. 294 */ 295 ARMCPU *armcpu; 296 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 297 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 298 299 if (vmc->claim_edge_triggered_timers) { 300 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 301 } 302 303 if (vms->gic_version == VIRT_GIC_VERSION_2) { 304 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 305 GIC_FDT_IRQ_PPI_CPU_WIDTH, 306 (1 << vms->smp_cpus) - 1); 307 } 308 309 qemu_fdt_add_subnode(vms->fdt, "/timer"); 310 311 armcpu = ARM_CPU(qemu_get_cpu(0)); 312 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 313 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 314 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 315 compat, sizeof(compat)); 316 } else { 317 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 318 "arm,armv7-timer"); 319 } 320 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 321 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 322 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 323 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 324 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 325 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 326 } 327 328 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 329 { 330 int cpu; 331 int addr_cells = 1; 332 const MachineState *ms = MACHINE(vms); 333 334 /* 335 * From Documentation/devicetree/bindings/arm/cpus.txt 336 * On ARM v8 64-bit systems value should be set to 2, 337 * that corresponds to the MPIDR_EL1 register size. 338 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 339 * in the system, #address-cells can be set to 1, since 340 * MPIDR_EL1[63:32] bits are not used for CPUs 341 * identification. 342 * 343 * Here we actually don't know whether our system is 32- or 64-bit one. 344 * The simplest way to go is to examine affinity IDs of all our CPUs. If 345 * at least one of them has Aff3 populated, we set #address-cells to 2. 346 */ 347 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 348 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 349 350 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 351 addr_cells = 2; 352 break; 353 } 354 } 355 356 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 357 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 358 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 359 360 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 361 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 362 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 363 CPUState *cs = CPU(armcpu); 364 365 qemu_fdt_add_subnode(vms->fdt, nodename); 366 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 367 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 368 armcpu->dtb_compatible); 369 370 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 371 && vms->smp_cpus > 1) { 372 qemu_fdt_setprop_string(vms->fdt, nodename, 373 "enable-method", "psci"); 374 } 375 376 if (addr_cells == 2) { 377 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 378 armcpu->mp_affinity); 379 } else { 380 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 381 armcpu->mp_affinity); 382 } 383 384 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 385 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 386 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 387 } 388 389 g_free(nodename); 390 } 391 } 392 393 static void fdt_add_its_gic_node(VirtMachineState *vms) 394 { 395 char *nodename; 396 397 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 398 nodename = g_strdup_printf("/intc/its@%" PRIx64, 399 vms->memmap[VIRT_GIC_ITS].base); 400 qemu_fdt_add_subnode(vms->fdt, nodename); 401 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 402 "arm,gic-v3-its"); 403 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 404 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 405 2, vms->memmap[VIRT_GIC_ITS].base, 406 2, vms->memmap[VIRT_GIC_ITS].size); 407 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 408 g_free(nodename); 409 } 410 411 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 412 { 413 char *nodename; 414 415 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 416 vms->memmap[VIRT_GIC_V2M].base); 417 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 418 qemu_fdt_add_subnode(vms->fdt, nodename); 419 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 420 "arm,gic-v2m-frame"); 421 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 422 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 423 2, vms->memmap[VIRT_GIC_V2M].base, 424 2, vms->memmap[VIRT_GIC_V2M].size); 425 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 426 g_free(nodename); 427 } 428 429 static void fdt_add_gic_node(VirtMachineState *vms) 430 { 431 char *nodename; 432 433 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 434 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 435 436 nodename = g_strdup_printf("/intc@%" PRIx64, 437 vms->memmap[VIRT_GIC_DIST].base); 438 qemu_fdt_add_subnode(vms->fdt, nodename); 439 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 440 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 441 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 442 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 443 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 444 if (vms->gic_version == VIRT_GIC_VERSION_3) { 445 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 446 447 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 448 "arm,gic-v3"); 449 450 qemu_fdt_setprop_cell(vms->fdt, nodename, 451 "#redistributor-regions", nb_redist_regions); 452 453 if (nb_redist_regions == 1) { 454 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 455 2, vms->memmap[VIRT_GIC_DIST].base, 456 2, vms->memmap[VIRT_GIC_DIST].size, 457 2, vms->memmap[VIRT_GIC_REDIST].base, 458 2, vms->memmap[VIRT_GIC_REDIST].size); 459 } else { 460 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 461 2, vms->memmap[VIRT_GIC_DIST].base, 462 2, vms->memmap[VIRT_GIC_DIST].size, 463 2, vms->memmap[VIRT_GIC_REDIST].base, 464 2, vms->memmap[VIRT_GIC_REDIST].size, 465 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 466 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 467 } 468 469 if (vms->virt) { 470 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 471 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 472 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 473 } 474 } else { 475 /* 'cortex-a15-gic' means 'GIC v2' */ 476 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 477 "arm,cortex-a15-gic"); 478 if (!vms->virt) { 479 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 480 2, vms->memmap[VIRT_GIC_DIST].base, 481 2, vms->memmap[VIRT_GIC_DIST].size, 482 2, vms->memmap[VIRT_GIC_CPU].base, 483 2, vms->memmap[VIRT_GIC_CPU].size); 484 } else { 485 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 486 2, vms->memmap[VIRT_GIC_DIST].base, 487 2, vms->memmap[VIRT_GIC_DIST].size, 488 2, vms->memmap[VIRT_GIC_CPU].base, 489 2, vms->memmap[VIRT_GIC_CPU].size, 490 2, vms->memmap[VIRT_GIC_HYP].base, 491 2, vms->memmap[VIRT_GIC_HYP].size, 492 2, vms->memmap[VIRT_GIC_VCPU].base, 493 2, vms->memmap[VIRT_GIC_VCPU].size); 494 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 495 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 496 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 497 } 498 } 499 500 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 501 g_free(nodename); 502 } 503 504 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 505 { 506 CPUState *cpu; 507 ARMCPU *armcpu; 508 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 509 510 CPU_FOREACH(cpu) { 511 armcpu = ARM_CPU(cpu); 512 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 513 return; 514 } 515 if (kvm_enabled()) { 516 if (kvm_irqchip_in_kernel()) { 517 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 518 } 519 kvm_arm_pmu_init(cpu); 520 } 521 } 522 523 if (vms->gic_version == VIRT_GIC_VERSION_2) { 524 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 525 GIC_FDT_IRQ_PPI_CPU_WIDTH, 526 (1 << vms->smp_cpus) - 1); 527 } 528 529 armcpu = ARM_CPU(qemu_get_cpu(0)); 530 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 531 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 532 const char compat[] = "arm,armv8-pmuv3"; 533 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 534 compat, sizeof(compat)); 535 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 536 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 537 } 538 } 539 540 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 541 { 542 DeviceState *dev; 543 MachineState *ms = MACHINE(vms); 544 int irq = vms->irqmap[VIRT_ACPI_GED]; 545 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 546 547 if (ms->ram_slots) { 548 event |= ACPI_GED_MEM_HOTPLUG_EVT; 549 } 550 551 dev = qdev_create(NULL, TYPE_ACPI_GED); 552 qdev_prop_set_uint32(dev, "ged-event", event); 553 554 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 555 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 556 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 557 558 qdev_init_nofail(dev); 559 560 return dev; 561 } 562 563 static void create_its(VirtMachineState *vms) 564 { 565 const char *itsclass = its_class_name(); 566 DeviceState *dev; 567 568 if (!itsclass) { 569 /* Do nothing if not supported */ 570 return; 571 } 572 573 dev = qdev_create(NULL, itsclass); 574 575 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 576 &error_abort); 577 qdev_init_nofail(dev); 578 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 579 580 fdt_add_its_gic_node(vms); 581 } 582 583 static void create_v2m(VirtMachineState *vms) 584 { 585 int i; 586 int irq = vms->irqmap[VIRT_GIC_V2M]; 587 DeviceState *dev; 588 589 dev = qdev_create(NULL, "arm-gicv2m"); 590 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 591 qdev_prop_set_uint32(dev, "base-spi", irq); 592 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 593 qdev_init_nofail(dev); 594 595 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 596 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 597 qdev_get_gpio_in(vms->gic, irq + i)); 598 } 599 600 fdt_add_v2m_gic_node(vms); 601 } 602 603 static void create_gic(VirtMachineState *vms) 604 { 605 MachineState *ms = MACHINE(vms); 606 /* We create a standalone GIC */ 607 SysBusDevice *gicbusdev; 608 const char *gictype; 609 int type = vms->gic_version, i; 610 unsigned int smp_cpus = ms->smp.cpus; 611 uint32_t nb_redist_regions = 0; 612 613 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 614 615 vms->gic = qdev_create(NULL, gictype); 616 qdev_prop_set_uint32(vms->gic, "revision", type); 617 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 618 /* Note that the num-irq property counts both internal and external 619 * interrupts; there are always 32 of the former (mandated by GIC spec). 620 */ 621 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 622 if (!kvm_irqchip_in_kernel()) { 623 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 624 } 625 626 if (type == 3) { 627 uint32_t redist0_capacity = 628 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 629 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 630 631 nb_redist_regions = virt_gicv3_redist_region_count(vms); 632 633 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 634 nb_redist_regions); 635 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 636 637 if (nb_redist_regions == 2) { 638 uint32_t redist1_capacity = 639 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 640 641 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 642 MIN(smp_cpus - redist0_count, redist1_capacity)); 643 } 644 } else { 645 if (!kvm_irqchip_in_kernel()) { 646 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 647 vms->virt); 648 } 649 } 650 qdev_init_nofail(vms->gic); 651 gicbusdev = SYS_BUS_DEVICE(vms->gic); 652 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 653 if (type == 3) { 654 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 655 if (nb_redist_regions == 2) { 656 sysbus_mmio_map(gicbusdev, 2, 657 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 658 } 659 } else { 660 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 661 if (vms->virt) { 662 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 663 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 664 } 665 } 666 667 /* Wire the outputs from each CPU's generic timer and the GICv3 668 * maintenance interrupt signal to the appropriate GIC PPI inputs, 669 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 670 */ 671 for (i = 0; i < smp_cpus; i++) { 672 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 673 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 674 int irq; 675 /* Mapping from the output timer irq lines from the CPU to the 676 * GIC PPI inputs we use for the virt board. 677 */ 678 const int timer_irq[] = { 679 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 680 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 681 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 682 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 683 }; 684 685 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 686 qdev_connect_gpio_out(cpudev, irq, 687 qdev_get_gpio_in(vms->gic, 688 ppibase + timer_irq[irq])); 689 } 690 691 if (type == 3) { 692 qemu_irq irq = qdev_get_gpio_in(vms->gic, 693 ppibase + ARCH_GIC_MAINT_IRQ); 694 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 695 0, irq); 696 } else if (vms->virt) { 697 qemu_irq irq = qdev_get_gpio_in(vms->gic, 698 ppibase + ARCH_GIC_MAINT_IRQ); 699 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 700 } 701 702 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 703 qdev_get_gpio_in(vms->gic, ppibase 704 + VIRTUAL_PMU_IRQ)); 705 706 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 707 sysbus_connect_irq(gicbusdev, i + smp_cpus, 708 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 709 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 710 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 711 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 712 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 713 } 714 715 fdt_add_gic_node(vms); 716 717 if (type == 3 && vms->its) { 718 create_its(vms); 719 } else if (type == 2) { 720 create_v2m(vms); 721 } 722 } 723 724 static void create_uart(const VirtMachineState *vms, int uart, 725 MemoryRegion *mem, Chardev *chr) 726 { 727 char *nodename; 728 hwaddr base = vms->memmap[uart].base; 729 hwaddr size = vms->memmap[uart].size; 730 int irq = vms->irqmap[uart]; 731 const char compat[] = "arm,pl011\0arm,primecell"; 732 const char clocknames[] = "uartclk\0apb_pclk"; 733 DeviceState *dev = qdev_create(NULL, TYPE_PL011); 734 SysBusDevice *s = SYS_BUS_DEVICE(dev); 735 736 qdev_prop_set_chr(dev, "chardev", chr); 737 qdev_init_nofail(dev); 738 memory_region_add_subregion(mem, base, 739 sysbus_mmio_get_region(s, 0)); 740 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 741 742 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 743 qemu_fdt_add_subnode(vms->fdt, nodename); 744 /* Note that we can't use setprop_string because of the embedded NUL */ 745 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 746 compat, sizeof(compat)); 747 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 748 2, base, 2, size); 749 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 750 GIC_FDT_IRQ_TYPE_SPI, irq, 751 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 752 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 753 vms->clock_phandle, vms->clock_phandle); 754 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 755 clocknames, sizeof(clocknames)); 756 757 if (uart == VIRT_UART) { 758 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 759 } else { 760 /* Mark as not usable by the normal world */ 761 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 762 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 763 764 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 765 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 766 nodename); 767 } 768 769 g_free(nodename); 770 } 771 772 static void create_rtc(const VirtMachineState *vms) 773 { 774 char *nodename; 775 hwaddr base = vms->memmap[VIRT_RTC].base; 776 hwaddr size = vms->memmap[VIRT_RTC].size; 777 int irq = vms->irqmap[VIRT_RTC]; 778 const char compat[] = "arm,pl031\0arm,primecell"; 779 780 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 781 782 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 783 qemu_fdt_add_subnode(vms->fdt, nodename); 784 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 785 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 786 2, base, 2, size); 787 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 788 GIC_FDT_IRQ_TYPE_SPI, irq, 789 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 790 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 791 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 792 g_free(nodename); 793 } 794 795 static DeviceState *gpio_key_dev; 796 static void virt_powerdown_req(Notifier *n, void *opaque) 797 { 798 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 799 800 if (s->acpi_dev) { 801 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 802 } else { 803 /* use gpio Pin 3 for power button event */ 804 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 805 } 806 } 807 808 static void create_gpio(const VirtMachineState *vms) 809 { 810 char *nodename; 811 DeviceState *pl061_dev; 812 hwaddr base = vms->memmap[VIRT_GPIO].base; 813 hwaddr size = vms->memmap[VIRT_GPIO].size; 814 int irq = vms->irqmap[VIRT_GPIO]; 815 const char compat[] = "arm,pl061\0arm,primecell"; 816 817 pl061_dev = sysbus_create_simple("pl061", base, 818 qdev_get_gpio_in(vms->gic, irq)); 819 820 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 821 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 822 qemu_fdt_add_subnode(vms->fdt, nodename); 823 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 824 2, base, 2, size); 825 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 826 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 827 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 828 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 829 GIC_FDT_IRQ_TYPE_SPI, irq, 830 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 831 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 832 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 833 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 834 835 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 836 qdev_get_gpio_in(pl061_dev, 3)); 837 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 838 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 839 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 840 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 841 842 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 843 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 844 "label", "GPIO Key Poweroff"); 845 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 846 KEY_POWER); 847 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 848 "gpios", phandle, 3, 0); 849 g_free(nodename); 850 } 851 852 static void create_virtio_devices(const VirtMachineState *vms) 853 { 854 int i; 855 hwaddr size = vms->memmap[VIRT_MMIO].size; 856 857 /* We create the transports in forwards order. Since qbus_realize() 858 * prepends (not appends) new child buses, the incrementing loop below will 859 * create a list of virtio-mmio buses with decreasing base addresses. 860 * 861 * When a -device option is processed from the command line, 862 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 863 * order. The upshot is that -device options in increasing command line 864 * order are mapped to virtio-mmio buses with decreasing base addresses. 865 * 866 * When this code was originally written, that arrangement ensured that the 867 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 868 * the first -device on the command line. (The end-to-end order is a 869 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 870 * guest kernel's name-to-address assignment strategy.) 871 * 872 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 873 * the message, if not necessarily the code, of commit 70161ff336. 874 * Therefore the loop now establishes the inverse of the original intent. 875 * 876 * Unfortunately, we can't counteract the kernel change by reversing the 877 * loop; it would break existing command lines. 878 * 879 * In any case, the kernel makes no guarantee about the stability of 880 * enumeration order of virtio devices (as demonstrated by it changing 881 * between kernel versions). For reliable and stable identification 882 * of disks users must use UUIDs or similar mechanisms. 883 */ 884 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 885 int irq = vms->irqmap[VIRT_MMIO] + i; 886 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 887 888 sysbus_create_simple("virtio-mmio", base, 889 qdev_get_gpio_in(vms->gic, irq)); 890 } 891 892 /* We add dtb nodes in reverse order so that they appear in the finished 893 * device tree lowest address first. 894 * 895 * Note that this mapping is independent of the loop above. The previous 896 * loop influences virtio device to virtio transport assignment, whereas 897 * this loop controls how virtio transports are laid out in the dtb. 898 */ 899 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 900 char *nodename; 901 int irq = vms->irqmap[VIRT_MMIO] + i; 902 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 903 904 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 905 qemu_fdt_add_subnode(vms->fdt, nodename); 906 qemu_fdt_setprop_string(vms->fdt, nodename, 907 "compatible", "virtio,mmio"); 908 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 909 2, base, 2, size); 910 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 911 GIC_FDT_IRQ_TYPE_SPI, irq, 912 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 913 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 914 g_free(nodename); 915 } 916 } 917 918 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 919 920 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 921 const char *name, 922 const char *alias_prop_name) 923 { 924 /* 925 * Create a single flash device. We use the same parameters as 926 * the flash devices on the Versatile Express board. 927 */ 928 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 929 930 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 931 qdev_prop_set_uint8(dev, "width", 4); 932 qdev_prop_set_uint8(dev, "device-width", 2); 933 qdev_prop_set_bit(dev, "big-endian", false); 934 qdev_prop_set_uint16(dev, "id0", 0x89); 935 qdev_prop_set_uint16(dev, "id1", 0x18); 936 qdev_prop_set_uint16(dev, "id2", 0x00); 937 qdev_prop_set_uint16(dev, "id3", 0x00); 938 qdev_prop_set_string(dev, "name", name); 939 object_property_add_child(OBJECT(vms), name, OBJECT(dev), 940 &error_abort); 941 object_property_add_alias(OBJECT(vms), alias_prop_name, 942 OBJECT(dev), "drive", &error_abort); 943 return PFLASH_CFI01(dev); 944 } 945 946 static void virt_flash_create(VirtMachineState *vms) 947 { 948 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 949 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 950 } 951 952 static void virt_flash_map1(PFlashCFI01 *flash, 953 hwaddr base, hwaddr size, 954 MemoryRegion *sysmem) 955 { 956 DeviceState *dev = DEVICE(flash); 957 958 assert(size % VIRT_FLASH_SECTOR_SIZE == 0); 959 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 960 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 961 qdev_init_nofail(dev); 962 963 memory_region_add_subregion(sysmem, base, 964 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 965 0)); 966 } 967 968 static void virt_flash_map(VirtMachineState *vms, 969 MemoryRegion *sysmem, 970 MemoryRegion *secure_sysmem) 971 { 972 /* 973 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 974 * sysmem is the system memory space. secure_sysmem is the secure view 975 * of the system, and the first flash device should be made visible only 976 * there. The second flash device is visible to both secure and nonsecure. 977 * If sysmem == secure_sysmem this means there is no separate Secure 978 * address space and both flash devices are generally visible. 979 */ 980 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 981 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 982 983 virt_flash_map1(vms->flash[0], flashbase, flashsize, 984 secure_sysmem); 985 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 986 sysmem); 987 } 988 989 static void virt_flash_fdt(VirtMachineState *vms, 990 MemoryRegion *sysmem, 991 MemoryRegion *secure_sysmem) 992 { 993 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 994 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 995 char *nodename; 996 997 if (sysmem == secure_sysmem) { 998 /* Report both flash devices as a single node in the DT */ 999 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1000 qemu_fdt_add_subnode(vms->fdt, nodename); 1001 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1002 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1003 2, flashbase, 2, flashsize, 1004 2, flashbase + flashsize, 2, flashsize); 1005 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1006 g_free(nodename); 1007 } else { 1008 /* 1009 * Report the devices as separate nodes so we can mark one as 1010 * only visible to the secure world. 1011 */ 1012 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1013 qemu_fdt_add_subnode(vms->fdt, nodename); 1014 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1015 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1016 2, flashbase, 2, flashsize); 1017 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1018 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1019 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1020 g_free(nodename); 1021 1022 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1023 qemu_fdt_add_subnode(vms->fdt, nodename); 1024 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1025 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1026 2, flashbase + flashsize, 2, flashsize); 1027 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1028 g_free(nodename); 1029 } 1030 } 1031 1032 static bool virt_firmware_init(VirtMachineState *vms, 1033 MemoryRegion *sysmem, 1034 MemoryRegion *secure_sysmem) 1035 { 1036 int i; 1037 BlockBackend *pflash_blk0; 1038 1039 /* Map legacy -drive if=pflash to machine properties */ 1040 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1041 pflash_cfi01_legacy_drive(vms->flash[i], 1042 drive_get(IF_PFLASH, 0, i)); 1043 } 1044 1045 virt_flash_map(vms, sysmem, secure_sysmem); 1046 1047 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1048 1049 if (bios_name) { 1050 char *fname; 1051 MemoryRegion *mr; 1052 int image_size; 1053 1054 if (pflash_blk0) { 1055 error_report("The contents of the first flash device may be " 1056 "specified with -bios or with -drive if=pflash... " 1057 "but you cannot use both options at once"); 1058 exit(1); 1059 } 1060 1061 /* Fall back to -bios */ 1062 1063 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1064 if (!fname) { 1065 error_report("Could not find ROM image '%s'", bios_name); 1066 exit(1); 1067 } 1068 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1069 image_size = load_image_mr(fname, mr); 1070 g_free(fname); 1071 if (image_size < 0) { 1072 error_report("Could not load ROM image '%s'", bios_name); 1073 exit(1); 1074 } 1075 } 1076 1077 return pflash_blk0 || bios_name; 1078 } 1079 1080 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1081 { 1082 MachineState *ms = MACHINE(vms); 1083 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1084 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1085 FWCfgState *fw_cfg; 1086 char *nodename; 1087 1088 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1089 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1090 1091 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1092 qemu_fdt_add_subnode(vms->fdt, nodename); 1093 qemu_fdt_setprop_string(vms->fdt, nodename, 1094 "compatible", "qemu,fw-cfg-mmio"); 1095 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1096 2, base, 2, size); 1097 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1098 g_free(nodename); 1099 return fw_cfg; 1100 } 1101 1102 static void create_pcie_irq_map(const VirtMachineState *vms, 1103 uint32_t gic_phandle, 1104 int first_irq, const char *nodename) 1105 { 1106 int devfn, pin; 1107 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1108 uint32_t *irq_map = full_irq_map; 1109 1110 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1111 for (pin = 0; pin < 4; pin++) { 1112 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1113 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1114 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1115 int i; 1116 1117 uint32_t map[] = { 1118 devfn << 8, 0, 0, /* devfn */ 1119 pin + 1, /* PCI pin */ 1120 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1121 1122 /* Convert map to big endian */ 1123 for (i = 0; i < 10; i++) { 1124 irq_map[i] = cpu_to_be32(map[i]); 1125 } 1126 irq_map += 10; 1127 } 1128 } 1129 1130 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1131 full_irq_map, sizeof(full_irq_map)); 1132 1133 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1134 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1135 0x7 /* PCI irq */); 1136 } 1137 1138 static void create_smmu(const VirtMachineState *vms, 1139 PCIBus *bus) 1140 { 1141 char *node; 1142 const char compat[] = "arm,smmu-v3"; 1143 int irq = vms->irqmap[VIRT_SMMU]; 1144 int i; 1145 hwaddr base = vms->memmap[VIRT_SMMU].base; 1146 hwaddr size = vms->memmap[VIRT_SMMU].size; 1147 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1148 DeviceState *dev; 1149 1150 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1151 return; 1152 } 1153 1154 dev = qdev_create(NULL, "arm-smmuv3"); 1155 1156 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1157 &error_abort); 1158 qdev_init_nofail(dev); 1159 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1160 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1161 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1162 qdev_get_gpio_in(vms->gic, irq + i)); 1163 } 1164 1165 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1166 qemu_fdt_add_subnode(vms->fdt, node); 1167 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1168 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1169 1170 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1171 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1172 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1173 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1174 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1175 1176 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1177 sizeof(irq_names)); 1178 1179 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1180 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1181 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1182 1183 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1184 1185 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1186 g_free(node); 1187 } 1188 1189 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms, Error **errp) 1190 { 1191 const char compat[] = "virtio,pci-iommu"; 1192 uint16_t bdf = vms->virtio_iommu_bdf; 1193 char *node; 1194 1195 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1196 1197 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1198 qemu_fdt_add_subnode(vms->fdt, node); 1199 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1200 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 1201 1, bdf << 8, 1, 0, 1, 0, 1202 1, 0, 1, 0); 1203 1204 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1205 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1206 g_free(node); 1207 1208 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map", 1209 0x0, vms->iommu_phandle, 0x0, bdf, 1210 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1211 } 1212 1213 static void create_pcie(VirtMachineState *vms) 1214 { 1215 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1216 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1217 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1218 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1219 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1220 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1221 hwaddr base_ecam, size_ecam; 1222 hwaddr base = base_mmio; 1223 int nr_pcie_buses; 1224 int irq = vms->irqmap[VIRT_PCIE]; 1225 MemoryRegion *mmio_alias; 1226 MemoryRegion *mmio_reg; 1227 MemoryRegion *ecam_alias; 1228 MemoryRegion *ecam_reg; 1229 DeviceState *dev; 1230 char *nodename; 1231 int i, ecam_id; 1232 PCIHostState *pci; 1233 1234 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1235 qdev_init_nofail(dev); 1236 1237 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1238 base_ecam = vms->memmap[ecam_id].base; 1239 size_ecam = vms->memmap[ecam_id].size; 1240 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1241 /* Map only the first size_ecam bytes of ECAM space */ 1242 ecam_alias = g_new0(MemoryRegion, 1); 1243 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1244 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1245 ecam_reg, 0, size_ecam); 1246 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1247 1248 /* Map the MMIO window into system address space so as to expose 1249 * the section of PCI MMIO space which starts at the same base address 1250 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1251 * the window). 1252 */ 1253 mmio_alias = g_new0(MemoryRegion, 1); 1254 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1255 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1256 mmio_reg, base_mmio, size_mmio); 1257 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1258 1259 if (vms->highmem) { 1260 /* Map high MMIO space */ 1261 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1262 1263 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1264 mmio_reg, base_mmio_high, size_mmio_high); 1265 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1266 high_mmio_alias); 1267 } 1268 1269 /* Map IO port space */ 1270 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1271 1272 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1273 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1274 qdev_get_gpio_in(vms->gic, irq + i)); 1275 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1276 } 1277 1278 pci = PCI_HOST_BRIDGE(dev); 1279 if (pci->bus) { 1280 for (i = 0; i < nb_nics; i++) { 1281 NICInfo *nd = &nd_table[i]; 1282 1283 if (!nd->model) { 1284 nd->model = g_strdup("virtio"); 1285 } 1286 1287 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1288 } 1289 } 1290 1291 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1292 qemu_fdt_add_subnode(vms->fdt, nodename); 1293 qemu_fdt_setprop_string(vms->fdt, nodename, 1294 "compatible", "pci-host-ecam-generic"); 1295 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1296 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1297 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1298 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1299 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1300 nr_pcie_buses - 1); 1301 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1302 1303 if (vms->msi_phandle) { 1304 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1305 vms->msi_phandle); 1306 } 1307 1308 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1309 2, base_ecam, 2, size_ecam); 1310 1311 if (vms->highmem) { 1312 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1313 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1314 2, base_pio, 2, size_pio, 1315 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1316 2, base_mmio, 2, size_mmio, 1317 1, FDT_PCI_RANGE_MMIO_64BIT, 1318 2, base_mmio_high, 1319 2, base_mmio_high, 2, size_mmio_high); 1320 } else { 1321 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1322 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1323 2, base_pio, 2, size_pio, 1324 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1325 2, base_mmio, 2, size_mmio); 1326 } 1327 1328 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1329 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1330 1331 if (vms->iommu) { 1332 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1333 1334 switch (vms->iommu) { 1335 case VIRT_IOMMU_SMMUV3: 1336 create_smmu(vms, pci->bus); 1337 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1338 0x0, vms->iommu_phandle, 0x0, 0x10000); 1339 break; 1340 default: 1341 g_assert_not_reached(); 1342 } 1343 } 1344 } 1345 1346 static void create_platform_bus(VirtMachineState *vms) 1347 { 1348 DeviceState *dev; 1349 SysBusDevice *s; 1350 int i; 1351 MemoryRegion *sysmem = get_system_memory(); 1352 1353 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1354 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1355 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1356 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1357 qdev_init_nofail(dev); 1358 vms->platform_bus_dev = dev; 1359 1360 s = SYS_BUS_DEVICE(dev); 1361 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1362 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1363 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1364 } 1365 1366 memory_region_add_subregion(sysmem, 1367 vms->memmap[VIRT_PLATFORM_BUS].base, 1368 sysbus_mmio_get_region(s, 0)); 1369 } 1370 1371 static void create_secure_ram(VirtMachineState *vms, 1372 MemoryRegion *secure_sysmem) 1373 { 1374 MemoryRegion *secram = g_new(MemoryRegion, 1); 1375 char *nodename; 1376 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1377 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1378 1379 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1380 &error_fatal); 1381 memory_region_add_subregion(secure_sysmem, base, secram); 1382 1383 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1384 qemu_fdt_add_subnode(vms->fdt, nodename); 1385 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1386 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1387 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1388 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1389 1390 g_free(nodename); 1391 } 1392 1393 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1394 { 1395 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1396 bootinfo); 1397 1398 *fdt_size = board->fdt_size; 1399 return board->fdt; 1400 } 1401 1402 static void virt_build_smbios(VirtMachineState *vms) 1403 { 1404 MachineClass *mc = MACHINE_GET_CLASS(vms); 1405 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1406 uint8_t *smbios_tables, *smbios_anchor; 1407 size_t smbios_tables_len, smbios_anchor_len; 1408 const char *product = "QEMU Virtual Machine"; 1409 1410 if (kvm_enabled()) { 1411 product = "KVM Virtual Machine"; 1412 } 1413 1414 smbios_set_defaults("QEMU", product, 1415 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1416 true, SMBIOS_ENTRY_POINT_30); 1417 1418 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, 1419 &smbios_anchor, &smbios_anchor_len); 1420 1421 if (smbios_anchor) { 1422 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1423 smbios_tables, smbios_tables_len); 1424 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1425 smbios_anchor, smbios_anchor_len); 1426 } 1427 } 1428 1429 static 1430 void virt_machine_done(Notifier *notifier, void *data) 1431 { 1432 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1433 machine_done); 1434 MachineState *ms = MACHINE(vms); 1435 ARMCPU *cpu = ARM_CPU(first_cpu); 1436 struct arm_boot_info *info = &vms->bootinfo; 1437 AddressSpace *as = arm_boot_address_space(cpu, info); 1438 1439 /* 1440 * If the user provided a dtb, we assume the dynamic sysbus nodes 1441 * already are integrated there. This corresponds to a use case where 1442 * the dynamic sysbus nodes are complex and their generation is not yet 1443 * supported. In that case the user can take charge of the guest dt 1444 * while qemu takes charge of the qom stuff. 1445 */ 1446 if (info->dtb_filename == NULL) { 1447 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1448 vms->memmap[VIRT_PLATFORM_BUS].base, 1449 vms->memmap[VIRT_PLATFORM_BUS].size, 1450 vms->irqmap[VIRT_PLATFORM_BUS]); 1451 } 1452 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1453 exit(1); 1454 } 1455 1456 virt_acpi_setup(vms); 1457 virt_build_smbios(vms); 1458 } 1459 1460 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1461 { 1462 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1463 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1464 1465 if (!vmc->disallow_affinity_adjustment) { 1466 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1467 * GIC's target-list limitations. 32-bit KVM hosts currently 1468 * always create clusters of 4 CPUs, but that is expected to 1469 * change when they gain support for gicv3. When KVM is enabled 1470 * it will override the changes we make here, therefore our 1471 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1472 * and to improve SGI efficiency. 1473 */ 1474 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1475 clustersz = GICV3_TARGETLIST_BITS; 1476 } else { 1477 clustersz = GIC_TARGETLIST_BITS; 1478 } 1479 } 1480 return arm_cpu_mp_affinity(idx, clustersz); 1481 } 1482 1483 static void virt_set_memmap(VirtMachineState *vms) 1484 { 1485 MachineState *ms = MACHINE(vms); 1486 hwaddr base, device_memory_base, device_memory_size; 1487 int i; 1488 1489 vms->memmap = extended_memmap; 1490 1491 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1492 vms->memmap[i] = base_memmap[i]; 1493 } 1494 1495 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1496 error_report("unsupported number of memory slots: %"PRIu64, 1497 ms->ram_slots); 1498 exit(EXIT_FAILURE); 1499 } 1500 1501 /* 1502 * We compute the base of the high IO region depending on the 1503 * amount of initial and device memory. The device memory start/size 1504 * is aligned on 1GiB. We never put the high IO region below 256GiB 1505 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1506 * The device region size assumes 1GiB page max alignment per slot. 1507 */ 1508 device_memory_base = 1509 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1510 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1511 1512 /* Base address of the high IO region */ 1513 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1514 if (base < device_memory_base) { 1515 error_report("maxmem/slots too huge"); 1516 exit(EXIT_FAILURE); 1517 } 1518 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1519 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1520 } 1521 1522 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1523 hwaddr size = extended_memmap[i].size; 1524 1525 base = ROUND_UP(base, size); 1526 vms->memmap[i].base = base; 1527 vms->memmap[i].size = size; 1528 base += size; 1529 } 1530 vms->highest_gpa = base - 1; 1531 if (device_memory_size > 0) { 1532 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1533 ms->device_memory->base = device_memory_base; 1534 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1535 "device-memory", device_memory_size); 1536 } 1537 } 1538 1539 /* 1540 * finalize_gic_version - Determines the final gic_version 1541 * according to the gic-version property 1542 * 1543 * Default GIC type is v2 1544 */ 1545 static void finalize_gic_version(VirtMachineState *vms) 1546 { 1547 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1548 1549 if (kvm_enabled()) { 1550 int probe_bitmap; 1551 1552 if (!kvm_irqchip_in_kernel()) { 1553 switch (vms->gic_version) { 1554 case VIRT_GIC_VERSION_HOST: 1555 warn_report( 1556 "gic-version=host not relevant with kernel-irqchip=off " 1557 "as only userspace GICv2 is supported. Using v2 ..."); 1558 return; 1559 case VIRT_GIC_VERSION_MAX: 1560 case VIRT_GIC_VERSION_NOSEL: 1561 vms->gic_version = VIRT_GIC_VERSION_2; 1562 return; 1563 case VIRT_GIC_VERSION_2: 1564 return; 1565 case VIRT_GIC_VERSION_3: 1566 error_report( 1567 "gic-version=3 is not supported with kernel-irqchip=off"); 1568 exit(1); 1569 } 1570 } 1571 1572 probe_bitmap = kvm_arm_vgic_probe(); 1573 if (!probe_bitmap) { 1574 error_report("Unable to determine GIC version supported by host"); 1575 exit(1); 1576 } 1577 1578 switch (vms->gic_version) { 1579 case VIRT_GIC_VERSION_HOST: 1580 case VIRT_GIC_VERSION_MAX: 1581 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1582 vms->gic_version = VIRT_GIC_VERSION_3; 1583 } else { 1584 vms->gic_version = VIRT_GIC_VERSION_2; 1585 } 1586 return; 1587 case VIRT_GIC_VERSION_NOSEL: 1588 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1589 vms->gic_version = VIRT_GIC_VERSION_2; 1590 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1591 /* 1592 * in case the host does not support v2 in-kernel emulation or 1593 * the end-user requested more than 8 VCPUs we now default 1594 * to v3. In any case defaulting to v2 would be broken. 1595 */ 1596 vms->gic_version = VIRT_GIC_VERSION_3; 1597 } else if (max_cpus > GIC_NCPU) { 1598 error_report("host only supports in-kernel GICv2 emulation " 1599 "but more than 8 vcpus are requested"); 1600 exit(1); 1601 } 1602 break; 1603 case VIRT_GIC_VERSION_2: 1604 case VIRT_GIC_VERSION_3: 1605 break; 1606 } 1607 1608 /* Check chosen version is effectively supported by the host */ 1609 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1610 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1611 error_report("host does not support in-kernel GICv2 emulation"); 1612 exit(1); 1613 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1614 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1615 error_report("host does not support in-kernel GICv3 emulation"); 1616 exit(1); 1617 } 1618 return; 1619 } 1620 1621 /* TCG mode */ 1622 switch (vms->gic_version) { 1623 case VIRT_GIC_VERSION_NOSEL: 1624 vms->gic_version = VIRT_GIC_VERSION_2; 1625 break; 1626 case VIRT_GIC_VERSION_MAX: 1627 vms->gic_version = VIRT_GIC_VERSION_3; 1628 break; 1629 case VIRT_GIC_VERSION_HOST: 1630 error_report("gic-version=host requires KVM"); 1631 exit(1); 1632 case VIRT_GIC_VERSION_2: 1633 case VIRT_GIC_VERSION_3: 1634 break; 1635 } 1636 } 1637 1638 static void machvirt_init(MachineState *machine) 1639 { 1640 VirtMachineState *vms = VIRT_MACHINE(machine); 1641 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1642 MachineClass *mc = MACHINE_GET_CLASS(machine); 1643 const CPUArchIdList *possible_cpus; 1644 MemoryRegion *sysmem = get_system_memory(); 1645 MemoryRegion *secure_sysmem = NULL; 1646 int n, virt_max_cpus; 1647 bool firmware_loaded; 1648 bool aarch64 = true; 1649 bool has_ged = !vmc->no_ged; 1650 unsigned int smp_cpus = machine->smp.cpus; 1651 unsigned int max_cpus = machine->smp.max_cpus; 1652 1653 /* 1654 * In accelerated mode, the memory map is computed earlier in kvm_type() 1655 * to create a VM with the right number of IPA bits. 1656 */ 1657 if (!vms->memmap) { 1658 virt_set_memmap(vms); 1659 } 1660 1661 /* We can probe only here because during property set 1662 * KVM is not available yet 1663 */ 1664 finalize_gic_version(vms); 1665 1666 if (!cpu_type_valid(machine->cpu_type)) { 1667 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1668 exit(1); 1669 } 1670 1671 if (vms->secure) { 1672 if (kvm_enabled()) { 1673 error_report("mach-virt: KVM does not support Security extensions"); 1674 exit(1); 1675 } 1676 1677 /* 1678 * The Secure view of the world is the same as the NonSecure, 1679 * but with a few extra devices. Create it as a container region 1680 * containing the system memory at low priority; any secure-only 1681 * devices go in at higher priority and take precedence. 1682 */ 1683 secure_sysmem = g_new(MemoryRegion, 1); 1684 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1685 UINT64_MAX); 1686 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1687 } 1688 1689 firmware_loaded = virt_firmware_init(vms, sysmem, 1690 secure_sysmem ?: sysmem); 1691 1692 /* If we have an EL3 boot ROM then the assumption is that it will 1693 * implement PSCI itself, so disable QEMU's internal implementation 1694 * so it doesn't get in the way. Instead of starting secondary 1695 * CPUs in PSCI powerdown state we will start them all running and 1696 * let the boot ROM sort them out. 1697 * The usual case is that we do use QEMU's PSCI implementation; 1698 * if the guest has EL2 then we will use SMC as the conduit, 1699 * and otherwise we will use HVC (for backwards compatibility and 1700 * because if we're using KVM then we must use HVC). 1701 */ 1702 if (vms->secure && firmware_loaded) { 1703 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1704 } else if (vms->virt) { 1705 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1706 } else { 1707 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1708 } 1709 1710 /* The maximum number of CPUs depends on the GIC version, or on how 1711 * many redistributors we can fit into the memory map. 1712 */ 1713 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1714 virt_max_cpus = 1715 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1716 virt_max_cpus += 1717 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1718 } else { 1719 virt_max_cpus = GIC_NCPU; 1720 } 1721 1722 if (max_cpus > virt_max_cpus) { 1723 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1724 "supported by machine 'mach-virt' (%d)", 1725 max_cpus, virt_max_cpus); 1726 exit(1); 1727 } 1728 1729 vms->smp_cpus = smp_cpus; 1730 1731 if (vms->virt && kvm_enabled()) { 1732 error_report("mach-virt: KVM does not support providing " 1733 "Virtualization extensions to the guest CPU"); 1734 exit(1); 1735 } 1736 1737 create_fdt(vms); 1738 1739 possible_cpus = mc->possible_cpu_arch_ids(machine); 1740 for (n = 0; n < possible_cpus->len; n++) { 1741 Object *cpuobj; 1742 CPUState *cs; 1743 1744 if (n >= smp_cpus) { 1745 break; 1746 } 1747 1748 cpuobj = object_new(possible_cpus->cpus[n].type); 1749 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1750 "mp-affinity", NULL); 1751 1752 cs = CPU(cpuobj); 1753 cs->cpu_index = n; 1754 1755 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1756 &error_fatal); 1757 1758 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1759 1760 if (!vms->secure) { 1761 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1762 } 1763 1764 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1765 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1766 } 1767 1768 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1769 object_property_set_int(cpuobj, vms->psci_conduit, 1770 "psci-conduit", NULL); 1771 1772 /* Secondary CPUs start in PSCI powered-down state */ 1773 if (n > 0) { 1774 object_property_set_bool(cpuobj, true, 1775 "start-powered-off", NULL); 1776 } 1777 } 1778 1779 if (vmc->kvm_no_adjvtime && 1780 object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { 1781 object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); 1782 } 1783 1784 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1785 object_property_set_bool(cpuobj, false, "pmu", NULL); 1786 } 1787 1788 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1789 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1790 "reset-cbar", &error_abort); 1791 } 1792 1793 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1794 &error_abort); 1795 if (vms->secure) { 1796 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1797 "secure-memory", &error_abort); 1798 } 1799 1800 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1801 object_unref(cpuobj); 1802 } 1803 fdt_add_timer_nodes(vms); 1804 fdt_add_cpu_nodes(vms); 1805 1806 if (!kvm_enabled()) { 1807 ARMCPU *cpu = ARM_CPU(first_cpu); 1808 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1809 1810 if (aarch64 && vms->highmem) { 1811 int requested_pa_size, pamax = arm_pamax(cpu); 1812 1813 requested_pa_size = 64 - clz64(vms->highest_gpa); 1814 if (pamax < requested_pa_size) { 1815 error_report("VCPU supports less PA bits (%d) than requested " 1816 "by the memory map (%d)", pamax, requested_pa_size); 1817 exit(1); 1818 } 1819 } 1820 } 1821 1822 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 1823 machine->ram); 1824 if (machine->device_memory) { 1825 memory_region_add_subregion(sysmem, machine->device_memory->base, 1826 &machine->device_memory->mr); 1827 } 1828 1829 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 1830 1831 create_gic(vms); 1832 1833 fdt_add_pmu_nodes(vms); 1834 1835 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 1836 1837 if (vms->secure) { 1838 create_secure_ram(vms, secure_sysmem); 1839 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1840 } 1841 1842 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1843 1844 create_rtc(vms); 1845 1846 create_pcie(vms); 1847 1848 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 1849 vms->acpi_dev = create_acpi_ged(vms); 1850 } else { 1851 create_gpio(vms); 1852 } 1853 1854 /* connect powerdown request */ 1855 vms->powerdown_notifier.notify = virt_powerdown_req; 1856 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 1857 1858 /* Create mmio transports, so the user can create virtio backends 1859 * (which will be automatically plugged in to the transports). If 1860 * no backend is created the transport will just sit harmlessly idle. 1861 */ 1862 create_virtio_devices(vms); 1863 1864 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1865 rom_set_fw(vms->fw_cfg); 1866 1867 create_platform_bus(vms); 1868 1869 vms->bootinfo.ram_size = machine->ram_size; 1870 vms->bootinfo.nb_cpus = smp_cpus; 1871 vms->bootinfo.board_id = -1; 1872 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1873 vms->bootinfo.get_dtb = machvirt_dtb; 1874 vms->bootinfo.skip_dtb_autoload = true; 1875 vms->bootinfo.firmware_loaded = firmware_loaded; 1876 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 1877 1878 vms->machine_done.notify = virt_machine_done; 1879 qemu_add_machine_init_done_notifier(&vms->machine_done); 1880 } 1881 1882 static bool virt_get_secure(Object *obj, Error **errp) 1883 { 1884 VirtMachineState *vms = VIRT_MACHINE(obj); 1885 1886 return vms->secure; 1887 } 1888 1889 static void virt_set_secure(Object *obj, bool value, Error **errp) 1890 { 1891 VirtMachineState *vms = VIRT_MACHINE(obj); 1892 1893 vms->secure = value; 1894 } 1895 1896 static bool virt_get_virt(Object *obj, Error **errp) 1897 { 1898 VirtMachineState *vms = VIRT_MACHINE(obj); 1899 1900 return vms->virt; 1901 } 1902 1903 static void virt_set_virt(Object *obj, bool value, Error **errp) 1904 { 1905 VirtMachineState *vms = VIRT_MACHINE(obj); 1906 1907 vms->virt = value; 1908 } 1909 1910 static bool virt_get_highmem(Object *obj, Error **errp) 1911 { 1912 VirtMachineState *vms = VIRT_MACHINE(obj); 1913 1914 return vms->highmem; 1915 } 1916 1917 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1918 { 1919 VirtMachineState *vms = VIRT_MACHINE(obj); 1920 1921 vms->highmem = value; 1922 } 1923 1924 static bool virt_get_its(Object *obj, Error **errp) 1925 { 1926 VirtMachineState *vms = VIRT_MACHINE(obj); 1927 1928 return vms->its; 1929 } 1930 1931 static void virt_set_its(Object *obj, bool value, Error **errp) 1932 { 1933 VirtMachineState *vms = VIRT_MACHINE(obj); 1934 1935 vms->its = value; 1936 } 1937 1938 bool virt_is_acpi_enabled(VirtMachineState *vms) 1939 { 1940 if (vms->acpi == ON_OFF_AUTO_OFF) { 1941 return false; 1942 } 1943 return true; 1944 } 1945 1946 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1947 void *opaque, Error **errp) 1948 { 1949 VirtMachineState *vms = VIRT_MACHINE(obj); 1950 OnOffAuto acpi = vms->acpi; 1951 1952 visit_type_OnOffAuto(v, name, &acpi, errp); 1953 } 1954 1955 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1956 void *opaque, Error **errp) 1957 { 1958 VirtMachineState *vms = VIRT_MACHINE(obj); 1959 1960 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 1961 } 1962 1963 static char *virt_get_gic_version(Object *obj, Error **errp) 1964 { 1965 VirtMachineState *vms = VIRT_MACHINE(obj); 1966 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; 1967 1968 return g_strdup(val); 1969 } 1970 1971 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1972 { 1973 VirtMachineState *vms = VIRT_MACHINE(obj); 1974 1975 if (!strcmp(value, "3")) { 1976 vms->gic_version = VIRT_GIC_VERSION_3; 1977 } else if (!strcmp(value, "2")) { 1978 vms->gic_version = VIRT_GIC_VERSION_2; 1979 } else if (!strcmp(value, "host")) { 1980 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 1981 } else if (!strcmp(value, "max")) { 1982 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 1983 } else { 1984 error_setg(errp, "Invalid gic-version value"); 1985 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1986 } 1987 } 1988 1989 static char *virt_get_iommu(Object *obj, Error **errp) 1990 { 1991 VirtMachineState *vms = VIRT_MACHINE(obj); 1992 1993 switch (vms->iommu) { 1994 case VIRT_IOMMU_NONE: 1995 return g_strdup("none"); 1996 case VIRT_IOMMU_SMMUV3: 1997 return g_strdup("smmuv3"); 1998 default: 1999 g_assert_not_reached(); 2000 } 2001 } 2002 2003 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2004 { 2005 VirtMachineState *vms = VIRT_MACHINE(obj); 2006 2007 if (!strcmp(value, "smmuv3")) { 2008 vms->iommu = VIRT_IOMMU_SMMUV3; 2009 } else if (!strcmp(value, "none")) { 2010 vms->iommu = VIRT_IOMMU_NONE; 2011 } else { 2012 error_setg(errp, "Invalid iommu value"); 2013 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2014 } 2015 } 2016 2017 static CpuInstanceProperties 2018 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2019 { 2020 MachineClass *mc = MACHINE_GET_CLASS(ms); 2021 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2022 2023 assert(cpu_index < possible_cpus->len); 2024 return possible_cpus->cpus[cpu_index].props; 2025 } 2026 2027 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2028 { 2029 return idx % ms->numa_state->num_nodes; 2030 } 2031 2032 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2033 { 2034 int n; 2035 unsigned int max_cpus = ms->smp.max_cpus; 2036 VirtMachineState *vms = VIRT_MACHINE(ms); 2037 2038 if (ms->possible_cpus) { 2039 assert(ms->possible_cpus->len == max_cpus); 2040 return ms->possible_cpus; 2041 } 2042 2043 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2044 sizeof(CPUArchId) * max_cpus); 2045 ms->possible_cpus->len = max_cpus; 2046 for (n = 0; n < ms->possible_cpus->len; n++) { 2047 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2048 ms->possible_cpus->cpus[n].arch_id = 2049 virt_cpu_mp_affinity(vms, n); 2050 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2051 ms->possible_cpus->cpus[n].props.thread_id = n; 2052 } 2053 return ms->possible_cpus; 2054 } 2055 2056 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2057 Error **errp) 2058 { 2059 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2060 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2061 2062 if (is_nvdimm) { 2063 error_setg(errp, "nvdimm is not yet supported"); 2064 return; 2065 } 2066 2067 if (!vms->acpi_dev) { 2068 error_setg(errp, 2069 "memory hotplug is not enabled: missing acpi-ged device"); 2070 return; 2071 } 2072 2073 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2074 } 2075 2076 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2077 DeviceState *dev, Error **errp) 2078 { 2079 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2080 Error *local_err = NULL; 2081 2082 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err); 2083 if (local_err) { 2084 goto out; 2085 } 2086 2087 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2088 dev, &error_abort); 2089 2090 out: 2091 error_propagate(errp, local_err); 2092 } 2093 2094 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2095 DeviceState *dev, Error **errp) 2096 { 2097 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2098 virt_memory_pre_plug(hotplug_dev, dev, errp); 2099 } 2100 } 2101 2102 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2103 DeviceState *dev, Error **errp) 2104 { 2105 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2106 2107 if (vms->platform_bus_dev) { 2108 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 2109 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2110 SYS_BUS_DEVICE(dev)); 2111 } 2112 } 2113 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2114 virt_memory_plug(hotplug_dev, dev, errp); 2115 } 2116 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2117 PCIDevice *pdev = PCI_DEVICE(dev); 2118 2119 vms->iommu = VIRT_IOMMU_VIRTIO; 2120 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2121 create_virtio_iommu_dt_bindings(vms, errp); 2122 } 2123 } 2124 2125 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2126 DeviceState *dev, Error **errp) 2127 { 2128 error_setg(errp, "device unplug request for unsupported device" 2129 " type: %s", object_get_typename(OBJECT(dev))); 2130 } 2131 2132 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2133 DeviceState *dev) 2134 { 2135 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) || 2136 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { 2137 return HOTPLUG_HANDLER(machine); 2138 } 2139 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2140 VirtMachineState *vms = VIRT_MACHINE(machine); 2141 2142 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { 2143 return HOTPLUG_HANDLER(machine); 2144 } 2145 } 2146 return NULL; 2147 } 2148 2149 /* 2150 * for arm64 kvm_type [7-0] encodes the requested number of bits 2151 * in the IPA address space 2152 */ 2153 static int virt_kvm_type(MachineState *ms, const char *type_str) 2154 { 2155 VirtMachineState *vms = VIRT_MACHINE(ms); 2156 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 2157 int requested_pa_size; 2158 2159 /* we freeze the memory map to compute the highest gpa */ 2160 virt_set_memmap(vms); 2161 2162 requested_pa_size = 64 - clz64(vms->highest_gpa); 2163 2164 if (requested_pa_size > max_vm_pa_size) { 2165 error_report("-m and ,maxmem option values " 2166 "require an IPA range (%d bits) larger than " 2167 "the one supported by the host (%d bits)", 2168 requested_pa_size, max_vm_pa_size); 2169 exit(1); 2170 } 2171 /* 2172 * By default we return 0 which corresponds to an implicit legacy 2173 * 40b IPA setting. Otherwise we return the actual requested PA 2174 * logsize 2175 */ 2176 return requested_pa_size > 40 ? requested_pa_size : 0; 2177 } 2178 2179 static void virt_machine_class_init(ObjectClass *oc, void *data) 2180 { 2181 MachineClass *mc = MACHINE_CLASS(oc); 2182 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2183 2184 mc->init = machvirt_init; 2185 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2186 * The value may be reduced later when we have more information about the 2187 * configuration of the particular instance. 2188 */ 2189 mc->max_cpus = 512; 2190 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2191 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2192 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2193 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2194 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2195 mc->block_default_type = IF_VIRTIO; 2196 mc->no_cdrom = 1; 2197 mc->pci_allow_0_address = true; 2198 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2199 mc->minimum_page_bits = 12; 2200 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2201 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2202 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2203 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2204 mc->kvm_type = virt_kvm_type; 2205 assert(!mc->get_hotplug_handler); 2206 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2207 hc->pre_plug = virt_machine_device_pre_plug_cb; 2208 hc->plug = virt_machine_device_plug_cb; 2209 hc->unplug_request = virt_machine_device_unplug_request_cb; 2210 mc->numa_mem_supported = true; 2211 mc->auto_enable_numa_with_memhp = true; 2212 mc->default_ram_id = "mach-virt.ram"; 2213 2214 object_class_property_add(oc, "acpi", "OnOffAuto", 2215 virt_get_acpi, virt_set_acpi, 2216 NULL, NULL, &error_abort); 2217 object_class_property_set_description(oc, "acpi", 2218 "Enable ACPI", &error_abort); 2219 } 2220 2221 static void virt_instance_init(Object *obj) 2222 { 2223 VirtMachineState *vms = VIRT_MACHINE(obj); 2224 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2225 2226 /* EL3 is disabled by default on virt: this makes us consistent 2227 * between KVM and TCG for this board, and it also allows us to 2228 * boot UEFI blobs which assume no TrustZone support. 2229 */ 2230 vms->secure = false; 2231 object_property_add_bool(obj, "secure", virt_get_secure, 2232 virt_set_secure, NULL); 2233 object_property_set_description(obj, "secure", 2234 "Set on/off to enable/disable the ARM " 2235 "Security Extensions (TrustZone)", 2236 NULL); 2237 2238 /* EL2 is also disabled by default, for similar reasons */ 2239 vms->virt = false; 2240 object_property_add_bool(obj, "virtualization", virt_get_virt, 2241 virt_set_virt, NULL); 2242 object_property_set_description(obj, "virtualization", 2243 "Set on/off to enable/disable emulating a " 2244 "guest CPU which implements the ARM " 2245 "Virtualization Extensions", 2246 NULL); 2247 2248 /* High memory is enabled by default */ 2249 vms->highmem = true; 2250 object_property_add_bool(obj, "highmem", virt_get_highmem, 2251 virt_set_highmem, NULL); 2252 object_property_set_description(obj, "highmem", 2253 "Set on/off to enable/disable using " 2254 "physical address space above 32 bits", 2255 NULL); 2256 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 2257 object_property_add_str(obj, "gic-version", virt_get_gic_version, 2258 virt_set_gic_version, NULL); 2259 object_property_set_description(obj, "gic-version", 2260 "Set GIC version. " 2261 "Valid values are 2, 3, host and max", 2262 NULL); 2263 2264 vms->highmem_ecam = !vmc->no_highmem_ecam; 2265 2266 if (vmc->no_its) { 2267 vms->its = false; 2268 } else { 2269 /* Default allows ITS instantiation */ 2270 vms->its = true; 2271 object_property_add_bool(obj, "its", virt_get_its, 2272 virt_set_its, NULL); 2273 object_property_set_description(obj, "its", 2274 "Set on/off to enable/disable " 2275 "ITS instantiation", 2276 NULL); 2277 } 2278 2279 /* Default disallows iommu instantiation */ 2280 vms->iommu = VIRT_IOMMU_NONE; 2281 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 2282 object_property_set_description(obj, "iommu", 2283 "Set the IOMMU type. " 2284 "Valid values are none and smmuv3", 2285 NULL); 2286 2287 vms->irqmap = a15irqmap; 2288 2289 virt_flash_create(vms); 2290 } 2291 2292 static const TypeInfo virt_machine_info = { 2293 .name = TYPE_VIRT_MACHINE, 2294 .parent = TYPE_MACHINE, 2295 .abstract = true, 2296 .instance_size = sizeof(VirtMachineState), 2297 .class_size = sizeof(VirtMachineClass), 2298 .class_init = virt_machine_class_init, 2299 .instance_init = virt_instance_init, 2300 .interfaces = (InterfaceInfo[]) { 2301 { TYPE_HOTPLUG_HANDLER }, 2302 { } 2303 }, 2304 }; 2305 2306 static void machvirt_machine_init(void) 2307 { 2308 type_register_static(&virt_machine_info); 2309 } 2310 type_init(machvirt_machine_init); 2311 2312 static void virt_machine_5_0_options(MachineClass *mc) 2313 { 2314 static GlobalProperty compat[] = { 2315 { TYPE_TPM_TIS_SYSBUS, "ppi", "false" }, 2316 }; 2317 2318 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 2319 } 2320 DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) 2321 2322 static void virt_machine_4_2_options(MachineClass *mc) 2323 { 2324 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2325 2326 virt_machine_5_0_options(mc); 2327 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 2328 vmc->kvm_no_adjvtime = true; 2329 } 2330 DEFINE_VIRT_MACHINE(4, 2) 2331 2332 static void virt_machine_4_1_options(MachineClass *mc) 2333 { 2334 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2335 2336 virt_machine_4_2_options(mc); 2337 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 2338 vmc->no_ged = true; 2339 mc->auto_enable_numa_with_memhp = false; 2340 } 2341 DEFINE_VIRT_MACHINE(4, 1) 2342 2343 static void virt_machine_4_0_options(MachineClass *mc) 2344 { 2345 virt_machine_4_1_options(mc); 2346 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2347 } 2348 DEFINE_VIRT_MACHINE(4, 0) 2349 2350 static void virt_machine_3_1_options(MachineClass *mc) 2351 { 2352 virt_machine_4_0_options(mc); 2353 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2354 } 2355 DEFINE_VIRT_MACHINE(3, 1) 2356 2357 static void virt_machine_3_0_options(MachineClass *mc) 2358 { 2359 virt_machine_3_1_options(mc); 2360 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2361 } 2362 DEFINE_VIRT_MACHINE(3, 0) 2363 2364 static void virt_machine_2_12_options(MachineClass *mc) 2365 { 2366 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2367 2368 virt_machine_3_0_options(mc); 2369 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2370 vmc->no_highmem_ecam = true; 2371 mc->max_cpus = 255; 2372 } 2373 DEFINE_VIRT_MACHINE(2, 12) 2374 2375 static void virt_machine_2_11_options(MachineClass *mc) 2376 { 2377 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2378 2379 virt_machine_2_12_options(mc); 2380 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2381 vmc->smbios_old_sys_ver = true; 2382 } 2383 DEFINE_VIRT_MACHINE(2, 11) 2384 2385 static void virt_machine_2_10_options(MachineClass *mc) 2386 { 2387 virt_machine_2_11_options(mc); 2388 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2389 /* before 2.11 we never faulted accesses to bad addresses */ 2390 mc->ignore_memory_transaction_failures = true; 2391 } 2392 DEFINE_VIRT_MACHINE(2, 10) 2393 2394 static void virt_machine_2_9_options(MachineClass *mc) 2395 { 2396 virt_machine_2_10_options(mc); 2397 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2398 } 2399 DEFINE_VIRT_MACHINE(2, 9) 2400 2401 static void virt_machine_2_8_options(MachineClass *mc) 2402 { 2403 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2404 2405 virt_machine_2_9_options(mc); 2406 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2407 /* For 2.8 and earlier we falsely claimed in the DT that 2408 * our timers were edge-triggered, not level-triggered. 2409 */ 2410 vmc->claim_edge_triggered_timers = true; 2411 } 2412 DEFINE_VIRT_MACHINE(2, 8) 2413 2414 static void virt_machine_2_7_options(MachineClass *mc) 2415 { 2416 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2417 2418 virt_machine_2_8_options(mc); 2419 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2420 /* ITS was introduced with 2.8 */ 2421 vmc->no_its = true; 2422 /* Stick with 1K pages for migration compatibility */ 2423 mc->minimum_page_bits = 0; 2424 } 2425 DEFINE_VIRT_MACHINE(2, 7) 2426 2427 static void virt_machine_2_6_options(MachineClass *mc) 2428 { 2429 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2430 2431 virt_machine_2_7_options(mc); 2432 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2433 vmc->disallow_affinity_adjustment = true; 2434 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2435 vmc->no_pmu = true; 2436 } 2437 DEFINE_VIRT_MACHINE(2, 6) 2438