1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/boards.h" 39 #include "hw/arm/boot.h" 40 #include "hw/arm/primecell.h" 41 #include "hw/arm/virt.h" 42 #include "hw/block/flash.h" 43 #include "hw/vfio/vfio-calxeda-xgmac.h" 44 #include "hw/vfio/vfio-amd-xgbe.h" 45 #include "hw/display/ramfb.h" 46 #include "net/net.h" 47 #include "sysemu/device_tree.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "sysemu/tpm.h" 52 #include "sysemu/kvm.h" 53 #include "hw/loader.h" 54 #include "exec/address-spaces.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/arm/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/irq.h" 67 #include "kvm_arm.h" 68 #include "hw/firmware/smbios.h" 69 #include "qapi/visitor.h" 70 #include "standard-headers/linux/input.h" 71 #include "hw/arm/smmuv3.h" 72 #include "hw/acpi/acpi.h" 73 #include "target/arm/internals.h" 74 #include "hw/mem/pc-dimm.h" 75 #include "hw/mem/nvdimm.h" 76 #include "hw/acpi/generic_event_device.h" 77 #include "hw/virtio/virtio-iommu.h" 78 #include "hw/char/pl011.h" 79 80 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 81 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 82 void *data) \ 83 { \ 84 MachineClass *mc = MACHINE_CLASS(oc); \ 85 virt_machine_##major##_##minor##_options(mc); \ 86 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 87 if (latest) { \ 88 mc->alias = "virt"; \ 89 } \ 90 } \ 91 static const TypeInfo machvirt_##major##_##minor##_info = { \ 92 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 93 .parent = TYPE_VIRT_MACHINE, \ 94 .class_init = virt_##major##_##minor##_class_init, \ 95 }; \ 96 static void machvirt_machine_##major##_##minor##_init(void) \ 97 { \ 98 type_register_static(&machvirt_##major##_##minor##_info); \ 99 } \ 100 type_init(machvirt_machine_##major##_##minor##_init); 101 102 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 103 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 104 #define DEFINE_VIRT_MACHINE(major, minor) \ 105 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 106 107 108 /* Number of external interrupt lines to configure the GIC with */ 109 #define NUM_IRQS 256 110 111 #define PLATFORM_BUS_NUM_IRQS 64 112 113 /* Legacy RAM limit in GB (< version 4.0) */ 114 #define LEGACY_RAMLIMIT_GB 255 115 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 116 117 /* Addresses and sizes of our components. 118 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 119 * 128MB..256MB is used for miscellaneous device I/O. 120 * 256MB..1GB is reserved for possible future PCI support (ie where the 121 * PCI memory window will go if we add a PCI host controller). 122 * 1GB and up is RAM (which may happily spill over into the 123 * high memory region beyond 4GB). 124 * This represents a compromise between how much RAM can be given to 125 * a 32 bit VM and leaving space for expansion and in particular for PCI. 126 * Note that devices should generally be placed at multiples of 0x10000, 127 * to accommodate guests using 64K pages. 128 */ 129 static const MemMapEntry base_memmap[] = { 130 /* Space up to 0x8000000 is reserved for a boot ROM */ 131 [VIRT_FLASH] = { 0, 0x08000000 }, 132 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 133 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 134 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 135 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 136 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 137 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 138 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 139 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 140 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 141 /* This redistributor space allows up to 2*64kB*123 CPUs */ 142 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 143 [VIRT_UART] = { 0x09000000, 0x00001000 }, 144 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 145 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 146 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 147 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 148 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 149 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 150 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 151 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 152 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 153 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 154 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 155 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 156 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 157 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 158 /* Actual RAM size depends on initial RAM and device memory settings */ 159 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 160 }; 161 162 /* 163 * Highmem IO Regions: This memory map is floating, located after the RAM. 164 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 165 * top of the RAM, so that its base get the same alignment as the size, 166 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 167 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 168 * Note the extended_memmap is sized so that it eventually also includes the 169 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 170 * index of base_memmap). 171 */ 172 static MemMapEntry extended_memmap[] = { 173 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 174 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 175 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 176 /* Second PCIe window */ 177 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 178 }; 179 180 static const int a15irqmap[] = { 181 [VIRT_UART] = 1, 182 [VIRT_RTC] = 2, 183 [VIRT_PCIE] = 3, /* ... to 6 */ 184 [VIRT_GPIO] = 7, 185 [VIRT_SECURE_UART] = 8, 186 [VIRT_ACPI_GED] = 9, 187 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 188 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 189 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 190 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 191 }; 192 193 static const char *valid_cpus[] = { 194 ARM_CPU_TYPE_NAME("cortex-a7"), 195 ARM_CPU_TYPE_NAME("cortex-a15"), 196 ARM_CPU_TYPE_NAME("cortex-a53"), 197 ARM_CPU_TYPE_NAME("cortex-a57"), 198 ARM_CPU_TYPE_NAME("cortex-a72"), 199 ARM_CPU_TYPE_NAME("host"), 200 ARM_CPU_TYPE_NAME("max"), 201 }; 202 203 static bool cpu_type_valid(const char *cpu) 204 { 205 int i; 206 207 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 208 if (strcmp(cpu, valid_cpus[i]) == 0) { 209 return true; 210 } 211 } 212 return false; 213 } 214 215 static void create_fdt(VirtMachineState *vms) 216 { 217 MachineState *ms = MACHINE(vms); 218 int nb_numa_nodes = ms->numa_state->num_nodes; 219 void *fdt = create_device_tree(&vms->fdt_size); 220 221 if (!fdt) { 222 error_report("create_device_tree() failed"); 223 exit(1); 224 } 225 226 vms->fdt = fdt; 227 228 /* Header */ 229 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 230 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 231 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 232 233 /* /chosen must exist for load_dtb to fill in necessary properties later */ 234 qemu_fdt_add_subnode(fdt, "/chosen"); 235 236 /* Clock node, for the benefit of the UART. The kernel device tree 237 * binding documentation claims the PL011 node clock properties are 238 * optional but in practice if you omit them the kernel refuses to 239 * probe for the device. 240 */ 241 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 242 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 243 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 244 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 245 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 246 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 247 "clk24mhz"); 248 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 249 250 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 251 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 252 uint32_t *matrix = g_malloc0(size); 253 int idx, i, j; 254 255 for (i = 0; i < nb_numa_nodes; i++) { 256 for (j = 0; j < nb_numa_nodes; j++) { 257 idx = (i * nb_numa_nodes + j) * 3; 258 matrix[idx + 0] = cpu_to_be32(i); 259 matrix[idx + 1] = cpu_to_be32(j); 260 matrix[idx + 2] = 261 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 262 } 263 } 264 265 qemu_fdt_add_subnode(fdt, "/distance-map"); 266 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 267 "numa-distance-map-v1"); 268 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 269 matrix, size); 270 g_free(matrix); 271 } 272 } 273 274 static void fdt_add_timer_nodes(const VirtMachineState *vms) 275 { 276 /* On real hardware these interrupts are level-triggered. 277 * On KVM they were edge-triggered before host kernel version 4.4, 278 * and level-triggered afterwards. 279 * On emulated QEMU they are level-triggered. 280 * 281 * Getting the DTB info about them wrong is awkward for some 282 * guest kernels: 283 * pre-4.8 ignore the DT and leave the interrupt configured 284 * with whatever the GIC reset value (or the bootloader) left it at 285 * 4.8 before rc6 honour the incorrect data by programming it back 286 * into the GIC, causing problems 287 * 4.8rc6 and later ignore the DT and always write "level triggered" 288 * into the GIC 289 * 290 * For backwards-compatibility, virt-2.8 and earlier will continue 291 * to say these are edge-triggered, but later machines will report 292 * the correct information. 293 */ 294 ARMCPU *armcpu; 295 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 296 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 297 298 if (vmc->claim_edge_triggered_timers) { 299 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 300 } 301 302 if (vms->gic_version == VIRT_GIC_VERSION_2) { 303 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 304 GIC_FDT_IRQ_PPI_CPU_WIDTH, 305 (1 << vms->smp_cpus) - 1); 306 } 307 308 qemu_fdt_add_subnode(vms->fdt, "/timer"); 309 310 armcpu = ARM_CPU(qemu_get_cpu(0)); 311 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 312 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 313 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 314 compat, sizeof(compat)); 315 } else { 316 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 317 "arm,armv7-timer"); 318 } 319 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 320 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 321 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 322 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 323 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 324 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 325 } 326 327 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 328 { 329 int cpu; 330 int addr_cells = 1; 331 const MachineState *ms = MACHINE(vms); 332 333 /* 334 * From Documentation/devicetree/bindings/arm/cpus.txt 335 * On ARM v8 64-bit systems value should be set to 2, 336 * that corresponds to the MPIDR_EL1 register size. 337 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 338 * in the system, #address-cells can be set to 1, since 339 * MPIDR_EL1[63:32] bits are not used for CPUs 340 * identification. 341 * 342 * Here we actually don't know whether our system is 32- or 64-bit one. 343 * The simplest way to go is to examine affinity IDs of all our CPUs. If 344 * at least one of them has Aff3 populated, we set #address-cells to 2. 345 */ 346 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 347 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 348 349 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 350 addr_cells = 2; 351 break; 352 } 353 } 354 355 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 356 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 357 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 358 359 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 360 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 361 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 362 CPUState *cs = CPU(armcpu); 363 364 qemu_fdt_add_subnode(vms->fdt, nodename); 365 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 366 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 367 armcpu->dtb_compatible); 368 369 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 370 && vms->smp_cpus > 1) { 371 qemu_fdt_setprop_string(vms->fdt, nodename, 372 "enable-method", "psci"); 373 } 374 375 if (addr_cells == 2) { 376 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 377 armcpu->mp_affinity); 378 } else { 379 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 380 armcpu->mp_affinity); 381 } 382 383 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 384 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 385 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 386 } 387 388 g_free(nodename); 389 } 390 } 391 392 static void fdt_add_its_gic_node(VirtMachineState *vms) 393 { 394 char *nodename; 395 396 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 397 nodename = g_strdup_printf("/intc/its@%" PRIx64, 398 vms->memmap[VIRT_GIC_ITS].base); 399 qemu_fdt_add_subnode(vms->fdt, nodename); 400 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 401 "arm,gic-v3-its"); 402 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 403 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 404 2, vms->memmap[VIRT_GIC_ITS].base, 405 2, vms->memmap[VIRT_GIC_ITS].size); 406 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 407 g_free(nodename); 408 } 409 410 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 411 { 412 char *nodename; 413 414 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 415 vms->memmap[VIRT_GIC_V2M].base); 416 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 417 qemu_fdt_add_subnode(vms->fdt, nodename); 418 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 419 "arm,gic-v2m-frame"); 420 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 421 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 422 2, vms->memmap[VIRT_GIC_V2M].base, 423 2, vms->memmap[VIRT_GIC_V2M].size); 424 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 425 g_free(nodename); 426 } 427 428 static void fdt_add_gic_node(VirtMachineState *vms) 429 { 430 char *nodename; 431 432 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 433 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 434 435 nodename = g_strdup_printf("/intc@%" PRIx64, 436 vms->memmap[VIRT_GIC_DIST].base); 437 qemu_fdt_add_subnode(vms->fdt, nodename); 438 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 439 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 440 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 441 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 442 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 443 if (vms->gic_version == VIRT_GIC_VERSION_3) { 444 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 445 446 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 447 "arm,gic-v3"); 448 449 qemu_fdt_setprop_cell(vms->fdt, nodename, 450 "#redistributor-regions", nb_redist_regions); 451 452 if (nb_redist_regions == 1) { 453 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 454 2, vms->memmap[VIRT_GIC_DIST].base, 455 2, vms->memmap[VIRT_GIC_DIST].size, 456 2, vms->memmap[VIRT_GIC_REDIST].base, 457 2, vms->memmap[VIRT_GIC_REDIST].size); 458 } else { 459 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 460 2, vms->memmap[VIRT_GIC_DIST].base, 461 2, vms->memmap[VIRT_GIC_DIST].size, 462 2, vms->memmap[VIRT_GIC_REDIST].base, 463 2, vms->memmap[VIRT_GIC_REDIST].size, 464 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 465 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 466 } 467 468 if (vms->virt) { 469 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 470 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 471 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 472 } 473 } else { 474 /* 'cortex-a15-gic' means 'GIC v2' */ 475 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 476 "arm,cortex-a15-gic"); 477 if (!vms->virt) { 478 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 479 2, vms->memmap[VIRT_GIC_DIST].base, 480 2, vms->memmap[VIRT_GIC_DIST].size, 481 2, vms->memmap[VIRT_GIC_CPU].base, 482 2, vms->memmap[VIRT_GIC_CPU].size); 483 } else { 484 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 485 2, vms->memmap[VIRT_GIC_DIST].base, 486 2, vms->memmap[VIRT_GIC_DIST].size, 487 2, vms->memmap[VIRT_GIC_CPU].base, 488 2, vms->memmap[VIRT_GIC_CPU].size, 489 2, vms->memmap[VIRT_GIC_HYP].base, 490 2, vms->memmap[VIRT_GIC_HYP].size, 491 2, vms->memmap[VIRT_GIC_VCPU].base, 492 2, vms->memmap[VIRT_GIC_VCPU].size); 493 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 494 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 495 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 496 } 497 } 498 499 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 500 g_free(nodename); 501 } 502 503 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 504 { 505 CPUState *cpu; 506 ARMCPU *armcpu; 507 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 508 509 CPU_FOREACH(cpu) { 510 armcpu = ARM_CPU(cpu); 511 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 512 return; 513 } 514 if (kvm_enabled()) { 515 if (kvm_irqchip_in_kernel()) { 516 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 517 } 518 kvm_arm_pmu_init(cpu); 519 } 520 } 521 522 if (vms->gic_version == VIRT_GIC_VERSION_2) { 523 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 524 GIC_FDT_IRQ_PPI_CPU_WIDTH, 525 (1 << vms->smp_cpus) - 1); 526 } 527 528 armcpu = ARM_CPU(qemu_get_cpu(0)); 529 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 530 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 531 const char compat[] = "arm,armv8-pmuv3"; 532 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 533 compat, sizeof(compat)); 534 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 535 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 536 } 537 } 538 539 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 540 { 541 DeviceState *dev; 542 MachineState *ms = MACHINE(vms); 543 int irq = vms->irqmap[VIRT_ACPI_GED]; 544 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 545 546 if (ms->ram_slots) { 547 event |= ACPI_GED_MEM_HOTPLUG_EVT; 548 } 549 550 dev = qdev_create(NULL, TYPE_ACPI_GED); 551 qdev_prop_set_uint32(dev, "ged-event", event); 552 553 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 554 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 555 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 556 557 qdev_init_nofail(dev); 558 559 return dev; 560 } 561 562 static void create_its(VirtMachineState *vms) 563 { 564 const char *itsclass = its_class_name(); 565 DeviceState *dev; 566 567 if (!itsclass) { 568 /* Do nothing if not supported */ 569 return; 570 } 571 572 dev = qdev_create(NULL, itsclass); 573 574 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 575 &error_abort); 576 qdev_init_nofail(dev); 577 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 578 579 fdt_add_its_gic_node(vms); 580 } 581 582 static void create_v2m(VirtMachineState *vms) 583 { 584 int i; 585 int irq = vms->irqmap[VIRT_GIC_V2M]; 586 DeviceState *dev; 587 588 dev = qdev_create(NULL, "arm-gicv2m"); 589 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 590 qdev_prop_set_uint32(dev, "base-spi", irq); 591 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 592 qdev_init_nofail(dev); 593 594 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 595 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 596 qdev_get_gpio_in(vms->gic, irq + i)); 597 } 598 599 fdt_add_v2m_gic_node(vms); 600 } 601 602 static void create_gic(VirtMachineState *vms) 603 { 604 MachineState *ms = MACHINE(vms); 605 /* We create a standalone GIC */ 606 SysBusDevice *gicbusdev; 607 const char *gictype; 608 int type = vms->gic_version, i; 609 unsigned int smp_cpus = ms->smp.cpus; 610 uint32_t nb_redist_regions = 0; 611 612 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 613 614 vms->gic = qdev_create(NULL, gictype); 615 qdev_prop_set_uint32(vms->gic, "revision", type); 616 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 617 /* Note that the num-irq property counts both internal and external 618 * interrupts; there are always 32 of the former (mandated by GIC spec). 619 */ 620 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 621 if (!kvm_irqchip_in_kernel()) { 622 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 623 } 624 625 if (type == 3) { 626 uint32_t redist0_capacity = 627 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 628 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 629 630 nb_redist_regions = virt_gicv3_redist_region_count(vms); 631 632 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 633 nb_redist_regions); 634 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 635 636 if (nb_redist_regions == 2) { 637 uint32_t redist1_capacity = 638 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 639 640 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 641 MIN(smp_cpus - redist0_count, redist1_capacity)); 642 } 643 } else { 644 if (!kvm_irqchip_in_kernel()) { 645 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 646 vms->virt); 647 } 648 } 649 qdev_init_nofail(vms->gic); 650 gicbusdev = SYS_BUS_DEVICE(vms->gic); 651 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 652 if (type == 3) { 653 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 654 if (nb_redist_regions == 2) { 655 sysbus_mmio_map(gicbusdev, 2, 656 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 657 } 658 } else { 659 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 660 if (vms->virt) { 661 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 662 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 663 } 664 } 665 666 /* Wire the outputs from each CPU's generic timer and the GICv3 667 * maintenance interrupt signal to the appropriate GIC PPI inputs, 668 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 669 */ 670 for (i = 0; i < smp_cpus; i++) { 671 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 672 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 673 int irq; 674 /* Mapping from the output timer irq lines from the CPU to the 675 * GIC PPI inputs we use for the virt board. 676 */ 677 const int timer_irq[] = { 678 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 679 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 680 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 681 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 682 }; 683 684 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 685 qdev_connect_gpio_out(cpudev, irq, 686 qdev_get_gpio_in(vms->gic, 687 ppibase + timer_irq[irq])); 688 } 689 690 if (type == 3) { 691 qemu_irq irq = qdev_get_gpio_in(vms->gic, 692 ppibase + ARCH_GIC_MAINT_IRQ); 693 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 694 0, irq); 695 } else if (vms->virt) { 696 qemu_irq irq = qdev_get_gpio_in(vms->gic, 697 ppibase + ARCH_GIC_MAINT_IRQ); 698 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 699 } 700 701 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 702 qdev_get_gpio_in(vms->gic, ppibase 703 + VIRTUAL_PMU_IRQ)); 704 705 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 706 sysbus_connect_irq(gicbusdev, i + smp_cpus, 707 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 708 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 709 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 710 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 711 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 712 } 713 714 fdt_add_gic_node(vms); 715 716 if (type == 3 && vms->its) { 717 create_its(vms); 718 } else if (type == 2) { 719 create_v2m(vms); 720 } 721 } 722 723 static void create_uart(const VirtMachineState *vms, int uart, 724 MemoryRegion *mem, Chardev *chr) 725 { 726 char *nodename; 727 hwaddr base = vms->memmap[uart].base; 728 hwaddr size = vms->memmap[uart].size; 729 int irq = vms->irqmap[uart]; 730 const char compat[] = "arm,pl011\0arm,primecell"; 731 const char clocknames[] = "uartclk\0apb_pclk"; 732 DeviceState *dev = qdev_create(NULL, TYPE_PL011); 733 SysBusDevice *s = SYS_BUS_DEVICE(dev); 734 735 qdev_prop_set_chr(dev, "chardev", chr); 736 qdev_init_nofail(dev); 737 memory_region_add_subregion(mem, base, 738 sysbus_mmio_get_region(s, 0)); 739 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 740 741 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 742 qemu_fdt_add_subnode(vms->fdt, nodename); 743 /* Note that we can't use setprop_string because of the embedded NUL */ 744 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 745 compat, sizeof(compat)); 746 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 747 2, base, 2, size); 748 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 749 GIC_FDT_IRQ_TYPE_SPI, irq, 750 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 751 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 752 vms->clock_phandle, vms->clock_phandle); 753 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 754 clocknames, sizeof(clocknames)); 755 756 if (uart == VIRT_UART) { 757 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 758 } else { 759 /* Mark as not usable by the normal world */ 760 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 761 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 762 763 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 764 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 765 nodename); 766 } 767 768 g_free(nodename); 769 } 770 771 static void create_rtc(const VirtMachineState *vms) 772 { 773 char *nodename; 774 hwaddr base = vms->memmap[VIRT_RTC].base; 775 hwaddr size = vms->memmap[VIRT_RTC].size; 776 int irq = vms->irqmap[VIRT_RTC]; 777 const char compat[] = "arm,pl031\0arm,primecell"; 778 779 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 780 781 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 782 qemu_fdt_add_subnode(vms->fdt, nodename); 783 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 784 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 785 2, base, 2, size); 786 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 787 GIC_FDT_IRQ_TYPE_SPI, irq, 788 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 789 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 790 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 791 g_free(nodename); 792 } 793 794 static DeviceState *gpio_key_dev; 795 static void virt_powerdown_req(Notifier *n, void *opaque) 796 { 797 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 798 799 if (s->acpi_dev) { 800 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 801 } else { 802 /* use gpio Pin 3 for power button event */ 803 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 804 } 805 } 806 807 static void create_gpio(const VirtMachineState *vms) 808 { 809 char *nodename; 810 DeviceState *pl061_dev; 811 hwaddr base = vms->memmap[VIRT_GPIO].base; 812 hwaddr size = vms->memmap[VIRT_GPIO].size; 813 int irq = vms->irqmap[VIRT_GPIO]; 814 const char compat[] = "arm,pl061\0arm,primecell"; 815 816 pl061_dev = sysbus_create_simple("pl061", base, 817 qdev_get_gpio_in(vms->gic, irq)); 818 819 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 820 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 821 qemu_fdt_add_subnode(vms->fdt, nodename); 822 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 823 2, base, 2, size); 824 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 825 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 826 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 827 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 828 GIC_FDT_IRQ_TYPE_SPI, irq, 829 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 830 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 831 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 832 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 833 834 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 835 qdev_get_gpio_in(pl061_dev, 3)); 836 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 837 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 838 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 839 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 840 841 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 842 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 843 "label", "GPIO Key Poweroff"); 844 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 845 KEY_POWER); 846 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 847 "gpios", phandle, 3, 0); 848 g_free(nodename); 849 } 850 851 static void create_virtio_devices(const VirtMachineState *vms) 852 { 853 int i; 854 hwaddr size = vms->memmap[VIRT_MMIO].size; 855 856 /* We create the transports in forwards order. Since qbus_realize() 857 * prepends (not appends) new child buses, the incrementing loop below will 858 * create a list of virtio-mmio buses with decreasing base addresses. 859 * 860 * When a -device option is processed from the command line, 861 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 862 * order. The upshot is that -device options in increasing command line 863 * order are mapped to virtio-mmio buses with decreasing base addresses. 864 * 865 * When this code was originally written, that arrangement ensured that the 866 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 867 * the first -device on the command line. (The end-to-end order is a 868 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 869 * guest kernel's name-to-address assignment strategy.) 870 * 871 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 872 * the message, if not necessarily the code, of commit 70161ff336. 873 * Therefore the loop now establishes the inverse of the original intent. 874 * 875 * Unfortunately, we can't counteract the kernel change by reversing the 876 * loop; it would break existing command lines. 877 * 878 * In any case, the kernel makes no guarantee about the stability of 879 * enumeration order of virtio devices (as demonstrated by it changing 880 * between kernel versions). For reliable and stable identification 881 * of disks users must use UUIDs or similar mechanisms. 882 */ 883 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 884 int irq = vms->irqmap[VIRT_MMIO] + i; 885 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 886 887 sysbus_create_simple("virtio-mmio", base, 888 qdev_get_gpio_in(vms->gic, irq)); 889 } 890 891 /* We add dtb nodes in reverse order so that they appear in the finished 892 * device tree lowest address first. 893 * 894 * Note that this mapping is independent of the loop above. The previous 895 * loop influences virtio device to virtio transport assignment, whereas 896 * this loop controls how virtio transports are laid out in the dtb. 897 */ 898 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 899 char *nodename; 900 int irq = vms->irqmap[VIRT_MMIO] + i; 901 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 902 903 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 904 qemu_fdt_add_subnode(vms->fdt, nodename); 905 qemu_fdt_setprop_string(vms->fdt, nodename, 906 "compatible", "virtio,mmio"); 907 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 908 2, base, 2, size); 909 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 910 GIC_FDT_IRQ_TYPE_SPI, irq, 911 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 912 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 913 g_free(nodename); 914 } 915 } 916 917 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 918 919 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 920 const char *name, 921 const char *alias_prop_name) 922 { 923 /* 924 * Create a single flash device. We use the same parameters as 925 * the flash devices on the Versatile Express board. 926 */ 927 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 928 929 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 930 qdev_prop_set_uint8(dev, "width", 4); 931 qdev_prop_set_uint8(dev, "device-width", 2); 932 qdev_prop_set_bit(dev, "big-endian", false); 933 qdev_prop_set_uint16(dev, "id0", 0x89); 934 qdev_prop_set_uint16(dev, "id1", 0x18); 935 qdev_prop_set_uint16(dev, "id2", 0x00); 936 qdev_prop_set_uint16(dev, "id3", 0x00); 937 qdev_prop_set_string(dev, "name", name); 938 object_property_add_child(OBJECT(vms), name, OBJECT(dev), 939 &error_abort); 940 object_property_add_alias(OBJECT(vms), alias_prop_name, 941 OBJECT(dev), "drive", &error_abort); 942 return PFLASH_CFI01(dev); 943 } 944 945 static void virt_flash_create(VirtMachineState *vms) 946 { 947 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 948 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 949 } 950 951 static void virt_flash_map1(PFlashCFI01 *flash, 952 hwaddr base, hwaddr size, 953 MemoryRegion *sysmem) 954 { 955 DeviceState *dev = DEVICE(flash); 956 957 assert(size % VIRT_FLASH_SECTOR_SIZE == 0); 958 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 959 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 960 qdev_init_nofail(dev); 961 962 memory_region_add_subregion(sysmem, base, 963 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 964 0)); 965 } 966 967 static void virt_flash_map(VirtMachineState *vms, 968 MemoryRegion *sysmem, 969 MemoryRegion *secure_sysmem) 970 { 971 /* 972 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 973 * sysmem is the system memory space. secure_sysmem is the secure view 974 * of the system, and the first flash device should be made visible only 975 * there. The second flash device is visible to both secure and nonsecure. 976 * If sysmem == secure_sysmem this means there is no separate Secure 977 * address space and both flash devices are generally visible. 978 */ 979 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 980 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 981 982 virt_flash_map1(vms->flash[0], flashbase, flashsize, 983 secure_sysmem); 984 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 985 sysmem); 986 } 987 988 static void virt_flash_fdt(VirtMachineState *vms, 989 MemoryRegion *sysmem, 990 MemoryRegion *secure_sysmem) 991 { 992 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 993 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 994 char *nodename; 995 996 if (sysmem == secure_sysmem) { 997 /* Report both flash devices as a single node in the DT */ 998 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 999 qemu_fdt_add_subnode(vms->fdt, nodename); 1000 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1001 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1002 2, flashbase, 2, flashsize, 1003 2, flashbase + flashsize, 2, flashsize); 1004 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1005 g_free(nodename); 1006 } else { 1007 /* 1008 * Report the devices as separate nodes so we can mark one as 1009 * only visible to the secure world. 1010 */ 1011 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1012 qemu_fdt_add_subnode(vms->fdt, nodename); 1013 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1014 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1015 2, flashbase, 2, flashsize); 1016 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1017 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1018 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1019 g_free(nodename); 1020 1021 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1022 qemu_fdt_add_subnode(vms->fdt, nodename); 1023 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1024 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1025 2, flashbase + flashsize, 2, flashsize); 1026 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1027 g_free(nodename); 1028 } 1029 } 1030 1031 static bool virt_firmware_init(VirtMachineState *vms, 1032 MemoryRegion *sysmem, 1033 MemoryRegion *secure_sysmem) 1034 { 1035 int i; 1036 BlockBackend *pflash_blk0; 1037 1038 /* Map legacy -drive if=pflash to machine properties */ 1039 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1040 pflash_cfi01_legacy_drive(vms->flash[i], 1041 drive_get(IF_PFLASH, 0, i)); 1042 } 1043 1044 virt_flash_map(vms, sysmem, secure_sysmem); 1045 1046 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1047 1048 if (bios_name) { 1049 char *fname; 1050 MemoryRegion *mr; 1051 int image_size; 1052 1053 if (pflash_blk0) { 1054 error_report("The contents of the first flash device may be " 1055 "specified with -bios or with -drive if=pflash... " 1056 "but you cannot use both options at once"); 1057 exit(1); 1058 } 1059 1060 /* Fall back to -bios */ 1061 1062 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1063 if (!fname) { 1064 error_report("Could not find ROM image '%s'", bios_name); 1065 exit(1); 1066 } 1067 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1068 image_size = load_image_mr(fname, mr); 1069 g_free(fname); 1070 if (image_size < 0) { 1071 error_report("Could not load ROM image '%s'", bios_name); 1072 exit(1); 1073 } 1074 } 1075 1076 return pflash_blk0 || bios_name; 1077 } 1078 1079 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1080 { 1081 MachineState *ms = MACHINE(vms); 1082 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1083 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1084 FWCfgState *fw_cfg; 1085 char *nodename; 1086 1087 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1088 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1089 1090 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1091 qemu_fdt_add_subnode(vms->fdt, nodename); 1092 qemu_fdt_setprop_string(vms->fdt, nodename, 1093 "compatible", "qemu,fw-cfg-mmio"); 1094 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1095 2, base, 2, size); 1096 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1097 g_free(nodename); 1098 return fw_cfg; 1099 } 1100 1101 static void create_pcie_irq_map(const VirtMachineState *vms, 1102 uint32_t gic_phandle, 1103 int first_irq, const char *nodename) 1104 { 1105 int devfn, pin; 1106 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1107 uint32_t *irq_map = full_irq_map; 1108 1109 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1110 for (pin = 0; pin < 4; pin++) { 1111 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1112 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1113 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1114 int i; 1115 1116 uint32_t map[] = { 1117 devfn << 8, 0, 0, /* devfn */ 1118 pin + 1, /* PCI pin */ 1119 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1120 1121 /* Convert map to big endian */ 1122 for (i = 0; i < 10; i++) { 1123 irq_map[i] = cpu_to_be32(map[i]); 1124 } 1125 irq_map += 10; 1126 } 1127 } 1128 1129 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1130 full_irq_map, sizeof(full_irq_map)); 1131 1132 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1133 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1134 0x7 /* PCI irq */); 1135 } 1136 1137 static void create_smmu(const VirtMachineState *vms, 1138 PCIBus *bus) 1139 { 1140 char *node; 1141 const char compat[] = "arm,smmu-v3"; 1142 int irq = vms->irqmap[VIRT_SMMU]; 1143 int i; 1144 hwaddr base = vms->memmap[VIRT_SMMU].base; 1145 hwaddr size = vms->memmap[VIRT_SMMU].size; 1146 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1147 DeviceState *dev; 1148 1149 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1150 return; 1151 } 1152 1153 dev = qdev_create(NULL, "arm-smmuv3"); 1154 1155 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1156 &error_abort); 1157 qdev_init_nofail(dev); 1158 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1159 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1160 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1161 qdev_get_gpio_in(vms->gic, irq + i)); 1162 } 1163 1164 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1165 qemu_fdt_add_subnode(vms->fdt, node); 1166 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1167 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1168 1169 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1170 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1171 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1172 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1173 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1174 1175 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1176 sizeof(irq_names)); 1177 1178 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1179 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1180 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1181 1182 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1183 1184 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1185 g_free(node); 1186 } 1187 1188 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms, Error **errp) 1189 { 1190 const char compat[] = "virtio,pci-iommu"; 1191 uint16_t bdf = vms->virtio_iommu_bdf; 1192 char *node; 1193 1194 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1195 1196 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1197 qemu_fdt_add_subnode(vms->fdt, node); 1198 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1199 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 1200 1, bdf << 8, 1, 0, 1, 0, 1201 1, 0, 1, 0); 1202 1203 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1204 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1205 g_free(node); 1206 1207 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map", 1208 0x0, vms->iommu_phandle, 0x0, bdf, 1209 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1210 } 1211 1212 static void create_pcie(VirtMachineState *vms) 1213 { 1214 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1215 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1216 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1217 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1218 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1219 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1220 hwaddr base_ecam, size_ecam; 1221 hwaddr base = base_mmio; 1222 int nr_pcie_buses; 1223 int irq = vms->irqmap[VIRT_PCIE]; 1224 MemoryRegion *mmio_alias; 1225 MemoryRegion *mmio_reg; 1226 MemoryRegion *ecam_alias; 1227 MemoryRegion *ecam_reg; 1228 DeviceState *dev; 1229 char *nodename; 1230 int i, ecam_id; 1231 PCIHostState *pci; 1232 1233 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1234 qdev_init_nofail(dev); 1235 1236 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1237 base_ecam = vms->memmap[ecam_id].base; 1238 size_ecam = vms->memmap[ecam_id].size; 1239 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1240 /* Map only the first size_ecam bytes of ECAM space */ 1241 ecam_alias = g_new0(MemoryRegion, 1); 1242 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1243 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1244 ecam_reg, 0, size_ecam); 1245 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1246 1247 /* Map the MMIO window into system address space so as to expose 1248 * the section of PCI MMIO space which starts at the same base address 1249 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1250 * the window). 1251 */ 1252 mmio_alias = g_new0(MemoryRegion, 1); 1253 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1254 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1255 mmio_reg, base_mmio, size_mmio); 1256 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1257 1258 if (vms->highmem) { 1259 /* Map high MMIO space */ 1260 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1261 1262 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1263 mmio_reg, base_mmio_high, size_mmio_high); 1264 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1265 high_mmio_alias); 1266 } 1267 1268 /* Map IO port space */ 1269 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1270 1271 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1272 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1273 qdev_get_gpio_in(vms->gic, irq + i)); 1274 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1275 } 1276 1277 pci = PCI_HOST_BRIDGE(dev); 1278 if (pci->bus) { 1279 for (i = 0; i < nb_nics; i++) { 1280 NICInfo *nd = &nd_table[i]; 1281 1282 if (!nd->model) { 1283 nd->model = g_strdup("virtio"); 1284 } 1285 1286 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1287 } 1288 } 1289 1290 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1291 qemu_fdt_add_subnode(vms->fdt, nodename); 1292 qemu_fdt_setprop_string(vms->fdt, nodename, 1293 "compatible", "pci-host-ecam-generic"); 1294 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1295 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1296 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1297 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1298 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1299 nr_pcie_buses - 1); 1300 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1301 1302 if (vms->msi_phandle) { 1303 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1304 vms->msi_phandle); 1305 } 1306 1307 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1308 2, base_ecam, 2, size_ecam); 1309 1310 if (vms->highmem) { 1311 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1312 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1313 2, base_pio, 2, size_pio, 1314 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1315 2, base_mmio, 2, size_mmio, 1316 1, FDT_PCI_RANGE_MMIO_64BIT, 1317 2, base_mmio_high, 1318 2, base_mmio_high, 2, size_mmio_high); 1319 } else { 1320 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1321 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1322 2, base_pio, 2, size_pio, 1323 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1324 2, base_mmio, 2, size_mmio); 1325 } 1326 1327 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1328 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1329 1330 if (vms->iommu) { 1331 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1332 1333 switch (vms->iommu) { 1334 case VIRT_IOMMU_SMMUV3: 1335 create_smmu(vms, pci->bus); 1336 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1337 0x0, vms->iommu_phandle, 0x0, 0x10000); 1338 break; 1339 default: 1340 g_assert_not_reached(); 1341 } 1342 } 1343 } 1344 1345 static void create_platform_bus(VirtMachineState *vms) 1346 { 1347 DeviceState *dev; 1348 SysBusDevice *s; 1349 int i; 1350 MemoryRegion *sysmem = get_system_memory(); 1351 1352 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1353 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1354 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1355 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1356 qdev_init_nofail(dev); 1357 vms->platform_bus_dev = dev; 1358 1359 s = SYS_BUS_DEVICE(dev); 1360 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1361 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1362 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1363 } 1364 1365 memory_region_add_subregion(sysmem, 1366 vms->memmap[VIRT_PLATFORM_BUS].base, 1367 sysbus_mmio_get_region(s, 0)); 1368 } 1369 1370 static void create_secure_ram(VirtMachineState *vms, 1371 MemoryRegion *secure_sysmem) 1372 { 1373 MemoryRegion *secram = g_new(MemoryRegion, 1); 1374 char *nodename; 1375 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1376 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1377 1378 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1379 &error_fatal); 1380 memory_region_add_subregion(secure_sysmem, base, secram); 1381 1382 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1383 qemu_fdt_add_subnode(vms->fdt, nodename); 1384 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1385 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1386 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1387 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1388 1389 g_free(nodename); 1390 } 1391 1392 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1393 { 1394 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1395 bootinfo); 1396 1397 *fdt_size = board->fdt_size; 1398 return board->fdt; 1399 } 1400 1401 static void virt_build_smbios(VirtMachineState *vms) 1402 { 1403 MachineClass *mc = MACHINE_GET_CLASS(vms); 1404 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1405 uint8_t *smbios_tables, *smbios_anchor; 1406 size_t smbios_tables_len, smbios_anchor_len; 1407 const char *product = "QEMU Virtual Machine"; 1408 1409 if (kvm_enabled()) { 1410 product = "KVM Virtual Machine"; 1411 } 1412 1413 smbios_set_defaults("QEMU", product, 1414 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1415 true, SMBIOS_ENTRY_POINT_30); 1416 1417 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, 1418 &smbios_anchor, &smbios_anchor_len); 1419 1420 if (smbios_anchor) { 1421 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1422 smbios_tables, smbios_tables_len); 1423 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1424 smbios_anchor, smbios_anchor_len); 1425 } 1426 } 1427 1428 static 1429 void virt_machine_done(Notifier *notifier, void *data) 1430 { 1431 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1432 machine_done); 1433 MachineState *ms = MACHINE(vms); 1434 ARMCPU *cpu = ARM_CPU(first_cpu); 1435 struct arm_boot_info *info = &vms->bootinfo; 1436 AddressSpace *as = arm_boot_address_space(cpu, info); 1437 1438 /* 1439 * If the user provided a dtb, we assume the dynamic sysbus nodes 1440 * already are integrated there. This corresponds to a use case where 1441 * the dynamic sysbus nodes are complex and their generation is not yet 1442 * supported. In that case the user can take charge of the guest dt 1443 * while qemu takes charge of the qom stuff. 1444 */ 1445 if (info->dtb_filename == NULL) { 1446 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1447 vms->memmap[VIRT_PLATFORM_BUS].base, 1448 vms->memmap[VIRT_PLATFORM_BUS].size, 1449 vms->irqmap[VIRT_PLATFORM_BUS]); 1450 } 1451 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1452 exit(1); 1453 } 1454 1455 virt_acpi_setup(vms); 1456 virt_build_smbios(vms); 1457 } 1458 1459 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1460 { 1461 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1462 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1463 1464 if (!vmc->disallow_affinity_adjustment) { 1465 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1466 * GIC's target-list limitations. 32-bit KVM hosts currently 1467 * always create clusters of 4 CPUs, but that is expected to 1468 * change when they gain support for gicv3. When KVM is enabled 1469 * it will override the changes we make here, therefore our 1470 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1471 * and to improve SGI efficiency. 1472 */ 1473 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1474 clustersz = GICV3_TARGETLIST_BITS; 1475 } else { 1476 clustersz = GIC_TARGETLIST_BITS; 1477 } 1478 } 1479 return arm_cpu_mp_affinity(idx, clustersz); 1480 } 1481 1482 static void virt_set_memmap(VirtMachineState *vms) 1483 { 1484 MachineState *ms = MACHINE(vms); 1485 hwaddr base, device_memory_base, device_memory_size; 1486 int i; 1487 1488 vms->memmap = extended_memmap; 1489 1490 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1491 vms->memmap[i] = base_memmap[i]; 1492 } 1493 1494 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1495 error_report("unsupported number of memory slots: %"PRIu64, 1496 ms->ram_slots); 1497 exit(EXIT_FAILURE); 1498 } 1499 1500 /* 1501 * We compute the base of the high IO region depending on the 1502 * amount of initial and device memory. The device memory start/size 1503 * is aligned on 1GiB. We never put the high IO region below 256GiB 1504 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1505 * The device region size assumes 1GiB page max alignment per slot. 1506 */ 1507 device_memory_base = 1508 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1509 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1510 1511 /* Base address of the high IO region */ 1512 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1513 if (base < device_memory_base) { 1514 error_report("maxmem/slots too huge"); 1515 exit(EXIT_FAILURE); 1516 } 1517 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1518 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1519 } 1520 1521 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1522 hwaddr size = extended_memmap[i].size; 1523 1524 base = ROUND_UP(base, size); 1525 vms->memmap[i].base = base; 1526 vms->memmap[i].size = size; 1527 base += size; 1528 } 1529 vms->highest_gpa = base - 1; 1530 if (device_memory_size > 0) { 1531 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1532 ms->device_memory->base = device_memory_base; 1533 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1534 "device-memory", device_memory_size); 1535 } 1536 } 1537 1538 /* 1539 * finalize_gic_version - Determines the final gic_version 1540 * according to the gic-version property 1541 * 1542 * Default GIC type is v2 1543 */ 1544 static void finalize_gic_version(VirtMachineState *vms) 1545 { 1546 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1547 1548 if (kvm_enabled()) { 1549 int probe_bitmap; 1550 1551 if (!kvm_irqchip_in_kernel()) { 1552 switch (vms->gic_version) { 1553 case VIRT_GIC_VERSION_HOST: 1554 warn_report( 1555 "gic-version=host not relevant with kernel-irqchip=off " 1556 "as only userspace GICv2 is supported. Using v2 ..."); 1557 return; 1558 case VIRT_GIC_VERSION_MAX: 1559 case VIRT_GIC_VERSION_NOSEL: 1560 vms->gic_version = VIRT_GIC_VERSION_2; 1561 return; 1562 case VIRT_GIC_VERSION_2: 1563 return; 1564 case VIRT_GIC_VERSION_3: 1565 error_report( 1566 "gic-version=3 is not supported with kernel-irqchip=off"); 1567 exit(1); 1568 } 1569 } 1570 1571 probe_bitmap = kvm_arm_vgic_probe(); 1572 if (!probe_bitmap) { 1573 error_report("Unable to determine GIC version supported by host"); 1574 exit(1); 1575 } 1576 1577 switch (vms->gic_version) { 1578 case VIRT_GIC_VERSION_HOST: 1579 case VIRT_GIC_VERSION_MAX: 1580 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1581 vms->gic_version = VIRT_GIC_VERSION_3; 1582 } else { 1583 vms->gic_version = VIRT_GIC_VERSION_2; 1584 } 1585 return; 1586 case VIRT_GIC_VERSION_NOSEL: 1587 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1588 vms->gic_version = VIRT_GIC_VERSION_2; 1589 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1590 /* 1591 * in case the host does not support v2 in-kernel emulation or 1592 * the end-user requested more than 8 VCPUs we now default 1593 * to v3. In any case defaulting to v2 would be broken. 1594 */ 1595 vms->gic_version = VIRT_GIC_VERSION_3; 1596 } else if (max_cpus > GIC_NCPU) { 1597 error_report("host only supports in-kernel GICv2 emulation " 1598 "but more than 8 vcpus are requested"); 1599 exit(1); 1600 } 1601 break; 1602 case VIRT_GIC_VERSION_2: 1603 case VIRT_GIC_VERSION_3: 1604 break; 1605 } 1606 1607 /* Check chosen version is effectively supported by the host */ 1608 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1609 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1610 error_report("host does not support in-kernel GICv2 emulation"); 1611 exit(1); 1612 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1613 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1614 error_report("host does not support in-kernel GICv3 emulation"); 1615 exit(1); 1616 } 1617 return; 1618 } 1619 1620 /* TCG mode */ 1621 switch (vms->gic_version) { 1622 case VIRT_GIC_VERSION_NOSEL: 1623 vms->gic_version = VIRT_GIC_VERSION_2; 1624 break; 1625 case VIRT_GIC_VERSION_MAX: 1626 vms->gic_version = VIRT_GIC_VERSION_3; 1627 break; 1628 case VIRT_GIC_VERSION_HOST: 1629 error_report("gic-version=host requires KVM"); 1630 exit(1); 1631 case VIRT_GIC_VERSION_2: 1632 case VIRT_GIC_VERSION_3: 1633 break; 1634 } 1635 } 1636 1637 static void machvirt_init(MachineState *machine) 1638 { 1639 VirtMachineState *vms = VIRT_MACHINE(machine); 1640 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1641 MachineClass *mc = MACHINE_GET_CLASS(machine); 1642 const CPUArchIdList *possible_cpus; 1643 MemoryRegion *sysmem = get_system_memory(); 1644 MemoryRegion *secure_sysmem = NULL; 1645 int n, virt_max_cpus; 1646 bool firmware_loaded; 1647 bool aarch64 = true; 1648 bool has_ged = !vmc->no_ged; 1649 unsigned int smp_cpus = machine->smp.cpus; 1650 unsigned int max_cpus = machine->smp.max_cpus; 1651 1652 /* 1653 * In accelerated mode, the memory map is computed earlier in kvm_type() 1654 * to create a VM with the right number of IPA bits. 1655 */ 1656 if (!vms->memmap) { 1657 virt_set_memmap(vms); 1658 } 1659 1660 /* We can probe only here because during property set 1661 * KVM is not available yet 1662 */ 1663 finalize_gic_version(vms); 1664 1665 if (!cpu_type_valid(machine->cpu_type)) { 1666 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1667 exit(1); 1668 } 1669 1670 if (vms->secure) { 1671 if (kvm_enabled()) { 1672 error_report("mach-virt: KVM does not support Security extensions"); 1673 exit(1); 1674 } 1675 1676 /* 1677 * The Secure view of the world is the same as the NonSecure, 1678 * but with a few extra devices. Create it as a container region 1679 * containing the system memory at low priority; any secure-only 1680 * devices go in at higher priority and take precedence. 1681 */ 1682 secure_sysmem = g_new(MemoryRegion, 1); 1683 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1684 UINT64_MAX); 1685 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1686 } 1687 1688 firmware_loaded = virt_firmware_init(vms, sysmem, 1689 secure_sysmem ?: sysmem); 1690 1691 /* If we have an EL3 boot ROM then the assumption is that it will 1692 * implement PSCI itself, so disable QEMU's internal implementation 1693 * so it doesn't get in the way. Instead of starting secondary 1694 * CPUs in PSCI powerdown state we will start them all running and 1695 * let the boot ROM sort them out. 1696 * The usual case is that we do use QEMU's PSCI implementation; 1697 * if the guest has EL2 then we will use SMC as the conduit, 1698 * and otherwise we will use HVC (for backwards compatibility and 1699 * because if we're using KVM then we must use HVC). 1700 */ 1701 if (vms->secure && firmware_loaded) { 1702 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1703 } else if (vms->virt) { 1704 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1705 } else { 1706 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1707 } 1708 1709 /* The maximum number of CPUs depends on the GIC version, or on how 1710 * many redistributors we can fit into the memory map. 1711 */ 1712 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1713 virt_max_cpus = 1714 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1715 virt_max_cpus += 1716 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1717 } else { 1718 virt_max_cpus = GIC_NCPU; 1719 } 1720 1721 if (max_cpus > virt_max_cpus) { 1722 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1723 "supported by machine 'mach-virt' (%d)", 1724 max_cpus, virt_max_cpus); 1725 exit(1); 1726 } 1727 1728 vms->smp_cpus = smp_cpus; 1729 1730 if (vms->virt && kvm_enabled()) { 1731 error_report("mach-virt: KVM does not support providing " 1732 "Virtualization extensions to the guest CPU"); 1733 exit(1); 1734 } 1735 1736 create_fdt(vms); 1737 1738 possible_cpus = mc->possible_cpu_arch_ids(machine); 1739 for (n = 0; n < possible_cpus->len; n++) { 1740 Object *cpuobj; 1741 CPUState *cs; 1742 1743 if (n >= smp_cpus) { 1744 break; 1745 } 1746 1747 cpuobj = object_new(possible_cpus->cpus[n].type); 1748 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1749 "mp-affinity", NULL); 1750 1751 cs = CPU(cpuobj); 1752 cs->cpu_index = n; 1753 1754 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1755 &error_fatal); 1756 1757 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1758 1759 if (!vms->secure) { 1760 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1761 } 1762 1763 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1764 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1765 } 1766 1767 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1768 object_property_set_int(cpuobj, vms->psci_conduit, 1769 "psci-conduit", NULL); 1770 1771 /* Secondary CPUs start in PSCI powered-down state */ 1772 if (n > 0) { 1773 object_property_set_bool(cpuobj, true, 1774 "start-powered-off", NULL); 1775 } 1776 } 1777 1778 if (vmc->kvm_no_adjvtime && 1779 object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { 1780 object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); 1781 } 1782 1783 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1784 object_property_set_bool(cpuobj, false, "pmu", NULL); 1785 } 1786 1787 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1788 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1789 "reset-cbar", &error_abort); 1790 } 1791 1792 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1793 &error_abort); 1794 if (vms->secure) { 1795 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1796 "secure-memory", &error_abort); 1797 } 1798 1799 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1800 object_unref(cpuobj); 1801 } 1802 fdt_add_timer_nodes(vms); 1803 fdt_add_cpu_nodes(vms); 1804 1805 if (!kvm_enabled()) { 1806 ARMCPU *cpu = ARM_CPU(first_cpu); 1807 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1808 1809 if (aarch64 && vms->highmem) { 1810 int requested_pa_size, pamax = arm_pamax(cpu); 1811 1812 requested_pa_size = 64 - clz64(vms->highest_gpa); 1813 if (pamax < requested_pa_size) { 1814 error_report("VCPU supports less PA bits (%d) than requested " 1815 "by the memory map (%d)", pamax, requested_pa_size); 1816 exit(1); 1817 } 1818 } 1819 } 1820 1821 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 1822 machine->ram); 1823 if (machine->device_memory) { 1824 memory_region_add_subregion(sysmem, machine->device_memory->base, 1825 &machine->device_memory->mr); 1826 } 1827 1828 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 1829 1830 create_gic(vms); 1831 1832 fdt_add_pmu_nodes(vms); 1833 1834 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 1835 1836 if (vms->secure) { 1837 create_secure_ram(vms, secure_sysmem); 1838 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1839 } 1840 1841 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1842 1843 create_rtc(vms); 1844 1845 create_pcie(vms); 1846 1847 if (has_ged && aarch64 && firmware_loaded && acpi_enabled) { 1848 vms->acpi_dev = create_acpi_ged(vms); 1849 } else { 1850 create_gpio(vms); 1851 } 1852 1853 /* connect powerdown request */ 1854 vms->powerdown_notifier.notify = virt_powerdown_req; 1855 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 1856 1857 /* Create mmio transports, so the user can create virtio backends 1858 * (which will be automatically plugged in to the transports). If 1859 * no backend is created the transport will just sit harmlessly idle. 1860 */ 1861 create_virtio_devices(vms); 1862 1863 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1864 rom_set_fw(vms->fw_cfg); 1865 1866 create_platform_bus(vms); 1867 1868 vms->bootinfo.ram_size = machine->ram_size; 1869 vms->bootinfo.nb_cpus = smp_cpus; 1870 vms->bootinfo.board_id = -1; 1871 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1872 vms->bootinfo.get_dtb = machvirt_dtb; 1873 vms->bootinfo.skip_dtb_autoload = true; 1874 vms->bootinfo.firmware_loaded = firmware_loaded; 1875 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 1876 1877 vms->machine_done.notify = virt_machine_done; 1878 qemu_add_machine_init_done_notifier(&vms->machine_done); 1879 } 1880 1881 static bool virt_get_secure(Object *obj, Error **errp) 1882 { 1883 VirtMachineState *vms = VIRT_MACHINE(obj); 1884 1885 return vms->secure; 1886 } 1887 1888 static void virt_set_secure(Object *obj, bool value, Error **errp) 1889 { 1890 VirtMachineState *vms = VIRT_MACHINE(obj); 1891 1892 vms->secure = value; 1893 } 1894 1895 static bool virt_get_virt(Object *obj, Error **errp) 1896 { 1897 VirtMachineState *vms = VIRT_MACHINE(obj); 1898 1899 return vms->virt; 1900 } 1901 1902 static void virt_set_virt(Object *obj, bool value, Error **errp) 1903 { 1904 VirtMachineState *vms = VIRT_MACHINE(obj); 1905 1906 vms->virt = value; 1907 } 1908 1909 static bool virt_get_highmem(Object *obj, Error **errp) 1910 { 1911 VirtMachineState *vms = VIRT_MACHINE(obj); 1912 1913 return vms->highmem; 1914 } 1915 1916 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1917 { 1918 VirtMachineState *vms = VIRT_MACHINE(obj); 1919 1920 vms->highmem = value; 1921 } 1922 1923 static bool virt_get_its(Object *obj, Error **errp) 1924 { 1925 VirtMachineState *vms = VIRT_MACHINE(obj); 1926 1927 return vms->its; 1928 } 1929 1930 static void virt_set_its(Object *obj, bool value, Error **errp) 1931 { 1932 VirtMachineState *vms = VIRT_MACHINE(obj); 1933 1934 vms->its = value; 1935 } 1936 1937 static char *virt_get_gic_version(Object *obj, Error **errp) 1938 { 1939 VirtMachineState *vms = VIRT_MACHINE(obj); 1940 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; 1941 1942 return g_strdup(val); 1943 } 1944 1945 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1946 { 1947 VirtMachineState *vms = VIRT_MACHINE(obj); 1948 1949 if (!strcmp(value, "3")) { 1950 vms->gic_version = VIRT_GIC_VERSION_3; 1951 } else if (!strcmp(value, "2")) { 1952 vms->gic_version = VIRT_GIC_VERSION_2; 1953 } else if (!strcmp(value, "host")) { 1954 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 1955 } else if (!strcmp(value, "max")) { 1956 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 1957 } else { 1958 error_setg(errp, "Invalid gic-version value"); 1959 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1960 } 1961 } 1962 1963 static char *virt_get_iommu(Object *obj, Error **errp) 1964 { 1965 VirtMachineState *vms = VIRT_MACHINE(obj); 1966 1967 switch (vms->iommu) { 1968 case VIRT_IOMMU_NONE: 1969 return g_strdup("none"); 1970 case VIRT_IOMMU_SMMUV3: 1971 return g_strdup("smmuv3"); 1972 default: 1973 g_assert_not_reached(); 1974 } 1975 } 1976 1977 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1978 { 1979 VirtMachineState *vms = VIRT_MACHINE(obj); 1980 1981 if (!strcmp(value, "smmuv3")) { 1982 vms->iommu = VIRT_IOMMU_SMMUV3; 1983 } else if (!strcmp(value, "none")) { 1984 vms->iommu = VIRT_IOMMU_NONE; 1985 } else { 1986 error_setg(errp, "Invalid iommu value"); 1987 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1988 } 1989 } 1990 1991 static CpuInstanceProperties 1992 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1993 { 1994 MachineClass *mc = MACHINE_GET_CLASS(ms); 1995 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1996 1997 assert(cpu_index < possible_cpus->len); 1998 return possible_cpus->cpus[cpu_index].props; 1999 } 2000 2001 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2002 { 2003 return idx % ms->numa_state->num_nodes; 2004 } 2005 2006 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2007 { 2008 int n; 2009 unsigned int max_cpus = ms->smp.max_cpus; 2010 VirtMachineState *vms = VIRT_MACHINE(ms); 2011 2012 if (ms->possible_cpus) { 2013 assert(ms->possible_cpus->len == max_cpus); 2014 return ms->possible_cpus; 2015 } 2016 2017 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2018 sizeof(CPUArchId) * max_cpus); 2019 ms->possible_cpus->len = max_cpus; 2020 for (n = 0; n < ms->possible_cpus->len; n++) { 2021 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2022 ms->possible_cpus->cpus[n].arch_id = 2023 virt_cpu_mp_affinity(vms, n); 2024 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2025 ms->possible_cpus->cpus[n].props.thread_id = n; 2026 } 2027 return ms->possible_cpus; 2028 } 2029 2030 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2031 Error **errp) 2032 { 2033 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2034 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2035 2036 if (is_nvdimm) { 2037 error_setg(errp, "nvdimm is not yet supported"); 2038 return; 2039 } 2040 2041 if (!vms->acpi_dev) { 2042 error_setg(errp, 2043 "memory hotplug is not enabled: missing acpi-ged device"); 2044 return; 2045 } 2046 2047 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2048 } 2049 2050 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2051 DeviceState *dev, Error **errp) 2052 { 2053 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2054 Error *local_err = NULL; 2055 2056 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err); 2057 if (local_err) { 2058 goto out; 2059 } 2060 2061 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2062 dev, &error_abort); 2063 2064 out: 2065 error_propagate(errp, local_err); 2066 } 2067 2068 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2069 DeviceState *dev, Error **errp) 2070 { 2071 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2072 virt_memory_pre_plug(hotplug_dev, dev, errp); 2073 } 2074 } 2075 2076 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2077 DeviceState *dev, Error **errp) 2078 { 2079 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2080 2081 if (vms->platform_bus_dev) { 2082 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 2083 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2084 SYS_BUS_DEVICE(dev)); 2085 } 2086 } 2087 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2088 virt_memory_plug(hotplug_dev, dev, errp); 2089 } 2090 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2091 PCIDevice *pdev = PCI_DEVICE(dev); 2092 2093 vms->iommu = VIRT_IOMMU_VIRTIO; 2094 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2095 create_virtio_iommu_dt_bindings(vms, errp); 2096 } 2097 } 2098 2099 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2100 DeviceState *dev, Error **errp) 2101 { 2102 error_setg(errp, "device unplug request for unsupported device" 2103 " type: %s", object_get_typename(OBJECT(dev))); 2104 } 2105 2106 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2107 DeviceState *dev) 2108 { 2109 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) || 2110 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { 2111 return HOTPLUG_HANDLER(machine); 2112 } 2113 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2114 VirtMachineState *vms = VIRT_MACHINE(machine); 2115 2116 if (!vms->bootinfo.firmware_loaded || !acpi_enabled) { 2117 return HOTPLUG_HANDLER(machine); 2118 } 2119 } 2120 return NULL; 2121 } 2122 2123 /* 2124 * for arm64 kvm_type [7-0] encodes the requested number of bits 2125 * in the IPA address space 2126 */ 2127 static int virt_kvm_type(MachineState *ms, const char *type_str) 2128 { 2129 VirtMachineState *vms = VIRT_MACHINE(ms); 2130 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 2131 int requested_pa_size; 2132 2133 /* we freeze the memory map to compute the highest gpa */ 2134 virt_set_memmap(vms); 2135 2136 requested_pa_size = 64 - clz64(vms->highest_gpa); 2137 2138 if (requested_pa_size > max_vm_pa_size) { 2139 error_report("-m and ,maxmem option values " 2140 "require an IPA range (%d bits) larger than " 2141 "the one supported by the host (%d bits)", 2142 requested_pa_size, max_vm_pa_size); 2143 exit(1); 2144 } 2145 /* 2146 * By default we return 0 which corresponds to an implicit legacy 2147 * 40b IPA setting. Otherwise we return the actual requested PA 2148 * logsize 2149 */ 2150 return requested_pa_size > 40 ? requested_pa_size : 0; 2151 } 2152 2153 static void virt_machine_class_init(ObjectClass *oc, void *data) 2154 { 2155 MachineClass *mc = MACHINE_CLASS(oc); 2156 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2157 2158 mc->init = machvirt_init; 2159 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2160 * The value may be reduced later when we have more information about the 2161 * configuration of the particular instance. 2162 */ 2163 mc->max_cpus = 512; 2164 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2165 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2166 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2167 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2168 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2169 mc->block_default_type = IF_VIRTIO; 2170 mc->no_cdrom = 1; 2171 mc->pci_allow_0_address = true; 2172 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2173 mc->minimum_page_bits = 12; 2174 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2175 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2176 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2177 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2178 mc->kvm_type = virt_kvm_type; 2179 assert(!mc->get_hotplug_handler); 2180 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2181 hc->pre_plug = virt_machine_device_pre_plug_cb; 2182 hc->plug = virt_machine_device_plug_cb; 2183 hc->unplug_request = virt_machine_device_unplug_request_cb; 2184 mc->numa_mem_supported = true; 2185 mc->auto_enable_numa_with_memhp = true; 2186 mc->default_ram_id = "mach-virt.ram"; 2187 } 2188 2189 static void virt_instance_init(Object *obj) 2190 { 2191 VirtMachineState *vms = VIRT_MACHINE(obj); 2192 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2193 2194 /* EL3 is disabled by default on virt: this makes us consistent 2195 * between KVM and TCG for this board, and it also allows us to 2196 * boot UEFI blobs which assume no TrustZone support. 2197 */ 2198 vms->secure = false; 2199 object_property_add_bool(obj, "secure", virt_get_secure, 2200 virt_set_secure, NULL); 2201 object_property_set_description(obj, "secure", 2202 "Set on/off to enable/disable the ARM " 2203 "Security Extensions (TrustZone)", 2204 NULL); 2205 2206 /* EL2 is also disabled by default, for similar reasons */ 2207 vms->virt = false; 2208 object_property_add_bool(obj, "virtualization", virt_get_virt, 2209 virt_set_virt, NULL); 2210 object_property_set_description(obj, "virtualization", 2211 "Set on/off to enable/disable emulating a " 2212 "guest CPU which implements the ARM " 2213 "Virtualization Extensions", 2214 NULL); 2215 2216 /* High memory is enabled by default */ 2217 vms->highmem = true; 2218 object_property_add_bool(obj, "highmem", virt_get_highmem, 2219 virt_set_highmem, NULL); 2220 object_property_set_description(obj, "highmem", 2221 "Set on/off to enable/disable using " 2222 "physical address space above 32 bits", 2223 NULL); 2224 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 2225 object_property_add_str(obj, "gic-version", virt_get_gic_version, 2226 virt_set_gic_version, NULL); 2227 object_property_set_description(obj, "gic-version", 2228 "Set GIC version. " 2229 "Valid values are 2, 3, host and max", 2230 NULL); 2231 2232 vms->highmem_ecam = !vmc->no_highmem_ecam; 2233 2234 if (vmc->no_its) { 2235 vms->its = false; 2236 } else { 2237 /* Default allows ITS instantiation */ 2238 vms->its = true; 2239 object_property_add_bool(obj, "its", virt_get_its, 2240 virt_set_its, NULL); 2241 object_property_set_description(obj, "its", 2242 "Set on/off to enable/disable " 2243 "ITS instantiation", 2244 NULL); 2245 } 2246 2247 /* Default disallows iommu instantiation */ 2248 vms->iommu = VIRT_IOMMU_NONE; 2249 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 2250 object_property_set_description(obj, "iommu", 2251 "Set the IOMMU type. " 2252 "Valid values are none and smmuv3", 2253 NULL); 2254 2255 vms->irqmap = a15irqmap; 2256 2257 virt_flash_create(vms); 2258 } 2259 2260 static const TypeInfo virt_machine_info = { 2261 .name = TYPE_VIRT_MACHINE, 2262 .parent = TYPE_MACHINE, 2263 .abstract = true, 2264 .instance_size = sizeof(VirtMachineState), 2265 .class_size = sizeof(VirtMachineClass), 2266 .class_init = virt_machine_class_init, 2267 .instance_init = virt_instance_init, 2268 .interfaces = (InterfaceInfo[]) { 2269 { TYPE_HOTPLUG_HANDLER }, 2270 { } 2271 }, 2272 }; 2273 2274 static void machvirt_machine_init(void) 2275 { 2276 type_register_static(&virt_machine_info); 2277 } 2278 type_init(machvirt_machine_init); 2279 2280 static void virt_machine_5_0_options(MachineClass *mc) 2281 { 2282 static GlobalProperty compat[] = { 2283 { TYPE_TPM_TIS_SYSBUS, "ppi", "false" }, 2284 }; 2285 2286 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 2287 } 2288 DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) 2289 2290 static void virt_machine_4_2_options(MachineClass *mc) 2291 { 2292 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2293 2294 virt_machine_5_0_options(mc); 2295 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 2296 vmc->kvm_no_adjvtime = true; 2297 } 2298 DEFINE_VIRT_MACHINE(4, 2) 2299 2300 static void virt_machine_4_1_options(MachineClass *mc) 2301 { 2302 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2303 2304 virt_machine_4_2_options(mc); 2305 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 2306 vmc->no_ged = true; 2307 mc->auto_enable_numa_with_memhp = false; 2308 } 2309 DEFINE_VIRT_MACHINE(4, 1) 2310 2311 static void virt_machine_4_0_options(MachineClass *mc) 2312 { 2313 virt_machine_4_1_options(mc); 2314 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2315 } 2316 DEFINE_VIRT_MACHINE(4, 0) 2317 2318 static void virt_machine_3_1_options(MachineClass *mc) 2319 { 2320 virt_machine_4_0_options(mc); 2321 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2322 } 2323 DEFINE_VIRT_MACHINE(3, 1) 2324 2325 static void virt_machine_3_0_options(MachineClass *mc) 2326 { 2327 virt_machine_3_1_options(mc); 2328 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2329 } 2330 DEFINE_VIRT_MACHINE(3, 0) 2331 2332 static void virt_machine_2_12_options(MachineClass *mc) 2333 { 2334 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2335 2336 virt_machine_3_0_options(mc); 2337 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2338 vmc->no_highmem_ecam = true; 2339 mc->max_cpus = 255; 2340 } 2341 DEFINE_VIRT_MACHINE(2, 12) 2342 2343 static void virt_machine_2_11_options(MachineClass *mc) 2344 { 2345 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2346 2347 virt_machine_2_12_options(mc); 2348 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2349 vmc->smbios_old_sys_ver = true; 2350 } 2351 DEFINE_VIRT_MACHINE(2, 11) 2352 2353 static void virt_machine_2_10_options(MachineClass *mc) 2354 { 2355 virt_machine_2_11_options(mc); 2356 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2357 /* before 2.11 we never faulted accesses to bad addresses */ 2358 mc->ignore_memory_transaction_failures = true; 2359 } 2360 DEFINE_VIRT_MACHINE(2, 10) 2361 2362 static void virt_machine_2_9_options(MachineClass *mc) 2363 { 2364 virt_machine_2_10_options(mc); 2365 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2366 } 2367 DEFINE_VIRT_MACHINE(2, 9) 2368 2369 static void virt_machine_2_8_options(MachineClass *mc) 2370 { 2371 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2372 2373 virt_machine_2_9_options(mc); 2374 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2375 /* For 2.8 and earlier we falsely claimed in the DT that 2376 * our timers were edge-triggered, not level-triggered. 2377 */ 2378 vmc->claim_edge_triggered_timers = true; 2379 } 2380 DEFINE_VIRT_MACHINE(2, 8) 2381 2382 static void virt_machine_2_7_options(MachineClass *mc) 2383 { 2384 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2385 2386 virt_machine_2_8_options(mc); 2387 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2388 /* ITS was introduced with 2.8 */ 2389 vmc->no_its = true; 2390 /* Stick with 1K pages for migration compatibility */ 2391 mc->minimum_page_bits = 0; 2392 } 2393 DEFINE_VIRT_MACHINE(2, 7) 2394 2395 static void virt_machine_2_6_options(MachineClass *mc) 2396 { 2397 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2398 2399 virt_machine_2_7_options(mc); 2400 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2401 vmc->disallow_affinity_adjustment = true; 2402 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2403 vmc->no_pmu = true; 2404 } 2405 DEFINE_VIRT_MACHINE(2, 6) 2406