1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/primecell.h" 40 #include "hw/arm/virt.h" 41 #include "hw/block/flash.h" 42 #include "hw/vfio/vfio-calxeda-xgmac.h" 43 #include "hw/vfio/vfio-amd-xgbe.h" 44 #include "hw/display/ramfb.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/tpm.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "hw/loader.h" 53 #include "qapi/error.h" 54 #include "qemu/bitops.h" 55 #include "qemu/error-report.h" 56 #include "qemu/module.h" 57 #include "hw/pci-host/gpex.h" 58 #include "hw/virtio/virtio-pci.h" 59 #include "hw/core/sysbus-fdt.h" 60 #include "hw/platform-bus.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/arm/fdt.h" 63 #include "hw/intc/arm_gic.h" 64 #include "hw/intc/arm_gicv3_common.h" 65 #include "hw/irq.h" 66 #include "kvm_arm.h" 67 #include "hw/firmware/smbios.h" 68 #include "qapi/visitor.h" 69 #include "qapi/qapi-visit-common.h" 70 #include "standard-headers/linux/input.h" 71 #include "hw/arm/smmuv3.h" 72 #include "hw/acpi/acpi.h" 73 #include "target/arm/internals.h" 74 #include "hw/mem/memory-device.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-mem-pci.h" 79 #include "hw/virtio/virtio-iommu.h" 80 #include "hw/char/pl011.h" 81 #include "qemu/guest-random.h" 82 83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 85 void *data) \ 86 { \ 87 MachineClass *mc = MACHINE_CLASS(oc); \ 88 virt_machine_##major##_##minor##_options(mc); \ 89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 90 if (latest) { \ 91 mc->alias = "virt"; \ 92 } \ 93 } \ 94 static const TypeInfo machvirt_##major##_##minor##_info = { \ 95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 96 .parent = TYPE_VIRT_MACHINE, \ 97 .class_init = virt_##major##_##minor##_class_init, \ 98 }; \ 99 static void machvirt_machine_##major##_##minor##_init(void) \ 100 { \ 101 type_register_static(&machvirt_##major##_##minor##_info); \ 102 } \ 103 type_init(machvirt_machine_##major##_##minor##_init); 104 105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 107 #define DEFINE_VIRT_MACHINE(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 109 110 111 /* Number of external interrupt lines to configure the GIC with */ 112 #define NUM_IRQS 256 113 114 #define PLATFORM_BUS_NUM_IRQS 64 115 116 /* Legacy RAM limit in GB (< version 4.0) */ 117 #define LEGACY_RAMLIMIT_GB 255 118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 119 120 /* Addresses and sizes of our components. 121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 122 * 128MB..256MB is used for miscellaneous device I/O. 123 * 256MB..1GB is reserved for possible future PCI support (ie where the 124 * PCI memory window will go if we add a PCI host controller). 125 * 1GB and up is RAM (which may happily spill over into the 126 * high memory region beyond 4GB). 127 * This represents a compromise between how much RAM can be given to 128 * a 32 bit VM and leaving space for expansion and in particular for PCI. 129 * Note that devices should generally be placed at multiples of 0x10000, 130 * to accommodate guests using 64K pages. 131 */ 132 static const MemMapEntry base_memmap[] = { 133 /* Space up to 0x8000000 is reserved for a boot ROM */ 134 [VIRT_FLASH] = { 0, 0x08000000 }, 135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 144 /* This redistributor space allows up to 2*64kB*123 CPUs */ 145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 146 [VIRT_UART] = { 0x09000000, 0x00001000 }, 147 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 149 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 151 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 164 /* Actual RAM size depends on initial RAM and device memory settings */ 165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 166 }; 167 168 /* 169 * Highmem IO Regions: This memory map is floating, located after the RAM. 170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 171 * top of the RAM, so that its base get the same alignment as the size, 172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 174 * Note the extended_memmap is sized so that it eventually also includes the 175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 176 * index of base_memmap). 177 */ 178 static MemMapEntry extended_memmap[] = { 179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 180 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 181 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 182 /* Second PCIe window */ 183 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 184 }; 185 186 static const int a15irqmap[] = { 187 [VIRT_UART] = 1, 188 [VIRT_RTC] = 2, 189 [VIRT_PCIE] = 3, /* ... to 6 */ 190 [VIRT_GPIO] = 7, 191 [VIRT_SECURE_UART] = 8, 192 [VIRT_ACPI_GED] = 9, 193 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 194 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 195 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 196 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 197 }; 198 199 static const char *valid_cpus[] = { 200 ARM_CPU_TYPE_NAME("cortex-a7"), 201 ARM_CPU_TYPE_NAME("cortex-a15"), 202 ARM_CPU_TYPE_NAME("cortex-a53"), 203 ARM_CPU_TYPE_NAME("cortex-a57"), 204 ARM_CPU_TYPE_NAME("cortex-a72"), 205 ARM_CPU_TYPE_NAME("cortex-a76"), 206 ARM_CPU_TYPE_NAME("a64fx"), 207 ARM_CPU_TYPE_NAME("neoverse-n1"), 208 ARM_CPU_TYPE_NAME("host"), 209 ARM_CPU_TYPE_NAME("max"), 210 }; 211 212 static bool cpu_type_valid(const char *cpu) 213 { 214 int i; 215 216 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 217 if (strcmp(cpu, valid_cpus[i]) == 0) { 218 return true; 219 } 220 } 221 return false; 222 } 223 224 static void create_kaslr_seed(MachineState *ms, const char *node) 225 { 226 uint64_t seed; 227 228 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 229 return; 230 } 231 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed); 232 } 233 234 static void create_fdt(VirtMachineState *vms) 235 { 236 MachineState *ms = MACHINE(vms); 237 int nb_numa_nodes = ms->numa_state->num_nodes; 238 void *fdt = create_device_tree(&vms->fdt_size); 239 240 if (!fdt) { 241 error_report("create_device_tree() failed"); 242 exit(1); 243 } 244 245 ms->fdt = fdt; 246 247 /* Header */ 248 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 249 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 250 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 251 252 /* /chosen must exist for load_dtb to fill in necessary properties later */ 253 qemu_fdt_add_subnode(fdt, "/chosen"); 254 if (vms->dtb_kaslr_seed) { 255 create_kaslr_seed(ms, "/chosen"); 256 } 257 258 if (vms->secure) { 259 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 260 if (vms->dtb_kaslr_seed) { 261 create_kaslr_seed(ms, "/secure-chosen"); 262 } 263 } 264 265 /* Clock node, for the benefit of the UART. The kernel device tree 266 * binding documentation claims the PL011 node clock properties are 267 * optional but in practice if you omit them the kernel refuses to 268 * probe for the device. 269 */ 270 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 271 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 272 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 273 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 274 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 275 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 276 "clk24mhz"); 277 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 278 279 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 280 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 281 uint32_t *matrix = g_malloc0(size); 282 int idx, i, j; 283 284 for (i = 0; i < nb_numa_nodes; i++) { 285 for (j = 0; j < nb_numa_nodes; j++) { 286 idx = (i * nb_numa_nodes + j) * 3; 287 matrix[idx + 0] = cpu_to_be32(i); 288 matrix[idx + 1] = cpu_to_be32(j); 289 matrix[idx + 2] = 290 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 291 } 292 } 293 294 qemu_fdt_add_subnode(fdt, "/distance-map"); 295 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 296 "numa-distance-map-v1"); 297 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 298 matrix, size); 299 g_free(matrix); 300 } 301 } 302 303 static void fdt_add_timer_nodes(const VirtMachineState *vms) 304 { 305 /* On real hardware these interrupts are level-triggered. 306 * On KVM they were edge-triggered before host kernel version 4.4, 307 * and level-triggered afterwards. 308 * On emulated QEMU they are level-triggered. 309 * 310 * Getting the DTB info about them wrong is awkward for some 311 * guest kernels: 312 * pre-4.8 ignore the DT and leave the interrupt configured 313 * with whatever the GIC reset value (or the bootloader) left it at 314 * 4.8 before rc6 honour the incorrect data by programming it back 315 * into the GIC, causing problems 316 * 4.8rc6 and later ignore the DT and always write "level triggered" 317 * into the GIC 318 * 319 * For backwards-compatibility, virt-2.8 and earlier will continue 320 * to say these are edge-triggered, but later machines will report 321 * the correct information. 322 */ 323 ARMCPU *armcpu; 324 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 325 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 326 MachineState *ms = MACHINE(vms); 327 328 if (vmc->claim_edge_triggered_timers) { 329 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 330 } 331 332 if (vms->gic_version == VIRT_GIC_VERSION_2) { 333 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 334 GIC_FDT_IRQ_PPI_CPU_WIDTH, 335 (1 << MACHINE(vms)->smp.cpus) - 1); 336 } 337 338 qemu_fdt_add_subnode(ms->fdt, "/timer"); 339 340 armcpu = ARM_CPU(qemu_get_cpu(0)); 341 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 342 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 343 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 344 compat, sizeof(compat)); 345 } else { 346 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 347 "arm,armv7-timer"); 348 } 349 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 350 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 351 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 352 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 353 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 354 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 355 } 356 357 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 358 { 359 int cpu; 360 int addr_cells = 1; 361 const MachineState *ms = MACHINE(vms); 362 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 363 int smp_cpus = ms->smp.cpus; 364 365 /* 366 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 367 * On ARM v8 64-bit systems value should be set to 2, 368 * that corresponds to the MPIDR_EL1 register size. 369 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 370 * in the system, #address-cells can be set to 1, since 371 * MPIDR_EL1[63:32] bits are not used for CPUs 372 * identification. 373 * 374 * Here we actually don't know whether our system is 32- or 64-bit one. 375 * The simplest way to go is to examine affinity IDs of all our CPUs. If 376 * at least one of them has Aff3 populated, we set #address-cells to 2. 377 */ 378 for (cpu = 0; cpu < smp_cpus; cpu++) { 379 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 380 381 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 382 addr_cells = 2; 383 break; 384 } 385 } 386 387 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 388 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 389 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 390 391 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 392 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 393 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 394 CPUState *cs = CPU(armcpu); 395 396 qemu_fdt_add_subnode(ms->fdt, nodename); 397 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 398 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 399 armcpu->dtb_compatible); 400 401 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 402 qemu_fdt_setprop_string(ms->fdt, nodename, 403 "enable-method", "psci"); 404 } 405 406 if (addr_cells == 2) { 407 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 408 armcpu->mp_affinity); 409 } else { 410 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 411 armcpu->mp_affinity); 412 } 413 414 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 415 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 416 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 417 } 418 419 if (!vmc->no_cpu_topology) { 420 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 421 qemu_fdt_alloc_phandle(ms->fdt)); 422 } 423 424 g_free(nodename); 425 } 426 427 if (!vmc->no_cpu_topology) { 428 /* 429 * Add vCPU topology description through fdt node cpu-map. 430 * 431 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 432 * In a SMP system, the hierarchy of CPUs can be defined through 433 * four entities that are used to describe the layout of CPUs in 434 * the system: socket/cluster/core/thread. 435 * 436 * A socket node represents the boundary of system physical package 437 * and its child nodes must be one or more cluster nodes. A system 438 * can contain several layers of clustering within a single physical 439 * package and cluster nodes can be contained in parent cluster nodes. 440 * 441 * Note: currently we only support one layer of clustering within 442 * each physical package. 443 */ 444 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 445 446 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 447 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 448 char *map_path; 449 450 if (ms->smp.threads > 1) { 451 map_path = g_strdup_printf( 452 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 453 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 454 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 455 (cpu / ms->smp.threads) % ms->smp.cores, 456 cpu % ms->smp.threads); 457 } else { 458 map_path = g_strdup_printf( 459 "/cpus/cpu-map/socket%d/cluster%d/core%d", 460 cpu / (ms->smp.clusters * ms->smp.cores), 461 (cpu / ms->smp.cores) % ms->smp.clusters, 462 cpu % ms->smp.cores); 463 } 464 qemu_fdt_add_path(ms->fdt, map_path); 465 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 466 467 g_free(map_path); 468 g_free(cpu_path); 469 } 470 } 471 } 472 473 static void fdt_add_its_gic_node(VirtMachineState *vms) 474 { 475 char *nodename; 476 MachineState *ms = MACHINE(vms); 477 478 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 479 nodename = g_strdup_printf("/intc/its@%" PRIx64, 480 vms->memmap[VIRT_GIC_ITS].base); 481 qemu_fdt_add_subnode(ms->fdt, nodename); 482 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 483 "arm,gic-v3-its"); 484 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 485 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 486 2, vms->memmap[VIRT_GIC_ITS].base, 487 2, vms->memmap[VIRT_GIC_ITS].size); 488 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 489 g_free(nodename); 490 } 491 492 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 493 { 494 MachineState *ms = MACHINE(vms); 495 char *nodename; 496 497 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 498 vms->memmap[VIRT_GIC_V2M].base); 499 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 500 qemu_fdt_add_subnode(ms->fdt, nodename); 501 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 502 "arm,gic-v2m-frame"); 503 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 504 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 505 2, vms->memmap[VIRT_GIC_V2M].base, 506 2, vms->memmap[VIRT_GIC_V2M].size); 507 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 508 g_free(nodename); 509 } 510 511 static void fdt_add_gic_node(VirtMachineState *vms) 512 { 513 MachineState *ms = MACHINE(vms); 514 char *nodename; 515 516 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 517 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 518 519 nodename = g_strdup_printf("/intc@%" PRIx64, 520 vms->memmap[VIRT_GIC_DIST].base); 521 qemu_fdt_add_subnode(ms->fdt, nodename); 522 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 523 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 524 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 525 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 526 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 527 if (vms->gic_version != VIRT_GIC_VERSION_2) { 528 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 529 530 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 531 "arm,gic-v3"); 532 533 qemu_fdt_setprop_cell(ms->fdt, nodename, 534 "#redistributor-regions", nb_redist_regions); 535 536 if (nb_redist_regions == 1) { 537 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 538 2, vms->memmap[VIRT_GIC_DIST].base, 539 2, vms->memmap[VIRT_GIC_DIST].size, 540 2, vms->memmap[VIRT_GIC_REDIST].base, 541 2, vms->memmap[VIRT_GIC_REDIST].size); 542 } else { 543 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 544 2, vms->memmap[VIRT_GIC_DIST].base, 545 2, vms->memmap[VIRT_GIC_DIST].size, 546 2, vms->memmap[VIRT_GIC_REDIST].base, 547 2, vms->memmap[VIRT_GIC_REDIST].size, 548 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 549 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 550 } 551 552 if (vms->virt) { 553 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 554 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 555 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 556 } 557 } else { 558 /* 'cortex-a15-gic' means 'GIC v2' */ 559 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 560 "arm,cortex-a15-gic"); 561 if (!vms->virt) { 562 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 563 2, vms->memmap[VIRT_GIC_DIST].base, 564 2, vms->memmap[VIRT_GIC_DIST].size, 565 2, vms->memmap[VIRT_GIC_CPU].base, 566 2, vms->memmap[VIRT_GIC_CPU].size); 567 } else { 568 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 569 2, vms->memmap[VIRT_GIC_DIST].base, 570 2, vms->memmap[VIRT_GIC_DIST].size, 571 2, vms->memmap[VIRT_GIC_CPU].base, 572 2, vms->memmap[VIRT_GIC_CPU].size, 573 2, vms->memmap[VIRT_GIC_HYP].base, 574 2, vms->memmap[VIRT_GIC_HYP].size, 575 2, vms->memmap[VIRT_GIC_VCPU].base, 576 2, vms->memmap[VIRT_GIC_VCPU].size); 577 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 578 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 579 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 580 } 581 } 582 583 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 584 g_free(nodename); 585 } 586 587 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 588 { 589 ARMCPU *armcpu = ARM_CPU(first_cpu); 590 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 591 MachineState *ms = MACHINE(vms); 592 593 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 594 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 595 return; 596 } 597 598 if (vms->gic_version == VIRT_GIC_VERSION_2) { 599 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 600 GIC_FDT_IRQ_PPI_CPU_WIDTH, 601 (1 << MACHINE(vms)->smp.cpus) - 1); 602 } 603 604 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 605 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 606 const char compat[] = "arm,armv8-pmuv3"; 607 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 608 compat, sizeof(compat)); 609 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 610 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 611 } 612 } 613 614 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 615 { 616 DeviceState *dev; 617 MachineState *ms = MACHINE(vms); 618 int irq = vms->irqmap[VIRT_ACPI_GED]; 619 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 620 621 if (ms->ram_slots) { 622 event |= ACPI_GED_MEM_HOTPLUG_EVT; 623 } 624 625 if (ms->nvdimms_state->is_enabled) { 626 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 627 } 628 629 dev = qdev_new(TYPE_ACPI_GED); 630 qdev_prop_set_uint32(dev, "ged-event", event); 631 632 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 633 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 634 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 635 636 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 637 638 return dev; 639 } 640 641 static void create_its(VirtMachineState *vms) 642 { 643 const char *itsclass = its_class_name(); 644 DeviceState *dev; 645 646 if (!strcmp(itsclass, "arm-gicv3-its")) { 647 if (!vms->tcg_its) { 648 itsclass = NULL; 649 } 650 } 651 652 if (!itsclass) { 653 /* Do nothing if not supported */ 654 return; 655 } 656 657 dev = qdev_new(itsclass); 658 659 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 660 &error_abort); 661 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 662 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 663 664 fdt_add_its_gic_node(vms); 665 vms->msi_controller = VIRT_MSI_CTRL_ITS; 666 } 667 668 static void create_v2m(VirtMachineState *vms) 669 { 670 int i; 671 int irq = vms->irqmap[VIRT_GIC_V2M]; 672 DeviceState *dev; 673 674 dev = qdev_new("arm-gicv2m"); 675 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 676 qdev_prop_set_uint32(dev, "base-spi", irq); 677 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 678 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 679 680 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 681 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 682 qdev_get_gpio_in(vms->gic, irq + i)); 683 } 684 685 fdt_add_v2m_gic_node(vms); 686 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 687 } 688 689 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 690 { 691 MachineState *ms = MACHINE(vms); 692 /* We create a standalone GIC */ 693 SysBusDevice *gicbusdev; 694 const char *gictype; 695 int i; 696 unsigned int smp_cpus = ms->smp.cpus; 697 uint32_t nb_redist_regions = 0; 698 int revision; 699 700 if (vms->gic_version == VIRT_GIC_VERSION_2) { 701 gictype = gic_class_name(); 702 } else { 703 gictype = gicv3_class_name(); 704 } 705 706 switch (vms->gic_version) { 707 case VIRT_GIC_VERSION_2: 708 revision = 2; 709 break; 710 case VIRT_GIC_VERSION_3: 711 revision = 3; 712 break; 713 case VIRT_GIC_VERSION_4: 714 revision = 4; 715 break; 716 default: 717 g_assert_not_reached(); 718 } 719 vms->gic = qdev_new(gictype); 720 qdev_prop_set_uint32(vms->gic, "revision", revision); 721 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 722 /* Note that the num-irq property counts both internal and external 723 * interrupts; there are always 32 of the former (mandated by GIC spec). 724 */ 725 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 726 if (!kvm_irqchip_in_kernel()) { 727 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 728 } 729 730 if (vms->gic_version != VIRT_GIC_VERSION_2) { 731 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 732 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 733 734 nb_redist_regions = virt_gicv3_redist_region_count(vms); 735 736 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 737 nb_redist_regions); 738 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 739 740 if (!kvm_irqchip_in_kernel()) { 741 if (vms->tcg_its) { 742 object_property_set_link(OBJECT(vms->gic), "sysmem", 743 OBJECT(mem), &error_fatal); 744 qdev_prop_set_bit(vms->gic, "has-lpi", true); 745 } 746 } 747 748 if (nb_redist_regions == 2) { 749 uint32_t redist1_capacity = 750 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 751 752 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 753 MIN(smp_cpus - redist0_count, redist1_capacity)); 754 } 755 } else { 756 if (!kvm_irqchip_in_kernel()) { 757 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 758 vms->virt); 759 } 760 } 761 gicbusdev = SYS_BUS_DEVICE(vms->gic); 762 sysbus_realize_and_unref(gicbusdev, &error_fatal); 763 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 764 if (vms->gic_version != VIRT_GIC_VERSION_2) { 765 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 766 if (nb_redist_regions == 2) { 767 sysbus_mmio_map(gicbusdev, 2, 768 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 769 } 770 } else { 771 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 772 if (vms->virt) { 773 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 774 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 775 } 776 } 777 778 /* Wire the outputs from each CPU's generic timer and the GICv3 779 * maintenance interrupt signal to the appropriate GIC PPI inputs, 780 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 781 */ 782 for (i = 0; i < smp_cpus; i++) { 783 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 784 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 785 int irq; 786 /* Mapping from the output timer irq lines from the CPU to the 787 * GIC PPI inputs we use for the virt board. 788 */ 789 const int timer_irq[] = { 790 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 791 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 792 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 793 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 794 }; 795 796 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 797 qdev_connect_gpio_out(cpudev, irq, 798 qdev_get_gpio_in(vms->gic, 799 ppibase + timer_irq[irq])); 800 } 801 802 if (vms->gic_version != VIRT_GIC_VERSION_2) { 803 qemu_irq irq = qdev_get_gpio_in(vms->gic, 804 ppibase + ARCH_GIC_MAINT_IRQ); 805 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 806 0, irq); 807 } else if (vms->virt) { 808 qemu_irq irq = qdev_get_gpio_in(vms->gic, 809 ppibase + ARCH_GIC_MAINT_IRQ); 810 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 811 } 812 813 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 814 qdev_get_gpio_in(vms->gic, ppibase 815 + VIRTUAL_PMU_IRQ)); 816 817 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 818 sysbus_connect_irq(gicbusdev, i + smp_cpus, 819 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 820 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 821 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 822 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 823 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 824 } 825 826 fdt_add_gic_node(vms); 827 828 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 829 create_its(vms); 830 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 831 create_v2m(vms); 832 } 833 } 834 835 static void create_uart(const VirtMachineState *vms, int uart, 836 MemoryRegion *mem, Chardev *chr) 837 { 838 char *nodename; 839 hwaddr base = vms->memmap[uart].base; 840 hwaddr size = vms->memmap[uart].size; 841 int irq = vms->irqmap[uart]; 842 const char compat[] = "arm,pl011\0arm,primecell"; 843 const char clocknames[] = "uartclk\0apb_pclk"; 844 DeviceState *dev = qdev_new(TYPE_PL011); 845 SysBusDevice *s = SYS_BUS_DEVICE(dev); 846 MachineState *ms = MACHINE(vms); 847 848 qdev_prop_set_chr(dev, "chardev", chr); 849 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 850 memory_region_add_subregion(mem, base, 851 sysbus_mmio_get_region(s, 0)); 852 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 853 854 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 855 qemu_fdt_add_subnode(ms->fdt, nodename); 856 /* Note that we can't use setprop_string because of the embedded NUL */ 857 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 858 compat, sizeof(compat)); 859 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 860 2, base, 2, size); 861 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 862 GIC_FDT_IRQ_TYPE_SPI, irq, 863 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 864 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 865 vms->clock_phandle, vms->clock_phandle); 866 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 867 clocknames, sizeof(clocknames)); 868 869 if (uart == VIRT_UART) { 870 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 871 } else { 872 /* Mark as not usable by the normal world */ 873 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 874 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 875 876 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 877 nodename); 878 } 879 880 g_free(nodename); 881 } 882 883 static void create_rtc(const VirtMachineState *vms) 884 { 885 char *nodename; 886 hwaddr base = vms->memmap[VIRT_RTC].base; 887 hwaddr size = vms->memmap[VIRT_RTC].size; 888 int irq = vms->irqmap[VIRT_RTC]; 889 const char compat[] = "arm,pl031\0arm,primecell"; 890 MachineState *ms = MACHINE(vms); 891 892 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 893 894 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 895 qemu_fdt_add_subnode(ms->fdt, nodename); 896 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 897 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 898 2, base, 2, size); 899 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 900 GIC_FDT_IRQ_TYPE_SPI, irq, 901 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 902 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 903 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 904 g_free(nodename); 905 } 906 907 static DeviceState *gpio_key_dev; 908 static void virt_powerdown_req(Notifier *n, void *opaque) 909 { 910 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 911 912 if (s->acpi_dev) { 913 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 914 } else { 915 /* use gpio Pin 3 for power button event */ 916 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 917 } 918 } 919 920 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 921 uint32_t phandle) 922 { 923 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 924 qdev_get_gpio_in(pl061_dev, 3)); 925 926 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 927 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 928 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0); 929 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1); 930 931 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 932 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 933 "label", "GPIO Key Poweroff"); 934 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 935 KEY_POWER); 936 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 937 "gpios", phandle, 3, 0); 938 } 939 940 #define SECURE_GPIO_POWEROFF 0 941 #define SECURE_GPIO_RESET 1 942 943 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 944 uint32_t phandle) 945 { 946 DeviceState *gpio_pwr_dev; 947 948 /* gpio-pwr */ 949 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 950 951 /* connect secure pl061 to gpio-pwr */ 952 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 953 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 954 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 955 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 956 957 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 958 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 959 "gpio-poweroff"); 960 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 961 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 962 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 963 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 964 "okay"); 965 966 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 967 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 968 "gpio-restart"); 969 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 970 "gpios", phandle, SECURE_GPIO_RESET, 0); 971 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 972 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 973 "okay"); 974 } 975 976 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 977 MemoryRegion *mem) 978 { 979 char *nodename; 980 DeviceState *pl061_dev; 981 hwaddr base = vms->memmap[gpio].base; 982 hwaddr size = vms->memmap[gpio].size; 983 int irq = vms->irqmap[gpio]; 984 const char compat[] = "arm,pl061\0arm,primecell"; 985 SysBusDevice *s; 986 MachineState *ms = MACHINE(vms); 987 988 pl061_dev = qdev_new("pl061"); 989 /* Pull lines down to 0 if not driven by the PL061 */ 990 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 991 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 992 s = SYS_BUS_DEVICE(pl061_dev); 993 sysbus_realize_and_unref(s, &error_fatal); 994 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 995 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 996 997 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 998 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 999 qemu_fdt_add_subnode(ms->fdt, nodename); 1000 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1001 2, base, 2, size); 1002 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1003 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1004 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1005 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1006 GIC_FDT_IRQ_TYPE_SPI, irq, 1007 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1008 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1009 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1010 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1011 1012 if (gpio != VIRT_GPIO) { 1013 /* Mark as not usable by the normal world */ 1014 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1015 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1016 } 1017 g_free(nodename); 1018 1019 /* Child gpio devices */ 1020 if (gpio == VIRT_GPIO) { 1021 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1022 } else { 1023 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1024 } 1025 } 1026 1027 static void create_virtio_devices(const VirtMachineState *vms) 1028 { 1029 int i; 1030 hwaddr size = vms->memmap[VIRT_MMIO].size; 1031 MachineState *ms = MACHINE(vms); 1032 1033 /* We create the transports in forwards order. Since qbus_realize() 1034 * prepends (not appends) new child buses, the incrementing loop below will 1035 * create a list of virtio-mmio buses with decreasing base addresses. 1036 * 1037 * When a -device option is processed from the command line, 1038 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1039 * order. The upshot is that -device options in increasing command line 1040 * order are mapped to virtio-mmio buses with decreasing base addresses. 1041 * 1042 * When this code was originally written, that arrangement ensured that the 1043 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1044 * the first -device on the command line. (The end-to-end order is a 1045 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1046 * guest kernel's name-to-address assignment strategy.) 1047 * 1048 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1049 * the message, if not necessarily the code, of commit 70161ff336. 1050 * Therefore the loop now establishes the inverse of the original intent. 1051 * 1052 * Unfortunately, we can't counteract the kernel change by reversing the 1053 * loop; it would break existing command lines. 1054 * 1055 * In any case, the kernel makes no guarantee about the stability of 1056 * enumeration order of virtio devices (as demonstrated by it changing 1057 * between kernel versions). For reliable and stable identification 1058 * of disks users must use UUIDs or similar mechanisms. 1059 */ 1060 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1061 int irq = vms->irqmap[VIRT_MMIO] + i; 1062 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1063 1064 sysbus_create_simple("virtio-mmio", base, 1065 qdev_get_gpio_in(vms->gic, irq)); 1066 } 1067 1068 /* We add dtb nodes in reverse order so that they appear in the finished 1069 * device tree lowest address first. 1070 * 1071 * Note that this mapping is independent of the loop above. The previous 1072 * loop influences virtio device to virtio transport assignment, whereas 1073 * this loop controls how virtio transports are laid out in the dtb. 1074 */ 1075 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1076 char *nodename; 1077 int irq = vms->irqmap[VIRT_MMIO] + i; 1078 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1079 1080 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1081 qemu_fdt_add_subnode(ms->fdt, nodename); 1082 qemu_fdt_setprop_string(ms->fdt, nodename, 1083 "compatible", "virtio,mmio"); 1084 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1085 2, base, 2, size); 1086 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1087 GIC_FDT_IRQ_TYPE_SPI, irq, 1088 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1089 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1090 g_free(nodename); 1091 } 1092 } 1093 1094 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1095 1096 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1097 const char *name, 1098 const char *alias_prop_name) 1099 { 1100 /* 1101 * Create a single flash device. We use the same parameters as 1102 * the flash devices on the Versatile Express board. 1103 */ 1104 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1105 1106 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1107 qdev_prop_set_uint8(dev, "width", 4); 1108 qdev_prop_set_uint8(dev, "device-width", 2); 1109 qdev_prop_set_bit(dev, "big-endian", false); 1110 qdev_prop_set_uint16(dev, "id0", 0x89); 1111 qdev_prop_set_uint16(dev, "id1", 0x18); 1112 qdev_prop_set_uint16(dev, "id2", 0x00); 1113 qdev_prop_set_uint16(dev, "id3", 0x00); 1114 qdev_prop_set_string(dev, "name", name); 1115 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1116 object_property_add_alias(OBJECT(vms), alias_prop_name, 1117 OBJECT(dev), "drive"); 1118 return PFLASH_CFI01(dev); 1119 } 1120 1121 static void virt_flash_create(VirtMachineState *vms) 1122 { 1123 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1124 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1125 } 1126 1127 static void virt_flash_map1(PFlashCFI01 *flash, 1128 hwaddr base, hwaddr size, 1129 MemoryRegion *sysmem) 1130 { 1131 DeviceState *dev = DEVICE(flash); 1132 1133 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1134 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1135 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1136 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1137 1138 memory_region_add_subregion(sysmem, base, 1139 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1140 0)); 1141 } 1142 1143 static void virt_flash_map(VirtMachineState *vms, 1144 MemoryRegion *sysmem, 1145 MemoryRegion *secure_sysmem) 1146 { 1147 /* 1148 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1149 * sysmem is the system memory space. secure_sysmem is the secure view 1150 * of the system, and the first flash device should be made visible only 1151 * there. The second flash device is visible to both secure and nonsecure. 1152 * If sysmem == secure_sysmem this means there is no separate Secure 1153 * address space and both flash devices are generally visible. 1154 */ 1155 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1156 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1157 1158 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1159 secure_sysmem); 1160 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1161 sysmem); 1162 } 1163 1164 static void virt_flash_fdt(VirtMachineState *vms, 1165 MemoryRegion *sysmem, 1166 MemoryRegion *secure_sysmem) 1167 { 1168 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1169 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1170 MachineState *ms = MACHINE(vms); 1171 char *nodename; 1172 1173 if (sysmem == secure_sysmem) { 1174 /* Report both flash devices as a single node in the DT */ 1175 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1176 qemu_fdt_add_subnode(ms->fdt, nodename); 1177 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1178 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1179 2, flashbase, 2, flashsize, 1180 2, flashbase + flashsize, 2, flashsize); 1181 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1182 g_free(nodename); 1183 } else { 1184 /* 1185 * Report the devices as separate nodes so we can mark one as 1186 * only visible to the secure world. 1187 */ 1188 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1189 qemu_fdt_add_subnode(ms->fdt, nodename); 1190 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1191 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1192 2, flashbase, 2, flashsize); 1193 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1194 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1195 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1196 g_free(nodename); 1197 1198 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1199 qemu_fdt_add_subnode(ms->fdt, nodename); 1200 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1201 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1202 2, flashbase + flashsize, 2, flashsize); 1203 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1204 g_free(nodename); 1205 } 1206 } 1207 1208 static bool virt_firmware_init(VirtMachineState *vms, 1209 MemoryRegion *sysmem, 1210 MemoryRegion *secure_sysmem) 1211 { 1212 int i; 1213 const char *bios_name; 1214 BlockBackend *pflash_blk0; 1215 1216 /* Map legacy -drive if=pflash to machine properties */ 1217 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1218 pflash_cfi01_legacy_drive(vms->flash[i], 1219 drive_get(IF_PFLASH, 0, i)); 1220 } 1221 1222 virt_flash_map(vms, sysmem, secure_sysmem); 1223 1224 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1225 1226 bios_name = MACHINE(vms)->firmware; 1227 if (bios_name) { 1228 char *fname; 1229 MemoryRegion *mr; 1230 int image_size; 1231 1232 if (pflash_blk0) { 1233 error_report("The contents of the first flash device may be " 1234 "specified with -bios or with -drive if=pflash... " 1235 "but you cannot use both options at once"); 1236 exit(1); 1237 } 1238 1239 /* Fall back to -bios */ 1240 1241 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1242 if (!fname) { 1243 error_report("Could not find ROM image '%s'", bios_name); 1244 exit(1); 1245 } 1246 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1247 image_size = load_image_mr(fname, mr); 1248 g_free(fname); 1249 if (image_size < 0) { 1250 error_report("Could not load ROM image '%s'", bios_name); 1251 exit(1); 1252 } 1253 } 1254 1255 return pflash_blk0 || bios_name; 1256 } 1257 1258 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1259 { 1260 MachineState *ms = MACHINE(vms); 1261 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1262 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1263 FWCfgState *fw_cfg; 1264 char *nodename; 1265 1266 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1267 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1268 1269 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1270 qemu_fdt_add_subnode(ms->fdt, nodename); 1271 qemu_fdt_setprop_string(ms->fdt, nodename, 1272 "compatible", "qemu,fw-cfg-mmio"); 1273 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1274 2, base, 2, size); 1275 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1276 g_free(nodename); 1277 return fw_cfg; 1278 } 1279 1280 static void create_pcie_irq_map(const MachineState *ms, 1281 uint32_t gic_phandle, 1282 int first_irq, const char *nodename) 1283 { 1284 int devfn, pin; 1285 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1286 uint32_t *irq_map = full_irq_map; 1287 1288 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1289 for (pin = 0; pin < 4; pin++) { 1290 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1291 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1292 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1293 int i; 1294 1295 uint32_t map[] = { 1296 devfn << 8, 0, 0, /* devfn */ 1297 pin + 1, /* PCI pin */ 1298 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1299 1300 /* Convert map to big endian */ 1301 for (i = 0; i < 10; i++) { 1302 irq_map[i] = cpu_to_be32(map[i]); 1303 } 1304 irq_map += 10; 1305 } 1306 } 1307 1308 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1309 full_irq_map, sizeof(full_irq_map)); 1310 1311 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1312 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1313 0, 0, 1314 0x7 /* PCI irq */); 1315 } 1316 1317 static void create_smmu(const VirtMachineState *vms, 1318 PCIBus *bus) 1319 { 1320 char *node; 1321 const char compat[] = "arm,smmu-v3"; 1322 int irq = vms->irqmap[VIRT_SMMU]; 1323 int i; 1324 hwaddr base = vms->memmap[VIRT_SMMU].base; 1325 hwaddr size = vms->memmap[VIRT_SMMU].size; 1326 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1327 DeviceState *dev; 1328 MachineState *ms = MACHINE(vms); 1329 1330 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1331 return; 1332 } 1333 1334 dev = qdev_new("arm-smmuv3"); 1335 1336 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1337 &error_abort); 1338 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1339 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1340 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1341 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1342 qdev_get_gpio_in(vms->gic, irq + i)); 1343 } 1344 1345 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1346 qemu_fdt_add_subnode(ms->fdt, node); 1347 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1348 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1349 1350 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1351 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1352 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1353 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1354 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1355 1356 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1357 sizeof(irq_names)); 1358 1359 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); 1360 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); 1361 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1362 1363 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1364 1365 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1366 g_free(node); 1367 } 1368 1369 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1370 { 1371 const char compat[] = "virtio,pci-iommu"; 1372 uint16_t bdf = vms->virtio_iommu_bdf; 1373 MachineState *ms = MACHINE(vms); 1374 char *node; 1375 1376 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1377 1378 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1379 qemu_fdt_add_subnode(ms->fdt, node); 1380 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1381 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1382 1, bdf << 8, 1, 0, 1, 0, 1383 1, 0, 1, 0); 1384 1385 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1386 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1387 g_free(node); 1388 1389 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1390 0x0, vms->iommu_phandle, 0x0, bdf, 1391 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1392 } 1393 1394 static void create_pcie(VirtMachineState *vms) 1395 { 1396 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1397 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1398 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1399 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1400 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1401 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1402 hwaddr base_ecam, size_ecam; 1403 hwaddr base = base_mmio; 1404 int nr_pcie_buses; 1405 int irq = vms->irqmap[VIRT_PCIE]; 1406 MemoryRegion *mmio_alias; 1407 MemoryRegion *mmio_reg; 1408 MemoryRegion *ecam_alias; 1409 MemoryRegion *ecam_reg; 1410 DeviceState *dev; 1411 char *nodename; 1412 int i, ecam_id; 1413 PCIHostState *pci; 1414 MachineState *ms = MACHINE(vms); 1415 1416 dev = qdev_new(TYPE_GPEX_HOST); 1417 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1418 1419 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1420 base_ecam = vms->memmap[ecam_id].base; 1421 size_ecam = vms->memmap[ecam_id].size; 1422 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1423 /* Map only the first size_ecam bytes of ECAM space */ 1424 ecam_alias = g_new0(MemoryRegion, 1); 1425 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1426 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1427 ecam_reg, 0, size_ecam); 1428 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1429 1430 /* Map the MMIO window into system address space so as to expose 1431 * the section of PCI MMIO space which starts at the same base address 1432 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1433 * the window). 1434 */ 1435 mmio_alias = g_new0(MemoryRegion, 1); 1436 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1437 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1438 mmio_reg, base_mmio, size_mmio); 1439 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1440 1441 if (vms->highmem_mmio) { 1442 /* Map high MMIO space */ 1443 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1444 1445 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1446 mmio_reg, base_mmio_high, size_mmio_high); 1447 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1448 high_mmio_alias); 1449 } 1450 1451 /* Map IO port space */ 1452 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1453 1454 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1455 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1456 qdev_get_gpio_in(vms->gic, irq + i)); 1457 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1458 } 1459 1460 pci = PCI_HOST_BRIDGE(dev); 1461 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1462 vms->bus = pci->bus; 1463 if (vms->bus) { 1464 for (i = 0; i < nb_nics; i++) { 1465 NICInfo *nd = &nd_table[i]; 1466 1467 if (!nd->model) { 1468 nd->model = g_strdup("virtio"); 1469 } 1470 1471 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1472 } 1473 } 1474 1475 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1476 qemu_fdt_add_subnode(ms->fdt, nodename); 1477 qemu_fdt_setprop_string(ms->fdt, nodename, 1478 "compatible", "pci-host-ecam-generic"); 1479 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1480 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1481 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1482 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1483 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1484 nr_pcie_buses - 1); 1485 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1486 1487 if (vms->msi_phandle) { 1488 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent", 1489 vms->msi_phandle); 1490 } 1491 1492 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1493 2, base_ecam, 2, size_ecam); 1494 1495 if (vms->highmem_mmio) { 1496 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1497 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1498 2, base_pio, 2, size_pio, 1499 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1500 2, base_mmio, 2, size_mmio, 1501 1, FDT_PCI_RANGE_MMIO_64BIT, 1502 2, base_mmio_high, 1503 2, base_mmio_high, 2, size_mmio_high); 1504 } else { 1505 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1506 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1507 2, base_pio, 2, size_pio, 1508 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1509 2, base_mmio, 2, size_mmio); 1510 } 1511 1512 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1513 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1514 1515 if (vms->iommu) { 1516 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1517 1518 switch (vms->iommu) { 1519 case VIRT_IOMMU_SMMUV3: 1520 create_smmu(vms, vms->bus); 1521 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1522 0x0, vms->iommu_phandle, 0x0, 0x10000); 1523 break; 1524 default: 1525 g_assert_not_reached(); 1526 } 1527 } 1528 } 1529 1530 static void create_platform_bus(VirtMachineState *vms) 1531 { 1532 DeviceState *dev; 1533 SysBusDevice *s; 1534 int i; 1535 MemoryRegion *sysmem = get_system_memory(); 1536 1537 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1538 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1539 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1540 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1541 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1542 vms->platform_bus_dev = dev; 1543 1544 s = SYS_BUS_DEVICE(dev); 1545 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1546 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1547 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1548 } 1549 1550 memory_region_add_subregion(sysmem, 1551 vms->memmap[VIRT_PLATFORM_BUS].base, 1552 sysbus_mmio_get_region(s, 0)); 1553 } 1554 1555 static void create_tag_ram(MemoryRegion *tag_sysmem, 1556 hwaddr base, hwaddr size, 1557 const char *name) 1558 { 1559 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1560 1561 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1562 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1563 } 1564 1565 static void create_secure_ram(VirtMachineState *vms, 1566 MemoryRegion *secure_sysmem, 1567 MemoryRegion *secure_tag_sysmem) 1568 { 1569 MemoryRegion *secram = g_new(MemoryRegion, 1); 1570 char *nodename; 1571 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1572 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1573 MachineState *ms = MACHINE(vms); 1574 1575 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1576 &error_fatal); 1577 memory_region_add_subregion(secure_sysmem, base, secram); 1578 1579 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1580 qemu_fdt_add_subnode(ms->fdt, nodename); 1581 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1582 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1583 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1584 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1585 1586 if (secure_tag_sysmem) { 1587 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1588 } 1589 1590 g_free(nodename); 1591 } 1592 1593 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1594 { 1595 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1596 bootinfo); 1597 MachineState *ms = MACHINE(board); 1598 1599 1600 *fdt_size = board->fdt_size; 1601 return ms->fdt; 1602 } 1603 1604 static void virt_build_smbios(VirtMachineState *vms) 1605 { 1606 MachineClass *mc = MACHINE_GET_CLASS(vms); 1607 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1608 uint8_t *smbios_tables, *smbios_anchor; 1609 size_t smbios_tables_len, smbios_anchor_len; 1610 const char *product = "QEMU Virtual Machine"; 1611 1612 if (kvm_enabled()) { 1613 product = "KVM Virtual Machine"; 1614 } 1615 1616 smbios_set_defaults("QEMU", product, 1617 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1618 true, SMBIOS_ENTRY_POINT_TYPE_64); 1619 1620 smbios_get_tables(MACHINE(vms), NULL, 0, 1621 &smbios_tables, &smbios_tables_len, 1622 &smbios_anchor, &smbios_anchor_len, 1623 &error_fatal); 1624 1625 if (smbios_anchor) { 1626 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1627 smbios_tables, smbios_tables_len); 1628 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1629 smbios_anchor, smbios_anchor_len); 1630 } 1631 } 1632 1633 static 1634 void virt_machine_done(Notifier *notifier, void *data) 1635 { 1636 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1637 machine_done); 1638 MachineState *ms = MACHINE(vms); 1639 ARMCPU *cpu = ARM_CPU(first_cpu); 1640 struct arm_boot_info *info = &vms->bootinfo; 1641 AddressSpace *as = arm_boot_address_space(cpu, info); 1642 1643 /* 1644 * If the user provided a dtb, we assume the dynamic sysbus nodes 1645 * already are integrated there. This corresponds to a use case where 1646 * the dynamic sysbus nodes are complex and their generation is not yet 1647 * supported. In that case the user can take charge of the guest dt 1648 * while qemu takes charge of the qom stuff. 1649 */ 1650 if (info->dtb_filename == NULL) { 1651 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1652 vms->memmap[VIRT_PLATFORM_BUS].base, 1653 vms->memmap[VIRT_PLATFORM_BUS].size, 1654 vms->irqmap[VIRT_PLATFORM_BUS]); 1655 } 1656 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1657 exit(1); 1658 } 1659 1660 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1661 1662 virt_acpi_setup(vms); 1663 virt_build_smbios(vms); 1664 } 1665 1666 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1667 { 1668 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1669 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1670 1671 if (!vmc->disallow_affinity_adjustment) { 1672 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1673 * GIC's target-list limitations. 32-bit KVM hosts currently 1674 * always create clusters of 4 CPUs, but that is expected to 1675 * change when they gain support for gicv3. When KVM is enabled 1676 * it will override the changes we make here, therefore our 1677 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1678 * and to improve SGI efficiency. 1679 */ 1680 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1681 clustersz = GIC_TARGETLIST_BITS; 1682 } else { 1683 clustersz = GICV3_TARGETLIST_BITS; 1684 } 1685 } 1686 return arm_cpu_mp_affinity(idx, clustersz); 1687 } 1688 1689 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1690 { 1691 MachineState *ms = MACHINE(vms); 1692 hwaddr base, device_memory_base, device_memory_size, memtop; 1693 int i; 1694 1695 vms->memmap = extended_memmap; 1696 1697 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1698 vms->memmap[i] = base_memmap[i]; 1699 } 1700 1701 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1702 error_report("unsupported number of memory slots: %"PRIu64, 1703 ms->ram_slots); 1704 exit(EXIT_FAILURE); 1705 } 1706 1707 /* 1708 * !highmem is exactly the same as limiting the PA space to 32bit, 1709 * irrespective of the underlying capabilities of the HW. 1710 */ 1711 if (!vms->highmem) { 1712 pa_bits = 32; 1713 } 1714 1715 /* 1716 * We compute the base of the high IO region depending on the 1717 * amount of initial and device memory. The device memory start/size 1718 * is aligned on 1GiB. We never put the high IO region below 256GiB 1719 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1720 * The device region size assumes 1GiB page max alignment per slot. 1721 */ 1722 device_memory_base = 1723 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1724 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1725 1726 /* Base address of the high IO region */ 1727 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1728 if (memtop > BIT_ULL(pa_bits)) { 1729 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1730 pa_bits, memtop - BIT_ULL(pa_bits)); 1731 exit(EXIT_FAILURE); 1732 } 1733 if (base < device_memory_base) { 1734 error_report("maxmem/slots too huge"); 1735 exit(EXIT_FAILURE); 1736 } 1737 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1738 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1739 } 1740 1741 /* We know for sure that at least the memory fits in the PA space */ 1742 vms->highest_gpa = memtop - 1; 1743 1744 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1745 hwaddr size = extended_memmap[i].size; 1746 bool fits; 1747 1748 base = ROUND_UP(base, size); 1749 vms->memmap[i].base = base; 1750 vms->memmap[i].size = size; 1751 1752 /* 1753 * Check each device to see if they fit in the PA space, 1754 * moving highest_gpa as we go. 1755 * 1756 * For each device that doesn't fit, disable it. 1757 */ 1758 fits = (base + size) <= BIT_ULL(pa_bits); 1759 if (fits) { 1760 vms->highest_gpa = base + size - 1; 1761 } 1762 1763 switch (i) { 1764 case VIRT_HIGH_GIC_REDIST2: 1765 vms->highmem_redists &= fits; 1766 break; 1767 case VIRT_HIGH_PCIE_ECAM: 1768 vms->highmem_ecam &= fits; 1769 break; 1770 case VIRT_HIGH_PCIE_MMIO: 1771 vms->highmem_mmio &= fits; 1772 break; 1773 } 1774 1775 base += size; 1776 } 1777 1778 if (device_memory_size > 0) { 1779 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1780 ms->device_memory->base = device_memory_base; 1781 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1782 "device-memory", device_memory_size); 1783 } 1784 } 1785 1786 /* 1787 * finalize_gic_version - Determines the final gic_version 1788 * according to the gic-version property 1789 * 1790 * Default GIC type is v2 1791 */ 1792 static void finalize_gic_version(VirtMachineState *vms) 1793 { 1794 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1795 1796 if (kvm_enabled()) { 1797 int probe_bitmap; 1798 1799 if (!kvm_irqchip_in_kernel()) { 1800 switch (vms->gic_version) { 1801 case VIRT_GIC_VERSION_HOST: 1802 warn_report( 1803 "gic-version=host not relevant with kernel-irqchip=off " 1804 "as only userspace GICv2 is supported. Using v2 ..."); 1805 return; 1806 case VIRT_GIC_VERSION_MAX: 1807 case VIRT_GIC_VERSION_NOSEL: 1808 vms->gic_version = VIRT_GIC_VERSION_2; 1809 return; 1810 case VIRT_GIC_VERSION_2: 1811 return; 1812 case VIRT_GIC_VERSION_3: 1813 error_report( 1814 "gic-version=3 is not supported with kernel-irqchip=off"); 1815 exit(1); 1816 case VIRT_GIC_VERSION_4: 1817 error_report( 1818 "gic-version=4 is not supported with kernel-irqchip=off"); 1819 exit(1); 1820 } 1821 } 1822 1823 probe_bitmap = kvm_arm_vgic_probe(); 1824 if (!probe_bitmap) { 1825 error_report("Unable to determine GIC version supported by host"); 1826 exit(1); 1827 } 1828 1829 switch (vms->gic_version) { 1830 case VIRT_GIC_VERSION_HOST: 1831 case VIRT_GIC_VERSION_MAX: 1832 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1833 vms->gic_version = VIRT_GIC_VERSION_3; 1834 } else { 1835 vms->gic_version = VIRT_GIC_VERSION_2; 1836 } 1837 return; 1838 case VIRT_GIC_VERSION_NOSEL: 1839 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1840 vms->gic_version = VIRT_GIC_VERSION_2; 1841 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1842 /* 1843 * in case the host does not support v2 in-kernel emulation or 1844 * the end-user requested more than 8 VCPUs we now default 1845 * to v3. In any case defaulting to v2 would be broken. 1846 */ 1847 vms->gic_version = VIRT_GIC_VERSION_3; 1848 } else if (max_cpus > GIC_NCPU) { 1849 error_report("host only supports in-kernel GICv2 emulation " 1850 "but more than 8 vcpus are requested"); 1851 exit(1); 1852 } 1853 break; 1854 case VIRT_GIC_VERSION_2: 1855 case VIRT_GIC_VERSION_3: 1856 break; 1857 case VIRT_GIC_VERSION_4: 1858 error_report("gic-version=4 is not supported with KVM"); 1859 exit(1); 1860 } 1861 1862 /* Check chosen version is effectively supported by the host */ 1863 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1864 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1865 error_report("host does not support in-kernel GICv2 emulation"); 1866 exit(1); 1867 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1868 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1869 error_report("host does not support in-kernel GICv3 emulation"); 1870 exit(1); 1871 } 1872 return; 1873 } 1874 1875 /* TCG mode */ 1876 switch (vms->gic_version) { 1877 case VIRT_GIC_VERSION_NOSEL: 1878 vms->gic_version = VIRT_GIC_VERSION_2; 1879 break; 1880 case VIRT_GIC_VERSION_MAX: 1881 if (module_object_class_by_name("arm-gicv3")) { 1882 /* CONFIG_ARM_GICV3_TCG was set */ 1883 if (vms->virt) { 1884 /* GICv4 only makes sense if CPU has EL2 */ 1885 vms->gic_version = VIRT_GIC_VERSION_4; 1886 } else { 1887 vms->gic_version = VIRT_GIC_VERSION_3; 1888 } 1889 } else { 1890 vms->gic_version = VIRT_GIC_VERSION_2; 1891 } 1892 break; 1893 case VIRT_GIC_VERSION_HOST: 1894 error_report("gic-version=host requires KVM"); 1895 exit(1); 1896 case VIRT_GIC_VERSION_4: 1897 if (!vms->virt) { 1898 error_report("gic-version=4 requires virtualization enabled"); 1899 exit(1); 1900 } 1901 break; 1902 case VIRT_GIC_VERSION_2: 1903 case VIRT_GIC_VERSION_3: 1904 break; 1905 } 1906 } 1907 1908 /* 1909 * virt_cpu_post_init() must be called after the CPUs have 1910 * been realized and the GIC has been created. 1911 */ 1912 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1913 { 1914 int max_cpus = MACHINE(vms)->smp.max_cpus; 1915 bool aarch64, pmu, steal_time; 1916 CPUState *cpu; 1917 1918 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1919 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1920 steal_time = object_property_get_bool(OBJECT(first_cpu), 1921 "kvm-steal-time", NULL); 1922 1923 if (kvm_enabled()) { 1924 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1925 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1926 1927 if (steal_time) { 1928 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1929 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1930 1931 /* The memory region size must be a multiple of host page size. */ 1932 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1933 1934 if (pvtime_size > pvtime_reg_size) { 1935 error_report("pvtime requires a %" HWADDR_PRId 1936 " byte memory region for %d CPUs," 1937 " but only %" HWADDR_PRId " has been reserved", 1938 pvtime_size, max_cpus, pvtime_reg_size); 1939 exit(1); 1940 } 1941 1942 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1943 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1944 } 1945 1946 CPU_FOREACH(cpu) { 1947 if (pmu) { 1948 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1949 if (kvm_irqchip_in_kernel()) { 1950 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1951 } 1952 kvm_arm_pmu_init(cpu); 1953 } 1954 if (steal_time) { 1955 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1956 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1957 } 1958 } 1959 } else { 1960 if (aarch64 && vms->highmem) { 1961 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1962 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1963 1964 if (pamax < requested_pa_size) { 1965 error_report("VCPU supports less PA bits (%d) than " 1966 "requested by the memory map (%d)", 1967 pamax, requested_pa_size); 1968 exit(1); 1969 } 1970 } 1971 } 1972 } 1973 1974 static void machvirt_init(MachineState *machine) 1975 { 1976 VirtMachineState *vms = VIRT_MACHINE(machine); 1977 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1978 MachineClass *mc = MACHINE_GET_CLASS(machine); 1979 const CPUArchIdList *possible_cpus; 1980 MemoryRegion *sysmem = get_system_memory(); 1981 MemoryRegion *secure_sysmem = NULL; 1982 MemoryRegion *tag_sysmem = NULL; 1983 MemoryRegion *secure_tag_sysmem = NULL; 1984 int n, virt_max_cpus; 1985 bool firmware_loaded; 1986 bool aarch64 = true; 1987 bool has_ged = !vmc->no_ged; 1988 unsigned int smp_cpus = machine->smp.cpus; 1989 unsigned int max_cpus = machine->smp.max_cpus; 1990 1991 if (!cpu_type_valid(machine->cpu_type)) { 1992 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1993 exit(1); 1994 } 1995 1996 possible_cpus = mc->possible_cpu_arch_ids(machine); 1997 1998 /* 1999 * In accelerated mode, the memory map is computed earlier in kvm_type() 2000 * to create a VM with the right number of IPA bits. 2001 */ 2002 if (!vms->memmap) { 2003 Object *cpuobj; 2004 ARMCPU *armcpu; 2005 int pa_bits; 2006 2007 /* 2008 * Instanciate a temporary CPU object to find out about what 2009 * we are about to deal with. Once this is done, get rid of 2010 * the object. 2011 */ 2012 cpuobj = object_new(possible_cpus->cpus[0].type); 2013 armcpu = ARM_CPU(cpuobj); 2014 2015 if (object_property_get_bool(cpuobj, "aarch64", NULL)) { 2016 pa_bits = arm_pamax(armcpu); 2017 } else if (arm_feature(&armcpu->env, ARM_FEATURE_LPAE)) { 2018 /* v7 with LPAE */ 2019 pa_bits = 40; 2020 } else { 2021 /* Anything else */ 2022 pa_bits = 32; 2023 } 2024 2025 object_unref(cpuobj); 2026 2027 virt_set_memmap(vms, pa_bits); 2028 } 2029 2030 /* We can probe only here because during property set 2031 * KVM is not available yet 2032 */ 2033 finalize_gic_version(vms); 2034 2035 if (vms->secure) { 2036 /* 2037 * The Secure view of the world is the same as the NonSecure, 2038 * but with a few extra devices. Create it as a container region 2039 * containing the system memory at low priority; any secure-only 2040 * devices go in at higher priority and take precedence. 2041 */ 2042 secure_sysmem = g_new(MemoryRegion, 1); 2043 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2044 UINT64_MAX); 2045 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2046 } 2047 2048 firmware_loaded = virt_firmware_init(vms, sysmem, 2049 secure_sysmem ?: sysmem); 2050 2051 /* If we have an EL3 boot ROM then the assumption is that it will 2052 * implement PSCI itself, so disable QEMU's internal implementation 2053 * so it doesn't get in the way. Instead of starting secondary 2054 * CPUs in PSCI powerdown state we will start them all running and 2055 * let the boot ROM sort them out. 2056 * The usual case is that we do use QEMU's PSCI implementation; 2057 * if the guest has EL2 then we will use SMC as the conduit, 2058 * and otherwise we will use HVC (for backwards compatibility and 2059 * because if we're using KVM then we must use HVC). 2060 */ 2061 if (vms->secure && firmware_loaded) { 2062 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2063 } else if (vms->virt) { 2064 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2065 } else { 2066 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2067 } 2068 2069 /* 2070 * The maximum number of CPUs depends on the GIC version, or on how 2071 * many redistributors we can fit into the memory map (which in turn 2072 * depends on whether this is a GICv3 or v4). 2073 */ 2074 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2075 virt_max_cpus = GIC_NCPU; 2076 } else { 2077 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + 2078 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2079 } 2080 2081 if (max_cpus > virt_max_cpus) { 2082 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2083 "supported by machine 'mach-virt' (%d)", 2084 max_cpus, virt_max_cpus); 2085 exit(1); 2086 } 2087 2088 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2089 error_report("mach-virt: %s does not support providing " 2090 "Security extensions (TrustZone) to the guest CPU", 2091 kvm_enabled() ? "KVM" : "HVF"); 2092 exit(1); 2093 } 2094 2095 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2096 error_report("mach-virt: %s does not support providing " 2097 "Virtualization extensions to the guest CPU", 2098 kvm_enabled() ? "KVM" : "HVF"); 2099 exit(1); 2100 } 2101 2102 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2103 error_report("mach-virt: %s does not support providing " 2104 "MTE to the guest CPU", 2105 kvm_enabled() ? "KVM" : "HVF"); 2106 exit(1); 2107 } 2108 2109 create_fdt(vms); 2110 2111 assert(possible_cpus->len == max_cpus); 2112 for (n = 0; n < possible_cpus->len; n++) { 2113 Object *cpuobj; 2114 CPUState *cs; 2115 2116 if (n >= smp_cpus) { 2117 break; 2118 } 2119 2120 cpuobj = object_new(possible_cpus->cpus[n].type); 2121 object_property_set_int(cpuobj, "mp-affinity", 2122 possible_cpus->cpus[n].arch_id, NULL); 2123 2124 cs = CPU(cpuobj); 2125 cs->cpu_index = n; 2126 2127 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2128 &error_fatal); 2129 2130 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2131 2132 if (!vms->secure) { 2133 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2134 } 2135 2136 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2137 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2138 } 2139 2140 if (vmc->kvm_no_adjvtime && 2141 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2142 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2143 } 2144 2145 if (vmc->no_kvm_steal_time && 2146 object_property_find(cpuobj, "kvm-steal-time")) { 2147 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2148 } 2149 2150 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2151 object_property_set_bool(cpuobj, "pmu", false, NULL); 2152 } 2153 2154 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2155 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2156 } 2157 2158 if (object_property_find(cpuobj, "reset-cbar")) { 2159 object_property_set_int(cpuobj, "reset-cbar", 2160 vms->memmap[VIRT_CPUPERIPHS].base, 2161 &error_abort); 2162 } 2163 2164 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2165 &error_abort); 2166 if (vms->secure) { 2167 object_property_set_link(cpuobj, "secure-memory", 2168 OBJECT(secure_sysmem), &error_abort); 2169 } 2170 2171 if (vms->mte) { 2172 /* Create the memory region only once, but link to all cpus. */ 2173 if (!tag_sysmem) { 2174 /* 2175 * The property exists only if MemTag is supported. 2176 * If it is, we must allocate the ram to back that up. 2177 */ 2178 if (!object_property_find(cpuobj, "tag-memory")) { 2179 error_report("MTE requested, but not supported " 2180 "by the guest CPU"); 2181 exit(1); 2182 } 2183 2184 tag_sysmem = g_new(MemoryRegion, 1); 2185 memory_region_init(tag_sysmem, OBJECT(machine), 2186 "tag-memory", UINT64_MAX / 32); 2187 2188 if (vms->secure) { 2189 secure_tag_sysmem = g_new(MemoryRegion, 1); 2190 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2191 "secure-tag-memory", UINT64_MAX / 32); 2192 2193 /* As with ram, secure-tag takes precedence over tag. */ 2194 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2195 tag_sysmem, -1); 2196 } 2197 } 2198 2199 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2200 &error_abort); 2201 if (vms->secure) { 2202 object_property_set_link(cpuobj, "secure-tag-memory", 2203 OBJECT(secure_tag_sysmem), 2204 &error_abort); 2205 } 2206 } 2207 2208 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2209 object_unref(cpuobj); 2210 } 2211 fdt_add_timer_nodes(vms); 2212 fdt_add_cpu_nodes(vms); 2213 2214 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2215 machine->ram); 2216 if (machine->device_memory) { 2217 memory_region_add_subregion(sysmem, machine->device_memory->base, 2218 &machine->device_memory->mr); 2219 } 2220 2221 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2222 2223 create_gic(vms, sysmem); 2224 2225 virt_cpu_post_init(vms, sysmem); 2226 2227 fdt_add_pmu_nodes(vms); 2228 2229 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2230 2231 if (vms->secure) { 2232 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2233 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2234 } 2235 2236 if (tag_sysmem) { 2237 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2238 machine->ram_size, "mach-virt.tag"); 2239 } 2240 2241 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2242 2243 create_rtc(vms); 2244 2245 create_pcie(vms); 2246 2247 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2248 vms->acpi_dev = create_acpi_ged(vms); 2249 } else { 2250 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2251 } 2252 2253 if (vms->secure && !vmc->no_secure_gpio) { 2254 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2255 } 2256 2257 /* connect powerdown request */ 2258 vms->powerdown_notifier.notify = virt_powerdown_req; 2259 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2260 2261 /* Create mmio transports, so the user can create virtio backends 2262 * (which will be automatically plugged in to the transports). If 2263 * no backend is created the transport will just sit harmlessly idle. 2264 */ 2265 create_virtio_devices(vms); 2266 2267 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2268 rom_set_fw(vms->fw_cfg); 2269 2270 create_platform_bus(vms); 2271 2272 if (machine->nvdimms_state->is_enabled) { 2273 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2274 .space_id = AML_AS_SYSTEM_MEMORY, 2275 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2276 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2277 }; 2278 2279 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2280 arm_virt_nvdimm_acpi_dsmio, 2281 vms->fw_cfg, OBJECT(vms)); 2282 } 2283 2284 vms->bootinfo.ram_size = machine->ram_size; 2285 vms->bootinfo.board_id = -1; 2286 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2287 vms->bootinfo.get_dtb = machvirt_dtb; 2288 vms->bootinfo.skip_dtb_autoload = true; 2289 vms->bootinfo.firmware_loaded = firmware_loaded; 2290 vms->bootinfo.psci_conduit = vms->psci_conduit; 2291 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2292 2293 vms->machine_done.notify = virt_machine_done; 2294 qemu_add_machine_init_done_notifier(&vms->machine_done); 2295 } 2296 2297 static bool virt_get_secure(Object *obj, Error **errp) 2298 { 2299 VirtMachineState *vms = VIRT_MACHINE(obj); 2300 2301 return vms->secure; 2302 } 2303 2304 static void virt_set_secure(Object *obj, bool value, Error **errp) 2305 { 2306 VirtMachineState *vms = VIRT_MACHINE(obj); 2307 2308 vms->secure = value; 2309 } 2310 2311 static bool virt_get_virt(Object *obj, Error **errp) 2312 { 2313 VirtMachineState *vms = VIRT_MACHINE(obj); 2314 2315 return vms->virt; 2316 } 2317 2318 static void virt_set_virt(Object *obj, bool value, Error **errp) 2319 { 2320 VirtMachineState *vms = VIRT_MACHINE(obj); 2321 2322 vms->virt = value; 2323 } 2324 2325 static bool virt_get_highmem(Object *obj, Error **errp) 2326 { 2327 VirtMachineState *vms = VIRT_MACHINE(obj); 2328 2329 return vms->highmem; 2330 } 2331 2332 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2333 { 2334 VirtMachineState *vms = VIRT_MACHINE(obj); 2335 2336 vms->highmem = value; 2337 } 2338 2339 static bool virt_get_its(Object *obj, Error **errp) 2340 { 2341 VirtMachineState *vms = VIRT_MACHINE(obj); 2342 2343 return vms->its; 2344 } 2345 2346 static void virt_set_its(Object *obj, bool value, Error **errp) 2347 { 2348 VirtMachineState *vms = VIRT_MACHINE(obj); 2349 2350 vms->its = value; 2351 } 2352 2353 static bool virt_get_dtb_kaslr_seed(Object *obj, Error **errp) 2354 { 2355 VirtMachineState *vms = VIRT_MACHINE(obj); 2356 2357 return vms->dtb_kaslr_seed; 2358 } 2359 2360 static void virt_set_dtb_kaslr_seed(Object *obj, bool value, Error **errp) 2361 { 2362 VirtMachineState *vms = VIRT_MACHINE(obj); 2363 2364 vms->dtb_kaslr_seed = value; 2365 } 2366 2367 static char *virt_get_oem_id(Object *obj, Error **errp) 2368 { 2369 VirtMachineState *vms = VIRT_MACHINE(obj); 2370 2371 return g_strdup(vms->oem_id); 2372 } 2373 2374 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2375 { 2376 VirtMachineState *vms = VIRT_MACHINE(obj); 2377 size_t len = strlen(value); 2378 2379 if (len > 6) { 2380 error_setg(errp, 2381 "User specified oem-id value is bigger than 6 bytes in size"); 2382 return; 2383 } 2384 2385 strncpy(vms->oem_id, value, 6); 2386 } 2387 2388 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2389 { 2390 VirtMachineState *vms = VIRT_MACHINE(obj); 2391 2392 return g_strdup(vms->oem_table_id); 2393 } 2394 2395 static void virt_set_oem_table_id(Object *obj, const char *value, 2396 Error **errp) 2397 { 2398 VirtMachineState *vms = VIRT_MACHINE(obj); 2399 size_t len = strlen(value); 2400 2401 if (len > 8) { 2402 error_setg(errp, 2403 "User specified oem-table-id value is bigger than 8 bytes in size"); 2404 return; 2405 } 2406 strncpy(vms->oem_table_id, value, 8); 2407 } 2408 2409 2410 bool virt_is_acpi_enabled(VirtMachineState *vms) 2411 { 2412 if (vms->acpi == ON_OFF_AUTO_OFF) { 2413 return false; 2414 } 2415 return true; 2416 } 2417 2418 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2419 void *opaque, Error **errp) 2420 { 2421 VirtMachineState *vms = VIRT_MACHINE(obj); 2422 OnOffAuto acpi = vms->acpi; 2423 2424 visit_type_OnOffAuto(v, name, &acpi, errp); 2425 } 2426 2427 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2428 void *opaque, Error **errp) 2429 { 2430 VirtMachineState *vms = VIRT_MACHINE(obj); 2431 2432 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2433 } 2434 2435 static bool virt_get_ras(Object *obj, Error **errp) 2436 { 2437 VirtMachineState *vms = VIRT_MACHINE(obj); 2438 2439 return vms->ras; 2440 } 2441 2442 static void virt_set_ras(Object *obj, bool value, Error **errp) 2443 { 2444 VirtMachineState *vms = VIRT_MACHINE(obj); 2445 2446 vms->ras = value; 2447 } 2448 2449 static bool virt_get_mte(Object *obj, Error **errp) 2450 { 2451 VirtMachineState *vms = VIRT_MACHINE(obj); 2452 2453 return vms->mte; 2454 } 2455 2456 static void virt_set_mte(Object *obj, bool value, Error **errp) 2457 { 2458 VirtMachineState *vms = VIRT_MACHINE(obj); 2459 2460 vms->mte = value; 2461 } 2462 2463 static char *virt_get_gic_version(Object *obj, Error **errp) 2464 { 2465 VirtMachineState *vms = VIRT_MACHINE(obj); 2466 const char *val; 2467 2468 switch (vms->gic_version) { 2469 case VIRT_GIC_VERSION_4: 2470 val = "4"; 2471 break; 2472 case VIRT_GIC_VERSION_3: 2473 val = "3"; 2474 break; 2475 default: 2476 val = "2"; 2477 break; 2478 } 2479 return g_strdup(val); 2480 } 2481 2482 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2483 { 2484 VirtMachineState *vms = VIRT_MACHINE(obj); 2485 2486 if (!strcmp(value, "4")) { 2487 vms->gic_version = VIRT_GIC_VERSION_4; 2488 } else if (!strcmp(value, "3")) { 2489 vms->gic_version = VIRT_GIC_VERSION_3; 2490 } else if (!strcmp(value, "2")) { 2491 vms->gic_version = VIRT_GIC_VERSION_2; 2492 } else if (!strcmp(value, "host")) { 2493 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2494 } else if (!strcmp(value, "max")) { 2495 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2496 } else { 2497 error_setg(errp, "Invalid gic-version value"); 2498 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2499 } 2500 } 2501 2502 static char *virt_get_iommu(Object *obj, Error **errp) 2503 { 2504 VirtMachineState *vms = VIRT_MACHINE(obj); 2505 2506 switch (vms->iommu) { 2507 case VIRT_IOMMU_NONE: 2508 return g_strdup("none"); 2509 case VIRT_IOMMU_SMMUV3: 2510 return g_strdup("smmuv3"); 2511 default: 2512 g_assert_not_reached(); 2513 } 2514 } 2515 2516 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2517 { 2518 VirtMachineState *vms = VIRT_MACHINE(obj); 2519 2520 if (!strcmp(value, "smmuv3")) { 2521 vms->iommu = VIRT_IOMMU_SMMUV3; 2522 } else if (!strcmp(value, "none")) { 2523 vms->iommu = VIRT_IOMMU_NONE; 2524 } else { 2525 error_setg(errp, "Invalid iommu value"); 2526 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2527 } 2528 } 2529 2530 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2531 { 2532 VirtMachineState *vms = VIRT_MACHINE(obj); 2533 2534 return vms->default_bus_bypass_iommu; 2535 } 2536 2537 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2538 Error **errp) 2539 { 2540 VirtMachineState *vms = VIRT_MACHINE(obj); 2541 2542 vms->default_bus_bypass_iommu = value; 2543 } 2544 2545 static CpuInstanceProperties 2546 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2547 { 2548 MachineClass *mc = MACHINE_GET_CLASS(ms); 2549 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2550 2551 assert(cpu_index < possible_cpus->len); 2552 return possible_cpus->cpus[cpu_index].props; 2553 } 2554 2555 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2556 { 2557 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2558 2559 return socket_id % ms->numa_state->num_nodes; 2560 } 2561 2562 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2563 { 2564 int n; 2565 unsigned int max_cpus = ms->smp.max_cpus; 2566 VirtMachineState *vms = VIRT_MACHINE(ms); 2567 MachineClass *mc = MACHINE_GET_CLASS(vms); 2568 2569 if (ms->possible_cpus) { 2570 assert(ms->possible_cpus->len == max_cpus); 2571 return ms->possible_cpus; 2572 } 2573 2574 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2575 sizeof(CPUArchId) * max_cpus); 2576 ms->possible_cpus->len = max_cpus; 2577 for (n = 0; n < ms->possible_cpus->len; n++) { 2578 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2579 ms->possible_cpus->cpus[n].arch_id = 2580 virt_cpu_mp_affinity(vms, n); 2581 2582 assert(!mc->smp_props.dies_supported); 2583 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2584 ms->possible_cpus->cpus[n].props.socket_id = 2585 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2586 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2587 ms->possible_cpus->cpus[n].props.cluster_id = 2588 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2589 ms->possible_cpus->cpus[n].props.has_core_id = true; 2590 ms->possible_cpus->cpus[n].props.core_id = 2591 (n / ms->smp.threads) % ms->smp.cores; 2592 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2593 ms->possible_cpus->cpus[n].props.thread_id = 2594 n % ms->smp.threads; 2595 } 2596 return ms->possible_cpus; 2597 } 2598 2599 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2600 Error **errp) 2601 { 2602 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2603 const MachineState *ms = MACHINE(hotplug_dev); 2604 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2605 2606 if (!vms->acpi_dev) { 2607 error_setg(errp, 2608 "memory hotplug is not enabled: missing acpi-ged device"); 2609 return; 2610 } 2611 2612 if (vms->mte) { 2613 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2614 return; 2615 } 2616 2617 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2618 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2619 return; 2620 } 2621 2622 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2623 } 2624 2625 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2626 DeviceState *dev, Error **errp) 2627 { 2628 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2629 MachineState *ms = MACHINE(hotplug_dev); 2630 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2631 2632 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2633 2634 if (is_nvdimm) { 2635 nvdimm_plug(ms->nvdimms_state); 2636 } 2637 2638 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2639 dev, &error_abort); 2640 } 2641 2642 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2643 DeviceState *dev, Error **errp) 2644 { 2645 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2646 Error *local_err = NULL; 2647 2648 if (!hotplug_dev2 && dev->hotplugged) { 2649 /* 2650 * Without a bus hotplug handler, we cannot control the plug/unplug 2651 * order. We should never reach this point when hotplugging on ARM. 2652 * However, it's nice to add a safety net, similar to what we have 2653 * on x86. 2654 */ 2655 error_setg(errp, "hotplug of virtio based memory devices not supported" 2656 " on this bus."); 2657 return; 2658 } 2659 /* 2660 * First, see if we can plug this memory device at all. If that 2661 * succeeds, branch of to the actual hotplug handler. 2662 */ 2663 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2664 &local_err); 2665 if (!local_err && hotplug_dev2) { 2666 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2667 } 2668 error_propagate(errp, local_err); 2669 } 2670 2671 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2672 DeviceState *dev, Error **errp) 2673 { 2674 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2675 Error *local_err = NULL; 2676 2677 /* 2678 * Plug the memory device first and then branch off to the actual 2679 * hotplug handler. If that one fails, we can easily undo the memory 2680 * device bits. 2681 */ 2682 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2683 if (hotplug_dev2) { 2684 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2685 if (local_err) { 2686 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2687 } 2688 } 2689 error_propagate(errp, local_err); 2690 } 2691 2692 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2693 DeviceState *dev, Error **errp) 2694 { 2695 /* We don't support hot unplug of virtio based memory devices */ 2696 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2697 } 2698 2699 2700 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2701 DeviceState *dev, Error **errp) 2702 { 2703 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2704 2705 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2706 virt_memory_pre_plug(hotplug_dev, dev, errp); 2707 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2708 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2709 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2710 hwaddr db_start = 0, db_end = 0; 2711 char *resv_prop_str; 2712 2713 if (vms->iommu != VIRT_IOMMU_NONE) { 2714 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2715 return; 2716 } 2717 2718 switch (vms->msi_controller) { 2719 case VIRT_MSI_CTRL_NONE: 2720 return; 2721 case VIRT_MSI_CTRL_ITS: 2722 /* GITS_TRANSLATER page */ 2723 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2724 db_end = base_memmap[VIRT_GIC_ITS].base + 2725 base_memmap[VIRT_GIC_ITS].size - 1; 2726 break; 2727 case VIRT_MSI_CTRL_GICV2M: 2728 /* MSI_SETSPI_NS page */ 2729 db_start = base_memmap[VIRT_GIC_V2M].base; 2730 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2731 break; 2732 } 2733 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2734 db_start, db_end, 2735 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2736 2737 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2738 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2739 resv_prop_str, errp); 2740 g_free(resv_prop_str); 2741 } 2742 } 2743 2744 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2745 DeviceState *dev, Error **errp) 2746 { 2747 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2748 2749 if (vms->platform_bus_dev) { 2750 MachineClass *mc = MACHINE_GET_CLASS(vms); 2751 2752 if (device_is_dynamic_sysbus(mc, dev)) { 2753 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2754 SYS_BUS_DEVICE(dev)); 2755 } 2756 } 2757 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2758 virt_memory_plug(hotplug_dev, dev, errp); 2759 } 2760 2761 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2762 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2763 } 2764 2765 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2766 PCIDevice *pdev = PCI_DEVICE(dev); 2767 2768 vms->iommu = VIRT_IOMMU_VIRTIO; 2769 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2770 create_virtio_iommu_dt_bindings(vms); 2771 } 2772 } 2773 2774 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2775 DeviceState *dev, Error **errp) 2776 { 2777 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2778 Error *local_err = NULL; 2779 2780 if (!vms->acpi_dev) { 2781 error_setg(&local_err, 2782 "memory hotplug is not enabled: missing acpi-ged device"); 2783 goto out; 2784 } 2785 2786 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2787 error_setg(&local_err, 2788 "nvdimm device hot unplug is not supported yet."); 2789 goto out; 2790 } 2791 2792 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2793 &local_err); 2794 out: 2795 error_propagate(errp, local_err); 2796 } 2797 2798 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2799 DeviceState *dev, Error **errp) 2800 { 2801 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2802 Error *local_err = NULL; 2803 2804 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2805 if (local_err) { 2806 goto out; 2807 } 2808 2809 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2810 qdev_unrealize(dev); 2811 2812 out: 2813 error_propagate(errp, local_err); 2814 } 2815 2816 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2817 DeviceState *dev, Error **errp) 2818 { 2819 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2820 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2821 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2822 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2823 } else { 2824 error_setg(errp, "device unplug request for unsupported device" 2825 " type: %s", object_get_typename(OBJECT(dev))); 2826 } 2827 } 2828 2829 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2830 DeviceState *dev, Error **errp) 2831 { 2832 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2833 virt_dimm_unplug(hotplug_dev, dev, errp); 2834 } else { 2835 error_setg(errp, "virt: device unplug for unsupported device" 2836 " type: %s", object_get_typename(OBJECT(dev))); 2837 } 2838 } 2839 2840 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2841 DeviceState *dev) 2842 { 2843 MachineClass *mc = MACHINE_GET_CLASS(machine); 2844 2845 if (device_is_dynamic_sysbus(mc, dev) || 2846 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2847 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2848 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2849 return HOTPLUG_HANDLER(machine); 2850 } 2851 return NULL; 2852 } 2853 2854 /* 2855 * for arm64 kvm_type [7-0] encodes the requested number of bits 2856 * in the IPA address space 2857 */ 2858 static int virt_kvm_type(MachineState *ms, const char *type_str) 2859 { 2860 VirtMachineState *vms = VIRT_MACHINE(ms); 2861 int max_vm_pa_size, requested_pa_size; 2862 bool fixed_ipa; 2863 2864 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2865 2866 /* we freeze the memory map to compute the highest gpa */ 2867 virt_set_memmap(vms, max_vm_pa_size); 2868 2869 requested_pa_size = 64 - clz64(vms->highest_gpa); 2870 2871 /* 2872 * KVM requires the IPA size to be at least 32 bits. 2873 */ 2874 if (requested_pa_size < 32) { 2875 requested_pa_size = 32; 2876 } 2877 2878 if (requested_pa_size > max_vm_pa_size) { 2879 error_report("-m and ,maxmem option values " 2880 "require an IPA range (%d bits) larger than " 2881 "the one supported by the host (%d bits)", 2882 requested_pa_size, max_vm_pa_size); 2883 exit(1); 2884 } 2885 /* 2886 * We return the requested PA log size, unless KVM only supports 2887 * the implicit legacy 40b IPA setting, in which case the kvm_type 2888 * must be 0. 2889 */ 2890 return fixed_ipa ? 0 : requested_pa_size; 2891 } 2892 2893 static void virt_machine_class_init(ObjectClass *oc, void *data) 2894 { 2895 MachineClass *mc = MACHINE_CLASS(oc); 2896 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2897 2898 mc->init = machvirt_init; 2899 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2900 * The value may be reduced later when we have more information about the 2901 * configuration of the particular instance. 2902 */ 2903 mc->max_cpus = 512; 2904 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2905 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2906 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2907 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2908 #ifdef CONFIG_TPM 2909 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2910 #endif 2911 mc->block_default_type = IF_VIRTIO; 2912 mc->no_cdrom = 1; 2913 mc->pci_allow_0_address = true; 2914 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2915 mc->minimum_page_bits = 12; 2916 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2917 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2918 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2919 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2920 mc->kvm_type = virt_kvm_type; 2921 assert(!mc->get_hotplug_handler); 2922 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2923 hc->pre_plug = virt_machine_device_pre_plug_cb; 2924 hc->plug = virt_machine_device_plug_cb; 2925 hc->unplug_request = virt_machine_device_unplug_request_cb; 2926 hc->unplug = virt_machine_device_unplug_cb; 2927 mc->nvdimm_supported = true; 2928 mc->smp_props.clusters_supported = true; 2929 mc->auto_enable_numa_with_memhp = true; 2930 mc->auto_enable_numa_with_memdev = true; 2931 mc->default_ram_id = "mach-virt.ram"; 2932 2933 object_class_property_add(oc, "acpi", "OnOffAuto", 2934 virt_get_acpi, virt_set_acpi, 2935 NULL, NULL); 2936 object_class_property_set_description(oc, "acpi", 2937 "Enable ACPI"); 2938 object_class_property_add_bool(oc, "secure", virt_get_secure, 2939 virt_set_secure); 2940 object_class_property_set_description(oc, "secure", 2941 "Set on/off to enable/disable the ARM " 2942 "Security Extensions (TrustZone)"); 2943 2944 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2945 virt_set_virt); 2946 object_class_property_set_description(oc, "virtualization", 2947 "Set on/off to enable/disable emulating a " 2948 "guest CPU which implements the ARM " 2949 "Virtualization Extensions"); 2950 2951 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2952 virt_set_highmem); 2953 object_class_property_set_description(oc, "highmem", 2954 "Set on/off to enable/disable using " 2955 "physical address space above 32 bits"); 2956 2957 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 2958 virt_set_gic_version); 2959 object_class_property_set_description(oc, "gic-version", 2960 "Set GIC version. " 2961 "Valid values are 2, 3, 4, host and max"); 2962 2963 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 2964 object_class_property_set_description(oc, "iommu", 2965 "Set the IOMMU type. " 2966 "Valid values are none and smmuv3"); 2967 2968 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 2969 virt_get_default_bus_bypass_iommu, 2970 virt_set_default_bus_bypass_iommu); 2971 object_class_property_set_description(oc, "default-bus-bypass-iommu", 2972 "Set on/off to enable/disable " 2973 "bypass_iommu for default root bus"); 2974 2975 object_class_property_add_bool(oc, "ras", virt_get_ras, 2976 virt_set_ras); 2977 object_class_property_set_description(oc, "ras", 2978 "Set on/off to enable/disable reporting host memory errors " 2979 "to a KVM guest using ACPI and guest external abort exceptions"); 2980 2981 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 2982 object_class_property_set_description(oc, "mte", 2983 "Set on/off to enable/disable emulating a " 2984 "guest CPU which implements the ARM " 2985 "Memory Tagging Extension"); 2986 2987 object_class_property_add_bool(oc, "its", virt_get_its, 2988 virt_set_its); 2989 object_class_property_set_description(oc, "its", 2990 "Set on/off to enable/disable " 2991 "ITS instantiation"); 2992 2993 object_class_property_add_bool(oc, "dtb-kaslr-seed", 2994 virt_get_dtb_kaslr_seed, 2995 virt_set_dtb_kaslr_seed); 2996 object_class_property_set_description(oc, "dtb-kaslr-seed", 2997 "Set off to disable passing of kaslr-seed " 2998 "dtb node to guest"); 2999 3000 object_class_property_add_str(oc, "x-oem-id", 3001 virt_get_oem_id, 3002 virt_set_oem_id); 3003 object_class_property_set_description(oc, "x-oem-id", 3004 "Override the default value of field OEMID " 3005 "in ACPI table header." 3006 "The string may be up to 6 bytes in size"); 3007 3008 3009 object_class_property_add_str(oc, "x-oem-table-id", 3010 virt_get_oem_table_id, 3011 virt_set_oem_table_id); 3012 object_class_property_set_description(oc, "x-oem-table-id", 3013 "Override the default value of field OEM Table ID " 3014 "in ACPI table header." 3015 "The string may be up to 8 bytes in size"); 3016 3017 } 3018 3019 static void virt_instance_init(Object *obj) 3020 { 3021 VirtMachineState *vms = VIRT_MACHINE(obj); 3022 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3023 3024 /* EL3 is disabled by default on virt: this makes us consistent 3025 * between KVM and TCG for this board, and it also allows us to 3026 * boot UEFI blobs which assume no TrustZone support. 3027 */ 3028 vms->secure = false; 3029 3030 /* EL2 is also disabled by default, for similar reasons */ 3031 vms->virt = false; 3032 3033 /* High memory is enabled by default */ 3034 vms->highmem = true; 3035 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3036 3037 vms->highmem_ecam = !vmc->no_highmem_ecam; 3038 vms->highmem_mmio = true; 3039 vms->highmem_redists = true; 3040 3041 if (vmc->no_its) { 3042 vms->its = false; 3043 } else { 3044 /* Default allows ITS instantiation */ 3045 vms->its = true; 3046 3047 if (vmc->no_tcg_its) { 3048 vms->tcg_its = false; 3049 } else { 3050 vms->tcg_its = true; 3051 } 3052 } 3053 3054 /* Default disallows iommu instantiation */ 3055 vms->iommu = VIRT_IOMMU_NONE; 3056 3057 /* The default root bus is attached to iommu by default */ 3058 vms->default_bus_bypass_iommu = false; 3059 3060 /* Default disallows RAS instantiation */ 3061 vms->ras = false; 3062 3063 /* MTE is disabled by default. */ 3064 vms->mte = false; 3065 3066 /* Supply a kaslr-seed by default */ 3067 vms->dtb_kaslr_seed = true; 3068 3069 vms->irqmap = a15irqmap; 3070 3071 virt_flash_create(vms); 3072 3073 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3074 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3075 } 3076 3077 static const TypeInfo virt_machine_info = { 3078 .name = TYPE_VIRT_MACHINE, 3079 .parent = TYPE_MACHINE, 3080 .abstract = true, 3081 .instance_size = sizeof(VirtMachineState), 3082 .class_size = sizeof(VirtMachineClass), 3083 .class_init = virt_machine_class_init, 3084 .instance_init = virt_instance_init, 3085 .interfaces = (InterfaceInfo[]) { 3086 { TYPE_HOTPLUG_HANDLER }, 3087 { } 3088 }, 3089 }; 3090 3091 static void machvirt_machine_init(void) 3092 { 3093 type_register_static(&virt_machine_info); 3094 } 3095 type_init(machvirt_machine_init); 3096 3097 static void virt_machine_7_1_options(MachineClass *mc) 3098 { 3099 } 3100 DEFINE_VIRT_MACHINE_AS_LATEST(7, 1) 3101 3102 static void virt_machine_7_0_options(MachineClass *mc) 3103 { 3104 virt_machine_7_1_options(mc); 3105 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3106 } 3107 DEFINE_VIRT_MACHINE(7, 0) 3108 3109 static void virt_machine_6_2_options(MachineClass *mc) 3110 { 3111 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3112 3113 virt_machine_7_0_options(mc); 3114 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3115 vmc->no_tcg_lpa2 = true; 3116 } 3117 DEFINE_VIRT_MACHINE(6, 2) 3118 3119 static void virt_machine_6_1_options(MachineClass *mc) 3120 { 3121 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3122 3123 virt_machine_6_2_options(mc); 3124 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3125 mc->smp_props.prefer_sockets = true; 3126 vmc->no_cpu_topology = true; 3127 3128 /* qemu ITS was introduced with 6.2 */ 3129 vmc->no_tcg_its = true; 3130 } 3131 DEFINE_VIRT_MACHINE(6, 1) 3132 3133 static void virt_machine_6_0_options(MachineClass *mc) 3134 { 3135 virt_machine_6_1_options(mc); 3136 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3137 } 3138 DEFINE_VIRT_MACHINE(6, 0) 3139 3140 static void virt_machine_5_2_options(MachineClass *mc) 3141 { 3142 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3143 3144 virt_machine_6_0_options(mc); 3145 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3146 vmc->no_secure_gpio = true; 3147 } 3148 DEFINE_VIRT_MACHINE(5, 2) 3149 3150 static void virt_machine_5_1_options(MachineClass *mc) 3151 { 3152 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3153 3154 virt_machine_5_2_options(mc); 3155 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3156 vmc->no_kvm_steal_time = true; 3157 } 3158 DEFINE_VIRT_MACHINE(5, 1) 3159 3160 static void virt_machine_5_0_options(MachineClass *mc) 3161 { 3162 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3163 3164 virt_machine_5_1_options(mc); 3165 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3166 mc->numa_mem_supported = true; 3167 vmc->acpi_expose_flash = true; 3168 mc->auto_enable_numa_with_memdev = false; 3169 } 3170 DEFINE_VIRT_MACHINE(5, 0) 3171 3172 static void virt_machine_4_2_options(MachineClass *mc) 3173 { 3174 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3175 3176 virt_machine_5_0_options(mc); 3177 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3178 vmc->kvm_no_adjvtime = true; 3179 } 3180 DEFINE_VIRT_MACHINE(4, 2) 3181 3182 static void virt_machine_4_1_options(MachineClass *mc) 3183 { 3184 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3185 3186 virt_machine_4_2_options(mc); 3187 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3188 vmc->no_ged = true; 3189 mc->auto_enable_numa_with_memhp = false; 3190 } 3191 DEFINE_VIRT_MACHINE(4, 1) 3192 3193 static void virt_machine_4_0_options(MachineClass *mc) 3194 { 3195 virt_machine_4_1_options(mc); 3196 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3197 } 3198 DEFINE_VIRT_MACHINE(4, 0) 3199 3200 static void virt_machine_3_1_options(MachineClass *mc) 3201 { 3202 virt_machine_4_0_options(mc); 3203 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3204 } 3205 DEFINE_VIRT_MACHINE(3, 1) 3206 3207 static void virt_machine_3_0_options(MachineClass *mc) 3208 { 3209 virt_machine_3_1_options(mc); 3210 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3211 } 3212 DEFINE_VIRT_MACHINE(3, 0) 3213 3214 static void virt_machine_2_12_options(MachineClass *mc) 3215 { 3216 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3217 3218 virt_machine_3_0_options(mc); 3219 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3220 vmc->no_highmem_ecam = true; 3221 mc->max_cpus = 255; 3222 } 3223 DEFINE_VIRT_MACHINE(2, 12) 3224 3225 static void virt_machine_2_11_options(MachineClass *mc) 3226 { 3227 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3228 3229 virt_machine_2_12_options(mc); 3230 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3231 vmc->smbios_old_sys_ver = true; 3232 } 3233 DEFINE_VIRT_MACHINE(2, 11) 3234 3235 static void virt_machine_2_10_options(MachineClass *mc) 3236 { 3237 virt_machine_2_11_options(mc); 3238 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3239 /* before 2.11 we never faulted accesses to bad addresses */ 3240 mc->ignore_memory_transaction_failures = true; 3241 } 3242 DEFINE_VIRT_MACHINE(2, 10) 3243 3244 static void virt_machine_2_9_options(MachineClass *mc) 3245 { 3246 virt_machine_2_10_options(mc); 3247 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3248 } 3249 DEFINE_VIRT_MACHINE(2, 9) 3250 3251 static void virt_machine_2_8_options(MachineClass *mc) 3252 { 3253 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3254 3255 virt_machine_2_9_options(mc); 3256 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3257 /* For 2.8 and earlier we falsely claimed in the DT that 3258 * our timers were edge-triggered, not level-triggered. 3259 */ 3260 vmc->claim_edge_triggered_timers = true; 3261 } 3262 DEFINE_VIRT_MACHINE(2, 8) 3263 3264 static void virt_machine_2_7_options(MachineClass *mc) 3265 { 3266 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3267 3268 virt_machine_2_8_options(mc); 3269 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3270 /* ITS was introduced with 2.8 */ 3271 vmc->no_its = true; 3272 /* Stick with 1K pages for migration compatibility */ 3273 mc->minimum_page_bits = 0; 3274 } 3275 DEFINE_VIRT_MACHINE(2, 7) 3276 3277 static void virt_machine_2_6_options(MachineClass *mc) 3278 { 3279 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3280 3281 virt_machine_2_7_options(mc); 3282 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3283 vmc->disallow_affinity_adjustment = true; 3284 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3285 vmc->no_pmu = true; 3286 } 3287 DEFINE_VIRT_MACHINE(2, 6) 3288