1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/irq.h" 67 #include "kvm_arm.h" 68 #include "hw/firmware/smbios.h" 69 #include "qapi/visitor.h" 70 #include "qapi/qapi-visit-common.h" 71 #include "standard-headers/linux/input.h" 72 #include "hw/arm/smmuv3.h" 73 #include "hw/acpi/acpi.h" 74 #include "target/arm/internals.h" 75 #include "hw/mem/memory-device.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/acpi/generic_event_device.h" 79 #include "hw/virtio/virtio-mem-pci.h" 80 #include "hw/virtio/virtio-iommu.h" 81 #include "hw/char/pl011.h" 82 #include "qemu/guest-random.h" 83 84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 86 void *data) \ 87 { \ 88 MachineClass *mc = MACHINE_CLASS(oc); \ 89 virt_machine_##major##_##minor##_options(mc); \ 90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 91 if (latest) { \ 92 mc->alias = "virt"; \ 93 } \ 94 } \ 95 static const TypeInfo machvirt_##major##_##minor##_info = { \ 96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 97 .parent = TYPE_VIRT_MACHINE, \ 98 .class_init = virt_##major##_##minor##_class_init, \ 99 }; \ 100 static void machvirt_machine_##major##_##minor##_init(void) \ 101 { \ 102 type_register_static(&machvirt_##major##_##minor##_info); \ 103 } \ 104 type_init(machvirt_machine_##major##_##minor##_init); 105 106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 108 #define DEFINE_VIRT_MACHINE(major, minor) \ 109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 110 111 112 /* Number of external interrupt lines to configure the GIC with */ 113 #define NUM_IRQS 256 114 115 #define PLATFORM_BUS_NUM_IRQS 64 116 117 /* Legacy RAM limit in GB (< version 4.0) */ 118 #define LEGACY_RAMLIMIT_GB 255 119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 120 121 /* Addresses and sizes of our components. 122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 123 * 128MB..256MB is used for miscellaneous device I/O. 124 * 256MB..1GB is reserved for possible future PCI support (ie where the 125 * PCI memory window will go if we add a PCI host controller). 126 * 1GB and up is RAM (which may happily spill over into the 127 * high memory region beyond 4GB). 128 * This represents a compromise between how much RAM can be given to 129 * a 32 bit VM and leaving space for expansion and in particular for PCI. 130 * Note that devices should generally be placed at multiples of 0x10000, 131 * to accommodate guests using 64K pages. 132 */ 133 static const MemMapEntry base_memmap[] = { 134 /* Space up to 0x8000000 is reserved for a boot ROM */ 135 [VIRT_FLASH] = { 0, 0x08000000 }, 136 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 138 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 139 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 140 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 141 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 142 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 144 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 145 /* This redistributor space allows up to 2*64kB*123 CPUs */ 146 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 147 [VIRT_UART] = { 0x09000000, 0x00001000 }, 148 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 149 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 150 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 151 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 152 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 153 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 154 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 155 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 156 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 157 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 158 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 160 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 161 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 162 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 163 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 164 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 165 /* Actual RAM size depends on initial RAM and device memory settings */ 166 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 167 }; 168 169 /* 170 * Highmem IO Regions: This memory map is floating, located after the RAM. 171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 172 * top of the RAM, so that its base get the same alignment as the size, 173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 175 * Note the extended_memmap is sized so that it eventually also includes the 176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 177 * index of base_memmap). 178 * 179 * The memory map for these Highmem IO Regions can be in legacy or compact 180 * layout, depending on 'compact-highmem' property. With legacy layout, the 181 * PA space for one specific region is always reserved, even if the region 182 * has been disabled or doesn't fit into the PA space. However, the PA space 183 * for the region won't be reserved in these circumstances with compact layout. 184 */ 185 static MemMapEntry extended_memmap[] = { 186 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 187 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 188 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 189 /* Second PCIe window */ 190 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 191 }; 192 193 static const int a15irqmap[] = { 194 [VIRT_UART] = 1, 195 [VIRT_RTC] = 2, 196 [VIRT_PCIE] = 3, /* ... to 6 */ 197 [VIRT_GPIO] = 7, 198 [VIRT_SECURE_UART] = 8, 199 [VIRT_ACPI_GED] = 9, 200 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 201 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 202 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 203 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 204 }; 205 206 static const char *valid_cpus[] = { 207 #ifdef CONFIG_TCG 208 ARM_CPU_TYPE_NAME("cortex-a7"), 209 ARM_CPU_TYPE_NAME("cortex-a15"), 210 ARM_CPU_TYPE_NAME("cortex-a35"), 211 ARM_CPU_TYPE_NAME("cortex-a55"), 212 ARM_CPU_TYPE_NAME("cortex-a72"), 213 ARM_CPU_TYPE_NAME("cortex-a76"), 214 ARM_CPU_TYPE_NAME("a64fx"), 215 ARM_CPU_TYPE_NAME("neoverse-n1"), 216 #endif 217 ARM_CPU_TYPE_NAME("cortex-a53"), 218 ARM_CPU_TYPE_NAME("cortex-a57"), 219 ARM_CPU_TYPE_NAME("host"), 220 ARM_CPU_TYPE_NAME("max"), 221 }; 222 223 static bool cpu_type_valid(const char *cpu) 224 { 225 int i; 226 227 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 228 if (strcmp(cpu, valid_cpus[i]) == 0) { 229 return true; 230 } 231 } 232 return false; 233 } 234 235 static void create_randomness(MachineState *ms, const char *node) 236 { 237 struct { 238 uint64_t kaslr; 239 uint8_t rng[32]; 240 } seed; 241 242 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 243 return; 244 } 245 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 246 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 247 } 248 249 static void create_fdt(VirtMachineState *vms) 250 { 251 MachineState *ms = MACHINE(vms); 252 int nb_numa_nodes = ms->numa_state->num_nodes; 253 void *fdt = create_device_tree(&vms->fdt_size); 254 255 if (!fdt) { 256 error_report("create_device_tree() failed"); 257 exit(1); 258 } 259 260 ms->fdt = fdt; 261 262 /* Header */ 263 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 264 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 265 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 266 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 267 268 /* /chosen must exist for load_dtb to fill in necessary properties later */ 269 qemu_fdt_add_subnode(fdt, "/chosen"); 270 if (vms->dtb_randomness) { 271 create_randomness(ms, "/chosen"); 272 } 273 274 if (vms->secure) { 275 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 276 if (vms->dtb_randomness) { 277 create_randomness(ms, "/secure-chosen"); 278 } 279 } 280 281 /* Clock node, for the benefit of the UART. The kernel device tree 282 * binding documentation claims the PL011 node clock properties are 283 * optional but in practice if you omit them the kernel refuses to 284 * probe for the device. 285 */ 286 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 287 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 288 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 289 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 290 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 291 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 292 "clk24mhz"); 293 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 294 295 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 296 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 297 uint32_t *matrix = g_malloc0(size); 298 int idx, i, j; 299 300 for (i = 0; i < nb_numa_nodes; i++) { 301 for (j = 0; j < nb_numa_nodes; j++) { 302 idx = (i * nb_numa_nodes + j) * 3; 303 matrix[idx + 0] = cpu_to_be32(i); 304 matrix[idx + 1] = cpu_to_be32(j); 305 matrix[idx + 2] = 306 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 307 } 308 } 309 310 qemu_fdt_add_subnode(fdt, "/distance-map"); 311 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 312 "numa-distance-map-v1"); 313 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 314 matrix, size); 315 g_free(matrix); 316 } 317 } 318 319 static void fdt_add_timer_nodes(const VirtMachineState *vms) 320 { 321 /* On real hardware these interrupts are level-triggered. 322 * On KVM they were edge-triggered before host kernel version 4.4, 323 * and level-triggered afterwards. 324 * On emulated QEMU they are level-triggered. 325 * 326 * Getting the DTB info about them wrong is awkward for some 327 * guest kernels: 328 * pre-4.8 ignore the DT and leave the interrupt configured 329 * with whatever the GIC reset value (or the bootloader) left it at 330 * 4.8 before rc6 honour the incorrect data by programming it back 331 * into the GIC, causing problems 332 * 4.8rc6 and later ignore the DT and always write "level triggered" 333 * into the GIC 334 * 335 * For backwards-compatibility, virt-2.8 and earlier will continue 336 * to say these are edge-triggered, but later machines will report 337 * the correct information. 338 */ 339 ARMCPU *armcpu; 340 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 341 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 342 MachineState *ms = MACHINE(vms); 343 344 if (vmc->claim_edge_triggered_timers) { 345 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 346 } 347 348 if (vms->gic_version == VIRT_GIC_VERSION_2) { 349 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 350 GIC_FDT_IRQ_PPI_CPU_WIDTH, 351 (1 << MACHINE(vms)->smp.cpus) - 1); 352 } 353 354 qemu_fdt_add_subnode(ms->fdt, "/timer"); 355 356 armcpu = ARM_CPU(qemu_get_cpu(0)); 357 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 358 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 359 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 360 compat, sizeof(compat)); 361 } else { 362 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 363 "arm,armv7-timer"); 364 } 365 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 366 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 367 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 368 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 370 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 371 } 372 373 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 374 { 375 int cpu; 376 int addr_cells = 1; 377 const MachineState *ms = MACHINE(vms); 378 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 379 int smp_cpus = ms->smp.cpus; 380 381 /* 382 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 383 * On ARM v8 64-bit systems value should be set to 2, 384 * that corresponds to the MPIDR_EL1 register size. 385 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 386 * in the system, #address-cells can be set to 1, since 387 * MPIDR_EL1[63:32] bits are not used for CPUs 388 * identification. 389 * 390 * Here we actually don't know whether our system is 32- or 64-bit one. 391 * The simplest way to go is to examine affinity IDs of all our CPUs. If 392 * at least one of them has Aff3 populated, we set #address-cells to 2. 393 */ 394 for (cpu = 0; cpu < smp_cpus; cpu++) { 395 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 396 397 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 398 addr_cells = 2; 399 break; 400 } 401 } 402 403 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 404 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 405 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 406 407 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 408 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 409 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 410 CPUState *cs = CPU(armcpu); 411 412 qemu_fdt_add_subnode(ms->fdt, nodename); 413 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 414 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 415 armcpu->dtb_compatible); 416 417 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 418 qemu_fdt_setprop_string(ms->fdt, nodename, 419 "enable-method", "psci"); 420 } 421 422 if (addr_cells == 2) { 423 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 424 armcpu->mp_affinity); 425 } else { 426 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 427 armcpu->mp_affinity); 428 } 429 430 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 431 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 432 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 433 } 434 435 if (!vmc->no_cpu_topology) { 436 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 437 qemu_fdt_alloc_phandle(ms->fdt)); 438 } 439 440 g_free(nodename); 441 } 442 443 if (!vmc->no_cpu_topology) { 444 /* 445 * Add vCPU topology description through fdt node cpu-map. 446 * 447 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 448 * In a SMP system, the hierarchy of CPUs can be defined through 449 * four entities that are used to describe the layout of CPUs in 450 * the system: socket/cluster/core/thread. 451 * 452 * A socket node represents the boundary of system physical package 453 * and its child nodes must be one or more cluster nodes. A system 454 * can contain several layers of clustering within a single physical 455 * package and cluster nodes can be contained in parent cluster nodes. 456 * 457 * Note: currently we only support one layer of clustering within 458 * each physical package. 459 */ 460 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 461 462 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 463 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 464 char *map_path; 465 466 if (ms->smp.threads > 1) { 467 map_path = g_strdup_printf( 468 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 469 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 470 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 471 (cpu / ms->smp.threads) % ms->smp.cores, 472 cpu % ms->smp.threads); 473 } else { 474 map_path = g_strdup_printf( 475 "/cpus/cpu-map/socket%d/cluster%d/core%d", 476 cpu / (ms->smp.clusters * ms->smp.cores), 477 (cpu / ms->smp.cores) % ms->smp.clusters, 478 cpu % ms->smp.cores); 479 } 480 qemu_fdt_add_path(ms->fdt, map_path); 481 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 482 483 g_free(map_path); 484 g_free(cpu_path); 485 } 486 } 487 } 488 489 static void fdt_add_its_gic_node(VirtMachineState *vms) 490 { 491 char *nodename; 492 MachineState *ms = MACHINE(vms); 493 494 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 495 nodename = g_strdup_printf("/intc/its@%" PRIx64, 496 vms->memmap[VIRT_GIC_ITS].base); 497 qemu_fdt_add_subnode(ms->fdt, nodename); 498 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 499 "arm,gic-v3-its"); 500 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 501 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 502 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 503 2, vms->memmap[VIRT_GIC_ITS].base, 504 2, vms->memmap[VIRT_GIC_ITS].size); 505 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 506 g_free(nodename); 507 } 508 509 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 510 { 511 MachineState *ms = MACHINE(vms); 512 char *nodename; 513 514 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 515 vms->memmap[VIRT_GIC_V2M].base); 516 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 517 qemu_fdt_add_subnode(ms->fdt, nodename); 518 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 519 "arm,gic-v2m-frame"); 520 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 521 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 522 2, vms->memmap[VIRT_GIC_V2M].base, 523 2, vms->memmap[VIRT_GIC_V2M].size); 524 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 525 g_free(nodename); 526 } 527 528 static void fdt_add_gic_node(VirtMachineState *vms) 529 { 530 MachineState *ms = MACHINE(vms); 531 char *nodename; 532 533 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 534 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 535 536 nodename = g_strdup_printf("/intc@%" PRIx64, 537 vms->memmap[VIRT_GIC_DIST].base); 538 qemu_fdt_add_subnode(ms->fdt, nodename); 539 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 540 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 541 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 542 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 543 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 544 if (vms->gic_version != VIRT_GIC_VERSION_2) { 545 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 546 547 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 548 "arm,gic-v3"); 549 550 qemu_fdt_setprop_cell(ms->fdt, nodename, 551 "#redistributor-regions", nb_redist_regions); 552 553 if (nb_redist_regions == 1) { 554 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 555 2, vms->memmap[VIRT_GIC_DIST].base, 556 2, vms->memmap[VIRT_GIC_DIST].size, 557 2, vms->memmap[VIRT_GIC_REDIST].base, 558 2, vms->memmap[VIRT_GIC_REDIST].size); 559 } else { 560 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 561 2, vms->memmap[VIRT_GIC_DIST].base, 562 2, vms->memmap[VIRT_GIC_DIST].size, 563 2, vms->memmap[VIRT_GIC_REDIST].base, 564 2, vms->memmap[VIRT_GIC_REDIST].size, 565 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 566 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 567 } 568 569 if (vms->virt) { 570 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 571 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 572 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 573 } 574 } else { 575 /* 'cortex-a15-gic' means 'GIC v2' */ 576 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 577 "arm,cortex-a15-gic"); 578 if (!vms->virt) { 579 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 580 2, vms->memmap[VIRT_GIC_DIST].base, 581 2, vms->memmap[VIRT_GIC_DIST].size, 582 2, vms->memmap[VIRT_GIC_CPU].base, 583 2, vms->memmap[VIRT_GIC_CPU].size); 584 } else { 585 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 586 2, vms->memmap[VIRT_GIC_DIST].base, 587 2, vms->memmap[VIRT_GIC_DIST].size, 588 2, vms->memmap[VIRT_GIC_CPU].base, 589 2, vms->memmap[VIRT_GIC_CPU].size, 590 2, vms->memmap[VIRT_GIC_HYP].base, 591 2, vms->memmap[VIRT_GIC_HYP].size, 592 2, vms->memmap[VIRT_GIC_VCPU].base, 593 2, vms->memmap[VIRT_GIC_VCPU].size); 594 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 595 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 596 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 597 } 598 } 599 600 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 601 g_free(nodename); 602 } 603 604 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 605 { 606 ARMCPU *armcpu = ARM_CPU(first_cpu); 607 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 608 MachineState *ms = MACHINE(vms); 609 610 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 611 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 612 return; 613 } 614 615 if (vms->gic_version == VIRT_GIC_VERSION_2) { 616 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 617 GIC_FDT_IRQ_PPI_CPU_WIDTH, 618 (1 << MACHINE(vms)->smp.cpus) - 1); 619 } 620 621 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 622 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 623 const char compat[] = "arm,armv8-pmuv3"; 624 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 625 compat, sizeof(compat)); 626 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 627 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 628 } 629 } 630 631 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 632 { 633 DeviceState *dev; 634 MachineState *ms = MACHINE(vms); 635 int irq = vms->irqmap[VIRT_ACPI_GED]; 636 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 637 638 if (ms->ram_slots) { 639 event |= ACPI_GED_MEM_HOTPLUG_EVT; 640 } 641 642 if (ms->nvdimms_state->is_enabled) { 643 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 644 } 645 646 dev = qdev_new(TYPE_ACPI_GED); 647 qdev_prop_set_uint32(dev, "ged-event", event); 648 649 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 650 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 651 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 652 653 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 654 655 return dev; 656 } 657 658 static void create_its(VirtMachineState *vms) 659 { 660 const char *itsclass = its_class_name(); 661 DeviceState *dev; 662 663 if (!strcmp(itsclass, "arm-gicv3-its")) { 664 if (!vms->tcg_its) { 665 itsclass = NULL; 666 } 667 } 668 669 if (!itsclass) { 670 /* Do nothing if not supported */ 671 return; 672 } 673 674 dev = qdev_new(itsclass); 675 676 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 677 &error_abort); 678 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 679 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 680 681 fdt_add_its_gic_node(vms); 682 vms->msi_controller = VIRT_MSI_CTRL_ITS; 683 } 684 685 static void create_v2m(VirtMachineState *vms) 686 { 687 int i; 688 int irq = vms->irqmap[VIRT_GIC_V2M]; 689 DeviceState *dev; 690 691 dev = qdev_new("arm-gicv2m"); 692 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 693 qdev_prop_set_uint32(dev, "base-spi", irq); 694 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 695 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 696 697 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 698 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 699 qdev_get_gpio_in(vms->gic, irq + i)); 700 } 701 702 fdt_add_v2m_gic_node(vms); 703 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 704 } 705 706 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 707 { 708 MachineState *ms = MACHINE(vms); 709 /* We create a standalone GIC */ 710 SysBusDevice *gicbusdev; 711 const char *gictype; 712 int i; 713 unsigned int smp_cpus = ms->smp.cpus; 714 uint32_t nb_redist_regions = 0; 715 int revision; 716 717 if (vms->gic_version == VIRT_GIC_VERSION_2) { 718 gictype = gic_class_name(); 719 } else { 720 gictype = gicv3_class_name(); 721 } 722 723 switch (vms->gic_version) { 724 case VIRT_GIC_VERSION_2: 725 revision = 2; 726 break; 727 case VIRT_GIC_VERSION_3: 728 revision = 3; 729 break; 730 case VIRT_GIC_VERSION_4: 731 revision = 4; 732 break; 733 default: 734 g_assert_not_reached(); 735 } 736 vms->gic = qdev_new(gictype); 737 qdev_prop_set_uint32(vms->gic, "revision", revision); 738 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 739 /* Note that the num-irq property counts both internal and external 740 * interrupts; there are always 32 of the former (mandated by GIC spec). 741 */ 742 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 743 if (!kvm_irqchip_in_kernel()) { 744 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 745 } 746 747 if (vms->gic_version != VIRT_GIC_VERSION_2) { 748 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 749 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 750 751 nb_redist_regions = virt_gicv3_redist_region_count(vms); 752 753 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 754 nb_redist_regions); 755 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 756 757 if (!kvm_irqchip_in_kernel()) { 758 if (vms->tcg_its) { 759 object_property_set_link(OBJECT(vms->gic), "sysmem", 760 OBJECT(mem), &error_fatal); 761 qdev_prop_set_bit(vms->gic, "has-lpi", true); 762 } 763 } 764 765 if (nb_redist_regions == 2) { 766 uint32_t redist1_capacity = 767 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 768 769 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 770 MIN(smp_cpus - redist0_count, redist1_capacity)); 771 } 772 } else { 773 if (!kvm_irqchip_in_kernel()) { 774 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 775 vms->virt); 776 } 777 } 778 gicbusdev = SYS_BUS_DEVICE(vms->gic); 779 sysbus_realize_and_unref(gicbusdev, &error_fatal); 780 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 781 if (vms->gic_version != VIRT_GIC_VERSION_2) { 782 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 783 if (nb_redist_regions == 2) { 784 sysbus_mmio_map(gicbusdev, 2, 785 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 786 } 787 } else { 788 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 789 if (vms->virt) { 790 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 791 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 792 } 793 } 794 795 /* Wire the outputs from each CPU's generic timer and the GICv3 796 * maintenance interrupt signal to the appropriate GIC PPI inputs, 797 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 798 */ 799 for (i = 0; i < smp_cpus; i++) { 800 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 801 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 802 int irq; 803 /* Mapping from the output timer irq lines from the CPU to the 804 * GIC PPI inputs we use for the virt board. 805 */ 806 const int timer_irq[] = { 807 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 808 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 809 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 810 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 811 }; 812 813 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 814 qdev_connect_gpio_out(cpudev, irq, 815 qdev_get_gpio_in(vms->gic, 816 ppibase + timer_irq[irq])); 817 } 818 819 if (vms->gic_version != VIRT_GIC_VERSION_2) { 820 qemu_irq irq = qdev_get_gpio_in(vms->gic, 821 ppibase + ARCH_GIC_MAINT_IRQ); 822 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 823 0, irq); 824 } else if (vms->virt) { 825 qemu_irq irq = qdev_get_gpio_in(vms->gic, 826 ppibase + ARCH_GIC_MAINT_IRQ); 827 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 828 } 829 830 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 831 qdev_get_gpio_in(vms->gic, ppibase 832 + VIRTUAL_PMU_IRQ)); 833 834 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 835 sysbus_connect_irq(gicbusdev, i + smp_cpus, 836 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 837 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 838 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 839 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 840 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 841 } 842 843 fdt_add_gic_node(vms); 844 845 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 846 create_its(vms); 847 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 848 create_v2m(vms); 849 } 850 } 851 852 static void create_uart(const VirtMachineState *vms, int uart, 853 MemoryRegion *mem, Chardev *chr) 854 { 855 char *nodename; 856 hwaddr base = vms->memmap[uart].base; 857 hwaddr size = vms->memmap[uart].size; 858 int irq = vms->irqmap[uart]; 859 const char compat[] = "arm,pl011\0arm,primecell"; 860 const char clocknames[] = "uartclk\0apb_pclk"; 861 DeviceState *dev = qdev_new(TYPE_PL011); 862 SysBusDevice *s = SYS_BUS_DEVICE(dev); 863 MachineState *ms = MACHINE(vms); 864 865 qdev_prop_set_chr(dev, "chardev", chr); 866 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 867 memory_region_add_subregion(mem, base, 868 sysbus_mmio_get_region(s, 0)); 869 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 870 871 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 872 qemu_fdt_add_subnode(ms->fdt, nodename); 873 /* Note that we can't use setprop_string because of the embedded NUL */ 874 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 875 compat, sizeof(compat)); 876 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 877 2, base, 2, size); 878 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 879 GIC_FDT_IRQ_TYPE_SPI, irq, 880 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 881 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 882 vms->clock_phandle, vms->clock_phandle); 883 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 884 clocknames, sizeof(clocknames)); 885 886 if (uart == VIRT_UART) { 887 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 888 } else { 889 /* Mark as not usable by the normal world */ 890 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 891 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 892 893 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 894 nodename); 895 } 896 897 g_free(nodename); 898 } 899 900 static void create_rtc(const VirtMachineState *vms) 901 { 902 char *nodename; 903 hwaddr base = vms->memmap[VIRT_RTC].base; 904 hwaddr size = vms->memmap[VIRT_RTC].size; 905 int irq = vms->irqmap[VIRT_RTC]; 906 const char compat[] = "arm,pl031\0arm,primecell"; 907 MachineState *ms = MACHINE(vms); 908 909 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 910 911 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 912 qemu_fdt_add_subnode(ms->fdt, nodename); 913 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 914 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 915 2, base, 2, size); 916 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 917 GIC_FDT_IRQ_TYPE_SPI, irq, 918 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 919 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 920 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 921 g_free(nodename); 922 } 923 924 static DeviceState *gpio_key_dev; 925 static void virt_powerdown_req(Notifier *n, void *opaque) 926 { 927 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 928 929 if (s->acpi_dev) { 930 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 931 } else { 932 /* use gpio Pin 3 for power button event */ 933 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 934 } 935 } 936 937 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 938 uint32_t phandle) 939 { 940 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 941 qdev_get_gpio_in(pl061_dev, 3)); 942 943 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 944 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 945 946 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 947 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 948 "label", "GPIO Key Poweroff"); 949 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 950 KEY_POWER); 951 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 952 "gpios", phandle, 3, 0); 953 } 954 955 #define SECURE_GPIO_POWEROFF 0 956 #define SECURE_GPIO_RESET 1 957 958 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 959 uint32_t phandle) 960 { 961 DeviceState *gpio_pwr_dev; 962 963 /* gpio-pwr */ 964 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 965 966 /* connect secure pl061 to gpio-pwr */ 967 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 968 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 969 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 970 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 971 972 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 973 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 974 "gpio-poweroff"); 975 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 976 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 977 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 978 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 979 "okay"); 980 981 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 982 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 983 "gpio-restart"); 984 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 985 "gpios", phandle, SECURE_GPIO_RESET, 0); 986 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 987 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 988 "okay"); 989 } 990 991 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 992 MemoryRegion *mem) 993 { 994 char *nodename; 995 DeviceState *pl061_dev; 996 hwaddr base = vms->memmap[gpio].base; 997 hwaddr size = vms->memmap[gpio].size; 998 int irq = vms->irqmap[gpio]; 999 const char compat[] = "arm,pl061\0arm,primecell"; 1000 SysBusDevice *s; 1001 MachineState *ms = MACHINE(vms); 1002 1003 pl061_dev = qdev_new("pl061"); 1004 /* Pull lines down to 0 if not driven by the PL061 */ 1005 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1006 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1007 s = SYS_BUS_DEVICE(pl061_dev); 1008 sysbus_realize_and_unref(s, &error_fatal); 1009 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1010 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1011 1012 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1013 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1014 qemu_fdt_add_subnode(ms->fdt, nodename); 1015 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1016 2, base, 2, size); 1017 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1018 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1019 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1020 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1021 GIC_FDT_IRQ_TYPE_SPI, irq, 1022 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1023 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1024 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1025 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1026 1027 if (gpio != VIRT_GPIO) { 1028 /* Mark as not usable by the normal world */ 1029 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1030 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1031 } 1032 g_free(nodename); 1033 1034 /* Child gpio devices */ 1035 if (gpio == VIRT_GPIO) { 1036 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1037 } else { 1038 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1039 } 1040 } 1041 1042 static void create_virtio_devices(const VirtMachineState *vms) 1043 { 1044 int i; 1045 hwaddr size = vms->memmap[VIRT_MMIO].size; 1046 MachineState *ms = MACHINE(vms); 1047 1048 /* We create the transports in forwards order. Since qbus_realize() 1049 * prepends (not appends) new child buses, the incrementing loop below will 1050 * create a list of virtio-mmio buses with decreasing base addresses. 1051 * 1052 * When a -device option is processed from the command line, 1053 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1054 * order. The upshot is that -device options in increasing command line 1055 * order are mapped to virtio-mmio buses with decreasing base addresses. 1056 * 1057 * When this code was originally written, that arrangement ensured that the 1058 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1059 * the first -device on the command line. (The end-to-end order is a 1060 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1061 * guest kernel's name-to-address assignment strategy.) 1062 * 1063 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1064 * the message, if not necessarily the code, of commit 70161ff336. 1065 * Therefore the loop now establishes the inverse of the original intent. 1066 * 1067 * Unfortunately, we can't counteract the kernel change by reversing the 1068 * loop; it would break existing command lines. 1069 * 1070 * In any case, the kernel makes no guarantee about the stability of 1071 * enumeration order of virtio devices (as demonstrated by it changing 1072 * between kernel versions). For reliable and stable identification 1073 * of disks users must use UUIDs or similar mechanisms. 1074 */ 1075 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1076 int irq = vms->irqmap[VIRT_MMIO] + i; 1077 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1078 1079 sysbus_create_simple("virtio-mmio", base, 1080 qdev_get_gpio_in(vms->gic, irq)); 1081 } 1082 1083 /* We add dtb nodes in reverse order so that they appear in the finished 1084 * device tree lowest address first. 1085 * 1086 * Note that this mapping is independent of the loop above. The previous 1087 * loop influences virtio device to virtio transport assignment, whereas 1088 * this loop controls how virtio transports are laid out in the dtb. 1089 */ 1090 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1091 char *nodename; 1092 int irq = vms->irqmap[VIRT_MMIO] + i; 1093 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1094 1095 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1096 qemu_fdt_add_subnode(ms->fdt, nodename); 1097 qemu_fdt_setprop_string(ms->fdt, nodename, 1098 "compatible", "virtio,mmio"); 1099 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1100 2, base, 2, size); 1101 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1102 GIC_FDT_IRQ_TYPE_SPI, irq, 1103 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1104 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1105 g_free(nodename); 1106 } 1107 } 1108 1109 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1110 1111 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1112 const char *name, 1113 const char *alias_prop_name) 1114 { 1115 /* 1116 * Create a single flash device. We use the same parameters as 1117 * the flash devices on the Versatile Express board. 1118 */ 1119 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1120 1121 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1122 qdev_prop_set_uint8(dev, "width", 4); 1123 qdev_prop_set_uint8(dev, "device-width", 2); 1124 qdev_prop_set_bit(dev, "big-endian", false); 1125 qdev_prop_set_uint16(dev, "id0", 0x89); 1126 qdev_prop_set_uint16(dev, "id1", 0x18); 1127 qdev_prop_set_uint16(dev, "id2", 0x00); 1128 qdev_prop_set_uint16(dev, "id3", 0x00); 1129 qdev_prop_set_string(dev, "name", name); 1130 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1131 object_property_add_alias(OBJECT(vms), alias_prop_name, 1132 OBJECT(dev), "drive"); 1133 return PFLASH_CFI01(dev); 1134 } 1135 1136 static void virt_flash_create(VirtMachineState *vms) 1137 { 1138 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1139 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1140 } 1141 1142 static void virt_flash_map1(PFlashCFI01 *flash, 1143 hwaddr base, hwaddr size, 1144 MemoryRegion *sysmem) 1145 { 1146 DeviceState *dev = DEVICE(flash); 1147 1148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1152 1153 memory_region_add_subregion(sysmem, base, 1154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1155 0)); 1156 } 1157 1158 static void virt_flash_map(VirtMachineState *vms, 1159 MemoryRegion *sysmem, 1160 MemoryRegion *secure_sysmem) 1161 { 1162 /* 1163 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1164 * sysmem is the system memory space. secure_sysmem is the secure view 1165 * of the system, and the first flash device should be made visible only 1166 * there. The second flash device is visible to both secure and nonsecure. 1167 * If sysmem == secure_sysmem this means there is no separate Secure 1168 * address space and both flash devices are generally visible. 1169 */ 1170 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1171 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1172 1173 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1174 secure_sysmem); 1175 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1176 sysmem); 1177 } 1178 1179 static void virt_flash_fdt(VirtMachineState *vms, 1180 MemoryRegion *sysmem, 1181 MemoryRegion *secure_sysmem) 1182 { 1183 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1184 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1185 MachineState *ms = MACHINE(vms); 1186 char *nodename; 1187 1188 if (sysmem == secure_sysmem) { 1189 /* Report both flash devices as a single node in the DT */ 1190 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1191 qemu_fdt_add_subnode(ms->fdt, nodename); 1192 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1193 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1194 2, flashbase, 2, flashsize, 1195 2, flashbase + flashsize, 2, flashsize); 1196 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1197 g_free(nodename); 1198 } else { 1199 /* 1200 * Report the devices as separate nodes so we can mark one as 1201 * only visible to the secure world. 1202 */ 1203 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1204 qemu_fdt_add_subnode(ms->fdt, nodename); 1205 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1206 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1207 2, flashbase, 2, flashsize); 1208 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1209 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1210 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1211 g_free(nodename); 1212 1213 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1214 qemu_fdt_add_subnode(ms->fdt, nodename); 1215 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1216 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1217 2, flashbase + flashsize, 2, flashsize); 1218 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1219 g_free(nodename); 1220 } 1221 } 1222 1223 static bool virt_firmware_init(VirtMachineState *vms, 1224 MemoryRegion *sysmem, 1225 MemoryRegion *secure_sysmem) 1226 { 1227 int i; 1228 const char *bios_name; 1229 BlockBackend *pflash_blk0; 1230 1231 /* Map legacy -drive if=pflash to machine properties */ 1232 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1233 pflash_cfi01_legacy_drive(vms->flash[i], 1234 drive_get(IF_PFLASH, 0, i)); 1235 } 1236 1237 virt_flash_map(vms, sysmem, secure_sysmem); 1238 1239 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1240 1241 bios_name = MACHINE(vms)->firmware; 1242 if (bios_name) { 1243 char *fname; 1244 MemoryRegion *mr; 1245 int image_size; 1246 1247 if (pflash_blk0) { 1248 error_report("The contents of the first flash device may be " 1249 "specified with -bios or with -drive if=pflash... " 1250 "but you cannot use both options at once"); 1251 exit(1); 1252 } 1253 1254 /* Fall back to -bios */ 1255 1256 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1257 if (!fname) { 1258 error_report("Could not find ROM image '%s'", bios_name); 1259 exit(1); 1260 } 1261 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1262 image_size = load_image_mr(fname, mr); 1263 g_free(fname); 1264 if (image_size < 0) { 1265 error_report("Could not load ROM image '%s'", bios_name); 1266 exit(1); 1267 } 1268 } 1269 1270 return pflash_blk0 || bios_name; 1271 } 1272 1273 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1274 { 1275 MachineState *ms = MACHINE(vms); 1276 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1277 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1278 FWCfgState *fw_cfg; 1279 char *nodename; 1280 1281 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1282 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1283 1284 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1285 qemu_fdt_add_subnode(ms->fdt, nodename); 1286 qemu_fdt_setprop_string(ms->fdt, nodename, 1287 "compatible", "qemu,fw-cfg-mmio"); 1288 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1289 2, base, 2, size); 1290 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1291 g_free(nodename); 1292 return fw_cfg; 1293 } 1294 1295 static void create_pcie_irq_map(const MachineState *ms, 1296 uint32_t gic_phandle, 1297 int first_irq, const char *nodename) 1298 { 1299 int devfn, pin; 1300 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1301 uint32_t *irq_map = full_irq_map; 1302 1303 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1304 for (pin = 0; pin < 4; pin++) { 1305 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1306 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1307 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1308 int i; 1309 1310 uint32_t map[] = { 1311 devfn << 8, 0, 0, /* devfn */ 1312 pin + 1, /* PCI pin */ 1313 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1314 1315 /* Convert map to big endian */ 1316 for (i = 0; i < 10; i++) { 1317 irq_map[i] = cpu_to_be32(map[i]); 1318 } 1319 irq_map += 10; 1320 } 1321 } 1322 1323 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1324 full_irq_map, sizeof(full_irq_map)); 1325 1326 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1327 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1328 0, 0, 1329 0x7 /* PCI irq */); 1330 } 1331 1332 static void create_smmu(const VirtMachineState *vms, 1333 PCIBus *bus) 1334 { 1335 char *node; 1336 const char compat[] = "arm,smmu-v3"; 1337 int irq = vms->irqmap[VIRT_SMMU]; 1338 int i; 1339 hwaddr base = vms->memmap[VIRT_SMMU].base; 1340 hwaddr size = vms->memmap[VIRT_SMMU].size; 1341 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1342 DeviceState *dev; 1343 MachineState *ms = MACHINE(vms); 1344 1345 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1346 return; 1347 } 1348 1349 dev = qdev_new(TYPE_ARM_SMMUV3); 1350 1351 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1352 &error_abort); 1353 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1354 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1355 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1356 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1357 qdev_get_gpio_in(vms->gic, irq + i)); 1358 } 1359 1360 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1361 qemu_fdt_add_subnode(ms->fdt, node); 1362 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1363 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1364 1365 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1366 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1367 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1368 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1369 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1370 1371 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1372 sizeof(irq_names)); 1373 1374 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1375 1376 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1377 1378 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1379 g_free(node); 1380 } 1381 1382 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1383 { 1384 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1385 uint16_t bdf = vms->virtio_iommu_bdf; 1386 MachineState *ms = MACHINE(vms); 1387 char *node; 1388 1389 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1390 1391 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1392 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1393 qemu_fdt_add_subnode(ms->fdt, node); 1394 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1395 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1396 1, bdf << 8, 1, 0, 1, 0, 1397 1, 0, 1, 0); 1398 1399 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1400 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1401 g_free(node); 1402 1403 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1404 0x0, vms->iommu_phandle, 0x0, bdf, 1405 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1406 } 1407 1408 static void create_pcie(VirtMachineState *vms) 1409 { 1410 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1411 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1412 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1413 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1414 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1415 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1416 hwaddr base_ecam, size_ecam; 1417 hwaddr base = base_mmio; 1418 int nr_pcie_buses; 1419 int irq = vms->irqmap[VIRT_PCIE]; 1420 MemoryRegion *mmio_alias; 1421 MemoryRegion *mmio_reg; 1422 MemoryRegion *ecam_alias; 1423 MemoryRegion *ecam_reg; 1424 DeviceState *dev; 1425 char *nodename; 1426 int i, ecam_id; 1427 PCIHostState *pci; 1428 MachineState *ms = MACHINE(vms); 1429 MachineClass *mc = MACHINE_GET_CLASS(ms); 1430 1431 dev = qdev_new(TYPE_GPEX_HOST); 1432 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1433 1434 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1435 base_ecam = vms->memmap[ecam_id].base; 1436 size_ecam = vms->memmap[ecam_id].size; 1437 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1438 /* Map only the first size_ecam bytes of ECAM space */ 1439 ecam_alias = g_new0(MemoryRegion, 1); 1440 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1441 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1442 ecam_reg, 0, size_ecam); 1443 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1444 1445 /* Map the MMIO window into system address space so as to expose 1446 * the section of PCI MMIO space which starts at the same base address 1447 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1448 * the window). 1449 */ 1450 mmio_alias = g_new0(MemoryRegion, 1); 1451 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1452 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1453 mmio_reg, base_mmio, size_mmio); 1454 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1455 1456 if (vms->highmem_mmio) { 1457 /* Map high MMIO space */ 1458 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1459 1460 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1461 mmio_reg, base_mmio_high, size_mmio_high); 1462 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1463 high_mmio_alias); 1464 } 1465 1466 /* Map IO port space */ 1467 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1468 1469 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1470 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1471 qdev_get_gpio_in(vms->gic, irq + i)); 1472 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1473 } 1474 1475 pci = PCI_HOST_BRIDGE(dev); 1476 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1477 vms->bus = pci->bus; 1478 if (vms->bus) { 1479 for (i = 0; i < nb_nics; i++) { 1480 NICInfo *nd = &nd_table[i]; 1481 1482 if (!nd->model) { 1483 nd->model = g_strdup(mc->default_nic); 1484 } 1485 1486 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1487 } 1488 } 1489 1490 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1491 qemu_fdt_add_subnode(ms->fdt, nodename); 1492 qemu_fdt_setprop_string(ms->fdt, nodename, 1493 "compatible", "pci-host-ecam-generic"); 1494 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1495 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1496 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1497 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1498 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1499 nr_pcie_buses - 1); 1500 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1501 1502 if (vms->msi_phandle) { 1503 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1504 0, vms->msi_phandle, 0, 0x10000); 1505 } 1506 1507 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1508 2, base_ecam, 2, size_ecam); 1509 1510 if (vms->highmem_mmio) { 1511 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1512 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1513 2, base_pio, 2, size_pio, 1514 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1515 2, base_mmio, 2, size_mmio, 1516 1, FDT_PCI_RANGE_MMIO_64BIT, 1517 2, base_mmio_high, 1518 2, base_mmio_high, 2, size_mmio_high); 1519 } else { 1520 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1521 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1522 2, base_pio, 2, size_pio, 1523 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1524 2, base_mmio, 2, size_mmio); 1525 } 1526 1527 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1528 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1529 1530 if (vms->iommu) { 1531 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1532 1533 switch (vms->iommu) { 1534 case VIRT_IOMMU_SMMUV3: 1535 create_smmu(vms, vms->bus); 1536 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1537 0x0, vms->iommu_phandle, 0x0, 0x10000); 1538 break; 1539 default: 1540 g_assert_not_reached(); 1541 } 1542 } 1543 } 1544 1545 static void create_platform_bus(VirtMachineState *vms) 1546 { 1547 DeviceState *dev; 1548 SysBusDevice *s; 1549 int i; 1550 MemoryRegion *sysmem = get_system_memory(); 1551 1552 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1553 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1554 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1555 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1556 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1557 vms->platform_bus_dev = dev; 1558 1559 s = SYS_BUS_DEVICE(dev); 1560 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1561 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1562 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1563 } 1564 1565 memory_region_add_subregion(sysmem, 1566 vms->memmap[VIRT_PLATFORM_BUS].base, 1567 sysbus_mmio_get_region(s, 0)); 1568 } 1569 1570 static void create_tag_ram(MemoryRegion *tag_sysmem, 1571 hwaddr base, hwaddr size, 1572 const char *name) 1573 { 1574 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1575 1576 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1577 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1578 } 1579 1580 static void create_secure_ram(VirtMachineState *vms, 1581 MemoryRegion *secure_sysmem, 1582 MemoryRegion *secure_tag_sysmem) 1583 { 1584 MemoryRegion *secram = g_new(MemoryRegion, 1); 1585 char *nodename; 1586 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1587 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1588 MachineState *ms = MACHINE(vms); 1589 1590 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1591 &error_fatal); 1592 memory_region_add_subregion(secure_sysmem, base, secram); 1593 1594 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1595 qemu_fdt_add_subnode(ms->fdt, nodename); 1596 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1597 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1598 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1599 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1600 1601 if (secure_tag_sysmem) { 1602 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1603 } 1604 1605 g_free(nodename); 1606 } 1607 1608 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1609 { 1610 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1611 bootinfo); 1612 MachineState *ms = MACHINE(board); 1613 1614 1615 *fdt_size = board->fdt_size; 1616 return ms->fdt; 1617 } 1618 1619 static void virt_build_smbios(VirtMachineState *vms) 1620 { 1621 MachineClass *mc = MACHINE_GET_CLASS(vms); 1622 MachineState *ms = MACHINE(vms); 1623 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1624 uint8_t *smbios_tables, *smbios_anchor; 1625 size_t smbios_tables_len, smbios_anchor_len; 1626 struct smbios_phys_mem_area mem_array; 1627 const char *product = "QEMU Virtual Machine"; 1628 1629 if (kvm_enabled()) { 1630 product = "KVM Virtual Machine"; 1631 } 1632 1633 smbios_set_defaults("QEMU", product, 1634 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1635 true, SMBIOS_ENTRY_POINT_TYPE_64); 1636 1637 /* build the array of physical mem area from base_memmap */ 1638 mem_array.address = vms->memmap[VIRT_MEM].base; 1639 mem_array.length = ms->ram_size; 1640 1641 smbios_get_tables(ms, &mem_array, 1, 1642 &smbios_tables, &smbios_tables_len, 1643 &smbios_anchor, &smbios_anchor_len, 1644 &error_fatal); 1645 1646 if (smbios_anchor) { 1647 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1648 smbios_tables, smbios_tables_len); 1649 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1650 smbios_anchor, smbios_anchor_len); 1651 } 1652 } 1653 1654 static 1655 void virt_machine_done(Notifier *notifier, void *data) 1656 { 1657 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1658 machine_done); 1659 MachineState *ms = MACHINE(vms); 1660 ARMCPU *cpu = ARM_CPU(first_cpu); 1661 struct arm_boot_info *info = &vms->bootinfo; 1662 AddressSpace *as = arm_boot_address_space(cpu, info); 1663 1664 /* 1665 * If the user provided a dtb, we assume the dynamic sysbus nodes 1666 * already are integrated there. This corresponds to a use case where 1667 * the dynamic sysbus nodes are complex and their generation is not yet 1668 * supported. In that case the user can take charge of the guest dt 1669 * while qemu takes charge of the qom stuff. 1670 */ 1671 if (info->dtb_filename == NULL) { 1672 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1673 vms->memmap[VIRT_PLATFORM_BUS].base, 1674 vms->memmap[VIRT_PLATFORM_BUS].size, 1675 vms->irqmap[VIRT_PLATFORM_BUS]); 1676 } 1677 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1678 exit(1); 1679 } 1680 1681 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1682 1683 virt_acpi_setup(vms); 1684 virt_build_smbios(vms); 1685 } 1686 1687 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1688 { 1689 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1690 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1691 1692 if (!vmc->disallow_affinity_adjustment) { 1693 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1694 * GIC's target-list limitations. 32-bit KVM hosts currently 1695 * always create clusters of 4 CPUs, but that is expected to 1696 * change when they gain support for gicv3. When KVM is enabled 1697 * it will override the changes we make here, therefore our 1698 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1699 * and to improve SGI efficiency. 1700 */ 1701 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1702 clustersz = GIC_TARGETLIST_BITS; 1703 } else { 1704 clustersz = GICV3_TARGETLIST_BITS; 1705 } 1706 } 1707 return arm_cpu_mp_affinity(idx, clustersz); 1708 } 1709 1710 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1711 int index) 1712 { 1713 bool *enabled_array[] = { 1714 &vms->highmem_redists, 1715 &vms->highmem_ecam, 1716 &vms->highmem_mmio, 1717 }; 1718 1719 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1720 ARRAY_SIZE(enabled_array)); 1721 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1722 1723 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1724 } 1725 1726 static void virt_set_high_memmap(VirtMachineState *vms, 1727 hwaddr base, int pa_bits) 1728 { 1729 hwaddr region_base, region_size; 1730 bool *region_enabled, fits; 1731 int i; 1732 1733 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1734 region_enabled = virt_get_high_memmap_enabled(vms, i); 1735 region_base = ROUND_UP(base, extended_memmap[i].size); 1736 region_size = extended_memmap[i].size; 1737 1738 vms->memmap[i].base = region_base; 1739 vms->memmap[i].size = region_size; 1740 1741 /* 1742 * Check each device to see if it fits in the PA space, 1743 * moving highest_gpa as we go. For compatibility, move 1744 * highest_gpa for disabled fitting devices as well, if 1745 * the compact layout has been disabled. 1746 * 1747 * For each device that doesn't fit, disable it. 1748 */ 1749 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1750 *region_enabled &= fits; 1751 if (vms->highmem_compact && !*region_enabled) { 1752 continue; 1753 } 1754 1755 base = region_base + region_size; 1756 if (fits) { 1757 vms->highest_gpa = base - 1; 1758 } 1759 } 1760 } 1761 1762 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1763 { 1764 MachineState *ms = MACHINE(vms); 1765 hwaddr base, device_memory_base, device_memory_size, memtop; 1766 int i; 1767 1768 vms->memmap = extended_memmap; 1769 1770 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1771 vms->memmap[i] = base_memmap[i]; 1772 } 1773 1774 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1775 error_report("unsupported number of memory slots: %"PRIu64, 1776 ms->ram_slots); 1777 exit(EXIT_FAILURE); 1778 } 1779 1780 /* 1781 * !highmem is exactly the same as limiting the PA space to 32bit, 1782 * irrespective of the underlying capabilities of the HW. 1783 */ 1784 if (!vms->highmem) { 1785 pa_bits = 32; 1786 } 1787 1788 /* 1789 * We compute the base of the high IO region depending on the 1790 * amount of initial and device memory. The device memory start/size 1791 * is aligned on 1GiB. We never put the high IO region below 256GiB 1792 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1793 * The device region size assumes 1GiB page max alignment per slot. 1794 */ 1795 device_memory_base = 1796 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1797 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1798 1799 /* Base address of the high IO region */ 1800 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1801 if (memtop > BIT_ULL(pa_bits)) { 1802 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1803 pa_bits, memtop - BIT_ULL(pa_bits)); 1804 exit(EXIT_FAILURE); 1805 } 1806 if (base < device_memory_base) { 1807 error_report("maxmem/slots too huge"); 1808 exit(EXIT_FAILURE); 1809 } 1810 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1811 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1812 } 1813 1814 /* We know for sure that at least the memory fits in the PA space */ 1815 vms->highest_gpa = memtop - 1; 1816 1817 virt_set_high_memmap(vms, base, pa_bits); 1818 1819 if (device_memory_size > 0) { 1820 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1821 ms->device_memory->base = device_memory_base; 1822 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1823 "device-memory", device_memory_size); 1824 } 1825 } 1826 1827 static VirtGICType finalize_gic_version_do(const char *accel_name, 1828 VirtGICType gic_version, 1829 int gics_supported, 1830 unsigned int max_cpus) 1831 { 1832 /* Convert host/max/nosel to GIC version number */ 1833 switch (gic_version) { 1834 case VIRT_GIC_VERSION_HOST: 1835 if (!kvm_enabled()) { 1836 error_report("gic-version=host requires KVM"); 1837 exit(1); 1838 } 1839 1840 /* For KVM, gic-version=host means gic-version=max */ 1841 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1842 gics_supported, max_cpus); 1843 case VIRT_GIC_VERSION_MAX: 1844 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1845 gic_version = VIRT_GIC_VERSION_4; 1846 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1847 gic_version = VIRT_GIC_VERSION_3; 1848 } else { 1849 gic_version = VIRT_GIC_VERSION_2; 1850 } 1851 break; 1852 case VIRT_GIC_VERSION_NOSEL: 1853 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1854 max_cpus <= GIC_NCPU) { 1855 gic_version = VIRT_GIC_VERSION_2; 1856 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1857 /* 1858 * in case the host does not support v2 emulation or 1859 * the end-user requested more than 8 VCPUs we now default 1860 * to v3. In any case defaulting to v2 would be broken. 1861 */ 1862 gic_version = VIRT_GIC_VERSION_3; 1863 } else if (max_cpus > GIC_NCPU) { 1864 error_report("%s only supports GICv2 emulation but more than 8 " 1865 "vcpus are requested", accel_name); 1866 exit(1); 1867 } 1868 break; 1869 case VIRT_GIC_VERSION_2: 1870 case VIRT_GIC_VERSION_3: 1871 case VIRT_GIC_VERSION_4: 1872 break; 1873 } 1874 1875 /* Check chosen version is effectively supported */ 1876 switch (gic_version) { 1877 case VIRT_GIC_VERSION_2: 1878 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1879 error_report("%s does not support GICv2 emulation", accel_name); 1880 exit(1); 1881 } 1882 break; 1883 case VIRT_GIC_VERSION_3: 1884 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1885 error_report("%s does not support GICv3 emulation", accel_name); 1886 exit(1); 1887 } 1888 break; 1889 case VIRT_GIC_VERSION_4: 1890 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1891 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1892 accel_name); 1893 exit(1); 1894 } 1895 break; 1896 default: 1897 error_report("logic error in finalize_gic_version"); 1898 exit(1); 1899 break; 1900 } 1901 1902 return gic_version; 1903 } 1904 1905 /* 1906 * finalize_gic_version - Determines the final gic_version 1907 * according to the gic-version property 1908 * 1909 * Default GIC type is v2 1910 */ 1911 static void finalize_gic_version(VirtMachineState *vms) 1912 { 1913 const char *accel_name = current_accel_name(); 1914 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1915 int gics_supported = 0; 1916 1917 /* Determine which GIC versions the current environment supports */ 1918 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1919 int probe_bitmap = kvm_arm_vgic_probe(); 1920 1921 if (!probe_bitmap) { 1922 error_report("Unable to determine GIC version supported by host"); 1923 exit(1); 1924 } 1925 1926 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1927 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1928 } 1929 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1930 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1931 } 1932 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1933 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1934 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1935 accel_name = "KVM with kernel-irqchip=off"; 1936 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1937 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1938 if (module_object_class_by_name("arm-gicv3")) { 1939 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1940 if (vms->virt) { 1941 /* GICv4 only makes sense if CPU has EL2 */ 1942 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1943 } 1944 } 1945 } else { 1946 error_report("Unsupported accelerator, can not determine GIC support"); 1947 exit(1); 1948 } 1949 1950 /* 1951 * Then convert helpers like host/max to concrete GIC versions and ensure 1952 * the desired version is supported 1953 */ 1954 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1955 gics_supported, max_cpus); 1956 } 1957 1958 /* 1959 * virt_cpu_post_init() must be called after the CPUs have 1960 * been realized and the GIC has been created. 1961 */ 1962 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1963 { 1964 int max_cpus = MACHINE(vms)->smp.max_cpus; 1965 bool aarch64, pmu, steal_time; 1966 CPUState *cpu; 1967 1968 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1969 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1970 steal_time = object_property_get_bool(OBJECT(first_cpu), 1971 "kvm-steal-time", NULL); 1972 1973 if (kvm_enabled()) { 1974 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1975 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1976 1977 if (steal_time) { 1978 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1979 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1980 1981 /* The memory region size must be a multiple of host page size. */ 1982 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1983 1984 if (pvtime_size > pvtime_reg_size) { 1985 error_report("pvtime requires a %" HWADDR_PRId 1986 " byte memory region for %d CPUs," 1987 " but only %" HWADDR_PRId " has been reserved", 1988 pvtime_size, max_cpus, pvtime_reg_size); 1989 exit(1); 1990 } 1991 1992 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1993 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1994 } 1995 1996 CPU_FOREACH(cpu) { 1997 if (pmu) { 1998 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1999 if (kvm_irqchip_in_kernel()) { 2000 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 2001 } 2002 kvm_arm_pmu_init(cpu); 2003 } 2004 if (steal_time) { 2005 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 2006 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 2007 } 2008 } 2009 } else { 2010 if (aarch64 && vms->highmem) { 2011 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2012 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2013 2014 if (pamax < requested_pa_size) { 2015 error_report("VCPU supports less PA bits (%d) than " 2016 "requested by the memory map (%d)", 2017 pamax, requested_pa_size); 2018 exit(1); 2019 } 2020 } 2021 } 2022 } 2023 2024 static void machvirt_init(MachineState *machine) 2025 { 2026 VirtMachineState *vms = VIRT_MACHINE(machine); 2027 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2028 MachineClass *mc = MACHINE_GET_CLASS(machine); 2029 const CPUArchIdList *possible_cpus; 2030 MemoryRegion *sysmem = get_system_memory(); 2031 MemoryRegion *secure_sysmem = NULL; 2032 MemoryRegion *tag_sysmem = NULL; 2033 MemoryRegion *secure_tag_sysmem = NULL; 2034 int n, virt_max_cpus; 2035 bool firmware_loaded; 2036 bool aarch64 = true; 2037 bool has_ged = !vmc->no_ged; 2038 unsigned int smp_cpus = machine->smp.cpus; 2039 unsigned int max_cpus = machine->smp.max_cpus; 2040 2041 if (!cpu_type_valid(machine->cpu_type)) { 2042 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2043 exit(1); 2044 } 2045 2046 possible_cpus = mc->possible_cpu_arch_ids(machine); 2047 2048 /* 2049 * In accelerated mode, the memory map is computed earlier in kvm_type() 2050 * to create a VM with the right number of IPA bits. 2051 */ 2052 if (!vms->memmap) { 2053 Object *cpuobj; 2054 ARMCPU *armcpu; 2055 int pa_bits; 2056 2057 /* 2058 * Instantiate a temporary CPU object to find out about what 2059 * we are about to deal with. Once this is done, get rid of 2060 * the object. 2061 */ 2062 cpuobj = object_new(possible_cpus->cpus[0].type); 2063 armcpu = ARM_CPU(cpuobj); 2064 2065 pa_bits = arm_pamax(armcpu); 2066 2067 object_unref(cpuobj); 2068 2069 virt_set_memmap(vms, pa_bits); 2070 } 2071 2072 /* We can probe only here because during property set 2073 * KVM is not available yet 2074 */ 2075 finalize_gic_version(vms); 2076 2077 if (vms->secure) { 2078 /* 2079 * The Secure view of the world is the same as the NonSecure, 2080 * but with a few extra devices. Create it as a container region 2081 * containing the system memory at low priority; any secure-only 2082 * devices go in at higher priority and take precedence. 2083 */ 2084 secure_sysmem = g_new(MemoryRegion, 1); 2085 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2086 UINT64_MAX); 2087 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2088 } 2089 2090 firmware_loaded = virt_firmware_init(vms, sysmem, 2091 secure_sysmem ?: sysmem); 2092 2093 /* If we have an EL3 boot ROM then the assumption is that it will 2094 * implement PSCI itself, so disable QEMU's internal implementation 2095 * so it doesn't get in the way. Instead of starting secondary 2096 * CPUs in PSCI powerdown state we will start them all running and 2097 * let the boot ROM sort them out. 2098 * The usual case is that we do use QEMU's PSCI implementation; 2099 * if the guest has EL2 then we will use SMC as the conduit, 2100 * and otherwise we will use HVC (for backwards compatibility and 2101 * because if we're using KVM then we must use HVC). 2102 */ 2103 if (vms->secure && firmware_loaded) { 2104 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2105 } else if (vms->virt) { 2106 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2107 } else { 2108 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2109 } 2110 2111 /* 2112 * The maximum number of CPUs depends on the GIC version, or on how 2113 * many redistributors we can fit into the memory map (which in turn 2114 * depends on whether this is a GICv3 or v4). 2115 */ 2116 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2117 virt_max_cpus = GIC_NCPU; 2118 } else { 2119 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2120 if (vms->highmem_redists) { 2121 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2122 } 2123 } 2124 2125 if (max_cpus > virt_max_cpus) { 2126 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2127 "supported by machine 'mach-virt' (%d)", 2128 max_cpus, virt_max_cpus); 2129 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2130 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2131 } 2132 2133 exit(1); 2134 } 2135 2136 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2137 error_report("mach-virt: %s does not support providing " 2138 "Security extensions (TrustZone) to the guest CPU", 2139 current_accel_name()); 2140 exit(1); 2141 } 2142 2143 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2144 error_report("mach-virt: %s does not support providing " 2145 "Virtualization extensions to the guest CPU", 2146 current_accel_name()); 2147 exit(1); 2148 } 2149 2150 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2151 error_report("mach-virt: %s does not support providing " 2152 "MTE to the guest CPU", 2153 current_accel_name()); 2154 exit(1); 2155 } 2156 2157 create_fdt(vms); 2158 2159 assert(possible_cpus->len == max_cpus); 2160 for (n = 0; n < possible_cpus->len; n++) { 2161 Object *cpuobj; 2162 CPUState *cs; 2163 2164 if (n >= smp_cpus) { 2165 break; 2166 } 2167 2168 cpuobj = object_new(possible_cpus->cpus[n].type); 2169 object_property_set_int(cpuobj, "mp-affinity", 2170 possible_cpus->cpus[n].arch_id, NULL); 2171 2172 cs = CPU(cpuobj); 2173 cs->cpu_index = n; 2174 2175 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2176 &error_fatal); 2177 2178 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2179 2180 if (!vms->secure) { 2181 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2182 } 2183 2184 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2185 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2186 } 2187 2188 if (vmc->kvm_no_adjvtime && 2189 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2190 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2191 } 2192 2193 if (vmc->no_kvm_steal_time && 2194 object_property_find(cpuobj, "kvm-steal-time")) { 2195 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2196 } 2197 2198 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2199 object_property_set_bool(cpuobj, "pmu", false, NULL); 2200 } 2201 2202 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2203 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2204 } 2205 2206 if (object_property_find(cpuobj, "reset-cbar")) { 2207 object_property_set_int(cpuobj, "reset-cbar", 2208 vms->memmap[VIRT_CPUPERIPHS].base, 2209 &error_abort); 2210 } 2211 2212 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2213 &error_abort); 2214 if (vms->secure) { 2215 object_property_set_link(cpuobj, "secure-memory", 2216 OBJECT(secure_sysmem), &error_abort); 2217 } 2218 2219 if (vms->mte) { 2220 /* Create the memory region only once, but link to all cpus. */ 2221 if (!tag_sysmem) { 2222 /* 2223 * The property exists only if MemTag is supported. 2224 * If it is, we must allocate the ram to back that up. 2225 */ 2226 if (!object_property_find(cpuobj, "tag-memory")) { 2227 error_report("MTE requested, but not supported " 2228 "by the guest CPU"); 2229 exit(1); 2230 } 2231 2232 tag_sysmem = g_new(MemoryRegion, 1); 2233 memory_region_init(tag_sysmem, OBJECT(machine), 2234 "tag-memory", UINT64_MAX / 32); 2235 2236 if (vms->secure) { 2237 secure_tag_sysmem = g_new(MemoryRegion, 1); 2238 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2239 "secure-tag-memory", UINT64_MAX / 32); 2240 2241 /* As with ram, secure-tag takes precedence over tag. */ 2242 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2243 tag_sysmem, -1); 2244 } 2245 } 2246 2247 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2248 &error_abort); 2249 if (vms->secure) { 2250 object_property_set_link(cpuobj, "secure-tag-memory", 2251 OBJECT(secure_tag_sysmem), 2252 &error_abort); 2253 } 2254 } 2255 2256 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2257 object_unref(cpuobj); 2258 } 2259 fdt_add_timer_nodes(vms); 2260 fdt_add_cpu_nodes(vms); 2261 2262 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2263 machine->ram); 2264 if (machine->device_memory) { 2265 memory_region_add_subregion(sysmem, machine->device_memory->base, 2266 &machine->device_memory->mr); 2267 } 2268 2269 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2270 2271 create_gic(vms, sysmem); 2272 2273 virt_cpu_post_init(vms, sysmem); 2274 2275 fdt_add_pmu_nodes(vms); 2276 2277 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2278 2279 if (vms->secure) { 2280 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2281 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2282 } 2283 2284 if (tag_sysmem) { 2285 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2286 machine->ram_size, "mach-virt.tag"); 2287 } 2288 2289 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2290 2291 create_rtc(vms); 2292 2293 create_pcie(vms); 2294 2295 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2296 vms->acpi_dev = create_acpi_ged(vms); 2297 } else { 2298 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2299 } 2300 2301 if (vms->secure && !vmc->no_secure_gpio) { 2302 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2303 } 2304 2305 /* connect powerdown request */ 2306 vms->powerdown_notifier.notify = virt_powerdown_req; 2307 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2308 2309 /* Create mmio transports, so the user can create virtio backends 2310 * (which will be automatically plugged in to the transports). If 2311 * no backend is created the transport will just sit harmlessly idle. 2312 */ 2313 create_virtio_devices(vms); 2314 2315 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2316 rom_set_fw(vms->fw_cfg); 2317 2318 create_platform_bus(vms); 2319 2320 if (machine->nvdimms_state->is_enabled) { 2321 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2322 .space_id = AML_AS_SYSTEM_MEMORY, 2323 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2324 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2325 }; 2326 2327 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2328 arm_virt_nvdimm_acpi_dsmio, 2329 vms->fw_cfg, OBJECT(vms)); 2330 } 2331 2332 vms->bootinfo.ram_size = machine->ram_size; 2333 vms->bootinfo.board_id = -1; 2334 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2335 vms->bootinfo.get_dtb = machvirt_dtb; 2336 vms->bootinfo.skip_dtb_autoload = true; 2337 vms->bootinfo.firmware_loaded = firmware_loaded; 2338 vms->bootinfo.psci_conduit = vms->psci_conduit; 2339 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2340 2341 vms->machine_done.notify = virt_machine_done; 2342 qemu_add_machine_init_done_notifier(&vms->machine_done); 2343 } 2344 2345 static bool virt_get_secure(Object *obj, Error **errp) 2346 { 2347 VirtMachineState *vms = VIRT_MACHINE(obj); 2348 2349 return vms->secure; 2350 } 2351 2352 static void virt_set_secure(Object *obj, bool value, Error **errp) 2353 { 2354 VirtMachineState *vms = VIRT_MACHINE(obj); 2355 2356 vms->secure = value; 2357 } 2358 2359 static bool virt_get_virt(Object *obj, Error **errp) 2360 { 2361 VirtMachineState *vms = VIRT_MACHINE(obj); 2362 2363 return vms->virt; 2364 } 2365 2366 static void virt_set_virt(Object *obj, bool value, Error **errp) 2367 { 2368 VirtMachineState *vms = VIRT_MACHINE(obj); 2369 2370 vms->virt = value; 2371 } 2372 2373 static bool virt_get_highmem(Object *obj, Error **errp) 2374 { 2375 VirtMachineState *vms = VIRT_MACHINE(obj); 2376 2377 return vms->highmem; 2378 } 2379 2380 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2381 { 2382 VirtMachineState *vms = VIRT_MACHINE(obj); 2383 2384 vms->highmem = value; 2385 } 2386 2387 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2388 { 2389 VirtMachineState *vms = VIRT_MACHINE(obj); 2390 2391 return vms->highmem_compact; 2392 } 2393 2394 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2395 { 2396 VirtMachineState *vms = VIRT_MACHINE(obj); 2397 2398 vms->highmem_compact = value; 2399 } 2400 2401 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2402 { 2403 VirtMachineState *vms = VIRT_MACHINE(obj); 2404 2405 return vms->highmem_redists; 2406 } 2407 2408 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2409 { 2410 VirtMachineState *vms = VIRT_MACHINE(obj); 2411 2412 vms->highmem_redists = value; 2413 } 2414 2415 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2416 { 2417 VirtMachineState *vms = VIRT_MACHINE(obj); 2418 2419 return vms->highmem_ecam; 2420 } 2421 2422 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2423 { 2424 VirtMachineState *vms = VIRT_MACHINE(obj); 2425 2426 vms->highmem_ecam = value; 2427 } 2428 2429 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2430 { 2431 VirtMachineState *vms = VIRT_MACHINE(obj); 2432 2433 return vms->highmem_mmio; 2434 } 2435 2436 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2437 { 2438 VirtMachineState *vms = VIRT_MACHINE(obj); 2439 2440 vms->highmem_mmio = value; 2441 } 2442 2443 2444 static bool virt_get_its(Object *obj, Error **errp) 2445 { 2446 VirtMachineState *vms = VIRT_MACHINE(obj); 2447 2448 return vms->its; 2449 } 2450 2451 static void virt_set_its(Object *obj, bool value, Error **errp) 2452 { 2453 VirtMachineState *vms = VIRT_MACHINE(obj); 2454 2455 vms->its = value; 2456 } 2457 2458 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2459 { 2460 VirtMachineState *vms = VIRT_MACHINE(obj); 2461 2462 return vms->dtb_randomness; 2463 } 2464 2465 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2466 { 2467 VirtMachineState *vms = VIRT_MACHINE(obj); 2468 2469 vms->dtb_randomness = value; 2470 } 2471 2472 static char *virt_get_oem_id(Object *obj, Error **errp) 2473 { 2474 VirtMachineState *vms = VIRT_MACHINE(obj); 2475 2476 return g_strdup(vms->oem_id); 2477 } 2478 2479 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2480 { 2481 VirtMachineState *vms = VIRT_MACHINE(obj); 2482 size_t len = strlen(value); 2483 2484 if (len > 6) { 2485 error_setg(errp, 2486 "User specified oem-id value is bigger than 6 bytes in size"); 2487 return; 2488 } 2489 2490 strncpy(vms->oem_id, value, 6); 2491 } 2492 2493 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2494 { 2495 VirtMachineState *vms = VIRT_MACHINE(obj); 2496 2497 return g_strdup(vms->oem_table_id); 2498 } 2499 2500 static void virt_set_oem_table_id(Object *obj, const char *value, 2501 Error **errp) 2502 { 2503 VirtMachineState *vms = VIRT_MACHINE(obj); 2504 size_t len = strlen(value); 2505 2506 if (len > 8) { 2507 error_setg(errp, 2508 "User specified oem-table-id value is bigger than 8 bytes in size"); 2509 return; 2510 } 2511 strncpy(vms->oem_table_id, value, 8); 2512 } 2513 2514 2515 bool virt_is_acpi_enabled(VirtMachineState *vms) 2516 { 2517 if (vms->acpi == ON_OFF_AUTO_OFF) { 2518 return false; 2519 } 2520 return true; 2521 } 2522 2523 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2524 void *opaque, Error **errp) 2525 { 2526 VirtMachineState *vms = VIRT_MACHINE(obj); 2527 OnOffAuto acpi = vms->acpi; 2528 2529 visit_type_OnOffAuto(v, name, &acpi, errp); 2530 } 2531 2532 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2533 void *opaque, Error **errp) 2534 { 2535 VirtMachineState *vms = VIRT_MACHINE(obj); 2536 2537 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2538 } 2539 2540 static bool virt_get_ras(Object *obj, Error **errp) 2541 { 2542 VirtMachineState *vms = VIRT_MACHINE(obj); 2543 2544 return vms->ras; 2545 } 2546 2547 static void virt_set_ras(Object *obj, bool value, Error **errp) 2548 { 2549 VirtMachineState *vms = VIRT_MACHINE(obj); 2550 2551 vms->ras = value; 2552 } 2553 2554 static bool virt_get_mte(Object *obj, Error **errp) 2555 { 2556 VirtMachineState *vms = VIRT_MACHINE(obj); 2557 2558 return vms->mte; 2559 } 2560 2561 static void virt_set_mte(Object *obj, bool value, Error **errp) 2562 { 2563 VirtMachineState *vms = VIRT_MACHINE(obj); 2564 2565 vms->mte = value; 2566 } 2567 2568 static char *virt_get_gic_version(Object *obj, Error **errp) 2569 { 2570 VirtMachineState *vms = VIRT_MACHINE(obj); 2571 const char *val; 2572 2573 switch (vms->gic_version) { 2574 case VIRT_GIC_VERSION_4: 2575 val = "4"; 2576 break; 2577 case VIRT_GIC_VERSION_3: 2578 val = "3"; 2579 break; 2580 default: 2581 val = "2"; 2582 break; 2583 } 2584 return g_strdup(val); 2585 } 2586 2587 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2588 { 2589 VirtMachineState *vms = VIRT_MACHINE(obj); 2590 2591 if (!strcmp(value, "4")) { 2592 vms->gic_version = VIRT_GIC_VERSION_4; 2593 } else if (!strcmp(value, "3")) { 2594 vms->gic_version = VIRT_GIC_VERSION_3; 2595 } else if (!strcmp(value, "2")) { 2596 vms->gic_version = VIRT_GIC_VERSION_2; 2597 } else if (!strcmp(value, "host")) { 2598 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2599 } else if (!strcmp(value, "max")) { 2600 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2601 } else { 2602 error_setg(errp, "Invalid gic-version value"); 2603 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2604 } 2605 } 2606 2607 static char *virt_get_iommu(Object *obj, Error **errp) 2608 { 2609 VirtMachineState *vms = VIRT_MACHINE(obj); 2610 2611 switch (vms->iommu) { 2612 case VIRT_IOMMU_NONE: 2613 return g_strdup("none"); 2614 case VIRT_IOMMU_SMMUV3: 2615 return g_strdup("smmuv3"); 2616 default: 2617 g_assert_not_reached(); 2618 } 2619 } 2620 2621 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2622 { 2623 VirtMachineState *vms = VIRT_MACHINE(obj); 2624 2625 if (!strcmp(value, "smmuv3")) { 2626 vms->iommu = VIRT_IOMMU_SMMUV3; 2627 } else if (!strcmp(value, "none")) { 2628 vms->iommu = VIRT_IOMMU_NONE; 2629 } else { 2630 error_setg(errp, "Invalid iommu value"); 2631 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2632 } 2633 } 2634 2635 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2636 { 2637 VirtMachineState *vms = VIRT_MACHINE(obj); 2638 2639 return vms->default_bus_bypass_iommu; 2640 } 2641 2642 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2643 Error **errp) 2644 { 2645 VirtMachineState *vms = VIRT_MACHINE(obj); 2646 2647 vms->default_bus_bypass_iommu = value; 2648 } 2649 2650 static CpuInstanceProperties 2651 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2652 { 2653 MachineClass *mc = MACHINE_GET_CLASS(ms); 2654 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2655 2656 assert(cpu_index < possible_cpus->len); 2657 return possible_cpus->cpus[cpu_index].props; 2658 } 2659 2660 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2661 { 2662 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2663 2664 return socket_id % ms->numa_state->num_nodes; 2665 } 2666 2667 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2668 { 2669 int n; 2670 unsigned int max_cpus = ms->smp.max_cpus; 2671 VirtMachineState *vms = VIRT_MACHINE(ms); 2672 MachineClass *mc = MACHINE_GET_CLASS(vms); 2673 2674 if (ms->possible_cpus) { 2675 assert(ms->possible_cpus->len == max_cpus); 2676 return ms->possible_cpus; 2677 } 2678 2679 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2680 sizeof(CPUArchId) * max_cpus); 2681 ms->possible_cpus->len = max_cpus; 2682 for (n = 0; n < ms->possible_cpus->len; n++) { 2683 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2684 ms->possible_cpus->cpus[n].arch_id = 2685 virt_cpu_mp_affinity(vms, n); 2686 2687 assert(!mc->smp_props.dies_supported); 2688 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2689 ms->possible_cpus->cpus[n].props.socket_id = 2690 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2691 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2692 ms->possible_cpus->cpus[n].props.cluster_id = 2693 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2694 ms->possible_cpus->cpus[n].props.has_core_id = true; 2695 ms->possible_cpus->cpus[n].props.core_id = 2696 (n / ms->smp.threads) % ms->smp.cores; 2697 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2698 ms->possible_cpus->cpus[n].props.thread_id = 2699 n % ms->smp.threads; 2700 } 2701 return ms->possible_cpus; 2702 } 2703 2704 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2705 Error **errp) 2706 { 2707 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2708 const MachineState *ms = MACHINE(hotplug_dev); 2709 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2710 2711 if (!vms->acpi_dev) { 2712 error_setg(errp, 2713 "memory hotplug is not enabled: missing acpi-ged device"); 2714 return; 2715 } 2716 2717 if (vms->mte) { 2718 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2719 return; 2720 } 2721 2722 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2723 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2724 return; 2725 } 2726 2727 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2728 } 2729 2730 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2731 DeviceState *dev, Error **errp) 2732 { 2733 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2734 MachineState *ms = MACHINE(hotplug_dev); 2735 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2736 2737 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2738 2739 if (is_nvdimm) { 2740 nvdimm_plug(ms->nvdimms_state); 2741 } 2742 2743 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2744 dev, &error_abort); 2745 } 2746 2747 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2748 DeviceState *dev, Error **errp) 2749 { 2750 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2751 Error *local_err = NULL; 2752 2753 if (!hotplug_dev2 && dev->hotplugged) { 2754 /* 2755 * Without a bus hotplug handler, we cannot control the plug/unplug 2756 * order. We should never reach this point when hotplugging on ARM. 2757 * However, it's nice to add a safety net, similar to what we have 2758 * on x86. 2759 */ 2760 error_setg(errp, "hotplug of virtio based memory devices not supported" 2761 " on this bus."); 2762 return; 2763 } 2764 /* 2765 * First, see if we can plug this memory device at all. If that 2766 * succeeds, branch of to the actual hotplug handler. 2767 */ 2768 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2769 &local_err); 2770 if (!local_err && hotplug_dev2) { 2771 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2772 } 2773 error_propagate(errp, local_err); 2774 } 2775 2776 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2777 DeviceState *dev, Error **errp) 2778 { 2779 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2780 Error *local_err = NULL; 2781 2782 /* 2783 * Plug the memory device first and then branch off to the actual 2784 * hotplug handler. If that one fails, we can easily undo the memory 2785 * device bits. 2786 */ 2787 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2788 if (hotplug_dev2) { 2789 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2790 if (local_err) { 2791 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2792 } 2793 } 2794 error_propagate(errp, local_err); 2795 } 2796 2797 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2798 DeviceState *dev, Error **errp) 2799 { 2800 /* We don't support hot unplug of virtio based memory devices */ 2801 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2802 } 2803 2804 2805 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2806 DeviceState *dev, Error **errp) 2807 { 2808 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2809 2810 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2811 virt_memory_pre_plug(hotplug_dev, dev, errp); 2812 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2813 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2814 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2815 hwaddr db_start = 0, db_end = 0; 2816 char *resv_prop_str; 2817 2818 if (vms->iommu != VIRT_IOMMU_NONE) { 2819 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2820 return; 2821 } 2822 2823 switch (vms->msi_controller) { 2824 case VIRT_MSI_CTRL_NONE: 2825 return; 2826 case VIRT_MSI_CTRL_ITS: 2827 /* GITS_TRANSLATER page */ 2828 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2829 db_end = base_memmap[VIRT_GIC_ITS].base + 2830 base_memmap[VIRT_GIC_ITS].size - 1; 2831 break; 2832 case VIRT_MSI_CTRL_GICV2M: 2833 /* MSI_SETSPI_NS page */ 2834 db_start = base_memmap[VIRT_GIC_V2M].base; 2835 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2836 break; 2837 } 2838 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2839 db_start, db_end, 2840 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2841 2842 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2843 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2844 resv_prop_str, errp); 2845 g_free(resv_prop_str); 2846 } 2847 } 2848 2849 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2850 DeviceState *dev, Error **errp) 2851 { 2852 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2853 2854 if (vms->platform_bus_dev) { 2855 MachineClass *mc = MACHINE_GET_CLASS(vms); 2856 2857 if (device_is_dynamic_sysbus(mc, dev)) { 2858 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2859 SYS_BUS_DEVICE(dev)); 2860 } 2861 } 2862 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2863 virt_memory_plug(hotplug_dev, dev, errp); 2864 } 2865 2866 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2867 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2868 } 2869 2870 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2871 PCIDevice *pdev = PCI_DEVICE(dev); 2872 2873 vms->iommu = VIRT_IOMMU_VIRTIO; 2874 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2875 create_virtio_iommu_dt_bindings(vms); 2876 } 2877 } 2878 2879 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2880 DeviceState *dev, Error **errp) 2881 { 2882 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2883 2884 if (!vms->acpi_dev) { 2885 error_setg(errp, 2886 "memory hotplug is not enabled: missing acpi-ged device"); 2887 return; 2888 } 2889 2890 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2891 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2892 return; 2893 } 2894 2895 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2896 errp); 2897 } 2898 2899 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2900 DeviceState *dev, Error **errp) 2901 { 2902 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2903 Error *local_err = NULL; 2904 2905 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2906 if (local_err) { 2907 goto out; 2908 } 2909 2910 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2911 qdev_unrealize(dev); 2912 2913 out: 2914 error_propagate(errp, local_err); 2915 } 2916 2917 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2918 DeviceState *dev, Error **errp) 2919 { 2920 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2921 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2922 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2923 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2924 } else { 2925 error_setg(errp, "device unplug request for unsupported device" 2926 " type: %s", object_get_typename(OBJECT(dev))); 2927 } 2928 } 2929 2930 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2931 DeviceState *dev, Error **errp) 2932 { 2933 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2934 virt_dimm_unplug(hotplug_dev, dev, errp); 2935 } else { 2936 error_setg(errp, "virt: device unplug for unsupported device" 2937 " type: %s", object_get_typename(OBJECT(dev))); 2938 } 2939 } 2940 2941 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2942 DeviceState *dev) 2943 { 2944 MachineClass *mc = MACHINE_GET_CLASS(machine); 2945 2946 if (device_is_dynamic_sysbus(mc, dev) || 2947 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2948 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2949 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2950 return HOTPLUG_HANDLER(machine); 2951 } 2952 return NULL; 2953 } 2954 2955 /* 2956 * for arm64 kvm_type [7-0] encodes the requested number of bits 2957 * in the IPA address space 2958 */ 2959 static int virt_kvm_type(MachineState *ms, const char *type_str) 2960 { 2961 VirtMachineState *vms = VIRT_MACHINE(ms); 2962 int max_vm_pa_size, requested_pa_size; 2963 bool fixed_ipa; 2964 2965 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2966 2967 /* we freeze the memory map to compute the highest gpa */ 2968 virt_set_memmap(vms, max_vm_pa_size); 2969 2970 requested_pa_size = 64 - clz64(vms->highest_gpa); 2971 2972 /* 2973 * KVM requires the IPA size to be at least 32 bits. 2974 */ 2975 if (requested_pa_size < 32) { 2976 requested_pa_size = 32; 2977 } 2978 2979 if (requested_pa_size > max_vm_pa_size) { 2980 error_report("-m and ,maxmem option values " 2981 "require an IPA range (%d bits) larger than " 2982 "the one supported by the host (%d bits)", 2983 requested_pa_size, max_vm_pa_size); 2984 exit(1); 2985 } 2986 /* 2987 * We return the requested PA log size, unless KVM only supports 2988 * the implicit legacy 40b IPA setting, in which case the kvm_type 2989 * must be 0. 2990 */ 2991 return fixed_ipa ? 0 : requested_pa_size; 2992 } 2993 2994 static void virt_machine_class_init(ObjectClass *oc, void *data) 2995 { 2996 MachineClass *mc = MACHINE_CLASS(oc); 2997 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2998 2999 mc->init = machvirt_init; 3000 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 3001 * The value may be reduced later when we have more information about the 3002 * configuration of the particular instance. 3003 */ 3004 mc->max_cpus = 512; 3005 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3006 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3007 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3008 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3009 #ifdef CONFIG_TPM 3010 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3011 #endif 3012 mc->block_default_type = IF_VIRTIO; 3013 mc->no_cdrom = 1; 3014 mc->pci_allow_0_address = true; 3015 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3016 mc->minimum_page_bits = 12; 3017 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3018 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3019 #ifdef CONFIG_TCG 3020 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3021 #else 3022 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3023 #endif 3024 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3025 mc->kvm_type = virt_kvm_type; 3026 assert(!mc->get_hotplug_handler); 3027 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3028 hc->pre_plug = virt_machine_device_pre_plug_cb; 3029 hc->plug = virt_machine_device_plug_cb; 3030 hc->unplug_request = virt_machine_device_unplug_request_cb; 3031 hc->unplug = virt_machine_device_unplug_cb; 3032 mc->nvdimm_supported = true; 3033 mc->smp_props.clusters_supported = true; 3034 mc->auto_enable_numa_with_memhp = true; 3035 mc->auto_enable_numa_with_memdev = true; 3036 mc->default_ram_id = "mach-virt.ram"; 3037 mc->default_nic = "virtio-net-pci"; 3038 3039 object_class_property_add(oc, "acpi", "OnOffAuto", 3040 virt_get_acpi, virt_set_acpi, 3041 NULL, NULL); 3042 object_class_property_set_description(oc, "acpi", 3043 "Enable ACPI"); 3044 object_class_property_add_bool(oc, "secure", virt_get_secure, 3045 virt_set_secure); 3046 object_class_property_set_description(oc, "secure", 3047 "Set on/off to enable/disable the ARM " 3048 "Security Extensions (TrustZone)"); 3049 3050 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3051 virt_set_virt); 3052 object_class_property_set_description(oc, "virtualization", 3053 "Set on/off to enable/disable emulating a " 3054 "guest CPU which implements the ARM " 3055 "Virtualization Extensions"); 3056 3057 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3058 virt_set_highmem); 3059 object_class_property_set_description(oc, "highmem", 3060 "Set on/off to enable/disable using " 3061 "physical address space above 32 bits"); 3062 3063 object_class_property_add_bool(oc, "compact-highmem", 3064 virt_get_compact_highmem, 3065 virt_set_compact_highmem); 3066 object_class_property_set_description(oc, "compact-highmem", 3067 "Set on/off to enable/disable compact " 3068 "layout for high memory regions"); 3069 3070 object_class_property_add_bool(oc, "highmem-redists", 3071 virt_get_highmem_redists, 3072 virt_set_highmem_redists); 3073 object_class_property_set_description(oc, "highmem-redists", 3074 "Set on/off to enable/disable high " 3075 "memory region for GICv3 or GICv4 " 3076 "redistributor"); 3077 3078 object_class_property_add_bool(oc, "highmem-ecam", 3079 virt_get_highmem_ecam, 3080 virt_set_highmem_ecam); 3081 object_class_property_set_description(oc, "highmem-ecam", 3082 "Set on/off to enable/disable high " 3083 "memory region for PCI ECAM"); 3084 3085 object_class_property_add_bool(oc, "highmem-mmio", 3086 virt_get_highmem_mmio, 3087 virt_set_highmem_mmio); 3088 object_class_property_set_description(oc, "highmem-mmio", 3089 "Set on/off to enable/disable high " 3090 "memory region for PCI MMIO"); 3091 3092 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3093 virt_set_gic_version); 3094 object_class_property_set_description(oc, "gic-version", 3095 "Set GIC version. " 3096 "Valid values are 2, 3, 4, host and max"); 3097 3098 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3099 object_class_property_set_description(oc, "iommu", 3100 "Set the IOMMU type. " 3101 "Valid values are none and smmuv3"); 3102 3103 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3104 virt_get_default_bus_bypass_iommu, 3105 virt_set_default_bus_bypass_iommu); 3106 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3107 "Set on/off to enable/disable " 3108 "bypass_iommu for default root bus"); 3109 3110 object_class_property_add_bool(oc, "ras", virt_get_ras, 3111 virt_set_ras); 3112 object_class_property_set_description(oc, "ras", 3113 "Set on/off to enable/disable reporting host memory errors " 3114 "to a KVM guest using ACPI and guest external abort exceptions"); 3115 3116 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3117 object_class_property_set_description(oc, "mte", 3118 "Set on/off to enable/disable emulating a " 3119 "guest CPU which implements the ARM " 3120 "Memory Tagging Extension"); 3121 3122 object_class_property_add_bool(oc, "its", virt_get_its, 3123 virt_set_its); 3124 object_class_property_set_description(oc, "its", 3125 "Set on/off to enable/disable " 3126 "ITS instantiation"); 3127 3128 object_class_property_add_bool(oc, "dtb-randomness", 3129 virt_get_dtb_randomness, 3130 virt_set_dtb_randomness); 3131 object_class_property_set_description(oc, "dtb-randomness", 3132 "Set off to disable passing random or " 3133 "non-deterministic dtb nodes to guest"); 3134 3135 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3136 virt_get_dtb_randomness, 3137 virt_set_dtb_randomness); 3138 object_class_property_set_description(oc, "dtb-kaslr-seed", 3139 "Deprecated synonym of dtb-randomness"); 3140 3141 object_class_property_add_str(oc, "x-oem-id", 3142 virt_get_oem_id, 3143 virt_set_oem_id); 3144 object_class_property_set_description(oc, "x-oem-id", 3145 "Override the default value of field OEMID " 3146 "in ACPI table header." 3147 "The string may be up to 6 bytes in size"); 3148 3149 3150 object_class_property_add_str(oc, "x-oem-table-id", 3151 virt_get_oem_table_id, 3152 virt_set_oem_table_id); 3153 object_class_property_set_description(oc, "x-oem-table-id", 3154 "Override the default value of field OEM Table ID " 3155 "in ACPI table header." 3156 "The string may be up to 8 bytes in size"); 3157 3158 } 3159 3160 static void virt_instance_init(Object *obj) 3161 { 3162 VirtMachineState *vms = VIRT_MACHINE(obj); 3163 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3164 3165 /* EL3 is disabled by default on virt: this makes us consistent 3166 * between KVM and TCG for this board, and it also allows us to 3167 * boot UEFI blobs which assume no TrustZone support. 3168 */ 3169 vms->secure = false; 3170 3171 /* EL2 is also disabled by default, for similar reasons */ 3172 vms->virt = false; 3173 3174 /* High memory is enabled by default */ 3175 vms->highmem = true; 3176 vms->highmem_compact = !vmc->no_highmem_compact; 3177 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3178 3179 vms->highmem_ecam = !vmc->no_highmem_ecam; 3180 vms->highmem_mmio = true; 3181 vms->highmem_redists = true; 3182 3183 if (vmc->no_its) { 3184 vms->its = false; 3185 } else { 3186 /* Default allows ITS instantiation */ 3187 vms->its = true; 3188 3189 if (vmc->no_tcg_its) { 3190 vms->tcg_its = false; 3191 } else { 3192 vms->tcg_its = true; 3193 } 3194 } 3195 3196 /* Default disallows iommu instantiation */ 3197 vms->iommu = VIRT_IOMMU_NONE; 3198 3199 /* The default root bus is attached to iommu by default */ 3200 vms->default_bus_bypass_iommu = false; 3201 3202 /* Default disallows RAS instantiation */ 3203 vms->ras = false; 3204 3205 /* MTE is disabled by default. */ 3206 vms->mte = false; 3207 3208 /* Supply kaslr-seed and rng-seed by default */ 3209 vms->dtb_randomness = true; 3210 3211 vms->irqmap = a15irqmap; 3212 3213 virt_flash_create(vms); 3214 3215 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3216 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3217 } 3218 3219 static const TypeInfo virt_machine_info = { 3220 .name = TYPE_VIRT_MACHINE, 3221 .parent = TYPE_MACHINE, 3222 .abstract = true, 3223 .instance_size = sizeof(VirtMachineState), 3224 .class_size = sizeof(VirtMachineClass), 3225 .class_init = virt_machine_class_init, 3226 .instance_init = virt_instance_init, 3227 .interfaces = (InterfaceInfo[]) { 3228 { TYPE_HOTPLUG_HANDLER }, 3229 { } 3230 }, 3231 }; 3232 3233 static void machvirt_machine_init(void) 3234 { 3235 type_register_static(&virt_machine_info); 3236 } 3237 type_init(machvirt_machine_init); 3238 3239 static void virt_machine_8_1_options(MachineClass *mc) 3240 { 3241 } 3242 DEFINE_VIRT_MACHINE_AS_LATEST(8, 1) 3243 3244 static void virt_machine_8_0_options(MachineClass *mc) 3245 { 3246 virt_machine_8_1_options(mc); 3247 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3248 } 3249 DEFINE_VIRT_MACHINE(8, 0) 3250 3251 static void virt_machine_7_2_options(MachineClass *mc) 3252 { 3253 virt_machine_8_0_options(mc); 3254 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3255 } 3256 DEFINE_VIRT_MACHINE(7, 2) 3257 3258 static void virt_machine_7_1_options(MachineClass *mc) 3259 { 3260 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3261 3262 virt_machine_7_2_options(mc); 3263 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3264 /* Compact layout for high memory regions was introduced with 7.2 */ 3265 vmc->no_highmem_compact = true; 3266 } 3267 DEFINE_VIRT_MACHINE(7, 1) 3268 3269 static void virt_machine_7_0_options(MachineClass *mc) 3270 { 3271 virt_machine_7_1_options(mc); 3272 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3273 } 3274 DEFINE_VIRT_MACHINE(7, 0) 3275 3276 static void virt_machine_6_2_options(MachineClass *mc) 3277 { 3278 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3279 3280 virt_machine_7_0_options(mc); 3281 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3282 vmc->no_tcg_lpa2 = true; 3283 } 3284 DEFINE_VIRT_MACHINE(6, 2) 3285 3286 static void virt_machine_6_1_options(MachineClass *mc) 3287 { 3288 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3289 3290 virt_machine_6_2_options(mc); 3291 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3292 mc->smp_props.prefer_sockets = true; 3293 vmc->no_cpu_topology = true; 3294 3295 /* qemu ITS was introduced with 6.2 */ 3296 vmc->no_tcg_its = true; 3297 } 3298 DEFINE_VIRT_MACHINE(6, 1) 3299 3300 static void virt_machine_6_0_options(MachineClass *mc) 3301 { 3302 virt_machine_6_1_options(mc); 3303 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3304 } 3305 DEFINE_VIRT_MACHINE(6, 0) 3306 3307 static void virt_machine_5_2_options(MachineClass *mc) 3308 { 3309 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3310 3311 virt_machine_6_0_options(mc); 3312 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3313 vmc->no_secure_gpio = true; 3314 } 3315 DEFINE_VIRT_MACHINE(5, 2) 3316 3317 static void virt_machine_5_1_options(MachineClass *mc) 3318 { 3319 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3320 3321 virt_machine_5_2_options(mc); 3322 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3323 vmc->no_kvm_steal_time = true; 3324 } 3325 DEFINE_VIRT_MACHINE(5, 1) 3326 3327 static void virt_machine_5_0_options(MachineClass *mc) 3328 { 3329 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3330 3331 virt_machine_5_1_options(mc); 3332 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3333 mc->numa_mem_supported = true; 3334 vmc->acpi_expose_flash = true; 3335 mc->auto_enable_numa_with_memdev = false; 3336 } 3337 DEFINE_VIRT_MACHINE(5, 0) 3338 3339 static void virt_machine_4_2_options(MachineClass *mc) 3340 { 3341 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3342 3343 virt_machine_5_0_options(mc); 3344 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3345 vmc->kvm_no_adjvtime = true; 3346 } 3347 DEFINE_VIRT_MACHINE(4, 2) 3348 3349 static void virt_machine_4_1_options(MachineClass *mc) 3350 { 3351 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3352 3353 virt_machine_4_2_options(mc); 3354 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3355 vmc->no_ged = true; 3356 mc->auto_enable_numa_with_memhp = false; 3357 } 3358 DEFINE_VIRT_MACHINE(4, 1) 3359 3360 static void virt_machine_4_0_options(MachineClass *mc) 3361 { 3362 virt_machine_4_1_options(mc); 3363 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3364 } 3365 DEFINE_VIRT_MACHINE(4, 0) 3366 3367 static void virt_machine_3_1_options(MachineClass *mc) 3368 { 3369 virt_machine_4_0_options(mc); 3370 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3371 } 3372 DEFINE_VIRT_MACHINE(3, 1) 3373 3374 static void virt_machine_3_0_options(MachineClass *mc) 3375 { 3376 virt_machine_3_1_options(mc); 3377 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3378 } 3379 DEFINE_VIRT_MACHINE(3, 0) 3380 3381 static void virt_machine_2_12_options(MachineClass *mc) 3382 { 3383 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3384 3385 virt_machine_3_0_options(mc); 3386 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3387 vmc->no_highmem_ecam = true; 3388 mc->max_cpus = 255; 3389 } 3390 DEFINE_VIRT_MACHINE(2, 12) 3391 3392 static void virt_machine_2_11_options(MachineClass *mc) 3393 { 3394 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3395 3396 virt_machine_2_12_options(mc); 3397 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3398 vmc->smbios_old_sys_ver = true; 3399 } 3400 DEFINE_VIRT_MACHINE(2, 11) 3401 3402 static void virt_machine_2_10_options(MachineClass *mc) 3403 { 3404 virt_machine_2_11_options(mc); 3405 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3406 /* before 2.11 we never faulted accesses to bad addresses */ 3407 mc->ignore_memory_transaction_failures = true; 3408 } 3409 DEFINE_VIRT_MACHINE(2, 10) 3410 3411 static void virt_machine_2_9_options(MachineClass *mc) 3412 { 3413 virt_machine_2_10_options(mc); 3414 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3415 } 3416 DEFINE_VIRT_MACHINE(2, 9) 3417 3418 static void virt_machine_2_8_options(MachineClass *mc) 3419 { 3420 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3421 3422 virt_machine_2_9_options(mc); 3423 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3424 /* For 2.8 and earlier we falsely claimed in the DT that 3425 * our timers were edge-triggered, not level-triggered. 3426 */ 3427 vmc->claim_edge_triggered_timers = true; 3428 } 3429 DEFINE_VIRT_MACHINE(2, 8) 3430 3431 static void virt_machine_2_7_options(MachineClass *mc) 3432 { 3433 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3434 3435 virt_machine_2_8_options(mc); 3436 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3437 /* ITS was introduced with 2.8 */ 3438 vmc->no_its = true; 3439 /* Stick with 1K pages for migration compatibility */ 3440 mc->minimum_page_bits = 0; 3441 } 3442 DEFINE_VIRT_MACHINE(2, 7) 3443 3444 static void virt_machine_2_6_options(MachineClass *mc) 3445 { 3446 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3447 3448 virt_machine_2_7_options(mc); 3449 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3450 vmc->disallow_affinity_adjustment = true; 3451 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3452 vmc->no_pmu = true; 3453 } 3454 DEFINE_VIRT_MACHINE(2, 6) 3455