1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "qapi/qmp/qlist.h" 73 #include "standard-headers/linux/input.h" 74 #include "hw/arm/smmuv3.h" 75 #include "hw/acpi/acpi.h" 76 #include "target/arm/cpu-qom.h" 77 #include "target/arm/internals.h" 78 #include "target/arm/multiprocessing.h" 79 #include "target/arm/gtimer.h" 80 #include "hw/mem/pc-dimm.h" 81 #include "hw/mem/nvdimm.h" 82 #include "hw/acpi/generic_event_device.h" 83 #include "hw/virtio/virtio-md-pci.h" 84 #include "hw/virtio/virtio-iommu.h" 85 #include "hw/char/pl011.h" 86 #include "qemu/guest-random.h" 87 88 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 89 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 90 void *data) \ 91 { \ 92 MachineClass *mc = MACHINE_CLASS(oc); \ 93 virt_machine_##major##_##minor##_options(mc); \ 94 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 95 if (latest) { \ 96 mc->alias = "virt"; \ 97 } \ 98 } \ 99 static const TypeInfo machvirt_##major##_##minor##_info = { \ 100 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 101 .parent = TYPE_VIRT_MACHINE, \ 102 .class_init = virt_##major##_##minor##_class_init, \ 103 }; \ 104 static void machvirt_machine_##major##_##minor##_init(void) \ 105 { \ 106 type_register_static(&machvirt_##major##_##minor##_info); \ 107 } \ 108 type_init(machvirt_machine_##major##_##minor##_init); 109 110 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 111 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 112 #define DEFINE_VIRT_MACHINE(major, minor) \ 113 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 114 115 116 /* Number of external interrupt lines to configure the GIC with */ 117 #define NUM_IRQS 256 118 119 #define PLATFORM_BUS_NUM_IRQS 64 120 121 /* Legacy RAM limit in GB (< version 4.0) */ 122 #define LEGACY_RAMLIMIT_GB 255 123 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 124 125 /* Addresses and sizes of our components. 126 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 127 * 128MB..256MB is used for miscellaneous device I/O. 128 * 256MB..1GB is reserved for possible future PCI support (ie where the 129 * PCI memory window will go if we add a PCI host controller). 130 * 1GB and up is RAM (which may happily spill over into the 131 * high memory region beyond 4GB). 132 * This represents a compromise between how much RAM can be given to 133 * a 32 bit VM and leaving space for expansion and in particular for PCI. 134 * Note that devices should generally be placed at multiples of 0x10000, 135 * to accommodate guests using 64K pages. 136 */ 137 static const MemMapEntry base_memmap[] = { 138 /* Space up to 0x8000000 is reserved for a boot ROM */ 139 [VIRT_FLASH] = { 0, 0x08000000 }, 140 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 141 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 142 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 143 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 144 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 145 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 146 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 147 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 148 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 149 /* This redistributor space allows up to 2*64kB*123 CPUs */ 150 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 151 [VIRT_UART] = { 0x09000000, 0x00001000 }, 152 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 153 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 154 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 155 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 156 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 157 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 158 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 159 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 160 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 161 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 162 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 163 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 164 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 165 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 166 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 167 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 168 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 169 /* Actual RAM size depends on initial RAM and device memory settings */ 170 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 171 }; 172 173 /* 174 * Highmem IO Regions: This memory map is floating, located after the RAM. 175 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 176 * top of the RAM, so that its base get the same alignment as the size, 177 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 178 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 179 * Note the extended_memmap is sized so that it eventually also includes the 180 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 181 * index of base_memmap). 182 * 183 * The memory map for these Highmem IO Regions can be in legacy or compact 184 * layout, depending on 'compact-highmem' property. With legacy layout, the 185 * PA space for one specific region is always reserved, even if the region 186 * has been disabled or doesn't fit into the PA space. However, the PA space 187 * for the region won't be reserved in these circumstances with compact layout. 188 */ 189 static MemMapEntry extended_memmap[] = { 190 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 191 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 192 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 193 /* Second PCIe window */ 194 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 195 }; 196 197 static const int a15irqmap[] = { 198 [VIRT_UART] = 1, 199 [VIRT_RTC] = 2, 200 [VIRT_PCIE] = 3, /* ... to 6 */ 201 [VIRT_GPIO] = 7, 202 [VIRT_SECURE_UART] = 8, 203 [VIRT_ACPI_GED] = 9, 204 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 205 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 206 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 207 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 208 }; 209 210 static void create_randomness(MachineState *ms, const char *node) 211 { 212 struct { 213 uint64_t kaslr; 214 uint8_t rng[32]; 215 } seed; 216 217 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 218 return; 219 } 220 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 221 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 222 } 223 224 static void create_fdt(VirtMachineState *vms) 225 { 226 MachineState *ms = MACHINE(vms); 227 int nb_numa_nodes = ms->numa_state->num_nodes; 228 void *fdt = create_device_tree(&vms->fdt_size); 229 230 if (!fdt) { 231 error_report("create_device_tree() failed"); 232 exit(1); 233 } 234 235 ms->fdt = fdt; 236 237 /* Header */ 238 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 239 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 240 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 241 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 242 243 /* /chosen must exist for load_dtb to fill in necessary properties later */ 244 qemu_fdt_add_subnode(fdt, "/chosen"); 245 if (vms->dtb_randomness) { 246 create_randomness(ms, "/chosen"); 247 } 248 249 if (vms->secure) { 250 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 251 if (vms->dtb_randomness) { 252 create_randomness(ms, "/secure-chosen"); 253 } 254 } 255 256 /* Clock node, for the benefit of the UART. The kernel device tree 257 * binding documentation claims the PL011 node clock properties are 258 * optional but in practice if you omit them the kernel refuses to 259 * probe for the device. 260 */ 261 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 262 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 263 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 266 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 267 "clk24mhz"); 268 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 269 270 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 271 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 272 uint32_t *matrix = g_malloc0(size); 273 int idx, i, j; 274 275 for (i = 0; i < nb_numa_nodes; i++) { 276 for (j = 0; j < nb_numa_nodes; j++) { 277 idx = (i * nb_numa_nodes + j) * 3; 278 matrix[idx + 0] = cpu_to_be32(i); 279 matrix[idx + 1] = cpu_to_be32(j); 280 matrix[idx + 2] = 281 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 282 } 283 } 284 285 qemu_fdt_add_subnode(fdt, "/distance-map"); 286 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 287 "numa-distance-map-v1"); 288 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 289 matrix, size); 290 g_free(matrix); 291 } 292 } 293 294 static void fdt_add_timer_nodes(const VirtMachineState *vms) 295 { 296 /* On real hardware these interrupts are level-triggered. 297 * On KVM they were edge-triggered before host kernel version 4.4, 298 * and level-triggered afterwards. 299 * On emulated QEMU they are level-triggered. 300 * 301 * Getting the DTB info about them wrong is awkward for some 302 * guest kernels: 303 * pre-4.8 ignore the DT and leave the interrupt configured 304 * with whatever the GIC reset value (or the bootloader) left it at 305 * 4.8 before rc6 honour the incorrect data by programming it back 306 * into the GIC, causing problems 307 * 4.8rc6 and later ignore the DT and always write "level triggered" 308 * into the GIC 309 * 310 * For backwards-compatibility, virt-2.8 and earlier will continue 311 * to say these are edge-triggered, but later machines will report 312 * the correct information. 313 */ 314 ARMCPU *armcpu; 315 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 316 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 317 MachineState *ms = MACHINE(vms); 318 319 if (vmc->claim_edge_triggered_timers) { 320 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 321 } 322 323 if (vms->gic_version == VIRT_GIC_VERSION_2) { 324 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 325 GIC_FDT_IRQ_PPI_CPU_WIDTH, 326 (1 << MACHINE(vms)->smp.cpus) - 1); 327 } 328 329 qemu_fdt_add_subnode(ms->fdt, "/timer"); 330 331 armcpu = ARM_CPU(qemu_get_cpu(0)); 332 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 333 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 334 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 335 compat, sizeof(compat)); 336 } else { 337 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 338 "arm,armv7-timer"); 339 } 340 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 341 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 342 GIC_FDT_IRQ_TYPE_PPI, 343 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 344 GIC_FDT_IRQ_TYPE_PPI, 345 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 346 GIC_FDT_IRQ_TYPE_PPI, 347 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 348 GIC_FDT_IRQ_TYPE_PPI, 349 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 350 } 351 352 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 353 { 354 int cpu; 355 int addr_cells = 1; 356 const MachineState *ms = MACHINE(vms); 357 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 358 int smp_cpus = ms->smp.cpus; 359 360 /* 361 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 362 * On ARM v8 64-bit systems value should be set to 2, 363 * that corresponds to the MPIDR_EL1 register size. 364 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 365 * in the system, #address-cells can be set to 1, since 366 * MPIDR_EL1[63:32] bits are not used for CPUs 367 * identification. 368 * 369 * Here we actually don't know whether our system is 32- or 64-bit one. 370 * The simplest way to go is to examine affinity IDs of all our CPUs. If 371 * at least one of them has Aff3 populated, we set #address-cells to 2. 372 */ 373 for (cpu = 0; cpu < smp_cpus; cpu++) { 374 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 375 376 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 377 addr_cells = 2; 378 break; 379 } 380 } 381 382 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 383 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 384 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 385 386 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 387 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 388 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 389 CPUState *cs = CPU(armcpu); 390 391 qemu_fdt_add_subnode(ms->fdt, nodename); 392 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 393 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 394 armcpu->dtb_compatible); 395 396 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 397 qemu_fdt_setprop_string(ms->fdt, nodename, 398 "enable-method", "psci"); 399 } 400 401 if (addr_cells == 2) { 402 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 403 arm_cpu_mp_affinity(armcpu)); 404 } else { 405 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 406 arm_cpu_mp_affinity(armcpu)); 407 } 408 409 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 410 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 411 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 412 } 413 414 if (!vmc->no_cpu_topology) { 415 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 416 qemu_fdt_alloc_phandle(ms->fdt)); 417 } 418 419 g_free(nodename); 420 } 421 422 if (!vmc->no_cpu_topology) { 423 /* 424 * Add vCPU topology description through fdt node cpu-map. 425 * 426 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 427 * In a SMP system, the hierarchy of CPUs can be defined through 428 * four entities that are used to describe the layout of CPUs in 429 * the system: socket/cluster/core/thread. 430 * 431 * A socket node represents the boundary of system physical package 432 * and its child nodes must be one or more cluster nodes. A system 433 * can contain several layers of clustering within a single physical 434 * package and cluster nodes can be contained in parent cluster nodes. 435 * 436 * Note: currently we only support one layer of clustering within 437 * each physical package. 438 */ 439 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 440 441 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 442 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 443 char *map_path; 444 445 if (ms->smp.threads > 1) { 446 map_path = g_strdup_printf( 447 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 448 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 449 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 450 (cpu / ms->smp.threads) % ms->smp.cores, 451 cpu % ms->smp.threads); 452 } else { 453 map_path = g_strdup_printf( 454 "/cpus/cpu-map/socket%d/cluster%d/core%d", 455 cpu / (ms->smp.clusters * ms->smp.cores), 456 (cpu / ms->smp.cores) % ms->smp.clusters, 457 cpu % ms->smp.cores); 458 } 459 qemu_fdt_add_path(ms->fdt, map_path); 460 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 461 462 g_free(map_path); 463 g_free(cpu_path); 464 } 465 } 466 } 467 468 static void fdt_add_its_gic_node(VirtMachineState *vms) 469 { 470 char *nodename; 471 MachineState *ms = MACHINE(vms); 472 473 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 474 nodename = g_strdup_printf("/intc/its@%" PRIx64, 475 vms->memmap[VIRT_GIC_ITS].base); 476 qemu_fdt_add_subnode(ms->fdt, nodename); 477 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 478 "arm,gic-v3-its"); 479 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 480 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 481 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 482 2, vms->memmap[VIRT_GIC_ITS].base, 483 2, vms->memmap[VIRT_GIC_ITS].size); 484 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 485 g_free(nodename); 486 } 487 488 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 489 { 490 MachineState *ms = MACHINE(vms); 491 char *nodename; 492 493 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 494 vms->memmap[VIRT_GIC_V2M].base); 495 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 496 qemu_fdt_add_subnode(ms->fdt, nodename); 497 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 498 "arm,gic-v2m-frame"); 499 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 500 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 501 2, vms->memmap[VIRT_GIC_V2M].base, 502 2, vms->memmap[VIRT_GIC_V2M].size); 503 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 504 g_free(nodename); 505 } 506 507 static void fdt_add_gic_node(VirtMachineState *vms) 508 { 509 MachineState *ms = MACHINE(vms); 510 char *nodename; 511 512 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 513 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 514 515 nodename = g_strdup_printf("/intc@%" PRIx64, 516 vms->memmap[VIRT_GIC_DIST].base); 517 qemu_fdt_add_subnode(ms->fdt, nodename); 518 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 519 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 520 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 521 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 522 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 523 if (vms->gic_version != VIRT_GIC_VERSION_2) { 524 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 525 526 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 527 "arm,gic-v3"); 528 529 qemu_fdt_setprop_cell(ms->fdt, nodename, 530 "#redistributor-regions", nb_redist_regions); 531 532 if (nb_redist_regions == 1) { 533 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 534 2, vms->memmap[VIRT_GIC_DIST].base, 535 2, vms->memmap[VIRT_GIC_DIST].size, 536 2, vms->memmap[VIRT_GIC_REDIST].base, 537 2, vms->memmap[VIRT_GIC_REDIST].size); 538 } else { 539 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 540 2, vms->memmap[VIRT_GIC_DIST].base, 541 2, vms->memmap[VIRT_GIC_DIST].size, 542 2, vms->memmap[VIRT_GIC_REDIST].base, 543 2, vms->memmap[VIRT_GIC_REDIST].size, 544 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 545 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 546 } 547 548 if (vms->virt) { 549 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 550 GIC_FDT_IRQ_TYPE_PPI, 551 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 552 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 553 } 554 } else { 555 /* 'cortex-a15-gic' means 'GIC v2' */ 556 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 557 "arm,cortex-a15-gic"); 558 if (!vms->virt) { 559 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 560 2, vms->memmap[VIRT_GIC_DIST].base, 561 2, vms->memmap[VIRT_GIC_DIST].size, 562 2, vms->memmap[VIRT_GIC_CPU].base, 563 2, vms->memmap[VIRT_GIC_CPU].size); 564 } else { 565 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 566 2, vms->memmap[VIRT_GIC_DIST].base, 567 2, vms->memmap[VIRT_GIC_DIST].size, 568 2, vms->memmap[VIRT_GIC_CPU].base, 569 2, vms->memmap[VIRT_GIC_CPU].size, 570 2, vms->memmap[VIRT_GIC_HYP].base, 571 2, vms->memmap[VIRT_GIC_HYP].size, 572 2, vms->memmap[VIRT_GIC_VCPU].base, 573 2, vms->memmap[VIRT_GIC_VCPU].size); 574 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 575 GIC_FDT_IRQ_TYPE_PPI, 576 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 577 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 578 } 579 } 580 581 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 582 g_free(nodename); 583 } 584 585 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 586 { 587 ARMCPU *armcpu = ARM_CPU(first_cpu); 588 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 589 MachineState *ms = MACHINE(vms); 590 591 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 592 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 593 return; 594 } 595 596 if (vms->gic_version == VIRT_GIC_VERSION_2) { 597 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 598 GIC_FDT_IRQ_PPI_CPU_WIDTH, 599 (1 << MACHINE(vms)->smp.cpus) - 1); 600 } 601 602 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 603 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 604 const char compat[] = "arm,armv8-pmuv3"; 605 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 606 compat, sizeof(compat)); 607 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 608 GIC_FDT_IRQ_TYPE_PPI, 609 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 610 } 611 } 612 613 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 614 { 615 DeviceState *dev; 616 MachineState *ms = MACHINE(vms); 617 int irq = vms->irqmap[VIRT_ACPI_GED]; 618 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 619 620 if (ms->ram_slots) { 621 event |= ACPI_GED_MEM_HOTPLUG_EVT; 622 } 623 624 if (ms->nvdimms_state->is_enabled) { 625 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 626 } 627 628 dev = qdev_new(TYPE_ACPI_GED); 629 qdev_prop_set_uint32(dev, "ged-event", event); 630 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 631 632 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 633 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 634 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 635 636 return dev; 637 } 638 639 static void create_its(VirtMachineState *vms) 640 { 641 const char *itsclass = its_class_name(); 642 DeviceState *dev; 643 644 if (!strcmp(itsclass, "arm-gicv3-its")) { 645 if (!vms->tcg_its) { 646 itsclass = NULL; 647 } 648 } 649 650 if (!itsclass) { 651 /* Do nothing if not supported */ 652 return; 653 } 654 655 dev = qdev_new(itsclass); 656 657 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 658 &error_abort); 659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 660 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 661 662 fdt_add_its_gic_node(vms); 663 vms->msi_controller = VIRT_MSI_CTRL_ITS; 664 } 665 666 static void create_v2m(VirtMachineState *vms) 667 { 668 int i; 669 int irq = vms->irqmap[VIRT_GIC_V2M]; 670 DeviceState *dev; 671 672 dev = qdev_new("arm-gicv2m"); 673 qdev_prop_set_uint32(dev, "base-spi", irq); 674 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 675 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 676 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 677 678 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 679 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 680 qdev_get_gpio_in(vms->gic, irq + i)); 681 } 682 683 fdt_add_v2m_gic_node(vms); 684 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 685 } 686 687 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 688 { 689 MachineState *ms = MACHINE(vms); 690 /* We create a standalone GIC */ 691 SysBusDevice *gicbusdev; 692 const char *gictype; 693 int i; 694 unsigned int smp_cpus = ms->smp.cpus; 695 uint32_t nb_redist_regions = 0; 696 int revision; 697 698 if (vms->gic_version == VIRT_GIC_VERSION_2) { 699 gictype = gic_class_name(); 700 } else { 701 gictype = gicv3_class_name(); 702 } 703 704 switch (vms->gic_version) { 705 case VIRT_GIC_VERSION_2: 706 revision = 2; 707 break; 708 case VIRT_GIC_VERSION_3: 709 revision = 3; 710 break; 711 case VIRT_GIC_VERSION_4: 712 revision = 4; 713 break; 714 default: 715 g_assert_not_reached(); 716 } 717 vms->gic = qdev_new(gictype); 718 qdev_prop_set_uint32(vms->gic, "revision", revision); 719 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 720 /* Note that the num-irq property counts both internal and external 721 * interrupts; there are always 32 of the former (mandated by GIC spec). 722 */ 723 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 724 if (!kvm_irqchip_in_kernel()) { 725 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 726 } 727 728 if (vms->gic_version != VIRT_GIC_VERSION_2) { 729 QList *redist_region_count; 730 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 731 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 732 733 nb_redist_regions = virt_gicv3_redist_region_count(vms); 734 735 redist_region_count = qlist_new(); 736 qlist_append_int(redist_region_count, redist0_count); 737 if (nb_redist_regions == 2) { 738 uint32_t redist1_capacity = 739 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 740 741 qlist_append_int(redist_region_count, 742 MIN(smp_cpus - redist0_count, redist1_capacity)); 743 } 744 qdev_prop_set_array(vms->gic, "redist-region-count", 745 redist_region_count); 746 747 if (!kvm_irqchip_in_kernel()) { 748 if (vms->tcg_its) { 749 object_property_set_link(OBJECT(vms->gic), "sysmem", 750 OBJECT(mem), &error_fatal); 751 qdev_prop_set_bit(vms->gic, "has-lpi", true); 752 } 753 } 754 } else { 755 if (!kvm_irqchip_in_kernel()) { 756 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 757 vms->virt); 758 } 759 } 760 gicbusdev = SYS_BUS_DEVICE(vms->gic); 761 sysbus_realize_and_unref(gicbusdev, &error_fatal); 762 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 763 if (vms->gic_version != VIRT_GIC_VERSION_2) { 764 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 765 if (nb_redist_regions == 2) { 766 sysbus_mmio_map(gicbusdev, 2, 767 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 768 } 769 } else { 770 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 771 if (vms->virt) { 772 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 773 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 774 } 775 } 776 777 /* Wire the outputs from each CPU's generic timer and the GICv3 778 * maintenance interrupt signal to the appropriate GIC PPI inputs, 779 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 780 */ 781 for (i = 0; i < smp_cpus; i++) { 782 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 783 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 784 /* Mapping from the output timer irq lines from the CPU to the 785 * GIC PPI inputs we use for the virt board. 786 */ 787 const int timer_irq[] = { 788 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 789 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 790 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 791 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 792 }; 793 794 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 795 qdev_connect_gpio_out(cpudev, irq, 796 qdev_get_gpio_in(vms->gic, 797 intidbase + timer_irq[irq])); 798 } 799 800 if (vms->gic_version != VIRT_GIC_VERSION_2) { 801 qemu_irq irq = qdev_get_gpio_in(vms->gic, 802 intidbase + ARCH_GIC_MAINT_IRQ); 803 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 804 0, irq); 805 } else if (vms->virt) { 806 qemu_irq irq = qdev_get_gpio_in(vms->gic, 807 intidbase + ARCH_GIC_MAINT_IRQ); 808 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 809 } 810 811 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 812 qdev_get_gpio_in(vms->gic, intidbase 813 + VIRTUAL_PMU_IRQ)); 814 815 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 816 sysbus_connect_irq(gicbusdev, i + smp_cpus, 817 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 818 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 819 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 820 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 821 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 822 } 823 824 fdt_add_gic_node(vms); 825 826 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 827 create_its(vms); 828 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 829 create_v2m(vms); 830 } 831 } 832 833 static void create_uart(const VirtMachineState *vms, int uart, 834 MemoryRegion *mem, Chardev *chr) 835 { 836 char *nodename; 837 hwaddr base = vms->memmap[uart].base; 838 hwaddr size = vms->memmap[uart].size; 839 int irq = vms->irqmap[uart]; 840 const char compat[] = "arm,pl011\0arm,primecell"; 841 const char clocknames[] = "uartclk\0apb_pclk"; 842 DeviceState *dev = qdev_new(TYPE_PL011); 843 SysBusDevice *s = SYS_BUS_DEVICE(dev); 844 MachineState *ms = MACHINE(vms); 845 846 qdev_prop_set_chr(dev, "chardev", chr); 847 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 848 memory_region_add_subregion(mem, base, 849 sysbus_mmio_get_region(s, 0)); 850 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 851 852 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 853 qemu_fdt_add_subnode(ms->fdt, nodename); 854 /* Note that we can't use setprop_string because of the embedded NUL */ 855 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 856 compat, sizeof(compat)); 857 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 858 2, base, 2, size); 859 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 860 GIC_FDT_IRQ_TYPE_SPI, irq, 861 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 862 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 863 vms->clock_phandle, vms->clock_phandle); 864 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 865 clocknames, sizeof(clocknames)); 866 867 if (uart == VIRT_UART) { 868 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 869 } else { 870 /* Mark as not usable by the normal world */ 871 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 872 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 873 874 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 875 nodename); 876 } 877 878 g_free(nodename); 879 } 880 881 static void create_rtc(const VirtMachineState *vms) 882 { 883 char *nodename; 884 hwaddr base = vms->memmap[VIRT_RTC].base; 885 hwaddr size = vms->memmap[VIRT_RTC].size; 886 int irq = vms->irqmap[VIRT_RTC]; 887 const char compat[] = "arm,pl031\0arm,primecell"; 888 MachineState *ms = MACHINE(vms); 889 890 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 891 892 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 893 qemu_fdt_add_subnode(ms->fdt, nodename); 894 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 895 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 896 2, base, 2, size); 897 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 898 GIC_FDT_IRQ_TYPE_SPI, irq, 899 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 900 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 901 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 902 g_free(nodename); 903 } 904 905 static DeviceState *gpio_key_dev; 906 static void virt_powerdown_req(Notifier *n, void *opaque) 907 { 908 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 909 910 if (s->acpi_dev) { 911 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 912 } else { 913 /* use gpio Pin 3 for power button event */ 914 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 915 } 916 } 917 918 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 919 uint32_t phandle) 920 { 921 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 922 qdev_get_gpio_in(pl061_dev, 3)); 923 924 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 925 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 926 927 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 928 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 929 "label", "GPIO Key Poweroff"); 930 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 931 KEY_POWER); 932 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 933 "gpios", phandle, 3, 0); 934 } 935 936 #define SECURE_GPIO_POWEROFF 0 937 #define SECURE_GPIO_RESET 1 938 939 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 940 uint32_t phandle) 941 { 942 DeviceState *gpio_pwr_dev; 943 944 /* gpio-pwr */ 945 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 946 947 /* connect secure pl061 to gpio-pwr */ 948 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 949 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 950 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 951 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 952 953 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 954 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 955 "gpio-poweroff"); 956 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 957 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 958 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 959 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 960 "okay"); 961 962 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 963 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 964 "gpio-restart"); 965 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 966 "gpios", phandle, SECURE_GPIO_RESET, 0); 967 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 968 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 969 "okay"); 970 } 971 972 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 973 MemoryRegion *mem) 974 { 975 char *nodename; 976 DeviceState *pl061_dev; 977 hwaddr base = vms->memmap[gpio].base; 978 hwaddr size = vms->memmap[gpio].size; 979 int irq = vms->irqmap[gpio]; 980 const char compat[] = "arm,pl061\0arm,primecell"; 981 SysBusDevice *s; 982 MachineState *ms = MACHINE(vms); 983 984 pl061_dev = qdev_new("pl061"); 985 /* Pull lines down to 0 if not driven by the PL061 */ 986 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 987 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 988 s = SYS_BUS_DEVICE(pl061_dev); 989 sysbus_realize_and_unref(s, &error_fatal); 990 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 991 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 992 993 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 994 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 995 qemu_fdt_add_subnode(ms->fdt, nodename); 996 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 997 2, base, 2, size); 998 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 999 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1000 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1001 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1002 GIC_FDT_IRQ_TYPE_SPI, irq, 1003 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1004 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1005 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1007 1008 if (gpio != VIRT_GPIO) { 1009 /* Mark as not usable by the normal world */ 1010 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1011 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1012 } 1013 g_free(nodename); 1014 1015 /* Child gpio devices */ 1016 if (gpio == VIRT_GPIO) { 1017 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1018 } else { 1019 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1020 } 1021 } 1022 1023 static void create_virtio_devices(const VirtMachineState *vms) 1024 { 1025 int i; 1026 hwaddr size = vms->memmap[VIRT_MMIO].size; 1027 MachineState *ms = MACHINE(vms); 1028 1029 /* We create the transports in forwards order. Since qbus_realize() 1030 * prepends (not appends) new child buses, the incrementing loop below will 1031 * create a list of virtio-mmio buses with decreasing base addresses. 1032 * 1033 * When a -device option is processed from the command line, 1034 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1035 * order. The upshot is that -device options in increasing command line 1036 * order are mapped to virtio-mmio buses with decreasing base addresses. 1037 * 1038 * When this code was originally written, that arrangement ensured that the 1039 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1040 * the first -device on the command line. (The end-to-end order is a 1041 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1042 * guest kernel's name-to-address assignment strategy.) 1043 * 1044 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1045 * the message, if not necessarily the code, of commit 70161ff336. 1046 * Therefore the loop now establishes the inverse of the original intent. 1047 * 1048 * Unfortunately, we can't counteract the kernel change by reversing the 1049 * loop; it would break existing command lines. 1050 * 1051 * In any case, the kernel makes no guarantee about the stability of 1052 * enumeration order of virtio devices (as demonstrated by it changing 1053 * between kernel versions). For reliable and stable identification 1054 * of disks users must use UUIDs or similar mechanisms. 1055 */ 1056 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1057 int irq = vms->irqmap[VIRT_MMIO] + i; 1058 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1059 1060 sysbus_create_simple("virtio-mmio", base, 1061 qdev_get_gpio_in(vms->gic, irq)); 1062 } 1063 1064 /* We add dtb nodes in reverse order so that they appear in the finished 1065 * device tree lowest address first. 1066 * 1067 * Note that this mapping is independent of the loop above. The previous 1068 * loop influences virtio device to virtio transport assignment, whereas 1069 * this loop controls how virtio transports are laid out in the dtb. 1070 */ 1071 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1072 char *nodename; 1073 int irq = vms->irqmap[VIRT_MMIO] + i; 1074 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1075 1076 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1077 qemu_fdt_add_subnode(ms->fdt, nodename); 1078 qemu_fdt_setprop_string(ms->fdt, nodename, 1079 "compatible", "virtio,mmio"); 1080 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1081 2, base, 2, size); 1082 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1083 GIC_FDT_IRQ_TYPE_SPI, irq, 1084 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1085 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1086 g_free(nodename); 1087 } 1088 } 1089 1090 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1091 1092 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1093 const char *name, 1094 const char *alias_prop_name) 1095 { 1096 /* 1097 * Create a single flash device. We use the same parameters as 1098 * the flash devices on the Versatile Express board. 1099 */ 1100 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1101 1102 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1103 qdev_prop_set_uint8(dev, "width", 4); 1104 qdev_prop_set_uint8(dev, "device-width", 2); 1105 qdev_prop_set_bit(dev, "big-endian", false); 1106 qdev_prop_set_uint16(dev, "id0", 0x89); 1107 qdev_prop_set_uint16(dev, "id1", 0x18); 1108 qdev_prop_set_uint16(dev, "id2", 0x00); 1109 qdev_prop_set_uint16(dev, "id3", 0x00); 1110 qdev_prop_set_string(dev, "name", name); 1111 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1112 object_property_add_alias(OBJECT(vms), alias_prop_name, 1113 OBJECT(dev), "drive"); 1114 return PFLASH_CFI01(dev); 1115 } 1116 1117 static void virt_flash_create(VirtMachineState *vms) 1118 { 1119 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1120 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1121 } 1122 1123 static void virt_flash_map1(PFlashCFI01 *flash, 1124 hwaddr base, hwaddr size, 1125 MemoryRegion *sysmem) 1126 { 1127 DeviceState *dev = DEVICE(flash); 1128 1129 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1130 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1131 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1132 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1133 1134 memory_region_add_subregion(sysmem, base, 1135 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1136 0)); 1137 } 1138 1139 static void virt_flash_map(VirtMachineState *vms, 1140 MemoryRegion *sysmem, 1141 MemoryRegion *secure_sysmem) 1142 { 1143 /* 1144 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1145 * sysmem is the system memory space. secure_sysmem is the secure view 1146 * of the system, and the first flash device should be made visible only 1147 * there. The second flash device is visible to both secure and nonsecure. 1148 * If sysmem == secure_sysmem this means there is no separate Secure 1149 * address space and both flash devices are generally visible. 1150 */ 1151 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1152 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1153 1154 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1155 secure_sysmem); 1156 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1157 sysmem); 1158 } 1159 1160 static void virt_flash_fdt(VirtMachineState *vms, 1161 MemoryRegion *sysmem, 1162 MemoryRegion *secure_sysmem) 1163 { 1164 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1165 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1166 MachineState *ms = MACHINE(vms); 1167 char *nodename; 1168 1169 if (sysmem == secure_sysmem) { 1170 /* Report both flash devices as a single node in the DT */ 1171 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1172 qemu_fdt_add_subnode(ms->fdt, nodename); 1173 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1174 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1175 2, flashbase, 2, flashsize, 1176 2, flashbase + flashsize, 2, flashsize); 1177 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1178 g_free(nodename); 1179 } else { 1180 /* 1181 * Report the devices as separate nodes so we can mark one as 1182 * only visible to the secure world. 1183 */ 1184 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1185 qemu_fdt_add_subnode(ms->fdt, nodename); 1186 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1187 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1188 2, flashbase, 2, flashsize); 1189 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1190 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1191 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1192 g_free(nodename); 1193 1194 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1195 qemu_fdt_add_subnode(ms->fdt, nodename); 1196 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1197 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1198 2, flashbase + flashsize, 2, flashsize); 1199 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1200 g_free(nodename); 1201 } 1202 } 1203 1204 static bool virt_firmware_init(VirtMachineState *vms, 1205 MemoryRegion *sysmem, 1206 MemoryRegion *secure_sysmem) 1207 { 1208 int i; 1209 const char *bios_name; 1210 BlockBackend *pflash_blk0; 1211 1212 /* Map legacy -drive if=pflash to machine properties */ 1213 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1214 pflash_cfi01_legacy_drive(vms->flash[i], 1215 drive_get(IF_PFLASH, 0, i)); 1216 } 1217 1218 virt_flash_map(vms, sysmem, secure_sysmem); 1219 1220 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1221 1222 bios_name = MACHINE(vms)->firmware; 1223 if (bios_name) { 1224 char *fname; 1225 MemoryRegion *mr; 1226 int image_size; 1227 1228 if (pflash_blk0) { 1229 error_report("The contents of the first flash device may be " 1230 "specified with -bios or with -drive if=pflash... " 1231 "but you cannot use both options at once"); 1232 exit(1); 1233 } 1234 1235 /* Fall back to -bios */ 1236 1237 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1238 if (!fname) { 1239 error_report("Could not find ROM image '%s'", bios_name); 1240 exit(1); 1241 } 1242 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1243 image_size = load_image_mr(fname, mr); 1244 g_free(fname); 1245 if (image_size < 0) { 1246 error_report("Could not load ROM image '%s'", bios_name); 1247 exit(1); 1248 } 1249 } 1250 1251 return pflash_blk0 || bios_name; 1252 } 1253 1254 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1255 { 1256 MachineState *ms = MACHINE(vms); 1257 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1258 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1259 FWCfgState *fw_cfg; 1260 char *nodename; 1261 1262 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1263 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1264 1265 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1266 qemu_fdt_add_subnode(ms->fdt, nodename); 1267 qemu_fdt_setprop_string(ms->fdt, nodename, 1268 "compatible", "qemu,fw-cfg-mmio"); 1269 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1270 2, base, 2, size); 1271 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1272 g_free(nodename); 1273 return fw_cfg; 1274 } 1275 1276 static void create_pcie_irq_map(const MachineState *ms, 1277 uint32_t gic_phandle, 1278 int first_irq, const char *nodename) 1279 { 1280 int devfn, pin; 1281 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1282 uint32_t *irq_map = full_irq_map; 1283 1284 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1285 for (pin = 0; pin < 4; pin++) { 1286 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1287 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1288 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1289 int i; 1290 1291 uint32_t map[] = { 1292 devfn << 8, 0, 0, /* devfn */ 1293 pin + 1, /* PCI pin */ 1294 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1295 1296 /* Convert map to big endian */ 1297 for (i = 0; i < 10; i++) { 1298 irq_map[i] = cpu_to_be32(map[i]); 1299 } 1300 irq_map += 10; 1301 } 1302 } 1303 1304 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1305 full_irq_map, sizeof(full_irq_map)); 1306 1307 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1308 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1309 0, 0, 1310 0x7 /* PCI irq */); 1311 } 1312 1313 static void create_smmu(const VirtMachineState *vms, 1314 PCIBus *bus) 1315 { 1316 char *node; 1317 const char compat[] = "arm,smmu-v3"; 1318 int irq = vms->irqmap[VIRT_SMMU]; 1319 int i; 1320 hwaddr base = vms->memmap[VIRT_SMMU].base; 1321 hwaddr size = vms->memmap[VIRT_SMMU].size; 1322 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1323 DeviceState *dev; 1324 MachineState *ms = MACHINE(vms); 1325 1326 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1327 return; 1328 } 1329 1330 dev = qdev_new(TYPE_ARM_SMMUV3); 1331 1332 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1333 &error_abort); 1334 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1335 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1336 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1337 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1338 qdev_get_gpio_in(vms->gic, irq + i)); 1339 } 1340 1341 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1342 qemu_fdt_add_subnode(ms->fdt, node); 1343 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1344 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1345 1346 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1347 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1348 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1349 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1350 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1351 1352 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1353 sizeof(irq_names)); 1354 1355 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1356 1357 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1358 1359 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1360 g_free(node); 1361 } 1362 1363 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1364 { 1365 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1366 uint16_t bdf = vms->virtio_iommu_bdf; 1367 MachineState *ms = MACHINE(vms); 1368 char *node; 1369 1370 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1371 1372 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1373 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1374 qemu_fdt_add_subnode(ms->fdt, node); 1375 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1376 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1377 1, bdf << 8, 1, 0, 1, 0, 1378 1, 0, 1, 0); 1379 1380 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1381 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1382 g_free(node); 1383 1384 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1385 0x0, vms->iommu_phandle, 0x0, bdf, 1386 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1387 } 1388 1389 static void create_pcie(VirtMachineState *vms) 1390 { 1391 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1392 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1393 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1394 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1395 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1396 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1397 hwaddr base_ecam, size_ecam; 1398 hwaddr base = base_mmio; 1399 int nr_pcie_buses; 1400 int irq = vms->irqmap[VIRT_PCIE]; 1401 MemoryRegion *mmio_alias; 1402 MemoryRegion *mmio_reg; 1403 MemoryRegion *ecam_alias; 1404 MemoryRegion *ecam_reg; 1405 DeviceState *dev; 1406 char *nodename; 1407 int i, ecam_id; 1408 PCIHostState *pci; 1409 MachineState *ms = MACHINE(vms); 1410 MachineClass *mc = MACHINE_GET_CLASS(ms); 1411 1412 dev = qdev_new(TYPE_GPEX_HOST); 1413 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1414 1415 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1416 base_ecam = vms->memmap[ecam_id].base; 1417 size_ecam = vms->memmap[ecam_id].size; 1418 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1419 /* Map only the first size_ecam bytes of ECAM space */ 1420 ecam_alias = g_new0(MemoryRegion, 1); 1421 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1422 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1423 ecam_reg, 0, size_ecam); 1424 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1425 1426 /* Map the MMIO window into system address space so as to expose 1427 * the section of PCI MMIO space which starts at the same base address 1428 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1429 * the window). 1430 */ 1431 mmio_alias = g_new0(MemoryRegion, 1); 1432 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1433 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1434 mmio_reg, base_mmio, size_mmio); 1435 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1436 1437 if (vms->highmem_mmio) { 1438 /* Map high MMIO space */ 1439 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1440 1441 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1442 mmio_reg, base_mmio_high, size_mmio_high); 1443 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1444 high_mmio_alias); 1445 } 1446 1447 /* Map IO port space */ 1448 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1449 1450 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1451 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1452 qdev_get_gpio_in(vms->gic, irq + i)); 1453 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1454 } 1455 1456 pci = PCI_HOST_BRIDGE(dev); 1457 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1458 vms->bus = pci->bus; 1459 if (vms->bus) { 1460 for (i = 0; i < nb_nics; i++) { 1461 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 1462 } 1463 } 1464 1465 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1466 qemu_fdt_add_subnode(ms->fdt, nodename); 1467 qemu_fdt_setprop_string(ms->fdt, nodename, 1468 "compatible", "pci-host-ecam-generic"); 1469 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1470 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1471 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1472 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1473 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1474 nr_pcie_buses - 1); 1475 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1476 1477 if (vms->msi_phandle) { 1478 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1479 0, vms->msi_phandle, 0, 0x10000); 1480 } 1481 1482 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1483 2, base_ecam, 2, size_ecam); 1484 1485 if (vms->highmem_mmio) { 1486 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1487 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1488 2, base_pio, 2, size_pio, 1489 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1490 2, base_mmio, 2, size_mmio, 1491 1, FDT_PCI_RANGE_MMIO_64BIT, 1492 2, base_mmio_high, 1493 2, base_mmio_high, 2, size_mmio_high); 1494 } else { 1495 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1496 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1497 2, base_pio, 2, size_pio, 1498 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1499 2, base_mmio, 2, size_mmio); 1500 } 1501 1502 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1503 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1504 1505 if (vms->iommu) { 1506 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1507 1508 switch (vms->iommu) { 1509 case VIRT_IOMMU_SMMUV3: 1510 create_smmu(vms, vms->bus); 1511 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1512 0x0, vms->iommu_phandle, 0x0, 0x10000); 1513 break; 1514 default: 1515 g_assert_not_reached(); 1516 } 1517 } 1518 } 1519 1520 static void create_platform_bus(VirtMachineState *vms) 1521 { 1522 DeviceState *dev; 1523 SysBusDevice *s; 1524 int i; 1525 MemoryRegion *sysmem = get_system_memory(); 1526 1527 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1528 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1529 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1530 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1531 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1532 vms->platform_bus_dev = dev; 1533 1534 s = SYS_BUS_DEVICE(dev); 1535 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1536 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1537 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1538 } 1539 1540 memory_region_add_subregion(sysmem, 1541 vms->memmap[VIRT_PLATFORM_BUS].base, 1542 sysbus_mmio_get_region(s, 0)); 1543 } 1544 1545 static void create_tag_ram(MemoryRegion *tag_sysmem, 1546 hwaddr base, hwaddr size, 1547 const char *name) 1548 { 1549 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1550 1551 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1552 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1553 } 1554 1555 static void create_secure_ram(VirtMachineState *vms, 1556 MemoryRegion *secure_sysmem, 1557 MemoryRegion *secure_tag_sysmem) 1558 { 1559 MemoryRegion *secram = g_new(MemoryRegion, 1); 1560 char *nodename; 1561 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1562 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1563 MachineState *ms = MACHINE(vms); 1564 1565 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1566 &error_fatal); 1567 memory_region_add_subregion(secure_sysmem, base, secram); 1568 1569 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1570 qemu_fdt_add_subnode(ms->fdt, nodename); 1571 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1573 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1574 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1575 1576 if (secure_tag_sysmem) { 1577 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1578 } 1579 1580 g_free(nodename); 1581 } 1582 1583 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1584 { 1585 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1586 bootinfo); 1587 MachineState *ms = MACHINE(board); 1588 1589 1590 *fdt_size = board->fdt_size; 1591 return ms->fdt; 1592 } 1593 1594 static void virt_build_smbios(VirtMachineState *vms) 1595 { 1596 MachineClass *mc = MACHINE_GET_CLASS(vms); 1597 MachineState *ms = MACHINE(vms); 1598 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1599 uint8_t *smbios_tables, *smbios_anchor; 1600 size_t smbios_tables_len, smbios_anchor_len; 1601 struct smbios_phys_mem_area mem_array; 1602 const char *product = "QEMU Virtual Machine"; 1603 1604 if (kvm_enabled()) { 1605 product = "KVM Virtual Machine"; 1606 } 1607 1608 smbios_set_defaults("QEMU", product, 1609 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1610 true, SMBIOS_ENTRY_POINT_TYPE_64); 1611 1612 /* build the array of physical mem area from base_memmap */ 1613 mem_array.address = vms->memmap[VIRT_MEM].base; 1614 mem_array.length = ms->ram_size; 1615 1616 smbios_get_tables(ms, &mem_array, 1, 1617 &smbios_tables, &smbios_tables_len, 1618 &smbios_anchor, &smbios_anchor_len, 1619 &error_fatal); 1620 1621 if (smbios_anchor) { 1622 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1623 smbios_tables, smbios_tables_len); 1624 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1625 smbios_anchor, smbios_anchor_len); 1626 } 1627 } 1628 1629 static 1630 void virt_machine_done(Notifier *notifier, void *data) 1631 { 1632 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1633 machine_done); 1634 MachineState *ms = MACHINE(vms); 1635 ARMCPU *cpu = ARM_CPU(first_cpu); 1636 struct arm_boot_info *info = &vms->bootinfo; 1637 AddressSpace *as = arm_boot_address_space(cpu, info); 1638 1639 /* 1640 * If the user provided a dtb, we assume the dynamic sysbus nodes 1641 * already are integrated there. This corresponds to a use case where 1642 * the dynamic sysbus nodes are complex and their generation is not yet 1643 * supported. In that case the user can take charge of the guest dt 1644 * while qemu takes charge of the qom stuff. 1645 */ 1646 if (info->dtb_filename == NULL) { 1647 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1648 vms->memmap[VIRT_PLATFORM_BUS].base, 1649 vms->memmap[VIRT_PLATFORM_BUS].size, 1650 vms->irqmap[VIRT_PLATFORM_BUS]); 1651 } 1652 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1653 exit(1); 1654 } 1655 1656 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1657 1658 virt_acpi_setup(vms); 1659 virt_build_smbios(vms); 1660 } 1661 1662 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1663 { 1664 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1665 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1666 1667 if (!vmc->disallow_affinity_adjustment) { 1668 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1669 * GIC's target-list limitations. 32-bit KVM hosts currently 1670 * always create clusters of 4 CPUs, but that is expected to 1671 * change when they gain support for gicv3. When KVM is enabled 1672 * it will override the changes we make here, therefore our 1673 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1674 * and to improve SGI efficiency. 1675 */ 1676 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1677 clustersz = GIC_TARGETLIST_BITS; 1678 } else { 1679 clustersz = GICV3_TARGETLIST_BITS; 1680 } 1681 } 1682 return arm_build_mp_affinity(idx, clustersz); 1683 } 1684 1685 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1686 int index) 1687 { 1688 bool *enabled_array[] = { 1689 &vms->highmem_redists, 1690 &vms->highmem_ecam, 1691 &vms->highmem_mmio, 1692 }; 1693 1694 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1695 ARRAY_SIZE(enabled_array)); 1696 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1697 1698 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1699 } 1700 1701 static void virt_set_high_memmap(VirtMachineState *vms, 1702 hwaddr base, int pa_bits) 1703 { 1704 hwaddr region_base, region_size; 1705 bool *region_enabled, fits; 1706 int i; 1707 1708 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1709 region_enabled = virt_get_high_memmap_enabled(vms, i); 1710 region_base = ROUND_UP(base, extended_memmap[i].size); 1711 region_size = extended_memmap[i].size; 1712 1713 vms->memmap[i].base = region_base; 1714 vms->memmap[i].size = region_size; 1715 1716 /* 1717 * Check each device to see if it fits in the PA space, 1718 * moving highest_gpa as we go. For compatibility, move 1719 * highest_gpa for disabled fitting devices as well, if 1720 * the compact layout has been disabled. 1721 * 1722 * For each device that doesn't fit, disable it. 1723 */ 1724 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1725 *region_enabled &= fits; 1726 if (vms->highmem_compact && !*region_enabled) { 1727 continue; 1728 } 1729 1730 base = region_base + region_size; 1731 if (fits) { 1732 vms->highest_gpa = base - 1; 1733 } 1734 } 1735 } 1736 1737 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1738 { 1739 MachineState *ms = MACHINE(vms); 1740 hwaddr base, device_memory_base, device_memory_size, memtop; 1741 int i; 1742 1743 vms->memmap = extended_memmap; 1744 1745 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1746 vms->memmap[i] = base_memmap[i]; 1747 } 1748 1749 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1750 error_report("unsupported number of memory slots: %"PRIu64, 1751 ms->ram_slots); 1752 exit(EXIT_FAILURE); 1753 } 1754 1755 /* 1756 * !highmem is exactly the same as limiting the PA space to 32bit, 1757 * irrespective of the underlying capabilities of the HW. 1758 */ 1759 if (!vms->highmem) { 1760 pa_bits = 32; 1761 } 1762 1763 /* 1764 * We compute the base of the high IO region depending on the 1765 * amount of initial and device memory. The device memory start/size 1766 * is aligned on 1GiB. We never put the high IO region below 256GiB 1767 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1768 * The device region size assumes 1GiB page max alignment per slot. 1769 */ 1770 device_memory_base = 1771 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1772 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1773 1774 /* Base address of the high IO region */ 1775 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1776 if (memtop > BIT_ULL(pa_bits)) { 1777 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1778 pa_bits, memtop - BIT_ULL(pa_bits)); 1779 exit(EXIT_FAILURE); 1780 } 1781 if (base < device_memory_base) { 1782 error_report("maxmem/slots too huge"); 1783 exit(EXIT_FAILURE); 1784 } 1785 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1786 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1787 } 1788 1789 /* We know for sure that at least the memory fits in the PA space */ 1790 vms->highest_gpa = memtop - 1; 1791 1792 virt_set_high_memmap(vms, base, pa_bits); 1793 1794 if (device_memory_size > 0) { 1795 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1796 } 1797 } 1798 1799 static VirtGICType finalize_gic_version_do(const char *accel_name, 1800 VirtGICType gic_version, 1801 int gics_supported, 1802 unsigned int max_cpus) 1803 { 1804 /* Convert host/max/nosel to GIC version number */ 1805 switch (gic_version) { 1806 case VIRT_GIC_VERSION_HOST: 1807 if (!kvm_enabled()) { 1808 error_report("gic-version=host requires KVM"); 1809 exit(1); 1810 } 1811 1812 /* For KVM, gic-version=host means gic-version=max */ 1813 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1814 gics_supported, max_cpus); 1815 case VIRT_GIC_VERSION_MAX: 1816 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1817 gic_version = VIRT_GIC_VERSION_4; 1818 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1819 gic_version = VIRT_GIC_VERSION_3; 1820 } else { 1821 gic_version = VIRT_GIC_VERSION_2; 1822 } 1823 break; 1824 case VIRT_GIC_VERSION_NOSEL: 1825 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1826 max_cpus <= GIC_NCPU) { 1827 gic_version = VIRT_GIC_VERSION_2; 1828 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1829 /* 1830 * in case the host does not support v2 emulation or 1831 * the end-user requested more than 8 VCPUs we now default 1832 * to v3. In any case defaulting to v2 would be broken. 1833 */ 1834 gic_version = VIRT_GIC_VERSION_3; 1835 } else if (max_cpus > GIC_NCPU) { 1836 error_report("%s only supports GICv2 emulation but more than 8 " 1837 "vcpus are requested", accel_name); 1838 exit(1); 1839 } 1840 break; 1841 case VIRT_GIC_VERSION_2: 1842 case VIRT_GIC_VERSION_3: 1843 case VIRT_GIC_VERSION_4: 1844 break; 1845 } 1846 1847 /* Check chosen version is effectively supported */ 1848 switch (gic_version) { 1849 case VIRT_GIC_VERSION_2: 1850 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1851 error_report("%s does not support GICv2 emulation", accel_name); 1852 exit(1); 1853 } 1854 break; 1855 case VIRT_GIC_VERSION_3: 1856 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1857 error_report("%s does not support GICv3 emulation", accel_name); 1858 exit(1); 1859 } 1860 break; 1861 case VIRT_GIC_VERSION_4: 1862 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1863 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1864 accel_name); 1865 exit(1); 1866 } 1867 break; 1868 default: 1869 error_report("logic error in finalize_gic_version"); 1870 exit(1); 1871 break; 1872 } 1873 1874 return gic_version; 1875 } 1876 1877 /* 1878 * finalize_gic_version - Determines the final gic_version 1879 * according to the gic-version property 1880 * 1881 * Default GIC type is v2 1882 */ 1883 static void finalize_gic_version(VirtMachineState *vms) 1884 { 1885 const char *accel_name = current_accel_name(); 1886 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1887 int gics_supported = 0; 1888 1889 /* Determine which GIC versions the current environment supports */ 1890 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1891 int probe_bitmap = kvm_arm_vgic_probe(); 1892 1893 if (!probe_bitmap) { 1894 error_report("Unable to determine GIC version supported by host"); 1895 exit(1); 1896 } 1897 1898 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1899 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1900 } 1901 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1902 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1903 } 1904 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1905 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1906 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1907 accel_name = "KVM with kernel-irqchip=off"; 1908 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1909 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1910 if (module_object_class_by_name("arm-gicv3")) { 1911 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1912 if (vms->virt) { 1913 /* GICv4 only makes sense if CPU has EL2 */ 1914 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1915 } 1916 } 1917 } else { 1918 error_report("Unsupported accelerator, can not determine GIC support"); 1919 exit(1); 1920 } 1921 1922 /* 1923 * Then convert helpers like host/max to concrete GIC versions and ensure 1924 * the desired version is supported 1925 */ 1926 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1927 gics_supported, max_cpus); 1928 } 1929 1930 /* 1931 * virt_cpu_post_init() must be called after the CPUs have 1932 * been realized and the GIC has been created. 1933 */ 1934 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1935 { 1936 int max_cpus = MACHINE(vms)->smp.max_cpus; 1937 bool aarch64, pmu, steal_time; 1938 CPUState *cpu; 1939 1940 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1941 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1942 steal_time = object_property_get_bool(OBJECT(first_cpu), 1943 "kvm-steal-time", NULL); 1944 1945 if (kvm_enabled()) { 1946 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1947 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1948 1949 if (steal_time) { 1950 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1951 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1952 1953 /* The memory region size must be a multiple of host page size. */ 1954 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1955 1956 if (pvtime_size > pvtime_reg_size) { 1957 error_report("pvtime requires a %" HWADDR_PRId 1958 " byte memory region for %d CPUs," 1959 " but only %" HWADDR_PRId " has been reserved", 1960 pvtime_size, max_cpus, pvtime_reg_size); 1961 exit(1); 1962 } 1963 1964 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1965 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1966 } 1967 1968 CPU_FOREACH(cpu) { 1969 if (pmu) { 1970 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1971 if (kvm_irqchip_in_kernel()) { 1972 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 1973 } 1974 kvm_arm_pmu_init(ARM_CPU(cpu)); 1975 } 1976 if (steal_time) { 1977 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 1978 + cpu->cpu_index 1979 * PVTIME_SIZE_PER_CPU); 1980 } 1981 } 1982 } else { 1983 if (aarch64 && vms->highmem) { 1984 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1985 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1986 1987 if (pamax < requested_pa_size) { 1988 error_report("VCPU supports less PA bits (%d) than " 1989 "requested by the memory map (%d)", 1990 pamax, requested_pa_size); 1991 exit(1); 1992 } 1993 } 1994 } 1995 } 1996 1997 static void machvirt_init(MachineState *machine) 1998 { 1999 VirtMachineState *vms = VIRT_MACHINE(machine); 2000 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2001 MachineClass *mc = MACHINE_GET_CLASS(machine); 2002 const CPUArchIdList *possible_cpus; 2003 MemoryRegion *sysmem = get_system_memory(); 2004 MemoryRegion *secure_sysmem = NULL; 2005 MemoryRegion *tag_sysmem = NULL; 2006 MemoryRegion *secure_tag_sysmem = NULL; 2007 int n, virt_max_cpus; 2008 bool firmware_loaded; 2009 bool aarch64 = true; 2010 bool has_ged = !vmc->no_ged; 2011 unsigned int smp_cpus = machine->smp.cpus; 2012 unsigned int max_cpus = machine->smp.max_cpus; 2013 2014 possible_cpus = mc->possible_cpu_arch_ids(machine); 2015 2016 /* 2017 * In accelerated mode, the memory map is computed earlier in kvm_type() 2018 * to create a VM with the right number of IPA bits. 2019 */ 2020 if (!vms->memmap) { 2021 Object *cpuobj; 2022 ARMCPU *armcpu; 2023 int pa_bits; 2024 2025 /* 2026 * Instantiate a temporary CPU object to find out about what 2027 * we are about to deal with. Once this is done, get rid of 2028 * the object. 2029 */ 2030 cpuobj = object_new(possible_cpus->cpus[0].type); 2031 armcpu = ARM_CPU(cpuobj); 2032 2033 pa_bits = arm_pamax(armcpu); 2034 2035 object_unref(cpuobj); 2036 2037 virt_set_memmap(vms, pa_bits); 2038 } 2039 2040 /* We can probe only here because during property set 2041 * KVM is not available yet 2042 */ 2043 finalize_gic_version(vms); 2044 2045 if (vms->secure) { 2046 /* 2047 * The Secure view of the world is the same as the NonSecure, 2048 * but with a few extra devices. Create it as a container region 2049 * containing the system memory at low priority; any secure-only 2050 * devices go in at higher priority and take precedence. 2051 */ 2052 secure_sysmem = g_new(MemoryRegion, 1); 2053 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2054 UINT64_MAX); 2055 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2056 } 2057 2058 firmware_loaded = virt_firmware_init(vms, sysmem, 2059 secure_sysmem ?: sysmem); 2060 2061 /* If we have an EL3 boot ROM then the assumption is that it will 2062 * implement PSCI itself, so disable QEMU's internal implementation 2063 * so it doesn't get in the way. Instead of starting secondary 2064 * CPUs in PSCI powerdown state we will start them all running and 2065 * let the boot ROM sort them out. 2066 * The usual case is that we do use QEMU's PSCI implementation; 2067 * if the guest has EL2 then we will use SMC as the conduit, 2068 * and otherwise we will use HVC (for backwards compatibility and 2069 * because if we're using KVM then we must use HVC). 2070 */ 2071 if (vms->secure && firmware_loaded) { 2072 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2073 } else if (vms->virt) { 2074 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2075 } else { 2076 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2077 } 2078 2079 /* 2080 * The maximum number of CPUs depends on the GIC version, or on how 2081 * many redistributors we can fit into the memory map (which in turn 2082 * depends on whether this is a GICv3 or v4). 2083 */ 2084 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2085 virt_max_cpus = GIC_NCPU; 2086 } else { 2087 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2088 if (vms->highmem_redists) { 2089 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2090 } 2091 } 2092 2093 if (max_cpus > virt_max_cpus) { 2094 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2095 "supported by machine 'mach-virt' (%d)", 2096 max_cpus, virt_max_cpus); 2097 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2098 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2099 } 2100 2101 exit(1); 2102 } 2103 2104 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2105 error_report("mach-virt: %s does not support providing " 2106 "Security extensions (TrustZone) to the guest CPU", 2107 current_accel_name()); 2108 exit(1); 2109 } 2110 2111 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2112 error_report("mach-virt: %s does not support providing " 2113 "Virtualization extensions to the guest CPU", 2114 current_accel_name()); 2115 exit(1); 2116 } 2117 2118 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2119 error_report("mach-virt: %s does not support providing " 2120 "MTE to the guest CPU", 2121 current_accel_name()); 2122 exit(1); 2123 } 2124 2125 create_fdt(vms); 2126 2127 assert(possible_cpus->len == max_cpus); 2128 for (n = 0; n < possible_cpus->len; n++) { 2129 Object *cpuobj; 2130 CPUState *cs; 2131 2132 if (n >= smp_cpus) { 2133 break; 2134 } 2135 2136 cpuobj = object_new(possible_cpus->cpus[n].type); 2137 object_property_set_int(cpuobj, "mp-affinity", 2138 possible_cpus->cpus[n].arch_id, NULL); 2139 2140 cs = CPU(cpuobj); 2141 cs->cpu_index = n; 2142 2143 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2144 &error_fatal); 2145 2146 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2147 2148 if (!vms->secure) { 2149 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2150 } 2151 2152 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2153 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2154 } 2155 2156 if (vmc->kvm_no_adjvtime && 2157 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2158 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2159 } 2160 2161 if (vmc->no_kvm_steal_time && 2162 object_property_find(cpuobj, "kvm-steal-time")) { 2163 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2164 } 2165 2166 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2167 object_property_set_bool(cpuobj, "pmu", false, NULL); 2168 } 2169 2170 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2171 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2172 } 2173 2174 if (object_property_find(cpuobj, "reset-cbar")) { 2175 object_property_set_int(cpuobj, "reset-cbar", 2176 vms->memmap[VIRT_CPUPERIPHS].base, 2177 &error_abort); 2178 } 2179 2180 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2181 &error_abort); 2182 if (vms->secure) { 2183 object_property_set_link(cpuobj, "secure-memory", 2184 OBJECT(secure_sysmem), &error_abort); 2185 } 2186 2187 if (vms->mte) { 2188 /* Create the memory region only once, but link to all cpus. */ 2189 if (!tag_sysmem) { 2190 /* 2191 * The property exists only if MemTag is supported. 2192 * If it is, we must allocate the ram to back that up. 2193 */ 2194 if (!object_property_find(cpuobj, "tag-memory")) { 2195 error_report("MTE requested, but not supported " 2196 "by the guest CPU"); 2197 exit(1); 2198 } 2199 2200 tag_sysmem = g_new(MemoryRegion, 1); 2201 memory_region_init(tag_sysmem, OBJECT(machine), 2202 "tag-memory", UINT64_MAX / 32); 2203 2204 if (vms->secure) { 2205 secure_tag_sysmem = g_new(MemoryRegion, 1); 2206 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2207 "secure-tag-memory", UINT64_MAX / 32); 2208 2209 /* As with ram, secure-tag takes precedence over tag. */ 2210 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2211 tag_sysmem, -1); 2212 } 2213 } 2214 2215 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2216 &error_abort); 2217 if (vms->secure) { 2218 object_property_set_link(cpuobj, "secure-tag-memory", 2219 OBJECT(secure_tag_sysmem), 2220 &error_abort); 2221 } 2222 } 2223 2224 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2225 object_unref(cpuobj); 2226 } 2227 fdt_add_timer_nodes(vms); 2228 fdt_add_cpu_nodes(vms); 2229 2230 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2231 machine->ram); 2232 2233 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2234 2235 create_gic(vms, sysmem); 2236 2237 virt_cpu_post_init(vms, sysmem); 2238 2239 fdt_add_pmu_nodes(vms); 2240 2241 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2242 2243 if (vms->secure) { 2244 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2245 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2246 } 2247 2248 if (tag_sysmem) { 2249 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2250 machine->ram_size, "mach-virt.tag"); 2251 } 2252 2253 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2254 2255 create_rtc(vms); 2256 2257 create_pcie(vms); 2258 2259 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2260 vms->acpi_dev = create_acpi_ged(vms); 2261 } else { 2262 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2263 } 2264 2265 if (vms->secure && !vmc->no_secure_gpio) { 2266 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2267 } 2268 2269 /* connect powerdown request */ 2270 vms->powerdown_notifier.notify = virt_powerdown_req; 2271 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2272 2273 /* Create mmio transports, so the user can create virtio backends 2274 * (which will be automatically plugged in to the transports). If 2275 * no backend is created the transport will just sit harmlessly idle. 2276 */ 2277 create_virtio_devices(vms); 2278 2279 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2280 rom_set_fw(vms->fw_cfg); 2281 2282 create_platform_bus(vms); 2283 2284 if (machine->nvdimms_state->is_enabled) { 2285 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2286 .space_id = AML_AS_SYSTEM_MEMORY, 2287 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2288 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2289 }; 2290 2291 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2292 arm_virt_nvdimm_acpi_dsmio, 2293 vms->fw_cfg, OBJECT(vms)); 2294 } 2295 2296 vms->bootinfo.ram_size = machine->ram_size; 2297 vms->bootinfo.board_id = -1; 2298 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2299 vms->bootinfo.get_dtb = machvirt_dtb; 2300 vms->bootinfo.skip_dtb_autoload = true; 2301 vms->bootinfo.firmware_loaded = firmware_loaded; 2302 vms->bootinfo.psci_conduit = vms->psci_conduit; 2303 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2304 2305 vms->machine_done.notify = virt_machine_done; 2306 qemu_add_machine_init_done_notifier(&vms->machine_done); 2307 } 2308 2309 static bool virt_get_secure(Object *obj, Error **errp) 2310 { 2311 VirtMachineState *vms = VIRT_MACHINE(obj); 2312 2313 return vms->secure; 2314 } 2315 2316 static void virt_set_secure(Object *obj, bool value, Error **errp) 2317 { 2318 VirtMachineState *vms = VIRT_MACHINE(obj); 2319 2320 vms->secure = value; 2321 } 2322 2323 static bool virt_get_virt(Object *obj, Error **errp) 2324 { 2325 VirtMachineState *vms = VIRT_MACHINE(obj); 2326 2327 return vms->virt; 2328 } 2329 2330 static void virt_set_virt(Object *obj, bool value, Error **errp) 2331 { 2332 VirtMachineState *vms = VIRT_MACHINE(obj); 2333 2334 vms->virt = value; 2335 } 2336 2337 static bool virt_get_highmem(Object *obj, Error **errp) 2338 { 2339 VirtMachineState *vms = VIRT_MACHINE(obj); 2340 2341 return vms->highmem; 2342 } 2343 2344 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2345 { 2346 VirtMachineState *vms = VIRT_MACHINE(obj); 2347 2348 vms->highmem = value; 2349 } 2350 2351 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2352 { 2353 VirtMachineState *vms = VIRT_MACHINE(obj); 2354 2355 return vms->highmem_compact; 2356 } 2357 2358 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2359 { 2360 VirtMachineState *vms = VIRT_MACHINE(obj); 2361 2362 vms->highmem_compact = value; 2363 } 2364 2365 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2366 { 2367 VirtMachineState *vms = VIRT_MACHINE(obj); 2368 2369 return vms->highmem_redists; 2370 } 2371 2372 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2373 { 2374 VirtMachineState *vms = VIRT_MACHINE(obj); 2375 2376 vms->highmem_redists = value; 2377 } 2378 2379 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2380 { 2381 VirtMachineState *vms = VIRT_MACHINE(obj); 2382 2383 return vms->highmem_ecam; 2384 } 2385 2386 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2387 { 2388 VirtMachineState *vms = VIRT_MACHINE(obj); 2389 2390 vms->highmem_ecam = value; 2391 } 2392 2393 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2394 { 2395 VirtMachineState *vms = VIRT_MACHINE(obj); 2396 2397 return vms->highmem_mmio; 2398 } 2399 2400 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2401 { 2402 VirtMachineState *vms = VIRT_MACHINE(obj); 2403 2404 vms->highmem_mmio = value; 2405 } 2406 2407 2408 static bool virt_get_its(Object *obj, Error **errp) 2409 { 2410 VirtMachineState *vms = VIRT_MACHINE(obj); 2411 2412 return vms->its; 2413 } 2414 2415 static void virt_set_its(Object *obj, bool value, Error **errp) 2416 { 2417 VirtMachineState *vms = VIRT_MACHINE(obj); 2418 2419 vms->its = value; 2420 } 2421 2422 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2423 { 2424 VirtMachineState *vms = VIRT_MACHINE(obj); 2425 2426 return vms->dtb_randomness; 2427 } 2428 2429 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2430 { 2431 VirtMachineState *vms = VIRT_MACHINE(obj); 2432 2433 vms->dtb_randomness = value; 2434 } 2435 2436 static char *virt_get_oem_id(Object *obj, Error **errp) 2437 { 2438 VirtMachineState *vms = VIRT_MACHINE(obj); 2439 2440 return g_strdup(vms->oem_id); 2441 } 2442 2443 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2444 { 2445 VirtMachineState *vms = VIRT_MACHINE(obj); 2446 size_t len = strlen(value); 2447 2448 if (len > 6) { 2449 error_setg(errp, 2450 "User specified oem-id value is bigger than 6 bytes in size"); 2451 return; 2452 } 2453 2454 strncpy(vms->oem_id, value, 6); 2455 } 2456 2457 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2458 { 2459 VirtMachineState *vms = VIRT_MACHINE(obj); 2460 2461 return g_strdup(vms->oem_table_id); 2462 } 2463 2464 static void virt_set_oem_table_id(Object *obj, const char *value, 2465 Error **errp) 2466 { 2467 VirtMachineState *vms = VIRT_MACHINE(obj); 2468 size_t len = strlen(value); 2469 2470 if (len > 8) { 2471 error_setg(errp, 2472 "User specified oem-table-id value is bigger than 8 bytes in size"); 2473 return; 2474 } 2475 strncpy(vms->oem_table_id, value, 8); 2476 } 2477 2478 2479 bool virt_is_acpi_enabled(VirtMachineState *vms) 2480 { 2481 if (vms->acpi == ON_OFF_AUTO_OFF) { 2482 return false; 2483 } 2484 return true; 2485 } 2486 2487 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2488 void *opaque, Error **errp) 2489 { 2490 VirtMachineState *vms = VIRT_MACHINE(obj); 2491 OnOffAuto acpi = vms->acpi; 2492 2493 visit_type_OnOffAuto(v, name, &acpi, errp); 2494 } 2495 2496 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2497 void *opaque, Error **errp) 2498 { 2499 VirtMachineState *vms = VIRT_MACHINE(obj); 2500 2501 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2502 } 2503 2504 static bool virt_get_ras(Object *obj, Error **errp) 2505 { 2506 VirtMachineState *vms = VIRT_MACHINE(obj); 2507 2508 return vms->ras; 2509 } 2510 2511 static void virt_set_ras(Object *obj, bool value, Error **errp) 2512 { 2513 VirtMachineState *vms = VIRT_MACHINE(obj); 2514 2515 vms->ras = value; 2516 } 2517 2518 static bool virt_get_mte(Object *obj, Error **errp) 2519 { 2520 VirtMachineState *vms = VIRT_MACHINE(obj); 2521 2522 return vms->mte; 2523 } 2524 2525 static void virt_set_mte(Object *obj, bool value, Error **errp) 2526 { 2527 VirtMachineState *vms = VIRT_MACHINE(obj); 2528 2529 vms->mte = value; 2530 } 2531 2532 static char *virt_get_gic_version(Object *obj, Error **errp) 2533 { 2534 VirtMachineState *vms = VIRT_MACHINE(obj); 2535 const char *val; 2536 2537 switch (vms->gic_version) { 2538 case VIRT_GIC_VERSION_4: 2539 val = "4"; 2540 break; 2541 case VIRT_GIC_VERSION_3: 2542 val = "3"; 2543 break; 2544 default: 2545 val = "2"; 2546 break; 2547 } 2548 return g_strdup(val); 2549 } 2550 2551 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2552 { 2553 VirtMachineState *vms = VIRT_MACHINE(obj); 2554 2555 if (!strcmp(value, "4")) { 2556 vms->gic_version = VIRT_GIC_VERSION_4; 2557 } else if (!strcmp(value, "3")) { 2558 vms->gic_version = VIRT_GIC_VERSION_3; 2559 } else if (!strcmp(value, "2")) { 2560 vms->gic_version = VIRT_GIC_VERSION_2; 2561 } else if (!strcmp(value, "host")) { 2562 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2563 } else if (!strcmp(value, "max")) { 2564 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2565 } else { 2566 error_setg(errp, "Invalid gic-version value"); 2567 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2568 } 2569 } 2570 2571 static char *virt_get_iommu(Object *obj, Error **errp) 2572 { 2573 VirtMachineState *vms = VIRT_MACHINE(obj); 2574 2575 switch (vms->iommu) { 2576 case VIRT_IOMMU_NONE: 2577 return g_strdup("none"); 2578 case VIRT_IOMMU_SMMUV3: 2579 return g_strdup("smmuv3"); 2580 default: 2581 g_assert_not_reached(); 2582 } 2583 } 2584 2585 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2586 { 2587 VirtMachineState *vms = VIRT_MACHINE(obj); 2588 2589 if (!strcmp(value, "smmuv3")) { 2590 vms->iommu = VIRT_IOMMU_SMMUV3; 2591 } else if (!strcmp(value, "none")) { 2592 vms->iommu = VIRT_IOMMU_NONE; 2593 } else { 2594 error_setg(errp, "Invalid iommu value"); 2595 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2596 } 2597 } 2598 2599 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2600 { 2601 VirtMachineState *vms = VIRT_MACHINE(obj); 2602 2603 return vms->default_bus_bypass_iommu; 2604 } 2605 2606 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2607 Error **errp) 2608 { 2609 VirtMachineState *vms = VIRT_MACHINE(obj); 2610 2611 vms->default_bus_bypass_iommu = value; 2612 } 2613 2614 static CpuInstanceProperties 2615 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2616 { 2617 MachineClass *mc = MACHINE_GET_CLASS(ms); 2618 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2619 2620 assert(cpu_index < possible_cpus->len); 2621 return possible_cpus->cpus[cpu_index].props; 2622 } 2623 2624 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2625 { 2626 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2627 2628 return socket_id % ms->numa_state->num_nodes; 2629 } 2630 2631 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2632 { 2633 int n; 2634 unsigned int max_cpus = ms->smp.max_cpus; 2635 VirtMachineState *vms = VIRT_MACHINE(ms); 2636 MachineClass *mc = MACHINE_GET_CLASS(vms); 2637 2638 if (ms->possible_cpus) { 2639 assert(ms->possible_cpus->len == max_cpus); 2640 return ms->possible_cpus; 2641 } 2642 2643 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2644 sizeof(CPUArchId) * max_cpus); 2645 ms->possible_cpus->len = max_cpus; 2646 for (n = 0; n < ms->possible_cpus->len; n++) { 2647 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2648 ms->possible_cpus->cpus[n].arch_id = 2649 virt_cpu_mp_affinity(vms, n); 2650 2651 assert(!mc->smp_props.dies_supported); 2652 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2653 ms->possible_cpus->cpus[n].props.socket_id = 2654 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2655 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2656 ms->possible_cpus->cpus[n].props.cluster_id = 2657 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2658 ms->possible_cpus->cpus[n].props.has_core_id = true; 2659 ms->possible_cpus->cpus[n].props.core_id = 2660 (n / ms->smp.threads) % ms->smp.cores; 2661 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2662 ms->possible_cpus->cpus[n].props.thread_id = 2663 n % ms->smp.threads; 2664 } 2665 return ms->possible_cpus; 2666 } 2667 2668 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2669 Error **errp) 2670 { 2671 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2672 const MachineState *ms = MACHINE(hotplug_dev); 2673 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2674 2675 if (!vms->acpi_dev) { 2676 error_setg(errp, 2677 "memory hotplug is not enabled: missing acpi-ged device"); 2678 return; 2679 } 2680 2681 if (vms->mte) { 2682 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2683 return; 2684 } 2685 2686 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2687 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2688 return; 2689 } 2690 2691 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2692 } 2693 2694 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2695 DeviceState *dev, Error **errp) 2696 { 2697 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2698 MachineState *ms = MACHINE(hotplug_dev); 2699 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2700 2701 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2702 2703 if (is_nvdimm) { 2704 nvdimm_plug(ms->nvdimms_state); 2705 } 2706 2707 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2708 dev, &error_abort); 2709 } 2710 2711 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2712 DeviceState *dev, Error **errp) 2713 { 2714 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2715 2716 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2717 virt_memory_pre_plug(hotplug_dev, dev, errp); 2718 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2719 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2720 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2721 hwaddr db_start = 0, db_end = 0; 2722 QList *reserved_regions; 2723 char *resv_prop_str; 2724 2725 if (vms->iommu != VIRT_IOMMU_NONE) { 2726 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2727 return; 2728 } 2729 2730 switch (vms->msi_controller) { 2731 case VIRT_MSI_CTRL_NONE: 2732 return; 2733 case VIRT_MSI_CTRL_ITS: 2734 /* GITS_TRANSLATER page */ 2735 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2736 db_end = base_memmap[VIRT_GIC_ITS].base + 2737 base_memmap[VIRT_GIC_ITS].size - 1; 2738 break; 2739 case VIRT_MSI_CTRL_GICV2M: 2740 /* MSI_SETSPI_NS page */ 2741 db_start = base_memmap[VIRT_GIC_V2M].base; 2742 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2743 break; 2744 } 2745 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2746 db_start, db_end, 2747 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2748 2749 reserved_regions = qlist_new(); 2750 qlist_append_str(reserved_regions, resv_prop_str); 2751 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2752 g_free(resv_prop_str); 2753 } 2754 } 2755 2756 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2757 DeviceState *dev, Error **errp) 2758 { 2759 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2760 2761 if (vms->platform_bus_dev) { 2762 MachineClass *mc = MACHINE_GET_CLASS(vms); 2763 2764 if (device_is_dynamic_sysbus(mc, dev)) { 2765 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2766 SYS_BUS_DEVICE(dev)); 2767 } 2768 } 2769 2770 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2771 virt_memory_plug(hotplug_dev, dev, errp); 2772 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2773 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2774 } 2775 2776 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2777 PCIDevice *pdev = PCI_DEVICE(dev); 2778 2779 vms->iommu = VIRT_IOMMU_VIRTIO; 2780 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2781 create_virtio_iommu_dt_bindings(vms); 2782 } 2783 } 2784 2785 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2786 DeviceState *dev, Error **errp) 2787 { 2788 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2789 2790 if (!vms->acpi_dev) { 2791 error_setg(errp, 2792 "memory hotplug is not enabled: missing acpi-ged device"); 2793 return; 2794 } 2795 2796 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2797 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2798 return; 2799 } 2800 2801 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2802 errp); 2803 } 2804 2805 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2806 DeviceState *dev, Error **errp) 2807 { 2808 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2809 Error *local_err = NULL; 2810 2811 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2812 if (local_err) { 2813 goto out; 2814 } 2815 2816 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2817 qdev_unrealize(dev); 2818 2819 out: 2820 error_propagate(errp, local_err); 2821 } 2822 2823 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2824 DeviceState *dev, Error **errp) 2825 { 2826 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2827 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2828 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2829 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2830 errp); 2831 } else { 2832 error_setg(errp, "device unplug request for unsupported device" 2833 " type: %s", object_get_typename(OBJECT(dev))); 2834 } 2835 } 2836 2837 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2838 DeviceState *dev, Error **errp) 2839 { 2840 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2841 virt_dimm_unplug(hotplug_dev, dev, errp); 2842 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2843 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2844 } else { 2845 error_setg(errp, "virt: device unplug for unsupported device" 2846 " type: %s", object_get_typename(OBJECT(dev))); 2847 } 2848 } 2849 2850 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2851 DeviceState *dev) 2852 { 2853 MachineClass *mc = MACHINE_GET_CLASS(machine); 2854 2855 if (device_is_dynamic_sysbus(mc, dev) || 2856 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2857 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2858 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2859 return HOTPLUG_HANDLER(machine); 2860 } 2861 return NULL; 2862 } 2863 2864 /* 2865 * for arm64 kvm_type [7-0] encodes the requested number of bits 2866 * in the IPA address space 2867 */ 2868 static int virt_kvm_type(MachineState *ms, const char *type_str) 2869 { 2870 VirtMachineState *vms = VIRT_MACHINE(ms); 2871 int max_vm_pa_size, requested_pa_size; 2872 bool fixed_ipa; 2873 2874 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2875 2876 /* we freeze the memory map to compute the highest gpa */ 2877 virt_set_memmap(vms, max_vm_pa_size); 2878 2879 requested_pa_size = 64 - clz64(vms->highest_gpa); 2880 2881 /* 2882 * KVM requires the IPA size to be at least 32 bits. 2883 */ 2884 if (requested_pa_size < 32) { 2885 requested_pa_size = 32; 2886 } 2887 2888 if (requested_pa_size > max_vm_pa_size) { 2889 error_report("-m and ,maxmem option values " 2890 "require an IPA range (%d bits) larger than " 2891 "the one supported by the host (%d bits)", 2892 requested_pa_size, max_vm_pa_size); 2893 return -1; 2894 } 2895 /* 2896 * We return the requested PA log size, unless KVM only supports 2897 * the implicit legacy 40b IPA setting, in which case the kvm_type 2898 * must be 0. 2899 */ 2900 return fixed_ipa ? 0 : requested_pa_size; 2901 } 2902 2903 static void virt_machine_class_init(ObjectClass *oc, void *data) 2904 { 2905 MachineClass *mc = MACHINE_CLASS(oc); 2906 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2907 static const char * const valid_cpu_types[] = { 2908 #ifdef CONFIG_TCG 2909 ARM_CPU_TYPE_NAME("cortex-a7"), 2910 ARM_CPU_TYPE_NAME("cortex-a15"), 2911 #ifdef TARGET_AARCH64 2912 ARM_CPU_TYPE_NAME("cortex-a35"), 2913 ARM_CPU_TYPE_NAME("cortex-a55"), 2914 ARM_CPU_TYPE_NAME("cortex-a72"), 2915 ARM_CPU_TYPE_NAME("cortex-a76"), 2916 ARM_CPU_TYPE_NAME("cortex-a710"), 2917 ARM_CPU_TYPE_NAME("a64fx"), 2918 ARM_CPU_TYPE_NAME("neoverse-n1"), 2919 ARM_CPU_TYPE_NAME("neoverse-v1"), 2920 ARM_CPU_TYPE_NAME("neoverse-n2"), 2921 #endif /* TARGET_AARCH64 */ 2922 #endif /* CONFIG_TCG */ 2923 #ifdef TARGET_AARCH64 2924 ARM_CPU_TYPE_NAME("cortex-a53"), 2925 ARM_CPU_TYPE_NAME("cortex-a57"), 2926 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 2927 ARM_CPU_TYPE_NAME("host"), 2928 #endif /* CONFIG_KVM || CONFIG_HVF */ 2929 #endif /* TARGET_AARCH64 */ 2930 ARM_CPU_TYPE_NAME("max"), 2931 NULL 2932 }; 2933 2934 mc->init = machvirt_init; 2935 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2936 * The value may be reduced later when we have more information about the 2937 * configuration of the particular instance. 2938 */ 2939 mc->max_cpus = 512; 2940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2943 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2944 #ifdef CONFIG_TPM 2945 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2946 #endif 2947 mc->block_default_type = IF_VIRTIO; 2948 mc->no_cdrom = 1; 2949 mc->pci_allow_0_address = true; 2950 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2951 mc->minimum_page_bits = 12; 2952 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2953 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2954 #ifdef CONFIG_TCG 2955 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2956 #else 2957 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2958 #endif 2959 mc->valid_cpu_types = valid_cpu_types; 2960 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2961 mc->kvm_type = virt_kvm_type; 2962 assert(!mc->get_hotplug_handler); 2963 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2964 hc->pre_plug = virt_machine_device_pre_plug_cb; 2965 hc->plug = virt_machine_device_plug_cb; 2966 hc->unplug_request = virt_machine_device_unplug_request_cb; 2967 hc->unplug = virt_machine_device_unplug_cb; 2968 mc->nvdimm_supported = true; 2969 mc->smp_props.clusters_supported = true; 2970 mc->auto_enable_numa_with_memhp = true; 2971 mc->auto_enable_numa_with_memdev = true; 2972 /* platform instead of architectural choice */ 2973 mc->cpu_cluster_has_numa_boundary = true; 2974 mc->default_ram_id = "mach-virt.ram"; 2975 mc->default_nic = "virtio-net-pci"; 2976 2977 object_class_property_add(oc, "acpi", "OnOffAuto", 2978 virt_get_acpi, virt_set_acpi, 2979 NULL, NULL); 2980 object_class_property_set_description(oc, "acpi", 2981 "Enable ACPI"); 2982 object_class_property_add_bool(oc, "secure", virt_get_secure, 2983 virt_set_secure); 2984 object_class_property_set_description(oc, "secure", 2985 "Set on/off to enable/disable the ARM " 2986 "Security Extensions (TrustZone)"); 2987 2988 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2989 virt_set_virt); 2990 object_class_property_set_description(oc, "virtualization", 2991 "Set on/off to enable/disable emulating a " 2992 "guest CPU which implements the ARM " 2993 "Virtualization Extensions"); 2994 2995 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2996 virt_set_highmem); 2997 object_class_property_set_description(oc, "highmem", 2998 "Set on/off to enable/disable using " 2999 "physical address space above 32 bits"); 3000 3001 object_class_property_add_bool(oc, "compact-highmem", 3002 virt_get_compact_highmem, 3003 virt_set_compact_highmem); 3004 object_class_property_set_description(oc, "compact-highmem", 3005 "Set on/off to enable/disable compact " 3006 "layout for high memory regions"); 3007 3008 object_class_property_add_bool(oc, "highmem-redists", 3009 virt_get_highmem_redists, 3010 virt_set_highmem_redists); 3011 object_class_property_set_description(oc, "highmem-redists", 3012 "Set on/off to enable/disable high " 3013 "memory region for GICv3 or GICv4 " 3014 "redistributor"); 3015 3016 object_class_property_add_bool(oc, "highmem-ecam", 3017 virt_get_highmem_ecam, 3018 virt_set_highmem_ecam); 3019 object_class_property_set_description(oc, "highmem-ecam", 3020 "Set on/off to enable/disable high " 3021 "memory region for PCI ECAM"); 3022 3023 object_class_property_add_bool(oc, "highmem-mmio", 3024 virt_get_highmem_mmio, 3025 virt_set_highmem_mmio); 3026 object_class_property_set_description(oc, "highmem-mmio", 3027 "Set on/off to enable/disable high " 3028 "memory region for PCI MMIO"); 3029 3030 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3031 virt_set_gic_version); 3032 object_class_property_set_description(oc, "gic-version", 3033 "Set GIC version. " 3034 "Valid values are 2, 3, 4, host and max"); 3035 3036 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3037 object_class_property_set_description(oc, "iommu", 3038 "Set the IOMMU type. " 3039 "Valid values are none and smmuv3"); 3040 3041 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3042 virt_get_default_bus_bypass_iommu, 3043 virt_set_default_bus_bypass_iommu); 3044 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3045 "Set on/off to enable/disable " 3046 "bypass_iommu for default root bus"); 3047 3048 object_class_property_add_bool(oc, "ras", virt_get_ras, 3049 virt_set_ras); 3050 object_class_property_set_description(oc, "ras", 3051 "Set on/off to enable/disable reporting host memory errors " 3052 "to a KVM guest using ACPI and guest external abort exceptions"); 3053 3054 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3055 object_class_property_set_description(oc, "mte", 3056 "Set on/off to enable/disable emulating a " 3057 "guest CPU which implements the ARM " 3058 "Memory Tagging Extension"); 3059 3060 object_class_property_add_bool(oc, "its", virt_get_its, 3061 virt_set_its); 3062 object_class_property_set_description(oc, "its", 3063 "Set on/off to enable/disable " 3064 "ITS instantiation"); 3065 3066 object_class_property_add_bool(oc, "dtb-randomness", 3067 virt_get_dtb_randomness, 3068 virt_set_dtb_randomness); 3069 object_class_property_set_description(oc, "dtb-randomness", 3070 "Set off to disable passing random or " 3071 "non-deterministic dtb nodes to guest"); 3072 3073 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3074 virt_get_dtb_randomness, 3075 virt_set_dtb_randomness); 3076 object_class_property_set_description(oc, "dtb-kaslr-seed", 3077 "Deprecated synonym of dtb-randomness"); 3078 3079 object_class_property_add_str(oc, "x-oem-id", 3080 virt_get_oem_id, 3081 virt_set_oem_id); 3082 object_class_property_set_description(oc, "x-oem-id", 3083 "Override the default value of field OEMID " 3084 "in ACPI table header." 3085 "The string may be up to 6 bytes in size"); 3086 3087 3088 object_class_property_add_str(oc, "x-oem-table-id", 3089 virt_get_oem_table_id, 3090 virt_set_oem_table_id); 3091 object_class_property_set_description(oc, "x-oem-table-id", 3092 "Override the default value of field OEM Table ID " 3093 "in ACPI table header." 3094 "The string may be up to 8 bytes in size"); 3095 3096 } 3097 3098 static void virt_instance_init(Object *obj) 3099 { 3100 VirtMachineState *vms = VIRT_MACHINE(obj); 3101 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3102 3103 /* EL3 is disabled by default on virt: this makes us consistent 3104 * between KVM and TCG for this board, and it also allows us to 3105 * boot UEFI blobs which assume no TrustZone support. 3106 */ 3107 vms->secure = false; 3108 3109 /* EL2 is also disabled by default, for similar reasons */ 3110 vms->virt = false; 3111 3112 /* High memory is enabled by default */ 3113 vms->highmem = true; 3114 vms->highmem_compact = !vmc->no_highmem_compact; 3115 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3116 3117 vms->highmem_ecam = !vmc->no_highmem_ecam; 3118 vms->highmem_mmio = true; 3119 vms->highmem_redists = true; 3120 3121 if (vmc->no_its) { 3122 vms->its = false; 3123 } else { 3124 /* Default allows ITS instantiation */ 3125 vms->its = true; 3126 3127 if (vmc->no_tcg_its) { 3128 vms->tcg_its = false; 3129 } else { 3130 vms->tcg_its = true; 3131 } 3132 } 3133 3134 /* Default disallows iommu instantiation */ 3135 vms->iommu = VIRT_IOMMU_NONE; 3136 3137 /* The default root bus is attached to iommu by default */ 3138 vms->default_bus_bypass_iommu = false; 3139 3140 /* Default disallows RAS instantiation */ 3141 vms->ras = false; 3142 3143 /* MTE is disabled by default. */ 3144 vms->mte = false; 3145 3146 /* Supply kaslr-seed and rng-seed by default */ 3147 vms->dtb_randomness = true; 3148 3149 vms->irqmap = a15irqmap; 3150 3151 virt_flash_create(vms); 3152 3153 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3154 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3155 } 3156 3157 static const TypeInfo virt_machine_info = { 3158 .name = TYPE_VIRT_MACHINE, 3159 .parent = TYPE_MACHINE, 3160 .abstract = true, 3161 .instance_size = sizeof(VirtMachineState), 3162 .class_size = sizeof(VirtMachineClass), 3163 .class_init = virt_machine_class_init, 3164 .instance_init = virt_instance_init, 3165 .interfaces = (InterfaceInfo[]) { 3166 { TYPE_HOTPLUG_HANDLER }, 3167 { } 3168 }, 3169 }; 3170 3171 static void machvirt_machine_init(void) 3172 { 3173 type_register_static(&virt_machine_info); 3174 } 3175 type_init(machvirt_machine_init); 3176 3177 static void virt_machine_9_0_options(MachineClass *mc) 3178 { 3179 } 3180 DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) 3181 3182 static void virt_machine_8_2_options(MachineClass *mc) 3183 { 3184 virt_machine_9_0_options(mc); 3185 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3186 } 3187 DEFINE_VIRT_MACHINE(8, 2) 3188 3189 static void virt_machine_8_1_options(MachineClass *mc) 3190 { 3191 virt_machine_8_2_options(mc); 3192 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3193 } 3194 DEFINE_VIRT_MACHINE(8, 1) 3195 3196 static void virt_machine_8_0_options(MachineClass *mc) 3197 { 3198 virt_machine_8_1_options(mc); 3199 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3200 } 3201 DEFINE_VIRT_MACHINE(8, 0) 3202 3203 static void virt_machine_7_2_options(MachineClass *mc) 3204 { 3205 virt_machine_8_0_options(mc); 3206 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3207 } 3208 DEFINE_VIRT_MACHINE(7, 2) 3209 3210 static void virt_machine_7_1_options(MachineClass *mc) 3211 { 3212 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3213 3214 virt_machine_7_2_options(mc); 3215 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3216 /* Compact layout for high memory regions was introduced with 7.2 */ 3217 vmc->no_highmem_compact = true; 3218 } 3219 DEFINE_VIRT_MACHINE(7, 1) 3220 3221 static void virt_machine_7_0_options(MachineClass *mc) 3222 { 3223 virt_machine_7_1_options(mc); 3224 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3225 } 3226 DEFINE_VIRT_MACHINE(7, 0) 3227 3228 static void virt_machine_6_2_options(MachineClass *mc) 3229 { 3230 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3231 3232 virt_machine_7_0_options(mc); 3233 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3234 vmc->no_tcg_lpa2 = true; 3235 } 3236 DEFINE_VIRT_MACHINE(6, 2) 3237 3238 static void virt_machine_6_1_options(MachineClass *mc) 3239 { 3240 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3241 3242 virt_machine_6_2_options(mc); 3243 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3244 mc->smp_props.prefer_sockets = true; 3245 vmc->no_cpu_topology = true; 3246 3247 /* qemu ITS was introduced with 6.2 */ 3248 vmc->no_tcg_its = true; 3249 } 3250 DEFINE_VIRT_MACHINE(6, 1) 3251 3252 static void virt_machine_6_0_options(MachineClass *mc) 3253 { 3254 virt_machine_6_1_options(mc); 3255 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3256 } 3257 DEFINE_VIRT_MACHINE(6, 0) 3258 3259 static void virt_machine_5_2_options(MachineClass *mc) 3260 { 3261 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3262 3263 virt_machine_6_0_options(mc); 3264 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3265 vmc->no_secure_gpio = true; 3266 } 3267 DEFINE_VIRT_MACHINE(5, 2) 3268 3269 static void virt_machine_5_1_options(MachineClass *mc) 3270 { 3271 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3272 3273 virt_machine_5_2_options(mc); 3274 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3275 vmc->no_kvm_steal_time = true; 3276 } 3277 DEFINE_VIRT_MACHINE(5, 1) 3278 3279 static void virt_machine_5_0_options(MachineClass *mc) 3280 { 3281 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3282 3283 virt_machine_5_1_options(mc); 3284 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3285 mc->numa_mem_supported = true; 3286 vmc->acpi_expose_flash = true; 3287 mc->auto_enable_numa_with_memdev = false; 3288 } 3289 DEFINE_VIRT_MACHINE(5, 0) 3290 3291 static void virt_machine_4_2_options(MachineClass *mc) 3292 { 3293 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3294 3295 virt_machine_5_0_options(mc); 3296 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3297 vmc->kvm_no_adjvtime = true; 3298 } 3299 DEFINE_VIRT_MACHINE(4, 2) 3300 3301 static void virt_machine_4_1_options(MachineClass *mc) 3302 { 3303 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3304 3305 virt_machine_4_2_options(mc); 3306 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3307 vmc->no_ged = true; 3308 mc->auto_enable_numa_with_memhp = false; 3309 } 3310 DEFINE_VIRT_MACHINE(4, 1) 3311 3312 static void virt_machine_4_0_options(MachineClass *mc) 3313 { 3314 virt_machine_4_1_options(mc); 3315 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3316 } 3317 DEFINE_VIRT_MACHINE(4, 0) 3318 3319 static void virt_machine_3_1_options(MachineClass *mc) 3320 { 3321 virt_machine_4_0_options(mc); 3322 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3323 } 3324 DEFINE_VIRT_MACHINE(3, 1) 3325 3326 static void virt_machine_3_0_options(MachineClass *mc) 3327 { 3328 virt_machine_3_1_options(mc); 3329 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3330 } 3331 DEFINE_VIRT_MACHINE(3, 0) 3332 3333 static void virt_machine_2_12_options(MachineClass *mc) 3334 { 3335 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3336 3337 virt_machine_3_0_options(mc); 3338 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3339 vmc->no_highmem_ecam = true; 3340 mc->max_cpus = 255; 3341 } 3342 DEFINE_VIRT_MACHINE(2, 12) 3343 3344 static void virt_machine_2_11_options(MachineClass *mc) 3345 { 3346 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3347 3348 virt_machine_2_12_options(mc); 3349 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3350 vmc->smbios_old_sys_ver = true; 3351 } 3352 DEFINE_VIRT_MACHINE(2, 11) 3353 3354 static void virt_machine_2_10_options(MachineClass *mc) 3355 { 3356 virt_machine_2_11_options(mc); 3357 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3358 /* before 2.11 we never faulted accesses to bad addresses */ 3359 mc->ignore_memory_transaction_failures = true; 3360 } 3361 DEFINE_VIRT_MACHINE(2, 10) 3362 3363 static void virt_machine_2_9_options(MachineClass *mc) 3364 { 3365 virt_machine_2_10_options(mc); 3366 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3367 } 3368 DEFINE_VIRT_MACHINE(2, 9) 3369 3370 static void virt_machine_2_8_options(MachineClass *mc) 3371 { 3372 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3373 3374 virt_machine_2_9_options(mc); 3375 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3376 /* For 2.8 and earlier we falsely claimed in the DT that 3377 * our timers were edge-triggered, not level-triggered. 3378 */ 3379 vmc->claim_edge_triggered_timers = true; 3380 } 3381 DEFINE_VIRT_MACHINE(2, 8) 3382 3383 static void virt_machine_2_7_options(MachineClass *mc) 3384 { 3385 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3386 3387 virt_machine_2_8_options(mc); 3388 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3389 /* ITS was introduced with 2.8 */ 3390 vmc->no_its = true; 3391 /* Stick with 1K pages for migration compatibility */ 3392 mc->minimum_page_bits = 0; 3393 } 3394 DEFINE_VIRT_MACHINE(2, 7) 3395 3396 static void virt_machine_2_6_options(MachineClass *mc) 3397 { 3398 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3399 3400 virt_machine_2_7_options(mc); 3401 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3402 vmc->disallow_affinity_adjustment = true; 3403 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3404 vmc->no_pmu = true; 3405 } 3406 DEFINE_VIRT_MACHINE(2, 6) 3407