1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/primecell.h" 40 #include "hw/arm/virt.h" 41 #include "hw/block/flash.h" 42 #include "hw/vfio/vfio-calxeda-xgmac.h" 43 #include "hw/vfio/vfio-amd-xgbe.h" 44 #include "hw/display/ramfb.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/tpm.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "hw/loader.h" 53 #include "qapi/error.h" 54 #include "qemu/bitops.h" 55 #include "qemu/error-report.h" 56 #include "qemu/module.h" 57 #include "hw/pci-host/gpex.h" 58 #include "hw/virtio/virtio-pci.h" 59 #include "hw/core/sysbus-fdt.h" 60 #include "hw/platform-bus.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/arm/fdt.h" 63 #include "hw/intc/arm_gic.h" 64 #include "hw/intc/arm_gicv3_common.h" 65 #include "hw/irq.h" 66 #include "kvm_arm.h" 67 #include "hw/firmware/smbios.h" 68 #include "qapi/visitor.h" 69 #include "qapi/qapi-visit-common.h" 70 #include "standard-headers/linux/input.h" 71 #include "hw/arm/smmuv3.h" 72 #include "hw/acpi/acpi.h" 73 #include "target/arm/internals.h" 74 #include "hw/mem/memory-device.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-mem-pci.h" 79 #include "hw/virtio/virtio-iommu.h" 80 #include "hw/char/pl011.h" 81 #include "qemu/guest-random.h" 82 83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 85 void *data) \ 86 { \ 87 MachineClass *mc = MACHINE_CLASS(oc); \ 88 virt_machine_##major##_##minor##_options(mc); \ 89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 90 if (latest) { \ 91 mc->alias = "virt"; \ 92 } \ 93 } \ 94 static const TypeInfo machvirt_##major##_##minor##_info = { \ 95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 96 .parent = TYPE_VIRT_MACHINE, \ 97 .class_init = virt_##major##_##minor##_class_init, \ 98 }; \ 99 static void machvirt_machine_##major##_##minor##_init(void) \ 100 { \ 101 type_register_static(&machvirt_##major##_##minor##_info); \ 102 } \ 103 type_init(machvirt_machine_##major##_##minor##_init); 104 105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 107 #define DEFINE_VIRT_MACHINE(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 109 110 111 /* Number of external interrupt lines to configure the GIC with */ 112 #define NUM_IRQS 256 113 114 #define PLATFORM_BUS_NUM_IRQS 64 115 116 /* Legacy RAM limit in GB (< version 4.0) */ 117 #define LEGACY_RAMLIMIT_GB 255 118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 119 120 /* Addresses and sizes of our components. 121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 122 * 128MB..256MB is used for miscellaneous device I/O. 123 * 256MB..1GB is reserved for possible future PCI support (ie where the 124 * PCI memory window will go if we add a PCI host controller). 125 * 1GB and up is RAM (which may happily spill over into the 126 * high memory region beyond 4GB). 127 * This represents a compromise between how much RAM can be given to 128 * a 32 bit VM and leaving space for expansion and in particular for PCI. 129 * Note that devices should generally be placed at multiples of 0x10000, 130 * to accommodate guests using 64K pages. 131 */ 132 static const MemMapEntry base_memmap[] = { 133 /* Space up to 0x8000000 is reserved for a boot ROM */ 134 [VIRT_FLASH] = { 0, 0x08000000 }, 135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 144 /* This redistributor space allows up to 2*64kB*123 CPUs */ 145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 146 [VIRT_UART] = { 0x09000000, 0x00001000 }, 147 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 149 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 151 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 164 /* Actual RAM size depends on initial RAM and device memory settings */ 165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 166 }; 167 168 /* 169 * Highmem IO Regions: This memory map is floating, located after the RAM. 170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 171 * top of the RAM, so that its base get the same alignment as the size, 172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 174 * Note the extended_memmap is sized so that it eventually also includes the 175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 176 * index of base_memmap). 177 */ 178 static MemMapEntry extended_memmap[] = { 179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 180 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 181 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 182 /* Second PCIe window */ 183 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 184 }; 185 186 static const int a15irqmap[] = { 187 [VIRT_UART] = 1, 188 [VIRT_RTC] = 2, 189 [VIRT_PCIE] = 3, /* ... to 6 */ 190 [VIRT_GPIO] = 7, 191 [VIRT_SECURE_UART] = 8, 192 [VIRT_ACPI_GED] = 9, 193 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 194 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 195 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 196 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 197 }; 198 199 static const char *valid_cpus[] = { 200 ARM_CPU_TYPE_NAME("cortex-a7"), 201 ARM_CPU_TYPE_NAME("cortex-a15"), 202 ARM_CPU_TYPE_NAME("cortex-a35"), 203 ARM_CPU_TYPE_NAME("cortex-a53"), 204 ARM_CPU_TYPE_NAME("cortex-a57"), 205 ARM_CPU_TYPE_NAME("cortex-a72"), 206 ARM_CPU_TYPE_NAME("cortex-a76"), 207 ARM_CPU_TYPE_NAME("a64fx"), 208 ARM_CPU_TYPE_NAME("neoverse-n1"), 209 ARM_CPU_TYPE_NAME("host"), 210 ARM_CPU_TYPE_NAME("max"), 211 }; 212 213 static bool cpu_type_valid(const char *cpu) 214 { 215 int i; 216 217 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 218 if (strcmp(cpu, valid_cpus[i]) == 0) { 219 return true; 220 } 221 } 222 return false; 223 } 224 225 static void create_randomness(MachineState *ms, const char *node) 226 { 227 struct { 228 uint64_t kaslr; 229 uint8_t rng[32]; 230 } seed; 231 232 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 233 return; 234 } 235 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 236 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 237 } 238 239 static void create_fdt(VirtMachineState *vms) 240 { 241 MachineState *ms = MACHINE(vms); 242 int nb_numa_nodes = ms->numa_state->num_nodes; 243 void *fdt = create_device_tree(&vms->fdt_size); 244 245 if (!fdt) { 246 error_report("create_device_tree() failed"); 247 exit(1); 248 } 249 250 ms->fdt = fdt; 251 252 /* Header */ 253 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 254 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 255 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 256 257 /* /chosen must exist for load_dtb to fill in necessary properties later */ 258 qemu_fdt_add_subnode(fdt, "/chosen"); 259 if (vms->dtb_randomness) { 260 create_randomness(ms, "/chosen"); 261 } 262 263 if (vms->secure) { 264 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 265 if (vms->dtb_randomness) { 266 create_randomness(ms, "/secure-chosen"); 267 } 268 } 269 270 /* Clock node, for the benefit of the UART. The kernel device tree 271 * binding documentation claims the PL011 node clock properties are 272 * optional but in practice if you omit them the kernel refuses to 273 * probe for the device. 274 */ 275 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 276 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 277 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 278 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 279 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 280 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 281 "clk24mhz"); 282 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 283 284 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 285 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 286 uint32_t *matrix = g_malloc0(size); 287 int idx, i, j; 288 289 for (i = 0; i < nb_numa_nodes; i++) { 290 for (j = 0; j < nb_numa_nodes; j++) { 291 idx = (i * nb_numa_nodes + j) * 3; 292 matrix[idx + 0] = cpu_to_be32(i); 293 matrix[idx + 1] = cpu_to_be32(j); 294 matrix[idx + 2] = 295 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 296 } 297 } 298 299 qemu_fdt_add_subnode(fdt, "/distance-map"); 300 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 301 "numa-distance-map-v1"); 302 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 303 matrix, size); 304 g_free(matrix); 305 } 306 } 307 308 static void fdt_add_timer_nodes(const VirtMachineState *vms) 309 { 310 /* On real hardware these interrupts are level-triggered. 311 * On KVM they were edge-triggered before host kernel version 4.4, 312 * and level-triggered afterwards. 313 * On emulated QEMU they are level-triggered. 314 * 315 * Getting the DTB info about them wrong is awkward for some 316 * guest kernels: 317 * pre-4.8 ignore the DT and leave the interrupt configured 318 * with whatever the GIC reset value (or the bootloader) left it at 319 * 4.8 before rc6 honour the incorrect data by programming it back 320 * into the GIC, causing problems 321 * 4.8rc6 and later ignore the DT and always write "level triggered" 322 * into the GIC 323 * 324 * For backwards-compatibility, virt-2.8 and earlier will continue 325 * to say these are edge-triggered, but later machines will report 326 * the correct information. 327 */ 328 ARMCPU *armcpu; 329 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 330 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 331 MachineState *ms = MACHINE(vms); 332 333 if (vmc->claim_edge_triggered_timers) { 334 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 335 } 336 337 if (vms->gic_version == VIRT_GIC_VERSION_2) { 338 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 339 GIC_FDT_IRQ_PPI_CPU_WIDTH, 340 (1 << MACHINE(vms)->smp.cpus) - 1); 341 } 342 343 qemu_fdt_add_subnode(ms->fdt, "/timer"); 344 345 armcpu = ARM_CPU(qemu_get_cpu(0)); 346 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 347 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 348 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 349 compat, sizeof(compat)); 350 } else { 351 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 352 "arm,armv7-timer"); 353 } 354 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 355 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 356 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 358 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 359 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 360 } 361 362 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 363 { 364 int cpu; 365 int addr_cells = 1; 366 const MachineState *ms = MACHINE(vms); 367 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 368 int smp_cpus = ms->smp.cpus; 369 370 /* 371 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 372 * On ARM v8 64-bit systems value should be set to 2, 373 * that corresponds to the MPIDR_EL1 register size. 374 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 375 * in the system, #address-cells can be set to 1, since 376 * MPIDR_EL1[63:32] bits are not used for CPUs 377 * identification. 378 * 379 * Here we actually don't know whether our system is 32- or 64-bit one. 380 * The simplest way to go is to examine affinity IDs of all our CPUs. If 381 * at least one of them has Aff3 populated, we set #address-cells to 2. 382 */ 383 for (cpu = 0; cpu < smp_cpus; cpu++) { 384 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 385 386 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 387 addr_cells = 2; 388 break; 389 } 390 } 391 392 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 393 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 394 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 395 396 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 397 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 398 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 399 CPUState *cs = CPU(armcpu); 400 401 qemu_fdt_add_subnode(ms->fdt, nodename); 402 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 403 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 404 armcpu->dtb_compatible); 405 406 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 407 qemu_fdt_setprop_string(ms->fdt, nodename, 408 "enable-method", "psci"); 409 } 410 411 if (addr_cells == 2) { 412 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 413 armcpu->mp_affinity); 414 } else { 415 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 416 armcpu->mp_affinity); 417 } 418 419 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 420 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 421 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 422 } 423 424 if (!vmc->no_cpu_topology) { 425 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 426 qemu_fdt_alloc_phandle(ms->fdt)); 427 } 428 429 g_free(nodename); 430 } 431 432 if (!vmc->no_cpu_topology) { 433 /* 434 * Add vCPU topology description through fdt node cpu-map. 435 * 436 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 437 * In a SMP system, the hierarchy of CPUs can be defined through 438 * four entities that are used to describe the layout of CPUs in 439 * the system: socket/cluster/core/thread. 440 * 441 * A socket node represents the boundary of system physical package 442 * and its child nodes must be one or more cluster nodes. A system 443 * can contain several layers of clustering within a single physical 444 * package and cluster nodes can be contained in parent cluster nodes. 445 * 446 * Note: currently we only support one layer of clustering within 447 * each physical package. 448 */ 449 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 450 451 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 452 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 453 char *map_path; 454 455 if (ms->smp.threads > 1) { 456 map_path = g_strdup_printf( 457 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 458 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 459 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 460 (cpu / ms->smp.threads) % ms->smp.cores, 461 cpu % ms->smp.threads); 462 } else { 463 map_path = g_strdup_printf( 464 "/cpus/cpu-map/socket%d/cluster%d/core%d", 465 cpu / (ms->smp.clusters * ms->smp.cores), 466 (cpu / ms->smp.cores) % ms->smp.clusters, 467 cpu % ms->smp.cores); 468 } 469 qemu_fdt_add_path(ms->fdt, map_path); 470 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 471 472 g_free(map_path); 473 g_free(cpu_path); 474 } 475 } 476 } 477 478 static void fdt_add_its_gic_node(VirtMachineState *vms) 479 { 480 char *nodename; 481 MachineState *ms = MACHINE(vms); 482 483 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 484 nodename = g_strdup_printf("/intc/its@%" PRIx64, 485 vms->memmap[VIRT_GIC_ITS].base); 486 qemu_fdt_add_subnode(ms->fdt, nodename); 487 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 488 "arm,gic-v3-its"); 489 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 490 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 491 2, vms->memmap[VIRT_GIC_ITS].base, 492 2, vms->memmap[VIRT_GIC_ITS].size); 493 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 494 g_free(nodename); 495 } 496 497 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 498 { 499 MachineState *ms = MACHINE(vms); 500 char *nodename; 501 502 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 503 vms->memmap[VIRT_GIC_V2M].base); 504 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 505 qemu_fdt_add_subnode(ms->fdt, nodename); 506 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 507 "arm,gic-v2m-frame"); 508 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 509 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 510 2, vms->memmap[VIRT_GIC_V2M].base, 511 2, vms->memmap[VIRT_GIC_V2M].size); 512 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 513 g_free(nodename); 514 } 515 516 static void fdt_add_gic_node(VirtMachineState *vms) 517 { 518 MachineState *ms = MACHINE(vms); 519 char *nodename; 520 521 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 522 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 523 524 nodename = g_strdup_printf("/intc@%" PRIx64, 525 vms->memmap[VIRT_GIC_DIST].base); 526 qemu_fdt_add_subnode(ms->fdt, nodename); 527 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 528 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 529 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 530 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 531 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 532 if (vms->gic_version != VIRT_GIC_VERSION_2) { 533 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 534 535 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 536 "arm,gic-v3"); 537 538 qemu_fdt_setprop_cell(ms->fdt, nodename, 539 "#redistributor-regions", nb_redist_regions); 540 541 if (nb_redist_regions == 1) { 542 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 543 2, vms->memmap[VIRT_GIC_DIST].base, 544 2, vms->memmap[VIRT_GIC_DIST].size, 545 2, vms->memmap[VIRT_GIC_REDIST].base, 546 2, vms->memmap[VIRT_GIC_REDIST].size); 547 } else { 548 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 549 2, vms->memmap[VIRT_GIC_DIST].base, 550 2, vms->memmap[VIRT_GIC_DIST].size, 551 2, vms->memmap[VIRT_GIC_REDIST].base, 552 2, vms->memmap[VIRT_GIC_REDIST].size, 553 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 554 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 555 } 556 557 if (vms->virt) { 558 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 559 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 560 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 561 } 562 } else { 563 /* 'cortex-a15-gic' means 'GIC v2' */ 564 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 565 "arm,cortex-a15-gic"); 566 if (!vms->virt) { 567 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 568 2, vms->memmap[VIRT_GIC_DIST].base, 569 2, vms->memmap[VIRT_GIC_DIST].size, 570 2, vms->memmap[VIRT_GIC_CPU].base, 571 2, vms->memmap[VIRT_GIC_CPU].size); 572 } else { 573 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 574 2, vms->memmap[VIRT_GIC_DIST].base, 575 2, vms->memmap[VIRT_GIC_DIST].size, 576 2, vms->memmap[VIRT_GIC_CPU].base, 577 2, vms->memmap[VIRT_GIC_CPU].size, 578 2, vms->memmap[VIRT_GIC_HYP].base, 579 2, vms->memmap[VIRT_GIC_HYP].size, 580 2, vms->memmap[VIRT_GIC_VCPU].base, 581 2, vms->memmap[VIRT_GIC_VCPU].size); 582 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 583 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 584 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 585 } 586 } 587 588 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 589 g_free(nodename); 590 } 591 592 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 593 { 594 ARMCPU *armcpu = ARM_CPU(first_cpu); 595 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 596 MachineState *ms = MACHINE(vms); 597 598 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 599 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 600 return; 601 } 602 603 if (vms->gic_version == VIRT_GIC_VERSION_2) { 604 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 605 GIC_FDT_IRQ_PPI_CPU_WIDTH, 606 (1 << MACHINE(vms)->smp.cpus) - 1); 607 } 608 609 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 610 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 611 const char compat[] = "arm,armv8-pmuv3"; 612 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 613 compat, sizeof(compat)); 614 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 615 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 616 } 617 } 618 619 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 620 { 621 DeviceState *dev; 622 MachineState *ms = MACHINE(vms); 623 int irq = vms->irqmap[VIRT_ACPI_GED]; 624 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 625 626 if (ms->ram_slots) { 627 event |= ACPI_GED_MEM_HOTPLUG_EVT; 628 } 629 630 if (ms->nvdimms_state->is_enabled) { 631 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 632 } 633 634 dev = qdev_new(TYPE_ACPI_GED); 635 qdev_prop_set_uint32(dev, "ged-event", event); 636 637 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 638 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 639 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 640 641 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 642 643 return dev; 644 } 645 646 static void create_its(VirtMachineState *vms) 647 { 648 const char *itsclass = its_class_name(); 649 DeviceState *dev; 650 651 if (!strcmp(itsclass, "arm-gicv3-its")) { 652 if (!vms->tcg_its) { 653 itsclass = NULL; 654 } 655 } 656 657 if (!itsclass) { 658 /* Do nothing if not supported */ 659 return; 660 } 661 662 dev = qdev_new(itsclass); 663 664 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 665 &error_abort); 666 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 667 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 668 669 fdt_add_its_gic_node(vms); 670 vms->msi_controller = VIRT_MSI_CTRL_ITS; 671 } 672 673 static void create_v2m(VirtMachineState *vms) 674 { 675 int i; 676 int irq = vms->irqmap[VIRT_GIC_V2M]; 677 DeviceState *dev; 678 679 dev = qdev_new("arm-gicv2m"); 680 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 681 qdev_prop_set_uint32(dev, "base-spi", irq); 682 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 683 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 684 685 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 686 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 687 qdev_get_gpio_in(vms->gic, irq + i)); 688 } 689 690 fdt_add_v2m_gic_node(vms); 691 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 692 } 693 694 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 695 { 696 MachineState *ms = MACHINE(vms); 697 /* We create a standalone GIC */ 698 SysBusDevice *gicbusdev; 699 const char *gictype; 700 int i; 701 unsigned int smp_cpus = ms->smp.cpus; 702 uint32_t nb_redist_regions = 0; 703 int revision; 704 705 if (vms->gic_version == VIRT_GIC_VERSION_2) { 706 gictype = gic_class_name(); 707 } else { 708 gictype = gicv3_class_name(); 709 } 710 711 switch (vms->gic_version) { 712 case VIRT_GIC_VERSION_2: 713 revision = 2; 714 break; 715 case VIRT_GIC_VERSION_3: 716 revision = 3; 717 break; 718 case VIRT_GIC_VERSION_4: 719 revision = 4; 720 break; 721 default: 722 g_assert_not_reached(); 723 } 724 vms->gic = qdev_new(gictype); 725 qdev_prop_set_uint32(vms->gic, "revision", revision); 726 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 727 /* Note that the num-irq property counts both internal and external 728 * interrupts; there are always 32 of the former (mandated by GIC spec). 729 */ 730 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 731 if (!kvm_irqchip_in_kernel()) { 732 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 733 } 734 735 if (vms->gic_version != VIRT_GIC_VERSION_2) { 736 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 737 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 738 739 nb_redist_regions = virt_gicv3_redist_region_count(vms); 740 741 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 742 nb_redist_regions); 743 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 744 745 if (!kvm_irqchip_in_kernel()) { 746 if (vms->tcg_its) { 747 object_property_set_link(OBJECT(vms->gic), "sysmem", 748 OBJECT(mem), &error_fatal); 749 qdev_prop_set_bit(vms->gic, "has-lpi", true); 750 } 751 } 752 753 if (nb_redist_regions == 2) { 754 uint32_t redist1_capacity = 755 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 756 757 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 758 MIN(smp_cpus - redist0_count, redist1_capacity)); 759 } 760 } else { 761 if (!kvm_irqchip_in_kernel()) { 762 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 763 vms->virt); 764 } 765 } 766 gicbusdev = SYS_BUS_DEVICE(vms->gic); 767 sysbus_realize_and_unref(gicbusdev, &error_fatal); 768 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 769 if (vms->gic_version != VIRT_GIC_VERSION_2) { 770 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 771 if (nb_redist_regions == 2) { 772 sysbus_mmio_map(gicbusdev, 2, 773 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 774 } 775 } else { 776 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 777 if (vms->virt) { 778 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 779 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 780 } 781 } 782 783 /* Wire the outputs from each CPU's generic timer and the GICv3 784 * maintenance interrupt signal to the appropriate GIC PPI inputs, 785 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 786 */ 787 for (i = 0; i < smp_cpus; i++) { 788 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 789 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 790 int irq; 791 /* Mapping from the output timer irq lines from the CPU to the 792 * GIC PPI inputs we use for the virt board. 793 */ 794 const int timer_irq[] = { 795 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 796 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 797 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 798 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 799 }; 800 801 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 802 qdev_connect_gpio_out(cpudev, irq, 803 qdev_get_gpio_in(vms->gic, 804 ppibase + timer_irq[irq])); 805 } 806 807 if (vms->gic_version != VIRT_GIC_VERSION_2) { 808 qemu_irq irq = qdev_get_gpio_in(vms->gic, 809 ppibase + ARCH_GIC_MAINT_IRQ); 810 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 811 0, irq); 812 } else if (vms->virt) { 813 qemu_irq irq = qdev_get_gpio_in(vms->gic, 814 ppibase + ARCH_GIC_MAINT_IRQ); 815 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 816 } 817 818 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 819 qdev_get_gpio_in(vms->gic, ppibase 820 + VIRTUAL_PMU_IRQ)); 821 822 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 823 sysbus_connect_irq(gicbusdev, i + smp_cpus, 824 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 825 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 826 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 827 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 828 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 829 } 830 831 fdt_add_gic_node(vms); 832 833 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 834 create_its(vms); 835 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 836 create_v2m(vms); 837 } 838 } 839 840 static void create_uart(const VirtMachineState *vms, int uart, 841 MemoryRegion *mem, Chardev *chr) 842 { 843 char *nodename; 844 hwaddr base = vms->memmap[uart].base; 845 hwaddr size = vms->memmap[uart].size; 846 int irq = vms->irqmap[uart]; 847 const char compat[] = "arm,pl011\0arm,primecell"; 848 const char clocknames[] = "uartclk\0apb_pclk"; 849 DeviceState *dev = qdev_new(TYPE_PL011); 850 SysBusDevice *s = SYS_BUS_DEVICE(dev); 851 MachineState *ms = MACHINE(vms); 852 853 qdev_prop_set_chr(dev, "chardev", chr); 854 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 855 memory_region_add_subregion(mem, base, 856 sysbus_mmio_get_region(s, 0)); 857 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 858 859 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 860 qemu_fdt_add_subnode(ms->fdt, nodename); 861 /* Note that we can't use setprop_string because of the embedded NUL */ 862 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 863 compat, sizeof(compat)); 864 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 865 2, base, 2, size); 866 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 867 GIC_FDT_IRQ_TYPE_SPI, irq, 868 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 869 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 870 vms->clock_phandle, vms->clock_phandle); 871 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 872 clocknames, sizeof(clocknames)); 873 874 if (uart == VIRT_UART) { 875 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 876 } else { 877 /* Mark as not usable by the normal world */ 878 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 879 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 880 881 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 882 nodename); 883 } 884 885 g_free(nodename); 886 } 887 888 static void create_rtc(const VirtMachineState *vms) 889 { 890 char *nodename; 891 hwaddr base = vms->memmap[VIRT_RTC].base; 892 hwaddr size = vms->memmap[VIRT_RTC].size; 893 int irq = vms->irqmap[VIRT_RTC]; 894 const char compat[] = "arm,pl031\0arm,primecell"; 895 MachineState *ms = MACHINE(vms); 896 897 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 898 899 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 900 qemu_fdt_add_subnode(ms->fdt, nodename); 901 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 902 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 903 2, base, 2, size); 904 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 905 GIC_FDT_IRQ_TYPE_SPI, irq, 906 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 907 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 908 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 909 g_free(nodename); 910 } 911 912 static DeviceState *gpio_key_dev; 913 static void virt_powerdown_req(Notifier *n, void *opaque) 914 { 915 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 916 917 if (s->acpi_dev) { 918 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 919 } else { 920 /* use gpio Pin 3 for power button event */ 921 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 922 } 923 } 924 925 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 926 uint32_t phandle) 927 { 928 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 929 qdev_get_gpio_in(pl061_dev, 3)); 930 931 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 932 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 933 934 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 935 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 936 "label", "GPIO Key Poweroff"); 937 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 938 KEY_POWER); 939 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 940 "gpios", phandle, 3, 0); 941 } 942 943 #define SECURE_GPIO_POWEROFF 0 944 #define SECURE_GPIO_RESET 1 945 946 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 947 uint32_t phandle) 948 { 949 DeviceState *gpio_pwr_dev; 950 951 /* gpio-pwr */ 952 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 953 954 /* connect secure pl061 to gpio-pwr */ 955 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 956 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 957 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 958 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 959 960 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 961 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 962 "gpio-poweroff"); 963 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 964 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 965 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 966 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 967 "okay"); 968 969 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 970 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 971 "gpio-restart"); 972 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 973 "gpios", phandle, SECURE_GPIO_RESET, 0); 974 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 975 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 976 "okay"); 977 } 978 979 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 980 MemoryRegion *mem) 981 { 982 char *nodename; 983 DeviceState *pl061_dev; 984 hwaddr base = vms->memmap[gpio].base; 985 hwaddr size = vms->memmap[gpio].size; 986 int irq = vms->irqmap[gpio]; 987 const char compat[] = "arm,pl061\0arm,primecell"; 988 SysBusDevice *s; 989 MachineState *ms = MACHINE(vms); 990 991 pl061_dev = qdev_new("pl061"); 992 /* Pull lines down to 0 if not driven by the PL061 */ 993 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 994 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 995 s = SYS_BUS_DEVICE(pl061_dev); 996 sysbus_realize_and_unref(s, &error_fatal); 997 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 998 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 999 1000 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1001 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1002 qemu_fdt_add_subnode(ms->fdt, nodename); 1003 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1004 2, base, 2, size); 1005 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1007 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1008 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1009 GIC_FDT_IRQ_TYPE_SPI, irq, 1010 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1011 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1012 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1013 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1014 1015 if (gpio != VIRT_GPIO) { 1016 /* Mark as not usable by the normal world */ 1017 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1018 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1019 } 1020 g_free(nodename); 1021 1022 /* Child gpio devices */ 1023 if (gpio == VIRT_GPIO) { 1024 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1025 } else { 1026 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1027 } 1028 } 1029 1030 static void create_virtio_devices(const VirtMachineState *vms) 1031 { 1032 int i; 1033 hwaddr size = vms->memmap[VIRT_MMIO].size; 1034 MachineState *ms = MACHINE(vms); 1035 1036 /* We create the transports in forwards order. Since qbus_realize() 1037 * prepends (not appends) new child buses, the incrementing loop below will 1038 * create a list of virtio-mmio buses with decreasing base addresses. 1039 * 1040 * When a -device option is processed from the command line, 1041 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1042 * order. The upshot is that -device options in increasing command line 1043 * order are mapped to virtio-mmio buses with decreasing base addresses. 1044 * 1045 * When this code was originally written, that arrangement ensured that the 1046 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1047 * the first -device on the command line. (The end-to-end order is a 1048 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1049 * guest kernel's name-to-address assignment strategy.) 1050 * 1051 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1052 * the message, if not necessarily the code, of commit 70161ff336. 1053 * Therefore the loop now establishes the inverse of the original intent. 1054 * 1055 * Unfortunately, we can't counteract the kernel change by reversing the 1056 * loop; it would break existing command lines. 1057 * 1058 * In any case, the kernel makes no guarantee about the stability of 1059 * enumeration order of virtio devices (as demonstrated by it changing 1060 * between kernel versions). For reliable and stable identification 1061 * of disks users must use UUIDs or similar mechanisms. 1062 */ 1063 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1064 int irq = vms->irqmap[VIRT_MMIO] + i; 1065 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1066 1067 sysbus_create_simple("virtio-mmio", base, 1068 qdev_get_gpio_in(vms->gic, irq)); 1069 } 1070 1071 /* We add dtb nodes in reverse order so that they appear in the finished 1072 * device tree lowest address first. 1073 * 1074 * Note that this mapping is independent of the loop above. The previous 1075 * loop influences virtio device to virtio transport assignment, whereas 1076 * this loop controls how virtio transports are laid out in the dtb. 1077 */ 1078 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1079 char *nodename; 1080 int irq = vms->irqmap[VIRT_MMIO] + i; 1081 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1082 1083 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1084 qemu_fdt_add_subnode(ms->fdt, nodename); 1085 qemu_fdt_setprop_string(ms->fdt, nodename, 1086 "compatible", "virtio,mmio"); 1087 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1088 2, base, 2, size); 1089 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1090 GIC_FDT_IRQ_TYPE_SPI, irq, 1091 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1092 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1093 g_free(nodename); 1094 } 1095 } 1096 1097 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1098 1099 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1100 const char *name, 1101 const char *alias_prop_name) 1102 { 1103 /* 1104 * Create a single flash device. We use the same parameters as 1105 * the flash devices on the Versatile Express board. 1106 */ 1107 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1108 1109 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1110 qdev_prop_set_uint8(dev, "width", 4); 1111 qdev_prop_set_uint8(dev, "device-width", 2); 1112 qdev_prop_set_bit(dev, "big-endian", false); 1113 qdev_prop_set_uint16(dev, "id0", 0x89); 1114 qdev_prop_set_uint16(dev, "id1", 0x18); 1115 qdev_prop_set_uint16(dev, "id2", 0x00); 1116 qdev_prop_set_uint16(dev, "id3", 0x00); 1117 qdev_prop_set_string(dev, "name", name); 1118 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1119 object_property_add_alias(OBJECT(vms), alias_prop_name, 1120 OBJECT(dev), "drive"); 1121 return PFLASH_CFI01(dev); 1122 } 1123 1124 static void virt_flash_create(VirtMachineState *vms) 1125 { 1126 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1127 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1128 } 1129 1130 static void virt_flash_map1(PFlashCFI01 *flash, 1131 hwaddr base, hwaddr size, 1132 MemoryRegion *sysmem) 1133 { 1134 DeviceState *dev = DEVICE(flash); 1135 1136 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1137 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1138 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1139 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1140 1141 memory_region_add_subregion(sysmem, base, 1142 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1143 0)); 1144 } 1145 1146 static void virt_flash_map(VirtMachineState *vms, 1147 MemoryRegion *sysmem, 1148 MemoryRegion *secure_sysmem) 1149 { 1150 /* 1151 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1152 * sysmem is the system memory space. secure_sysmem is the secure view 1153 * of the system, and the first flash device should be made visible only 1154 * there. The second flash device is visible to both secure and nonsecure. 1155 * If sysmem == secure_sysmem this means there is no separate Secure 1156 * address space and both flash devices are generally visible. 1157 */ 1158 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1159 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1160 1161 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1162 secure_sysmem); 1163 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1164 sysmem); 1165 } 1166 1167 static void virt_flash_fdt(VirtMachineState *vms, 1168 MemoryRegion *sysmem, 1169 MemoryRegion *secure_sysmem) 1170 { 1171 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1172 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1173 MachineState *ms = MACHINE(vms); 1174 char *nodename; 1175 1176 if (sysmem == secure_sysmem) { 1177 /* Report both flash devices as a single node in the DT */ 1178 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1179 qemu_fdt_add_subnode(ms->fdt, nodename); 1180 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1181 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1182 2, flashbase, 2, flashsize, 1183 2, flashbase + flashsize, 2, flashsize); 1184 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1185 g_free(nodename); 1186 } else { 1187 /* 1188 * Report the devices as separate nodes so we can mark one as 1189 * only visible to the secure world. 1190 */ 1191 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1192 qemu_fdt_add_subnode(ms->fdt, nodename); 1193 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1194 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1195 2, flashbase, 2, flashsize); 1196 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1197 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1198 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1199 g_free(nodename); 1200 1201 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1202 qemu_fdt_add_subnode(ms->fdt, nodename); 1203 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1204 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1205 2, flashbase + flashsize, 2, flashsize); 1206 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1207 g_free(nodename); 1208 } 1209 } 1210 1211 static bool virt_firmware_init(VirtMachineState *vms, 1212 MemoryRegion *sysmem, 1213 MemoryRegion *secure_sysmem) 1214 { 1215 int i; 1216 const char *bios_name; 1217 BlockBackend *pflash_blk0; 1218 1219 /* Map legacy -drive if=pflash to machine properties */ 1220 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1221 pflash_cfi01_legacy_drive(vms->flash[i], 1222 drive_get(IF_PFLASH, 0, i)); 1223 } 1224 1225 virt_flash_map(vms, sysmem, secure_sysmem); 1226 1227 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1228 1229 bios_name = MACHINE(vms)->firmware; 1230 if (bios_name) { 1231 char *fname; 1232 MemoryRegion *mr; 1233 int image_size; 1234 1235 if (pflash_blk0) { 1236 error_report("The contents of the first flash device may be " 1237 "specified with -bios or with -drive if=pflash... " 1238 "but you cannot use both options at once"); 1239 exit(1); 1240 } 1241 1242 /* Fall back to -bios */ 1243 1244 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1245 if (!fname) { 1246 error_report("Could not find ROM image '%s'", bios_name); 1247 exit(1); 1248 } 1249 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1250 image_size = load_image_mr(fname, mr); 1251 g_free(fname); 1252 if (image_size < 0) { 1253 error_report("Could not load ROM image '%s'", bios_name); 1254 exit(1); 1255 } 1256 } 1257 1258 return pflash_blk0 || bios_name; 1259 } 1260 1261 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1262 { 1263 MachineState *ms = MACHINE(vms); 1264 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1265 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1266 FWCfgState *fw_cfg; 1267 char *nodename; 1268 1269 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1270 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1271 1272 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1273 qemu_fdt_add_subnode(ms->fdt, nodename); 1274 qemu_fdt_setprop_string(ms->fdt, nodename, 1275 "compatible", "qemu,fw-cfg-mmio"); 1276 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1277 2, base, 2, size); 1278 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1279 g_free(nodename); 1280 return fw_cfg; 1281 } 1282 1283 static void create_pcie_irq_map(const MachineState *ms, 1284 uint32_t gic_phandle, 1285 int first_irq, const char *nodename) 1286 { 1287 int devfn, pin; 1288 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1289 uint32_t *irq_map = full_irq_map; 1290 1291 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1292 for (pin = 0; pin < 4; pin++) { 1293 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1294 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1295 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1296 int i; 1297 1298 uint32_t map[] = { 1299 devfn << 8, 0, 0, /* devfn */ 1300 pin + 1, /* PCI pin */ 1301 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1302 1303 /* Convert map to big endian */ 1304 for (i = 0; i < 10; i++) { 1305 irq_map[i] = cpu_to_be32(map[i]); 1306 } 1307 irq_map += 10; 1308 } 1309 } 1310 1311 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1312 full_irq_map, sizeof(full_irq_map)); 1313 1314 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1315 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1316 0, 0, 1317 0x7 /* PCI irq */); 1318 } 1319 1320 static void create_smmu(const VirtMachineState *vms, 1321 PCIBus *bus) 1322 { 1323 char *node; 1324 const char compat[] = "arm,smmu-v3"; 1325 int irq = vms->irqmap[VIRT_SMMU]; 1326 int i; 1327 hwaddr base = vms->memmap[VIRT_SMMU].base; 1328 hwaddr size = vms->memmap[VIRT_SMMU].size; 1329 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1330 DeviceState *dev; 1331 MachineState *ms = MACHINE(vms); 1332 1333 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1334 return; 1335 } 1336 1337 dev = qdev_new("arm-smmuv3"); 1338 1339 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1340 &error_abort); 1341 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1342 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1343 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1344 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1345 qdev_get_gpio_in(vms->gic, irq + i)); 1346 } 1347 1348 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1349 qemu_fdt_add_subnode(ms->fdt, node); 1350 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1351 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1352 1353 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1354 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1355 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1356 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1357 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1358 1359 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1360 sizeof(irq_names)); 1361 1362 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); 1363 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); 1364 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1365 1366 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1367 1368 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1369 g_free(node); 1370 } 1371 1372 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1373 { 1374 const char compat[] = "virtio,pci-iommu"; 1375 uint16_t bdf = vms->virtio_iommu_bdf; 1376 MachineState *ms = MACHINE(vms); 1377 char *node; 1378 1379 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1380 1381 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1382 qemu_fdt_add_subnode(ms->fdt, node); 1383 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1384 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1385 1, bdf << 8, 1, 0, 1, 0, 1386 1, 0, 1, 0); 1387 1388 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1389 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1390 g_free(node); 1391 1392 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1393 0x0, vms->iommu_phandle, 0x0, bdf, 1394 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1395 } 1396 1397 static void create_pcie(VirtMachineState *vms) 1398 { 1399 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1400 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1401 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1402 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1403 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1404 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1405 hwaddr base_ecam, size_ecam; 1406 hwaddr base = base_mmio; 1407 int nr_pcie_buses; 1408 int irq = vms->irqmap[VIRT_PCIE]; 1409 MemoryRegion *mmio_alias; 1410 MemoryRegion *mmio_reg; 1411 MemoryRegion *ecam_alias; 1412 MemoryRegion *ecam_reg; 1413 DeviceState *dev; 1414 char *nodename; 1415 int i, ecam_id; 1416 PCIHostState *pci; 1417 MachineState *ms = MACHINE(vms); 1418 1419 dev = qdev_new(TYPE_GPEX_HOST); 1420 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1421 1422 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1423 base_ecam = vms->memmap[ecam_id].base; 1424 size_ecam = vms->memmap[ecam_id].size; 1425 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1426 /* Map only the first size_ecam bytes of ECAM space */ 1427 ecam_alias = g_new0(MemoryRegion, 1); 1428 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1429 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1430 ecam_reg, 0, size_ecam); 1431 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1432 1433 /* Map the MMIO window into system address space so as to expose 1434 * the section of PCI MMIO space which starts at the same base address 1435 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1436 * the window). 1437 */ 1438 mmio_alias = g_new0(MemoryRegion, 1); 1439 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1440 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1441 mmio_reg, base_mmio, size_mmio); 1442 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1443 1444 if (vms->highmem_mmio) { 1445 /* Map high MMIO space */ 1446 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1447 1448 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1449 mmio_reg, base_mmio_high, size_mmio_high); 1450 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1451 high_mmio_alias); 1452 } 1453 1454 /* Map IO port space */ 1455 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1456 1457 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1458 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1459 qdev_get_gpio_in(vms->gic, irq + i)); 1460 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1461 } 1462 1463 pci = PCI_HOST_BRIDGE(dev); 1464 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1465 vms->bus = pci->bus; 1466 if (vms->bus) { 1467 for (i = 0; i < nb_nics; i++) { 1468 NICInfo *nd = &nd_table[i]; 1469 1470 if (!nd->model) { 1471 nd->model = g_strdup("virtio"); 1472 } 1473 1474 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1475 } 1476 } 1477 1478 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1479 qemu_fdt_add_subnode(ms->fdt, nodename); 1480 qemu_fdt_setprop_string(ms->fdt, nodename, 1481 "compatible", "pci-host-ecam-generic"); 1482 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1483 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1484 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1485 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1486 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1487 nr_pcie_buses - 1); 1488 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1489 1490 if (vms->msi_phandle) { 1491 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent", 1492 vms->msi_phandle); 1493 } 1494 1495 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1496 2, base_ecam, 2, size_ecam); 1497 1498 if (vms->highmem_mmio) { 1499 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1500 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1501 2, base_pio, 2, size_pio, 1502 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1503 2, base_mmio, 2, size_mmio, 1504 1, FDT_PCI_RANGE_MMIO_64BIT, 1505 2, base_mmio_high, 1506 2, base_mmio_high, 2, size_mmio_high); 1507 } else { 1508 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1509 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1510 2, base_pio, 2, size_pio, 1511 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1512 2, base_mmio, 2, size_mmio); 1513 } 1514 1515 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1516 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1517 1518 if (vms->iommu) { 1519 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1520 1521 switch (vms->iommu) { 1522 case VIRT_IOMMU_SMMUV3: 1523 create_smmu(vms, vms->bus); 1524 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1525 0x0, vms->iommu_phandle, 0x0, 0x10000); 1526 break; 1527 default: 1528 g_assert_not_reached(); 1529 } 1530 } 1531 } 1532 1533 static void create_platform_bus(VirtMachineState *vms) 1534 { 1535 DeviceState *dev; 1536 SysBusDevice *s; 1537 int i; 1538 MemoryRegion *sysmem = get_system_memory(); 1539 1540 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1541 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1542 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1543 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1544 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1545 vms->platform_bus_dev = dev; 1546 1547 s = SYS_BUS_DEVICE(dev); 1548 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1549 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1550 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1551 } 1552 1553 memory_region_add_subregion(sysmem, 1554 vms->memmap[VIRT_PLATFORM_BUS].base, 1555 sysbus_mmio_get_region(s, 0)); 1556 } 1557 1558 static void create_tag_ram(MemoryRegion *tag_sysmem, 1559 hwaddr base, hwaddr size, 1560 const char *name) 1561 { 1562 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1563 1564 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1565 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1566 } 1567 1568 static void create_secure_ram(VirtMachineState *vms, 1569 MemoryRegion *secure_sysmem, 1570 MemoryRegion *secure_tag_sysmem) 1571 { 1572 MemoryRegion *secram = g_new(MemoryRegion, 1); 1573 char *nodename; 1574 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1575 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1576 MachineState *ms = MACHINE(vms); 1577 1578 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1579 &error_fatal); 1580 memory_region_add_subregion(secure_sysmem, base, secram); 1581 1582 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1583 qemu_fdt_add_subnode(ms->fdt, nodename); 1584 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1585 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1586 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1587 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1588 1589 if (secure_tag_sysmem) { 1590 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1591 } 1592 1593 g_free(nodename); 1594 } 1595 1596 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1597 { 1598 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1599 bootinfo); 1600 MachineState *ms = MACHINE(board); 1601 1602 1603 *fdt_size = board->fdt_size; 1604 return ms->fdt; 1605 } 1606 1607 static void virt_build_smbios(VirtMachineState *vms) 1608 { 1609 MachineClass *mc = MACHINE_GET_CLASS(vms); 1610 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1611 uint8_t *smbios_tables, *smbios_anchor; 1612 size_t smbios_tables_len, smbios_anchor_len; 1613 const char *product = "QEMU Virtual Machine"; 1614 1615 if (kvm_enabled()) { 1616 product = "KVM Virtual Machine"; 1617 } 1618 1619 smbios_set_defaults("QEMU", product, 1620 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1621 true, SMBIOS_ENTRY_POINT_TYPE_64); 1622 1623 smbios_get_tables(MACHINE(vms), NULL, 0, 1624 &smbios_tables, &smbios_tables_len, 1625 &smbios_anchor, &smbios_anchor_len, 1626 &error_fatal); 1627 1628 if (smbios_anchor) { 1629 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1630 smbios_tables, smbios_tables_len); 1631 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1632 smbios_anchor, smbios_anchor_len); 1633 } 1634 } 1635 1636 static 1637 void virt_machine_done(Notifier *notifier, void *data) 1638 { 1639 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1640 machine_done); 1641 MachineState *ms = MACHINE(vms); 1642 ARMCPU *cpu = ARM_CPU(first_cpu); 1643 struct arm_boot_info *info = &vms->bootinfo; 1644 AddressSpace *as = arm_boot_address_space(cpu, info); 1645 1646 /* 1647 * If the user provided a dtb, we assume the dynamic sysbus nodes 1648 * already are integrated there. This corresponds to a use case where 1649 * the dynamic sysbus nodes are complex and their generation is not yet 1650 * supported. In that case the user can take charge of the guest dt 1651 * while qemu takes charge of the qom stuff. 1652 */ 1653 if (info->dtb_filename == NULL) { 1654 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1655 vms->memmap[VIRT_PLATFORM_BUS].base, 1656 vms->memmap[VIRT_PLATFORM_BUS].size, 1657 vms->irqmap[VIRT_PLATFORM_BUS]); 1658 } 1659 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1660 exit(1); 1661 } 1662 1663 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1664 1665 virt_acpi_setup(vms); 1666 virt_build_smbios(vms); 1667 } 1668 1669 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1670 { 1671 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1672 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1673 1674 if (!vmc->disallow_affinity_adjustment) { 1675 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1676 * GIC's target-list limitations. 32-bit KVM hosts currently 1677 * always create clusters of 4 CPUs, but that is expected to 1678 * change when they gain support for gicv3. When KVM is enabled 1679 * it will override the changes we make here, therefore our 1680 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1681 * and to improve SGI efficiency. 1682 */ 1683 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1684 clustersz = GIC_TARGETLIST_BITS; 1685 } else { 1686 clustersz = GICV3_TARGETLIST_BITS; 1687 } 1688 } 1689 return arm_cpu_mp_affinity(idx, clustersz); 1690 } 1691 1692 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1693 { 1694 MachineState *ms = MACHINE(vms); 1695 hwaddr base, device_memory_base, device_memory_size, memtop; 1696 int i; 1697 1698 vms->memmap = extended_memmap; 1699 1700 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1701 vms->memmap[i] = base_memmap[i]; 1702 } 1703 1704 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1705 error_report("unsupported number of memory slots: %"PRIu64, 1706 ms->ram_slots); 1707 exit(EXIT_FAILURE); 1708 } 1709 1710 /* 1711 * !highmem is exactly the same as limiting the PA space to 32bit, 1712 * irrespective of the underlying capabilities of the HW. 1713 */ 1714 if (!vms->highmem) { 1715 pa_bits = 32; 1716 } 1717 1718 /* 1719 * We compute the base of the high IO region depending on the 1720 * amount of initial and device memory. The device memory start/size 1721 * is aligned on 1GiB. We never put the high IO region below 256GiB 1722 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1723 * The device region size assumes 1GiB page max alignment per slot. 1724 */ 1725 device_memory_base = 1726 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1727 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1728 1729 /* Base address of the high IO region */ 1730 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1731 if (memtop > BIT_ULL(pa_bits)) { 1732 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1733 pa_bits, memtop - BIT_ULL(pa_bits)); 1734 exit(EXIT_FAILURE); 1735 } 1736 if (base < device_memory_base) { 1737 error_report("maxmem/slots too huge"); 1738 exit(EXIT_FAILURE); 1739 } 1740 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1741 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1742 } 1743 1744 /* We know for sure that at least the memory fits in the PA space */ 1745 vms->highest_gpa = memtop - 1; 1746 1747 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1748 hwaddr size = extended_memmap[i].size; 1749 bool fits; 1750 1751 base = ROUND_UP(base, size); 1752 vms->memmap[i].base = base; 1753 vms->memmap[i].size = size; 1754 1755 /* 1756 * Check each device to see if they fit in the PA space, 1757 * moving highest_gpa as we go. 1758 * 1759 * For each device that doesn't fit, disable it. 1760 */ 1761 fits = (base + size) <= BIT_ULL(pa_bits); 1762 if (fits) { 1763 vms->highest_gpa = base + size - 1; 1764 } 1765 1766 switch (i) { 1767 case VIRT_HIGH_GIC_REDIST2: 1768 vms->highmem_redists &= fits; 1769 break; 1770 case VIRT_HIGH_PCIE_ECAM: 1771 vms->highmem_ecam &= fits; 1772 break; 1773 case VIRT_HIGH_PCIE_MMIO: 1774 vms->highmem_mmio &= fits; 1775 break; 1776 } 1777 1778 base += size; 1779 } 1780 1781 if (device_memory_size > 0) { 1782 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1783 ms->device_memory->base = device_memory_base; 1784 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1785 "device-memory", device_memory_size); 1786 } 1787 } 1788 1789 /* 1790 * finalize_gic_version - Determines the final gic_version 1791 * according to the gic-version property 1792 * 1793 * Default GIC type is v2 1794 */ 1795 static void finalize_gic_version(VirtMachineState *vms) 1796 { 1797 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1798 1799 if (kvm_enabled()) { 1800 int probe_bitmap; 1801 1802 if (!kvm_irqchip_in_kernel()) { 1803 switch (vms->gic_version) { 1804 case VIRT_GIC_VERSION_HOST: 1805 warn_report( 1806 "gic-version=host not relevant with kernel-irqchip=off " 1807 "as only userspace GICv2 is supported. Using v2 ..."); 1808 return; 1809 case VIRT_GIC_VERSION_MAX: 1810 case VIRT_GIC_VERSION_NOSEL: 1811 vms->gic_version = VIRT_GIC_VERSION_2; 1812 return; 1813 case VIRT_GIC_VERSION_2: 1814 return; 1815 case VIRT_GIC_VERSION_3: 1816 error_report( 1817 "gic-version=3 is not supported with kernel-irqchip=off"); 1818 exit(1); 1819 case VIRT_GIC_VERSION_4: 1820 error_report( 1821 "gic-version=4 is not supported with kernel-irqchip=off"); 1822 exit(1); 1823 } 1824 } 1825 1826 probe_bitmap = kvm_arm_vgic_probe(); 1827 if (!probe_bitmap) { 1828 error_report("Unable to determine GIC version supported by host"); 1829 exit(1); 1830 } 1831 1832 switch (vms->gic_version) { 1833 case VIRT_GIC_VERSION_HOST: 1834 case VIRT_GIC_VERSION_MAX: 1835 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1836 vms->gic_version = VIRT_GIC_VERSION_3; 1837 } else { 1838 vms->gic_version = VIRT_GIC_VERSION_2; 1839 } 1840 return; 1841 case VIRT_GIC_VERSION_NOSEL: 1842 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1843 vms->gic_version = VIRT_GIC_VERSION_2; 1844 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1845 /* 1846 * in case the host does not support v2 in-kernel emulation or 1847 * the end-user requested more than 8 VCPUs we now default 1848 * to v3. In any case defaulting to v2 would be broken. 1849 */ 1850 vms->gic_version = VIRT_GIC_VERSION_3; 1851 } else if (max_cpus > GIC_NCPU) { 1852 error_report("host only supports in-kernel GICv2 emulation " 1853 "but more than 8 vcpus are requested"); 1854 exit(1); 1855 } 1856 break; 1857 case VIRT_GIC_VERSION_2: 1858 case VIRT_GIC_VERSION_3: 1859 break; 1860 case VIRT_GIC_VERSION_4: 1861 error_report("gic-version=4 is not supported with KVM"); 1862 exit(1); 1863 } 1864 1865 /* Check chosen version is effectively supported by the host */ 1866 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1867 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1868 error_report("host does not support in-kernel GICv2 emulation"); 1869 exit(1); 1870 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1871 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1872 error_report("host does not support in-kernel GICv3 emulation"); 1873 exit(1); 1874 } 1875 return; 1876 } 1877 1878 /* TCG mode */ 1879 switch (vms->gic_version) { 1880 case VIRT_GIC_VERSION_NOSEL: 1881 vms->gic_version = VIRT_GIC_VERSION_2; 1882 break; 1883 case VIRT_GIC_VERSION_MAX: 1884 if (module_object_class_by_name("arm-gicv3")) { 1885 /* CONFIG_ARM_GICV3_TCG was set */ 1886 if (vms->virt) { 1887 /* GICv4 only makes sense if CPU has EL2 */ 1888 vms->gic_version = VIRT_GIC_VERSION_4; 1889 } else { 1890 vms->gic_version = VIRT_GIC_VERSION_3; 1891 } 1892 } else { 1893 vms->gic_version = VIRT_GIC_VERSION_2; 1894 } 1895 break; 1896 case VIRT_GIC_VERSION_HOST: 1897 error_report("gic-version=host requires KVM"); 1898 exit(1); 1899 case VIRT_GIC_VERSION_4: 1900 if (!vms->virt) { 1901 error_report("gic-version=4 requires virtualization enabled"); 1902 exit(1); 1903 } 1904 break; 1905 case VIRT_GIC_VERSION_2: 1906 case VIRT_GIC_VERSION_3: 1907 break; 1908 } 1909 } 1910 1911 /* 1912 * virt_cpu_post_init() must be called after the CPUs have 1913 * been realized and the GIC has been created. 1914 */ 1915 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1916 { 1917 int max_cpus = MACHINE(vms)->smp.max_cpus; 1918 bool aarch64, pmu, steal_time; 1919 CPUState *cpu; 1920 1921 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1922 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1923 steal_time = object_property_get_bool(OBJECT(first_cpu), 1924 "kvm-steal-time", NULL); 1925 1926 if (kvm_enabled()) { 1927 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1928 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1929 1930 if (steal_time) { 1931 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1932 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1933 1934 /* The memory region size must be a multiple of host page size. */ 1935 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1936 1937 if (pvtime_size > pvtime_reg_size) { 1938 error_report("pvtime requires a %" HWADDR_PRId 1939 " byte memory region for %d CPUs," 1940 " but only %" HWADDR_PRId " has been reserved", 1941 pvtime_size, max_cpus, pvtime_reg_size); 1942 exit(1); 1943 } 1944 1945 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1946 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1947 } 1948 1949 CPU_FOREACH(cpu) { 1950 if (pmu) { 1951 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1952 if (kvm_irqchip_in_kernel()) { 1953 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1954 } 1955 kvm_arm_pmu_init(cpu); 1956 } 1957 if (steal_time) { 1958 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1959 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1960 } 1961 } 1962 } else { 1963 if (aarch64 && vms->highmem) { 1964 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1965 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1966 1967 if (pamax < requested_pa_size) { 1968 error_report("VCPU supports less PA bits (%d) than " 1969 "requested by the memory map (%d)", 1970 pamax, requested_pa_size); 1971 exit(1); 1972 } 1973 } 1974 } 1975 } 1976 1977 static void machvirt_init(MachineState *machine) 1978 { 1979 VirtMachineState *vms = VIRT_MACHINE(machine); 1980 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1981 MachineClass *mc = MACHINE_GET_CLASS(machine); 1982 const CPUArchIdList *possible_cpus; 1983 MemoryRegion *sysmem = get_system_memory(); 1984 MemoryRegion *secure_sysmem = NULL; 1985 MemoryRegion *tag_sysmem = NULL; 1986 MemoryRegion *secure_tag_sysmem = NULL; 1987 int n, virt_max_cpus; 1988 bool firmware_loaded; 1989 bool aarch64 = true; 1990 bool has_ged = !vmc->no_ged; 1991 unsigned int smp_cpus = machine->smp.cpus; 1992 unsigned int max_cpus = machine->smp.max_cpus; 1993 1994 if (!cpu_type_valid(machine->cpu_type)) { 1995 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1996 exit(1); 1997 } 1998 1999 possible_cpus = mc->possible_cpu_arch_ids(machine); 2000 2001 /* 2002 * In accelerated mode, the memory map is computed earlier in kvm_type() 2003 * to create a VM with the right number of IPA bits. 2004 */ 2005 if (!vms->memmap) { 2006 Object *cpuobj; 2007 ARMCPU *armcpu; 2008 int pa_bits; 2009 2010 /* 2011 * Instanciate a temporary CPU object to find out about what 2012 * we are about to deal with. Once this is done, get rid of 2013 * the object. 2014 */ 2015 cpuobj = object_new(possible_cpus->cpus[0].type); 2016 armcpu = ARM_CPU(cpuobj); 2017 2018 pa_bits = arm_pamax(armcpu); 2019 2020 object_unref(cpuobj); 2021 2022 virt_set_memmap(vms, pa_bits); 2023 } 2024 2025 /* We can probe only here because during property set 2026 * KVM is not available yet 2027 */ 2028 finalize_gic_version(vms); 2029 2030 if (vms->secure) { 2031 /* 2032 * The Secure view of the world is the same as the NonSecure, 2033 * but with a few extra devices. Create it as a container region 2034 * containing the system memory at low priority; any secure-only 2035 * devices go in at higher priority and take precedence. 2036 */ 2037 secure_sysmem = g_new(MemoryRegion, 1); 2038 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2039 UINT64_MAX); 2040 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2041 } 2042 2043 firmware_loaded = virt_firmware_init(vms, sysmem, 2044 secure_sysmem ?: sysmem); 2045 2046 /* If we have an EL3 boot ROM then the assumption is that it will 2047 * implement PSCI itself, so disable QEMU's internal implementation 2048 * so it doesn't get in the way. Instead of starting secondary 2049 * CPUs in PSCI powerdown state we will start them all running and 2050 * let the boot ROM sort them out. 2051 * The usual case is that we do use QEMU's PSCI implementation; 2052 * if the guest has EL2 then we will use SMC as the conduit, 2053 * and otherwise we will use HVC (for backwards compatibility and 2054 * because if we're using KVM then we must use HVC). 2055 */ 2056 if (vms->secure && firmware_loaded) { 2057 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2058 } else if (vms->virt) { 2059 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2060 } else { 2061 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2062 } 2063 2064 /* 2065 * The maximum number of CPUs depends on the GIC version, or on how 2066 * many redistributors we can fit into the memory map (which in turn 2067 * depends on whether this is a GICv3 or v4). 2068 */ 2069 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2070 virt_max_cpus = GIC_NCPU; 2071 } else { 2072 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + 2073 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2074 } 2075 2076 if (max_cpus > virt_max_cpus) { 2077 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2078 "supported by machine 'mach-virt' (%d)", 2079 max_cpus, virt_max_cpus); 2080 exit(1); 2081 } 2082 2083 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2084 error_report("mach-virt: %s does not support providing " 2085 "Security extensions (TrustZone) to the guest CPU", 2086 kvm_enabled() ? "KVM" : "HVF"); 2087 exit(1); 2088 } 2089 2090 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2091 error_report("mach-virt: %s does not support providing " 2092 "Virtualization extensions to the guest CPU", 2093 kvm_enabled() ? "KVM" : "HVF"); 2094 exit(1); 2095 } 2096 2097 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2098 error_report("mach-virt: %s does not support providing " 2099 "MTE to the guest CPU", 2100 kvm_enabled() ? "KVM" : "HVF"); 2101 exit(1); 2102 } 2103 2104 create_fdt(vms); 2105 2106 assert(possible_cpus->len == max_cpus); 2107 for (n = 0; n < possible_cpus->len; n++) { 2108 Object *cpuobj; 2109 CPUState *cs; 2110 2111 if (n >= smp_cpus) { 2112 break; 2113 } 2114 2115 cpuobj = object_new(possible_cpus->cpus[n].type); 2116 object_property_set_int(cpuobj, "mp-affinity", 2117 possible_cpus->cpus[n].arch_id, NULL); 2118 2119 cs = CPU(cpuobj); 2120 cs->cpu_index = n; 2121 2122 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2123 &error_fatal); 2124 2125 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2126 2127 if (!vms->secure) { 2128 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2129 } 2130 2131 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2132 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2133 } 2134 2135 if (vmc->kvm_no_adjvtime && 2136 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2137 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2138 } 2139 2140 if (vmc->no_kvm_steal_time && 2141 object_property_find(cpuobj, "kvm-steal-time")) { 2142 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2143 } 2144 2145 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2146 object_property_set_bool(cpuobj, "pmu", false, NULL); 2147 } 2148 2149 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2150 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2151 } 2152 2153 if (object_property_find(cpuobj, "reset-cbar")) { 2154 object_property_set_int(cpuobj, "reset-cbar", 2155 vms->memmap[VIRT_CPUPERIPHS].base, 2156 &error_abort); 2157 } 2158 2159 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2160 &error_abort); 2161 if (vms->secure) { 2162 object_property_set_link(cpuobj, "secure-memory", 2163 OBJECT(secure_sysmem), &error_abort); 2164 } 2165 2166 if (vms->mte) { 2167 /* Create the memory region only once, but link to all cpus. */ 2168 if (!tag_sysmem) { 2169 /* 2170 * The property exists only if MemTag is supported. 2171 * If it is, we must allocate the ram to back that up. 2172 */ 2173 if (!object_property_find(cpuobj, "tag-memory")) { 2174 error_report("MTE requested, but not supported " 2175 "by the guest CPU"); 2176 exit(1); 2177 } 2178 2179 tag_sysmem = g_new(MemoryRegion, 1); 2180 memory_region_init(tag_sysmem, OBJECT(machine), 2181 "tag-memory", UINT64_MAX / 32); 2182 2183 if (vms->secure) { 2184 secure_tag_sysmem = g_new(MemoryRegion, 1); 2185 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2186 "secure-tag-memory", UINT64_MAX / 32); 2187 2188 /* As with ram, secure-tag takes precedence over tag. */ 2189 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2190 tag_sysmem, -1); 2191 } 2192 } 2193 2194 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2195 &error_abort); 2196 if (vms->secure) { 2197 object_property_set_link(cpuobj, "secure-tag-memory", 2198 OBJECT(secure_tag_sysmem), 2199 &error_abort); 2200 } 2201 } 2202 2203 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2204 object_unref(cpuobj); 2205 } 2206 fdt_add_timer_nodes(vms); 2207 fdt_add_cpu_nodes(vms); 2208 2209 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2210 machine->ram); 2211 if (machine->device_memory) { 2212 memory_region_add_subregion(sysmem, machine->device_memory->base, 2213 &machine->device_memory->mr); 2214 } 2215 2216 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2217 2218 create_gic(vms, sysmem); 2219 2220 virt_cpu_post_init(vms, sysmem); 2221 2222 fdt_add_pmu_nodes(vms); 2223 2224 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2225 2226 if (vms->secure) { 2227 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2228 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2229 } 2230 2231 if (tag_sysmem) { 2232 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2233 machine->ram_size, "mach-virt.tag"); 2234 } 2235 2236 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2237 2238 create_rtc(vms); 2239 2240 create_pcie(vms); 2241 2242 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2243 vms->acpi_dev = create_acpi_ged(vms); 2244 } else { 2245 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2246 } 2247 2248 if (vms->secure && !vmc->no_secure_gpio) { 2249 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2250 } 2251 2252 /* connect powerdown request */ 2253 vms->powerdown_notifier.notify = virt_powerdown_req; 2254 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2255 2256 /* Create mmio transports, so the user can create virtio backends 2257 * (which will be automatically plugged in to the transports). If 2258 * no backend is created the transport will just sit harmlessly idle. 2259 */ 2260 create_virtio_devices(vms); 2261 2262 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2263 rom_set_fw(vms->fw_cfg); 2264 2265 create_platform_bus(vms); 2266 2267 if (machine->nvdimms_state->is_enabled) { 2268 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2269 .space_id = AML_AS_SYSTEM_MEMORY, 2270 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2271 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2272 }; 2273 2274 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2275 arm_virt_nvdimm_acpi_dsmio, 2276 vms->fw_cfg, OBJECT(vms)); 2277 } 2278 2279 vms->bootinfo.ram_size = machine->ram_size; 2280 vms->bootinfo.board_id = -1; 2281 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2282 vms->bootinfo.get_dtb = machvirt_dtb; 2283 vms->bootinfo.skip_dtb_autoload = true; 2284 vms->bootinfo.firmware_loaded = firmware_loaded; 2285 vms->bootinfo.psci_conduit = vms->psci_conduit; 2286 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2287 2288 vms->machine_done.notify = virt_machine_done; 2289 qemu_add_machine_init_done_notifier(&vms->machine_done); 2290 } 2291 2292 static bool virt_get_secure(Object *obj, Error **errp) 2293 { 2294 VirtMachineState *vms = VIRT_MACHINE(obj); 2295 2296 return vms->secure; 2297 } 2298 2299 static void virt_set_secure(Object *obj, bool value, Error **errp) 2300 { 2301 VirtMachineState *vms = VIRT_MACHINE(obj); 2302 2303 vms->secure = value; 2304 } 2305 2306 static bool virt_get_virt(Object *obj, Error **errp) 2307 { 2308 VirtMachineState *vms = VIRT_MACHINE(obj); 2309 2310 return vms->virt; 2311 } 2312 2313 static void virt_set_virt(Object *obj, bool value, Error **errp) 2314 { 2315 VirtMachineState *vms = VIRT_MACHINE(obj); 2316 2317 vms->virt = value; 2318 } 2319 2320 static bool virt_get_highmem(Object *obj, Error **errp) 2321 { 2322 VirtMachineState *vms = VIRT_MACHINE(obj); 2323 2324 return vms->highmem; 2325 } 2326 2327 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2328 { 2329 VirtMachineState *vms = VIRT_MACHINE(obj); 2330 2331 vms->highmem = value; 2332 } 2333 2334 static bool virt_get_its(Object *obj, Error **errp) 2335 { 2336 VirtMachineState *vms = VIRT_MACHINE(obj); 2337 2338 return vms->its; 2339 } 2340 2341 static void virt_set_its(Object *obj, bool value, Error **errp) 2342 { 2343 VirtMachineState *vms = VIRT_MACHINE(obj); 2344 2345 vms->its = value; 2346 } 2347 2348 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2349 { 2350 VirtMachineState *vms = VIRT_MACHINE(obj); 2351 2352 return vms->dtb_randomness; 2353 } 2354 2355 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2356 { 2357 VirtMachineState *vms = VIRT_MACHINE(obj); 2358 2359 vms->dtb_randomness = value; 2360 } 2361 2362 static char *virt_get_oem_id(Object *obj, Error **errp) 2363 { 2364 VirtMachineState *vms = VIRT_MACHINE(obj); 2365 2366 return g_strdup(vms->oem_id); 2367 } 2368 2369 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2370 { 2371 VirtMachineState *vms = VIRT_MACHINE(obj); 2372 size_t len = strlen(value); 2373 2374 if (len > 6) { 2375 error_setg(errp, 2376 "User specified oem-id value is bigger than 6 bytes in size"); 2377 return; 2378 } 2379 2380 strncpy(vms->oem_id, value, 6); 2381 } 2382 2383 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2384 { 2385 VirtMachineState *vms = VIRT_MACHINE(obj); 2386 2387 return g_strdup(vms->oem_table_id); 2388 } 2389 2390 static void virt_set_oem_table_id(Object *obj, const char *value, 2391 Error **errp) 2392 { 2393 VirtMachineState *vms = VIRT_MACHINE(obj); 2394 size_t len = strlen(value); 2395 2396 if (len > 8) { 2397 error_setg(errp, 2398 "User specified oem-table-id value is bigger than 8 bytes in size"); 2399 return; 2400 } 2401 strncpy(vms->oem_table_id, value, 8); 2402 } 2403 2404 2405 bool virt_is_acpi_enabled(VirtMachineState *vms) 2406 { 2407 if (vms->acpi == ON_OFF_AUTO_OFF) { 2408 return false; 2409 } 2410 return true; 2411 } 2412 2413 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2414 void *opaque, Error **errp) 2415 { 2416 VirtMachineState *vms = VIRT_MACHINE(obj); 2417 OnOffAuto acpi = vms->acpi; 2418 2419 visit_type_OnOffAuto(v, name, &acpi, errp); 2420 } 2421 2422 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2423 void *opaque, Error **errp) 2424 { 2425 VirtMachineState *vms = VIRT_MACHINE(obj); 2426 2427 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2428 } 2429 2430 static bool virt_get_ras(Object *obj, Error **errp) 2431 { 2432 VirtMachineState *vms = VIRT_MACHINE(obj); 2433 2434 return vms->ras; 2435 } 2436 2437 static void virt_set_ras(Object *obj, bool value, Error **errp) 2438 { 2439 VirtMachineState *vms = VIRT_MACHINE(obj); 2440 2441 vms->ras = value; 2442 } 2443 2444 static bool virt_get_mte(Object *obj, Error **errp) 2445 { 2446 VirtMachineState *vms = VIRT_MACHINE(obj); 2447 2448 return vms->mte; 2449 } 2450 2451 static void virt_set_mte(Object *obj, bool value, Error **errp) 2452 { 2453 VirtMachineState *vms = VIRT_MACHINE(obj); 2454 2455 vms->mte = value; 2456 } 2457 2458 static char *virt_get_gic_version(Object *obj, Error **errp) 2459 { 2460 VirtMachineState *vms = VIRT_MACHINE(obj); 2461 const char *val; 2462 2463 switch (vms->gic_version) { 2464 case VIRT_GIC_VERSION_4: 2465 val = "4"; 2466 break; 2467 case VIRT_GIC_VERSION_3: 2468 val = "3"; 2469 break; 2470 default: 2471 val = "2"; 2472 break; 2473 } 2474 return g_strdup(val); 2475 } 2476 2477 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2478 { 2479 VirtMachineState *vms = VIRT_MACHINE(obj); 2480 2481 if (!strcmp(value, "4")) { 2482 vms->gic_version = VIRT_GIC_VERSION_4; 2483 } else if (!strcmp(value, "3")) { 2484 vms->gic_version = VIRT_GIC_VERSION_3; 2485 } else if (!strcmp(value, "2")) { 2486 vms->gic_version = VIRT_GIC_VERSION_2; 2487 } else if (!strcmp(value, "host")) { 2488 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2489 } else if (!strcmp(value, "max")) { 2490 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2491 } else { 2492 error_setg(errp, "Invalid gic-version value"); 2493 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2494 } 2495 } 2496 2497 static char *virt_get_iommu(Object *obj, Error **errp) 2498 { 2499 VirtMachineState *vms = VIRT_MACHINE(obj); 2500 2501 switch (vms->iommu) { 2502 case VIRT_IOMMU_NONE: 2503 return g_strdup("none"); 2504 case VIRT_IOMMU_SMMUV3: 2505 return g_strdup("smmuv3"); 2506 default: 2507 g_assert_not_reached(); 2508 } 2509 } 2510 2511 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2512 { 2513 VirtMachineState *vms = VIRT_MACHINE(obj); 2514 2515 if (!strcmp(value, "smmuv3")) { 2516 vms->iommu = VIRT_IOMMU_SMMUV3; 2517 } else if (!strcmp(value, "none")) { 2518 vms->iommu = VIRT_IOMMU_NONE; 2519 } else { 2520 error_setg(errp, "Invalid iommu value"); 2521 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2522 } 2523 } 2524 2525 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2526 { 2527 VirtMachineState *vms = VIRT_MACHINE(obj); 2528 2529 return vms->default_bus_bypass_iommu; 2530 } 2531 2532 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2533 Error **errp) 2534 { 2535 VirtMachineState *vms = VIRT_MACHINE(obj); 2536 2537 vms->default_bus_bypass_iommu = value; 2538 } 2539 2540 static CpuInstanceProperties 2541 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2542 { 2543 MachineClass *mc = MACHINE_GET_CLASS(ms); 2544 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2545 2546 assert(cpu_index < possible_cpus->len); 2547 return possible_cpus->cpus[cpu_index].props; 2548 } 2549 2550 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2551 { 2552 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2553 2554 return socket_id % ms->numa_state->num_nodes; 2555 } 2556 2557 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2558 { 2559 int n; 2560 unsigned int max_cpus = ms->smp.max_cpus; 2561 VirtMachineState *vms = VIRT_MACHINE(ms); 2562 MachineClass *mc = MACHINE_GET_CLASS(vms); 2563 2564 if (ms->possible_cpus) { 2565 assert(ms->possible_cpus->len == max_cpus); 2566 return ms->possible_cpus; 2567 } 2568 2569 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2570 sizeof(CPUArchId) * max_cpus); 2571 ms->possible_cpus->len = max_cpus; 2572 for (n = 0; n < ms->possible_cpus->len; n++) { 2573 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2574 ms->possible_cpus->cpus[n].arch_id = 2575 virt_cpu_mp_affinity(vms, n); 2576 2577 assert(!mc->smp_props.dies_supported); 2578 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2579 ms->possible_cpus->cpus[n].props.socket_id = 2580 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2581 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2582 ms->possible_cpus->cpus[n].props.cluster_id = 2583 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2584 ms->possible_cpus->cpus[n].props.has_core_id = true; 2585 ms->possible_cpus->cpus[n].props.core_id = 2586 (n / ms->smp.threads) % ms->smp.cores; 2587 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2588 ms->possible_cpus->cpus[n].props.thread_id = 2589 n % ms->smp.threads; 2590 } 2591 return ms->possible_cpus; 2592 } 2593 2594 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2595 Error **errp) 2596 { 2597 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2598 const MachineState *ms = MACHINE(hotplug_dev); 2599 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2600 2601 if (!vms->acpi_dev) { 2602 error_setg(errp, 2603 "memory hotplug is not enabled: missing acpi-ged device"); 2604 return; 2605 } 2606 2607 if (vms->mte) { 2608 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2609 return; 2610 } 2611 2612 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2613 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2614 return; 2615 } 2616 2617 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2618 } 2619 2620 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2621 DeviceState *dev, Error **errp) 2622 { 2623 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2624 MachineState *ms = MACHINE(hotplug_dev); 2625 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2626 2627 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2628 2629 if (is_nvdimm) { 2630 nvdimm_plug(ms->nvdimms_state); 2631 } 2632 2633 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2634 dev, &error_abort); 2635 } 2636 2637 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2638 DeviceState *dev, Error **errp) 2639 { 2640 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2641 Error *local_err = NULL; 2642 2643 if (!hotplug_dev2 && dev->hotplugged) { 2644 /* 2645 * Without a bus hotplug handler, we cannot control the plug/unplug 2646 * order. We should never reach this point when hotplugging on ARM. 2647 * However, it's nice to add a safety net, similar to what we have 2648 * on x86. 2649 */ 2650 error_setg(errp, "hotplug of virtio based memory devices not supported" 2651 " on this bus."); 2652 return; 2653 } 2654 /* 2655 * First, see if we can plug this memory device at all. If that 2656 * succeeds, branch of to the actual hotplug handler. 2657 */ 2658 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2659 &local_err); 2660 if (!local_err && hotplug_dev2) { 2661 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2662 } 2663 error_propagate(errp, local_err); 2664 } 2665 2666 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2667 DeviceState *dev, Error **errp) 2668 { 2669 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2670 Error *local_err = NULL; 2671 2672 /* 2673 * Plug the memory device first and then branch off to the actual 2674 * hotplug handler. If that one fails, we can easily undo the memory 2675 * device bits. 2676 */ 2677 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2678 if (hotplug_dev2) { 2679 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2680 if (local_err) { 2681 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2682 } 2683 } 2684 error_propagate(errp, local_err); 2685 } 2686 2687 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2688 DeviceState *dev, Error **errp) 2689 { 2690 /* We don't support hot unplug of virtio based memory devices */ 2691 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2692 } 2693 2694 2695 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2696 DeviceState *dev, Error **errp) 2697 { 2698 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2699 2700 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2701 virt_memory_pre_plug(hotplug_dev, dev, errp); 2702 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2703 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2704 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2705 hwaddr db_start = 0, db_end = 0; 2706 char *resv_prop_str; 2707 2708 if (vms->iommu != VIRT_IOMMU_NONE) { 2709 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2710 return; 2711 } 2712 2713 switch (vms->msi_controller) { 2714 case VIRT_MSI_CTRL_NONE: 2715 return; 2716 case VIRT_MSI_CTRL_ITS: 2717 /* GITS_TRANSLATER page */ 2718 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2719 db_end = base_memmap[VIRT_GIC_ITS].base + 2720 base_memmap[VIRT_GIC_ITS].size - 1; 2721 break; 2722 case VIRT_MSI_CTRL_GICV2M: 2723 /* MSI_SETSPI_NS page */ 2724 db_start = base_memmap[VIRT_GIC_V2M].base; 2725 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2726 break; 2727 } 2728 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2729 db_start, db_end, 2730 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2731 2732 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2733 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2734 resv_prop_str, errp); 2735 g_free(resv_prop_str); 2736 } 2737 } 2738 2739 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2740 DeviceState *dev, Error **errp) 2741 { 2742 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2743 2744 if (vms->platform_bus_dev) { 2745 MachineClass *mc = MACHINE_GET_CLASS(vms); 2746 2747 if (device_is_dynamic_sysbus(mc, dev)) { 2748 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2749 SYS_BUS_DEVICE(dev)); 2750 } 2751 } 2752 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2753 virt_memory_plug(hotplug_dev, dev, errp); 2754 } 2755 2756 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2757 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2758 } 2759 2760 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2761 PCIDevice *pdev = PCI_DEVICE(dev); 2762 2763 vms->iommu = VIRT_IOMMU_VIRTIO; 2764 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2765 create_virtio_iommu_dt_bindings(vms); 2766 } 2767 } 2768 2769 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2770 DeviceState *dev, Error **errp) 2771 { 2772 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2773 Error *local_err = NULL; 2774 2775 if (!vms->acpi_dev) { 2776 error_setg(&local_err, 2777 "memory hotplug is not enabled: missing acpi-ged device"); 2778 goto out; 2779 } 2780 2781 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2782 error_setg(&local_err, 2783 "nvdimm device hot unplug is not supported yet."); 2784 goto out; 2785 } 2786 2787 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2788 &local_err); 2789 out: 2790 error_propagate(errp, local_err); 2791 } 2792 2793 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2794 DeviceState *dev, Error **errp) 2795 { 2796 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2797 Error *local_err = NULL; 2798 2799 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2800 if (local_err) { 2801 goto out; 2802 } 2803 2804 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2805 qdev_unrealize(dev); 2806 2807 out: 2808 error_propagate(errp, local_err); 2809 } 2810 2811 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2812 DeviceState *dev, Error **errp) 2813 { 2814 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2815 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2816 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2817 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2818 } else { 2819 error_setg(errp, "device unplug request for unsupported device" 2820 " type: %s", object_get_typename(OBJECT(dev))); 2821 } 2822 } 2823 2824 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2825 DeviceState *dev, Error **errp) 2826 { 2827 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2828 virt_dimm_unplug(hotplug_dev, dev, errp); 2829 } else { 2830 error_setg(errp, "virt: device unplug for unsupported device" 2831 " type: %s", object_get_typename(OBJECT(dev))); 2832 } 2833 } 2834 2835 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2836 DeviceState *dev) 2837 { 2838 MachineClass *mc = MACHINE_GET_CLASS(machine); 2839 2840 if (device_is_dynamic_sysbus(mc, dev) || 2841 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2842 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2843 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2844 return HOTPLUG_HANDLER(machine); 2845 } 2846 return NULL; 2847 } 2848 2849 /* 2850 * for arm64 kvm_type [7-0] encodes the requested number of bits 2851 * in the IPA address space 2852 */ 2853 static int virt_kvm_type(MachineState *ms, const char *type_str) 2854 { 2855 VirtMachineState *vms = VIRT_MACHINE(ms); 2856 int max_vm_pa_size, requested_pa_size; 2857 bool fixed_ipa; 2858 2859 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2860 2861 /* we freeze the memory map to compute the highest gpa */ 2862 virt_set_memmap(vms, max_vm_pa_size); 2863 2864 requested_pa_size = 64 - clz64(vms->highest_gpa); 2865 2866 /* 2867 * KVM requires the IPA size to be at least 32 bits. 2868 */ 2869 if (requested_pa_size < 32) { 2870 requested_pa_size = 32; 2871 } 2872 2873 if (requested_pa_size > max_vm_pa_size) { 2874 error_report("-m and ,maxmem option values " 2875 "require an IPA range (%d bits) larger than " 2876 "the one supported by the host (%d bits)", 2877 requested_pa_size, max_vm_pa_size); 2878 exit(1); 2879 } 2880 /* 2881 * We return the requested PA log size, unless KVM only supports 2882 * the implicit legacy 40b IPA setting, in which case the kvm_type 2883 * must be 0. 2884 */ 2885 return fixed_ipa ? 0 : requested_pa_size; 2886 } 2887 2888 static void virt_machine_class_init(ObjectClass *oc, void *data) 2889 { 2890 MachineClass *mc = MACHINE_CLASS(oc); 2891 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2892 2893 mc->init = machvirt_init; 2894 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2895 * The value may be reduced later when we have more information about the 2896 * configuration of the particular instance. 2897 */ 2898 mc->max_cpus = 512; 2899 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2900 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2901 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2902 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2903 #ifdef CONFIG_TPM 2904 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2905 #endif 2906 mc->block_default_type = IF_VIRTIO; 2907 mc->no_cdrom = 1; 2908 mc->pci_allow_0_address = true; 2909 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2910 mc->minimum_page_bits = 12; 2911 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2912 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2913 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2914 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2915 mc->kvm_type = virt_kvm_type; 2916 assert(!mc->get_hotplug_handler); 2917 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2918 hc->pre_plug = virt_machine_device_pre_plug_cb; 2919 hc->plug = virt_machine_device_plug_cb; 2920 hc->unplug_request = virt_machine_device_unplug_request_cb; 2921 hc->unplug = virt_machine_device_unplug_cb; 2922 mc->nvdimm_supported = true; 2923 mc->smp_props.clusters_supported = true; 2924 mc->auto_enable_numa_with_memhp = true; 2925 mc->auto_enable_numa_with_memdev = true; 2926 mc->default_ram_id = "mach-virt.ram"; 2927 2928 object_class_property_add(oc, "acpi", "OnOffAuto", 2929 virt_get_acpi, virt_set_acpi, 2930 NULL, NULL); 2931 object_class_property_set_description(oc, "acpi", 2932 "Enable ACPI"); 2933 object_class_property_add_bool(oc, "secure", virt_get_secure, 2934 virt_set_secure); 2935 object_class_property_set_description(oc, "secure", 2936 "Set on/off to enable/disable the ARM " 2937 "Security Extensions (TrustZone)"); 2938 2939 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2940 virt_set_virt); 2941 object_class_property_set_description(oc, "virtualization", 2942 "Set on/off to enable/disable emulating a " 2943 "guest CPU which implements the ARM " 2944 "Virtualization Extensions"); 2945 2946 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2947 virt_set_highmem); 2948 object_class_property_set_description(oc, "highmem", 2949 "Set on/off to enable/disable using " 2950 "physical address space above 32 bits"); 2951 2952 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 2953 virt_set_gic_version); 2954 object_class_property_set_description(oc, "gic-version", 2955 "Set GIC version. " 2956 "Valid values are 2, 3, 4, host and max"); 2957 2958 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 2959 object_class_property_set_description(oc, "iommu", 2960 "Set the IOMMU type. " 2961 "Valid values are none and smmuv3"); 2962 2963 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 2964 virt_get_default_bus_bypass_iommu, 2965 virt_set_default_bus_bypass_iommu); 2966 object_class_property_set_description(oc, "default-bus-bypass-iommu", 2967 "Set on/off to enable/disable " 2968 "bypass_iommu for default root bus"); 2969 2970 object_class_property_add_bool(oc, "ras", virt_get_ras, 2971 virt_set_ras); 2972 object_class_property_set_description(oc, "ras", 2973 "Set on/off to enable/disable reporting host memory errors " 2974 "to a KVM guest using ACPI and guest external abort exceptions"); 2975 2976 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 2977 object_class_property_set_description(oc, "mte", 2978 "Set on/off to enable/disable emulating a " 2979 "guest CPU which implements the ARM " 2980 "Memory Tagging Extension"); 2981 2982 object_class_property_add_bool(oc, "its", virt_get_its, 2983 virt_set_its); 2984 object_class_property_set_description(oc, "its", 2985 "Set on/off to enable/disable " 2986 "ITS instantiation"); 2987 2988 object_class_property_add_bool(oc, "dtb-randomness", 2989 virt_get_dtb_randomness, 2990 virt_set_dtb_randomness); 2991 object_class_property_set_description(oc, "dtb-randomness", 2992 "Set off to disable passing random or " 2993 "non-deterministic dtb nodes to guest"); 2994 2995 object_class_property_add_bool(oc, "dtb-kaslr-seed", 2996 virt_get_dtb_randomness, 2997 virt_set_dtb_randomness); 2998 object_class_property_set_description(oc, "dtb-kaslr-seed", 2999 "Deprecated synonym of dtb-randomness"); 3000 3001 object_class_property_add_str(oc, "x-oem-id", 3002 virt_get_oem_id, 3003 virt_set_oem_id); 3004 object_class_property_set_description(oc, "x-oem-id", 3005 "Override the default value of field OEMID " 3006 "in ACPI table header." 3007 "The string may be up to 6 bytes in size"); 3008 3009 3010 object_class_property_add_str(oc, "x-oem-table-id", 3011 virt_get_oem_table_id, 3012 virt_set_oem_table_id); 3013 object_class_property_set_description(oc, "x-oem-table-id", 3014 "Override the default value of field OEM Table ID " 3015 "in ACPI table header." 3016 "The string may be up to 8 bytes in size"); 3017 3018 } 3019 3020 static void virt_instance_init(Object *obj) 3021 { 3022 VirtMachineState *vms = VIRT_MACHINE(obj); 3023 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3024 3025 /* EL3 is disabled by default on virt: this makes us consistent 3026 * between KVM and TCG for this board, and it also allows us to 3027 * boot UEFI blobs which assume no TrustZone support. 3028 */ 3029 vms->secure = false; 3030 3031 /* EL2 is also disabled by default, for similar reasons */ 3032 vms->virt = false; 3033 3034 /* High memory is enabled by default */ 3035 vms->highmem = true; 3036 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3037 3038 vms->highmem_ecam = !vmc->no_highmem_ecam; 3039 vms->highmem_mmio = true; 3040 vms->highmem_redists = true; 3041 3042 if (vmc->no_its) { 3043 vms->its = false; 3044 } else { 3045 /* Default allows ITS instantiation */ 3046 vms->its = true; 3047 3048 if (vmc->no_tcg_its) { 3049 vms->tcg_its = false; 3050 } else { 3051 vms->tcg_its = true; 3052 } 3053 } 3054 3055 /* Default disallows iommu instantiation */ 3056 vms->iommu = VIRT_IOMMU_NONE; 3057 3058 /* The default root bus is attached to iommu by default */ 3059 vms->default_bus_bypass_iommu = false; 3060 3061 /* Default disallows RAS instantiation */ 3062 vms->ras = false; 3063 3064 /* MTE is disabled by default. */ 3065 vms->mte = false; 3066 3067 /* Supply kaslr-seed and rng-seed by default */ 3068 vms->dtb_randomness = true; 3069 3070 vms->irqmap = a15irqmap; 3071 3072 virt_flash_create(vms); 3073 3074 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3075 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3076 } 3077 3078 static const TypeInfo virt_machine_info = { 3079 .name = TYPE_VIRT_MACHINE, 3080 .parent = TYPE_MACHINE, 3081 .abstract = true, 3082 .instance_size = sizeof(VirtMachineState), 3083 .class_size = sizeof(VirtMachineClass), 3084 .class_init = virt_machine_class_init, 3085 .instance_init = virt_instance_init, 3086 .interfaces = (InterfaceInfo[]) { 3087 { TYPE_HOTPLUG_HANDLER }, 3088 { } 3089 }, 3090 }; 3091 3092 static void machvirt_machine_init(void) 3093 { 3094 type_register_static(&virt_machine_info); 3095 } 3096 type_init(machvirt_machine_init); 3097 3098 static void virt_machine_7_2_options(MachineClass *mc) 3099 { 3100 } 3101 DEFINE_VIRT_MACHINE_AS_LATEST(7, 2) 3102 3103 static void virt_machine_7_1_options(MachineClass *mc) 3104 { 3105 virt_machine_7_2_options(mc); 3106 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3107 } 3108 DEFINE_VIRT_MACHINE(7, 1) 3109 3110 static void virt_machine_7_0_options(MachineClass *mc) 3111 { 3112 virt_machine_7_1_options(mc); 3113 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3114 } 3115 DEFINE_VIRT_MACHINE(7, 0) 3116 3117 static void virt_machine_6_2_options(MachineClass *mc) 3118 { 3119 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3120 3121 virt_machine_7_0_options(mc); 3122 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3123 vmc->no_tcg_lpa2 = true; 3124 } 3125 DEFINE_VIRT_MACHINE(6, 2) 3126 3127 static void virt_machine_6_1_options(MachineClass *mc) 3128 { 3129 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3130 3131 virt_machine_6_2_options(mc); 3132 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3133 mc->smp_props.prefer_sockets = true; 3134 vmc->no_cpu_topology = true; 3135 3136 /* qemu ITS was introduced with 6.2 */ 3137 vmc->no_tcg_its = true; 3138 } 3139 DEFINE_VIRT_MACHINE(6, 1) 3140 3141 static void virt_machine_6_0_options(MachineClass *mc) 3142 { 3143 virt_machine_6_1_options(mc); 3144 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3145 } 3146 DEFINE_VIRT_MACHINE(6, 0) 3147 3148 static void virt_machine_5_2_options(MachineClass *mc) 3149 { 3150 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3151 3152 virt_machine_6_0_options(mc); 3153 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3154 vmc->no_secure_gpio = true; 3155 } 3156 DEFINE_VIRT_MACHINE(5, 2) 3157 3158 static void virt_machine_5_1_options(MachineClass *mc) 3159 { 3160 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3161 3162 virt_machine_5_2_options(mc); 3163 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3164 vmc->no_kvm_steal_time = true; 3165 } 3166 DEFINE_VIRT_MACHINE(5, 1) 3167 3168 static void virt_machine_5_0_options(MachineClass *mc) 3169 { 3170 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3171 3172 virt_machine_5_1_options(mc); 3173 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3174 mc->numa_mem_supported = true; 3175 vmc->acpi_expose_flash = true; 3176 mc->auto_enable_numa_with_memdev = false; 3177 } 3178 DEFINE_VIRT_MACHINE(5, 0) 3179 3180 static void virt_machine_4_2_options(MachineClass *mc) 3181 { 3182 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3183 3184 virt_machine_5_0_options(mc); 3185 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3186 vmc->kvm_no_adjvtime = true; 3187 } 3188 DEFINE_VIRT_MACHINE(4, 2) 3189 3190 static void virt_machine_4_1_options(MachineClass *mc) 3191 { 3192 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3193 3194 virt_machine_4_2_options(mc); 3195 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3196 vmc->no_ged = true; 3197 mc->auto_enable_numa_with_memhp = false; 3198 } 3199 DEFINE_VIRT_MACHINE(4, 1) 3200 3201 static void virt_machine_4_0_options(MachineClass *mc) 3202 { 3203 virt_machine_4_1_options(mc); 3204 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3205 } 3206 DEFINE_VIRT_MACHINE(4, 0) 3207 3208 static void virt_machine_3_1_options(MachineClass *mc) 3209 { 3210 virt_machine_4_0_options(mc); 3211 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3212 } 3213 DEFINE_VIRT_MACHINE(3, 1) 3214 3215 static void virt_machine_3_0_options(MachineClass *mc) 3216 { 3217 virt_machine_3_1_options(mc); 3218 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3219 } 3220 DEFINE_VIRT_MACHINE(3, 0) 3221 3222 static void virt_machine_2_12_options(MachineClass *mc) 3223 { 3224 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3225 3226 virt_machine_3_0_options(mc); 3227 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3228 vmc->no_highmem_ecam = true; 3229 mc->max_cpus = 255; 3230 } 3231 DEFINE_VIRT_MACHINE(2, 12) 3232 3233 static void virt_machine_2_11_options(MachineClass *mc) 3234 { 3235 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3236 3237 virt_machine_2_12_options(mc); 3238 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3239 vmc->smbios_old_sys_ver = true; 3240 } 3241 DEFINE_VIRT_MACHINE(2, 11) 3242 3243 static void virt_machine_2_10_options(MachineClass *mc) 3244 { 3245 virt_machine_2_11_options(mc); 3246 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3247 /* before 2.11 we never faulted accesses to bad addresses */ 3248 mc->ignore_memory_transaction_failures = true; 3249 } 3250 DEFINE_VIRT_MACHINE(2, 10) 3251 3252 static void virt_machine_2_9_options(MachineClass *mc) 3253 { 3254 virt_machine_2_10_options(mc); 3255 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3256 } 3257 DEFINE_VIRT_MACHINE(2, 9) 3258 3259 static void virt_machine_2_8_options(MachineClass *mc) 3260 { 3261 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3262 3263 virt_machine_2_9_options(mc); 3264 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3265 /* For 2.8 and earlier we falsely claimed in the DT that 3266 * our timers were edge-triggered, not level-triggered. 3267 */ 3268 vmc->claim_edge_triggered_timers = true; 3269 } 3270 DEFINE_VIRT_MACHINE(2, 8) 3271 3272 static void virt_machine_2_7_options(MachineClass *mc) 3273 { 3274 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3275 3276 virt_machine_2_8_options(mc); 3277 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3278 /* ITS was introduced with 2.8 */ 3279 vmc->no_its = true; 3280 /* Stick with 1K pages for migration compatibility */ 3281 mc->minimum_page_bits = 0; 3282 } 3283 DEFINE_VIRT_MACHINE(2, 7) 3284 3285 static void virt_machine_2_6_options(MachineClass *mc) 3286 { 3287 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3288 3289 virt_machine_2_7_options(mc); 3290 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3291 vmc->disallow_affinity_adjustment = true; 3292 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3293 vmc->no_pmu = true; 3294 } 3295 DEFINE_VIRT_MACHINE(2, 6) 3296