1 /* 2 * Xilinx Zynq Baseboard System emulation. 3 * 4 * Copyright (c) 2010 Xilinx. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) 6 * Copyright (c) 2012 Petalogix Pty Ltd. 7 * Written by Haibing Ma 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/arm.h" 24 #include "net/net.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/block-backend.h" 30 #include "hw/loader.h" 31 #include "hw/misc/zynq-xadc.h" 32 #include "hw/ssi/ssi.h" 33 #include "qemu/error-report.h" 34 #include "hw/sd/sd.h" 35 #include "hw/char/cadence_uart.h" 36 37 #define NUM_SPI_FLASHES 4 38 #define NUM_QSPI_FLASHES 2 39 #define NUM_QSPI_BUSSES 2 40 41 #define FLASH_SIZE (64 * 1024 * 1024) 42 #define FLASH_SECTOR_SIZE (128 * 1024) 43 44 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ 45 46 #define MPCORE_PERIPHBASE 0xF8F00000 47 #define ZYNQ_BOARD_MIDR 0x413FC090 48 49 static const int dma_irqs[8] = { 50 46, 47, 48, 49, 72, 73, 74, 75 51 }; 52 53 #define BOARD_SETUP_ADDR 0x100 54 55 #define SLCR_LOCK_OFFSET 0x004 56 #define SLCR_UNLOCK_OFFSET 0x008 57 #define SLCR_ARM_PLL_OFFSET 0x100 58 59 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d 60 #define SLCR_XILINX_LOCK_KEY 0x767b 61 62 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 63 extract32((x), 12, 4) << 16) 64 65 /* Write immediate val to address r0 + addr. r0 should contain base offset 66 * of the SLCR block. Clobbers r1. 67 */ 68 69 #define SLCR_WRITE(addr, val) \ 70 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ 71 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 72 0xe5801000 + (addr) 73 74 static void zynq_write_board_setup(ARMCPU *cpu, 75 const struct arm_boot_info *info) 76 { 77 int n; 78 uint32_t board_setup_blob[] = { 79 0xe3a004f8, /* mov r0, #0xf8000000 */ 80 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), 81 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), 82 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), 83 0xe12fff1e, /* bx lr */ 84 }; 85 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 86 board_setup_blob[n] = tswap32(board_setup_blob[n]); 87 } 88 rom_add_blob_fixed("board-setup", board_setup_blob, 89 sizeof(board_setup_blob), BOARD_SETUP_ADDR); 90 } 91 92 static struct arm_boot_info zynq_binfo = {}; 93 94 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) 95 { 96 DeviceState *dev; 97 SysBusDevice *s; 98 99 dev = qdev_create(NULL, "cadence_gem"); 100 if (nd->used) { 101 qemu_check_nic_model(nd, "cadence_gem"); 102 qdev_set_nic_properties(dev, nd); 103 } 104 qdev_init_nofail(dev); 105 s = SYS_BUS_DEVICE(dev); 106 sysbus_mmio_map(s, 0, base); 107 sysbus_connect_irq(s, 0, irq); 108 } 109 110 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, 111 bool is_qspi) 112 { 113 DeviceState *dev; 114 SysBusDevice *busdev; 115 SSIBus *spi; 116 DeviceState *flash_dev; 117 int i, j; 118 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 119 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 120 121 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 122 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 123 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 124 qdev_prop_set_uint8(dev, "num-busses", num_busses); 125 qdev_init_nofail(dev); 126 busdev = SYS_BUS_DEVICE(dev); 127 sysbus_mmio_map(busdev, 0, base_addr); 128 if (is_qspi) { 129 sysbus_mmio_map(busdev, 1, 0xFC000000); 130 } 131 sysbus_connect_irq(busdev, 0, irq); 132 133 for (i = 0; i < num_busses; ++i) { 134 char bus_name[16]; 135 qemu_irq cs_line; 136 137 snprintf(bus_name, 16, "spi%d", i); 138 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); 139 140 for (j = 0; j < num_ss; ++j) { 141 flash_dev = ssi_create_slave(spi, "n25q128"); 142 143 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 144 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); 145 } 146 } 147 148 } 149 150 static void zynq_init(MachineState *machine) 151 { 152 ram_addr_t ram_size = machine->ram_size; 153 const char *cpu_model = machine->cpu_model; 154 const char *kernel_filename = machine->kernel_filename; 155 const char *kernel_cmdline = machine->kernel_cmdline; 156 const char *initrd_filename = machine->initrd_filename; 157 ObjectClass *cpu_oc; 158 ARMCPU *cpu; 159 MemoryRegion *address_space_mem = get_system_memory(); 160 MemoryRegion *ext_ram = g_new(MemoryRegion, 1); 161 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 162 DeviceState *dev, *carddev; 163 SysBusDevice *busdev; 164 DriveInfo *di; 165 BlockBackend *blk; 166 qemu_irq pic[64]; 167 int n; 168 169 if (!cpu_model) { 170 cpu_model = "cortex-a9"; 171 } 172 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 173 174 cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); 175 176 /* By default A9 CPUs have EL3 enabled. This board does not 177 * currently support EL3 so the CPU EL3 property is disabled before 178 * realization. 179 */ 180 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { 181 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); 182 } 183 184 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", 185 &error_fatal); 186 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", 187 &error_fatal); 188 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); 189 190 /* max 2GB ram */ 191 if (ram_size > 0x80000000) { 192 ram_size = 0x80000000; 193 } 194 195 /* DDR remapped to address zero. */ 196 memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", 197 ram_size); 198 memory_region_add_subregion(address_space_mem, 0, ext_ram); 199 200 /* 256K of on-chip memory */ 201 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, 202 &error_fatal); 203 vmstate_register_ram_global(ocm_ram); 204 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); 205 206 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 207 208 /* AMD */ 209 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, 210 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 211 FLASH_SECTOR_SIZE, 212 FLASH_SIZE/FLASH_SECTOR_SIZE, 1, 213 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 214 0); 215 216 dev = qdev_create(NULL, "xilinx,zynq_slcr"); 217 qdev_init_nofail(dev); 218 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); 219 220 dev = qdev_create(NULL, "a9mpcore_priv"); 221 qdev_prop_set_uint32(dev, "num-cpu", 1); 222 qdev_init_nofail(dev); 223 busdev = SYS_BUS_DEVICE(dev); 224 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 225 sysbus_connect_irq(busdev, 0, 226 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 227 228 for (n = 0; n < 64; n++) { 229 pic[n] = qdev_get_gpio_in(dev, n); 230 } 231 232 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); 233 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); 234 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); 235 236 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); 237 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); 238 239 cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hds[0]); 240 cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hds[1]); 241 242 sysbus_create_varargs("cadence_ttc", 0xF8001000, 243 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); 244 sysbus_create_varargs("cadence_ttc", 0xF8002000, 245 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); 246 247 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); 248 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); 249 250 dev = qdev_create(NULL, "generic-sdhci"); 251 qdev_init_nofail(dev); 252 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); 253 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); 254 255 di = drive_get_next(IF_SD); 256 blk = di ? blk_by_legacy_dinfo(di) : NULL; 257 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 258 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 259 object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 260 261 dev = qdev_create(NULL, "generic-sdhci"); 262 qdev_init_nofail(dev); 263 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); 264 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); 265 266 di = drive_get_next(IF_SD); 267 blk = di ? blk_by_legacy_dinfo(di) : NULL; 268 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 269 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 270 object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 271 272 dev = qdev_create(NULL, TYPE_ZYNQ_XADC); 273 qdev_init_nofail(dev); 274 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 275 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 276 277 dev = qdev_create(NULL, "pl330"); 278 qdev_prop_set_uint8(dev, "num_chnls", 8); 279 qdev_prop_set_uint8(dev, "num_periph_req", 4); 280 qdev_prop_set_uint8(dev, "num_events", 16); 281 282 qdev_prop_set_uint8(dev, "data_width", 64); 283 qdev_prop_set_uint8(dev, "wr_cap", 8); 284 qdev_prop_set_uint8(dev, "wr_q_dep", 16); 285 qdev_prop_set_uint8(dev, "rd_cap", 8); 286 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 287 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 288 289 qdev_init_nofail(dev); 290 busdev = SYS_BUS_DEVICE(dev); 291 sysbus_mmio_map(busdev, 0, 0xF8003000); 292 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 293 for (n = 0; n < 8; ++n) { /* event irqs */ 294 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 295 } 296 297 zynq_binfo.ram_size = ram_size; 298 zynq_binfo.kernel_filename = kernel_filename; 299 zynq_binfo.kernel_cmdline = kernel_cmdline; 300 zynq_binfo.initrd_filename = initrd_filename; 301 zynq_binfo.nb_cpus = 1; 302 zynq_binfo.board_id = 0xd32; 303 zynq_binfo.loader_start = 0; 304 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; 305 zynq_binfo.write_board_setup = zynq_write_board_setup; 306 307 arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); 308 } 309 310 static void zynq_machine_init(MachineClass *mc) 311 { 312 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; 313 mc->init = zynq_init; 314 mc->block_default_type = IF_SCSI; 315 mc->max_cpus = 1; 316 mc->no_sdcard = 1; 317 } 318 319 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) 320