1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/error-report.h" 15 #include "qapi/error.h" 16 #include "sysemu/device_tree.h" 17 #include "exec/address-spaces.h" 18 #include "hw/boards.h" 19 #include "hw/sysbus.h" 20 #include "hw/arm/sysbus-fdt.h" 21 #include "hw/arm/fdt.h" 22 #include "cpu.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/arm/xlnx-versal.h" 25 #include "qom/object.h" 26 27 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 28 typedef struct VersalVirt VersalVirt; 29 DECLARE_INSTANCE_CHECKER(VersalVirt, XLNX_VERSAL_VIRT_MACHINE, 30 TYPE_XLNX_VERSAL_VIRT_MACHINE) 31 32 struct VersalVirt { 33 MachineState parent_obj; 34 35 Versal soc; 36 37 void *fdt; 38 int fdt_size; 39 struct { 40 uint32_t gic; 41 uint32_t ethernet_phy[2]; 42 uint32_t clk_125Mhz; 43 uint32_t clk_25Mhz; 44 } phandle; 45 struct arm_boot_info binfo; 46 47 struct { 48 bool secure; 49 } cfg; 50 }; 51 52 static void fdt_create(VersalVirt *s) 53 { 54 MachineClass *mc = MACHINE_GET_CLASS(s); 55 int i; 56 57 s->fdt = create_device_tree(&s->fdt_size); 58 if (!s->fdt) { 59 error_report("create_device_tree() failed"); 60 exit(1); 61 } 62 63 /* Allocate all phandles. */ 64 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 65 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 66 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 67 } 68 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 69 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 70 71 /* Create /chosen node for load_dtb. */ 72 qemu_fdt_add_subnode(s->fdt, "/chosen"); 73 74 /* Header */ 75 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 76 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 77 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 78 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 79 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 80 } 81 82 static void fdt_add_clk_node(VersalVirt *s, const char *name, 83 unsigned int freq_hz, uint32_t phandle) 84 { 85 qemu_fdt_add_subnode(s->fdt, name); 86 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 87 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 88 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 89 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 90 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 91 } 92 93 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 94 { 95 int i; 96 97 qemu_fdt_add_subnode(s->fdt, "/cpus"); 98 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 99 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 100 101 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 102 char *name = g_strdup_printf("/cpus/cpu@%d", i); 103 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 104 105 qemu_fdt_add_subnode(s->fdt, name); 106 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); 107 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 108 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 109 } 110 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 111 qemu_fdt_setprop_string(s->fdt, name, "compatible", 112 armcpu->dtb_compatible); 113 g_free(name); 114 } 115 } 116 117 static void fdt_add_gic_nodes(VersalVirt *s) 118 { 119 char *nodename; 120 121 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 122 qemu_fdt_add_subnode(s->fdt, nodename); 123 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 124 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 125 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 126 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 127 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 128 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 129 2, MM_GIC_APU_DIST_MAIN, 130 2, MM_GIC_APU_DIST_MAIN_SIZE, 131 2, MM_GIC_APU_REDIST_0, 132 2, MM_GIC_APU_REDIST_0_SIZE); 133 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 134 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 135 g_free(nodename); 136 } 137 138 static void fdt_add_timer_nodes(VersalVirt *s) 139 { 140 const char compat[] = "arm,armv8-timer"; 141 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 142 143 qemu_fdt_add_subnode(s->fdt, "/timer"); 144 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 145 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 146 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 147 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 148 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 149 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 150 compat, sizeof(compat)); 151 } 152 153 static void fdt_add_uart_nodes(VersalVirt *s) 154 { 155 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 156 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 157 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 158 const char clocknames[] = "uartclk\0apb_pclk"; 159 int i; 160 161 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 162 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 163 qemu_fdt_add_subnode(s->fdt, name); 164 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 165 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 166 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 167 qemu_fdt_setprop(s->fdt, name, "clock-names", 168 clocknames, sizeof(clocknames)); 169 170 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 171 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 172 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 173 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 174 2, addrs[i], 2, 0x1000); 175 qemu_fdt_setprop(s->fdt, name, "compatible", 176 compat, sizeof(compat)); 177 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 178 179 if (addrs[i] == MM_UART0) { 180 /* Select UART0. */ 181 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 182 } 183 g_free(name); 184 } 185 } 186 187 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 188 uint32_t phandle) 189 { 190 char *name = g_strdup_printf("%s/fixed-link", gemname); 191 192 qemu_fdt_add_subnode(s->fdt, name); 193 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 194 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 195 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 196 g_free(name); 197 } 198 199 static void fdt_add_gem_nodes(VersalVirt *s) 200 { 201 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 202 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 203 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 204 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 205 int i; 206 207 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 208 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 209 qemu_fdt_add_subnode(s->fdt, name); 210 211 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 212 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 213 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 214 s->phandle.ethernet_phy[i]); 215 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 216 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 217 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 218 qemu_fdt_setprop(s->fdt, name, "clock-names", 219 clocknames, sizeof(clocknames)); 220 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 221 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 222 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 223 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 224 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 225 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 226 2, addrs[i], 2, 0x1000); 227 qemu_fdt_setprop(s->fdt, name, "compatible", 228 compat_gem, sizeof(compat_gem)); 229 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 230 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 231 g_free(name); 232 } 233 } 234 235 static void fdt_add_zdma_nodes(VersalVirt *s) 236 { 237 const char clocknames[] = "clk_main\0clk_apb"; 238 const char compat[] = "xlnx,zynqmp-dma-1.0"; 239 int i; 240 241 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 242 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 243 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 244 245 qemu_fdt_add_subnode(s->fdt, name); 246 247 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 248 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 249 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 250 qemu_fdt_setprop(s->fdt, name, "clock-names", 251 clocknames, sizeof(clocknames)); 252 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 253 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 254 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 255 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 256 2, addr, 2, 0x1000); 257 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 258 g_free(name); 259 } 260 } 261 262 static void fdt_add_sd_nodes(VersalVirt *s) 263 { 264 const char clocknames[] = "clk_xin\0clk_ahb"; 265 const char compat[] = "arasan,sdhci-8.9a"; 266 int i; 267 268 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 269 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 270 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 271 272 qemu_fdt_add_subnode(s->fdt, name); 273 274 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 275 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 276 qemu_fdt_setprop(s->fdt, name, "clock-names", 277 clocknames, sizeof(clocknames)); 278 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 279 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 280 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 281 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 282 2, addr, 2, MM_PMC_SD0_SIZE); 283 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 284 g_free(name); 285 } 286 } 287 288 static void fdt_add_rtc_node(VersalVirt *s) 289 { 290 const char compat[] = "xlnx,zynqmp-rtc"; 291 const char interrupt_names[] = "alarm\0sec"; 292 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 293 294 qemu_fdt_add_subnode(s->fdt, name); 295 296 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 297 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 298 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 299 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 300 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 301 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 302 interrupt_names, sizeof(interrupt_names)); 303 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 304 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 305 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 306 g_free(name); 307 } 308 309 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 310 { 311 Error *err = NULL; 312 char **node_path; 313 int n = 0; 314 315 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 316 if (err) { 317 error_propagate(errp, err); 318 return; 319 } 320 while (node_path[n]) { 321 if (g_str_has_prefix(node_path[n], "/memory")) { 322 qemu_fdt_nop_node(fdt, node_path[n]); 323 } 324 n++; 325 } 326 g_strfreev(node_path); 327 } 328 329 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 330 { 331 /* Describes the various split DDR access regions. */ 332 static const struct { 333 uint64_t base; 334 uint64_t size; 335 } addr_ranges[] = { 336 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 337 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 338 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 339 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 340 }; 341 uint64_t mem_reg_prop[8] = {0}; 342 uint64_t size = ram_size; 343 Error *err = NULL; 344 char *name; 345 int i; 346 347 fdt_nop_memory_nodes(fdt, &err); 348 if (err) { 349 error_report_err(err); 350 return; 351 } 352 353 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 354 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 355 uint64_t mapsize; 356 357 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 358 359 mem_reg_prop[i * 2] = addr_ranges[i].base; 360 mem_reg_prop[i * 2 + 1] = mapsize; 361 size -= mapsize; 362 } 363 qemu_fdt_add_subnode(fdt, name); 364 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 365 366 switch (i) { 367 case 1: 368 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 369 2, mem_reg_prop[0], 370 2, mem_reg_prop[1]); 371 break; 372 case 2: 373 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 374 2, mem_reg_prop[0], 375 2, mem_reg_prop[1], 376 2, mem_reg_prop[2], 377 2, mem_reg_prop[3]); 378 break; 379 case 3: 380 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 381 2, mem_reg_prop[0], 382 2, mem_reg_prop[1], 383 2, mem_reg_prop[2], 384 2, mem_reg_prop[3], 385 2, mem_reg_prop[4], 386 2, mem_reg_prop[5]); 387 break; 388 case 4: 389 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 390 2, mem_reg_prop[0], 391 2, mem_reg_prop[1], 392 2, mem_reg_prop[2], 393 2, mem_reg_prop[3], 394 2, mem_reg_prop[4], 395 2, mem_reg_prop[5], 396 2, mem_reg_prop[6], 397 2, mem_reg_prop[7]); 398 break; 399 default: 400 g_assert_not_reached(); 401 } 402 g_free(name); 403 } 404 405 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 406 void *fdt) 407 { 408 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 409 410 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 411 } 412 413 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 414 int *fdt_size) 415 { 416 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 417 418 *fdt_size = board->fdt_size; 419 return board->fdt; 420 } 421 422 #define NUM_VIRTIO_TRANSPORT 8 423 static void create_virtio_regions(VersalVirt *s) 424 { 425 int virtio_mmio_size = 0x200; 426 int i; 427 428 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 429 char *name = g_strdup_printf("virtio%d", i); 430 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 431 int irq = VERSAL_RSVD_IRQ_FIRST + i; 432 MemoryRegion *mr; 433 DeviceState *dev; 434 qemu_irq pic_irq; 435 436 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 437 dev = qdev_new("virtio-mmio"); 438 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 439 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 440 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 441 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 442 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 443 g_free(name); 444 } 445 446 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 447 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 448 int irq = VERSAL_RSVD_IRQ_FIRST + i; 449 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 450 451 qemu_fdt_add_subnode(s->fdt, name); 452 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 453 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 454 GIC_FDT_IRQ_TYPE_SPI, irq, 455 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 456 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 457 2, base, 2, virtio_mmio_size); 458 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 459 g_free(name); 460 } 461 } 462 463 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 464 { 465 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 466 DeviceState *card; 467 468 card = qdev_new(TYPE_SD_CARD); 469 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 470 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 471 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 472 &error_fatal); 473 } 474 475 static void versal_virt_init(MachineState *machine) 476 { 477 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 478 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 479 int i; 480 481 /* 482 * If the user provides an Operating System to be loaded, we expect them 483 * to use the -kernel command line option. 484 * 485 * Users can load firmware or boot-loaders with the -device loader options. 486 * 487 * When loading an OS, we generate a dtb and let arm_load_kernel() select 488 * where it gets loaded. This dtb will be passed to the kernel in x0. 489 * 490 * If there's no -kernel option, we generate a DTB and place it at 0x1000 491 * for the bootloaders or firmware to pick up. 492 * 493 * If users want to provide their own DTB, they can use the -dtb option. 494 * These dtb's will have their memory nodes modified to match QEMU's 495 * selected ram_size option before they get passed to the kernel or fw. 496 * 497 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 498 * as the PSCI conduit. When there's no -kernel, we assume the user 499 * provides EL3 firmware to handle PSCI. 500 */ 501 if (machine->kernel_filename) { 502 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 503 } 504 505 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 506 TYPE_XLNX_VERSAL); 507 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 508 &error_abort); 509 object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit, 510 &error_abort); 511 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 512 513 fdt_create(s); 514 create_virtio_regions(s); 515 fdt_add_gem_nodes(s); 516 fdt_add_uart_nodes(s); 517 fdt_add_gic_nodes(s); 518 fdt_add_timer_nodes(s); 519 fdt_add_zdma_nodes(s); 520 fdt_add_sd_nodes(s); 521 fdt_add_rtc_node(s); 522 fdt_add_cpu_nodes(s, psci_conduit); 523 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 524 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 525 526 /* Make the APU cpu address space visible to virtio and other 527 * modules unaware of muliple address-spaces. */ 528 memory_region_add_subregion_overlap(get_system_memory(), 529 0, &s->soc.fpd.apu.mr, 0); 530 531 /* Plugin SD cards. */ 532 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 533 sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); 534 } 535 536 s->binfo.ram_size = machine->ram_size; 537 s->binfo.loader_start = 0x0; 538 s->binfo.get_dtb = versal_virt_get_dtb; 539 s->binfo.modify_dtb = versal_virt_modify_dtb; 540 if (machine->kernel_filename) { 541 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 542 } else { 543 AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0], 544 &s->binfo); 545 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 546 * Offset things by 4K. */ 547 s->binfo.loader_start = 0x1000; 548 s->binfo.dtb_limit = 0x1000000; 549 if (arm_load_dtb(s->binfo.loader_start, 550 &s->binfo, s->binfo.dtb_limit, as, machine) < 0) { 551 exit(EXIT_FAILURE); 552 } 553 } 554 } 555 556 static void versal_virt_machine_instance_init(Object *obj) 557 { 558 } 559 560 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 561 { 562 MachineClass *mc = MACHINE_CLASS(oc); 563 564 mc->desc = "Xilinx Versal Virtual development board"; 565 mc->init = versal_virt_init; 566 mc->max_cpus = XLNX_VERSAL_NR_ACPUS; 567 mc->default_cpus = XLNX_VERSAL_NR_ACPUS; 568 mc->no_cdrom = true; 569 mc->default_ram_id = "ddr"; 570 } 571 572 static const TypeInfo versal_virt_machine_init_typeinfo = { 573 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 574 .parent = TYPE_MACHINE, 575 .class_init = versal_virt_machine_class_init, 576 .instance_init = versal_virt_machine_instance_init, 577 .instance_size = sizeof(VersalVirt), 578 }; 579 580 static void versal_virt_machine_init_register_types(void) 581 { 582 type_register_static(&versal_virt_machine_init_typeinfo); 583 } 584 585 type_init(versal_virt_machine_init_register_types) 586 587