1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "hw/boards.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/sysemu.h" 28 #include "kvm_arm.h" 29 30 #define GIC_NUM_SPI_INTR 160 31 32 #define ARM_PHYS_TIMER_PPI 30 33 #define ARM_VIRT_TIMER_PPI 27 34 #define ARM_HYP_TIMER_PPI 26 35 #define ARM_SEC_TIMER_PPI 29 36 #define GIC_MAINTENANCE_PPI 25 37 38 #define GEM_REVISION 0x40070106 39 40 #define GIC_BASE_ADDR 0xf9000000 41 #define GIC_DIST_ADDR 0xf9010000 42 #define GIC_CPU_ADDR 0xf9020000 43 #define GIC_VIFACE_ADDR 0xf9040000 44 #define GIC_VCPU_ADDR 0xf9060000 45 46 #define SATA_INTR 133 47 #define SATA_ADDR 0xFD0C0000 48 #define SATA_NUM_PORTS 2 49 50 #define QSPI_ADDR 0xff0f0000 51 #define LQSPI_ADDR 0xc0000000 52 #define QSPI_IRQ 15 53 54 #define DP_ADDR 0xfd4a0000 55 #define DP_IRQ 113 56 57 #define DPDMA_ADDR 0xfd4c0000 58 #define DPDMA_IRQ 116 59 60 #define IPI_ADDR 0xFF300000 61 #define IPI_IRQ 64 62 63 #define RTC_ADDR 0xffa60000 64 #define RTC_IRQ 26 65 66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 67 68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 70 }; 71 72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 73 57, 59, 61, 63, 74 }; 75 76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 77 0xFF000000, 0xFF010000, 78 }; 79 80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 81 21, 22, 82 }; 83 84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 85 0xFF160000, 0xFF170000, 86 }; 87 88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 89 48, 49, 90 }; 91 92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 93 0xFF040000, 0xFF050000, 94 }; 95 96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 97 19, 20, 98 }; 99 100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 101 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 102 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 103 }; 104 105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 106 124, 125, 126, 127, 128, 129, 130, 131 107 }; 108 109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 110 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 111 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 112 }; 113 114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 115 77, 78, 79, 80, 81, 82, 83, 84 116 }; 117 118 typedef struct XlnxZynqMPGICRegion { 119 int region_index; 120 uint32_t address; 121 uint32_t offset; 122 bool virt; 123 } XlnxZynqMPGICRegion; 124 125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 126 /* Distributor */ 127 { 128 .region_index = 0, 129 .address = GIC_DIST_ADDR, 130 .offset = 0, 131 .virt = false 132 }, 133 134 /* CPU interface */ 135 { 136 .region_index = 1, 137 .address = GIC_CPU_ADDR, 138 .offset = 0, 139 .virt = false 140 }, 141 { 142 .region_index = 1, 143 .address = GIC_CPU_ADDR + 0x10000, 144 .offset = 0x1000, 145 .virt = false 146 }, 147 148 /* Virtual interface */ 149 { 150 .region_index = 2, 151 .address = GIC_VIFACE_ADDR, 152 .offset = 0, 153 .virt = true 154 }, 155 156 /* Virtual CPU interface */ 157 { 158 .region_index = 3, 159 .address = GIC_VCPU_ADDR, 160 .offset = 0, 161 .virt = true 162 }, 163 { 164 .region_index = 3, 165 .address = GIC_VCPU_ADDR + 0x10000, 166 .offset = 0x1000, 167 .virt = true 168 }, 169 }; 170 171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 172 { 173 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 174 } 175 176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 177 const char *boot_cpu, Error **errp) 178 { 179 int i; 180 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 181 XLNX_ZYNQMP_NUM_RPU_CPUS); 182 183 if (num_rpus <= 0) { 184 /* Don't create rpu-cluster object if there's nothing to put in it */ 185 return; 186 } 187 188 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 189 TYPE_CPU_CLUSTER); 190 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 191 192 for (i = 0; i < num_rpus; i++) { 193 char *name; 194 195 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 196 &s->rpu_cpu[i], 197 ARM_CPU_TYPE_NAME("cortex-r5f")); 198 199 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 200 if (strcmp(name, boot_cpu)) { 201 /* Secondary CPUs start in PSCI powered-down state */ 202 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 203 "start-powered-off", true, &error_abort); 204 } else { 205 s->boot_cpu_ptr = &s->rpu_cpu[i]; 206 } 207 g_free(name); 208 209 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 210 &error_abort); 211 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { 212 return; 213 } 214 } 215 216 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 217 } 218 219 static void xlnx_zynqmp_init(Object *obj) 220 { 221 MachineState *ms = MACHINE(qdev_get_machine()); 222 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 223 int i; 224 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 225 226 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 227 TYPE_CPU_CLUSTER); 228 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 229 230 for (i = 0; i < num_apus; i++) { 231 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 232 &s->apu_cpu[i], 233 ARM_CPU_TYPE_NAME("cortex-a53")); 234 } 235 236 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 237 238 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 239 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 240 } 241 242 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 243 object_initialize_child(obj, "uart[*]", &s->uart[i], 244 TYPE_CADENCE_UART); 245 } 246 247 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 248 249 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 250 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 251 TYPE_SYSBUS_SDHCI); 252 } 253 254 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 255 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 256 } 257 258 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 259 260 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 261 262 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 263 264 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 265 266 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 267 268 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 269 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 270 } 271 272 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 273 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 274 } 275 } 276 277 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 278 { 279 MachineState *ms = MACHINE(qdev_get_machine()); 280 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 281 MemoryRegion *system_memory = get_system_memory(); 282 uint8_t i; 283 uint64_t ram_size; 284 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 285 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 286 ram_addr_t ddr_low_size, ddr_high_size; 287 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 288 Error *err = NULL; 289 290 ram_size = memory_region_size(s->ddr_ram); 291 292 /* Create the DDR Memory Regions. User friendly checks should happen at 293 * the board level 294 */ 295 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 296 /* The RAM size is above the maximum available for the low DDR. 297 * Create the high DDR memory region as well. 298 */ 299 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 300 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 301 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 302 303 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 304 "ddr-ram-high", s->ddr_ram, ddr_low_size, 305 ddr_high_size); 306 memory_region_add_subregion(get_system_memory(), 307 XLNX_ZYNQMP_HIGH_RAM_START, 308 &s->ddr_ram_high); 309 } else { 310 /* RAM must be non-zero */ 311 assert(ram_size); 312 ddr_low_size = ram_size; 313 } 314 315 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 316 s->ddr_ram, 0, ddr_low_size); 317 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 318 319 /* Create the four OCM banks */ 320 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 321 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 322 323 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 324 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 325 memory_region_add_subregion(get_system_memory(), 326 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 327 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 328 &s->ocm_ram[i]); 329 330 g_free(ocm_name); 331 } 332 333 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 334 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 335 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 336 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 337 qdev_prop_set_bit(DEVICE(&s->gic), 338 "has-virtualization-extensions", s->virt); 339 340 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 341 342 /* Realize APUs before realizing the GIC. KVM requires this. */ 343 for (i = 0; i < num_apus; i++) { 344 char *name; 345 346 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit", 347 QEMU_PSCI_CONDUIT_SMC, &error_abort); 348 349 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 350 if (strcmp(name, boot_cpu)) { 351 /* Secondary CPUs start in PSCI powered-down state */ 352 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 353 "start-powered-off", true, &error_abort); 354 } else { 355 s->boot_cpu_ptr = &s->apu_cpu[i]; 356 } 357 g_free(name); 358 359 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 360 NULL); 361 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 362 NULL); 363 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 364 GIC_BASE_ADDR, &error_abort); 365 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 366 num_apus, &error_abort); 367 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { 368 return; 369 } 370 } 371 372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 373 return; 374 } 375 376 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 377 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 378 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 379 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 380 MemoryRegion *mr; 381 uint32_t addr = r->address; 382 int j; 383 384 if (r->virt && !s->virt) { 385 continue; 386 } 387 388 mr = sysbus_mmio_get_region(gic, r->region_index); 389 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 390 MemoryRegion *alias = &s->gic_mr[i][j]; 391 392 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 393 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 394 memory_region_add_subregion(system_memory, addr, alias); 395 396 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 397 } 398 } 399 400 for (i = 0; i < num_apus; i++) { 401 qemu_irq irq; 402 403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 404 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 405 ARM_CPU_IRQ)); 406 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 407 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 408 ARM_CPU_FIQ)); 409 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 410 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 411 ARM_CPU_VIRQ)); 412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 413 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 414 ARM_CPU_VFIQ)); 415 irq = qdev_get_gpio_in(DEVICE(&s->gic), 416 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 417 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 418 irq = qdev_get_gpio_in(DEVICE(&s->gic), 419 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 420 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 421 irq = qdev_get_gpio_in(DEVICE(&s->gic), 422 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 423 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 424 irq = qdev_get_gpio_in(DEVICE(&s->gic), 425 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 426 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 427 428 if (s->virt) { 429 irq = qdev_get_gpio_in(DEVICE(&s->gic), 430 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 431 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 432 } 433 } 434 435 if (s->has_rpu) { 436 info_report("The 'has_rpu' property is no longer required, to use the " 437 "RPUs just use -smp 6."); 438 } 439 440 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 441 if (err) { 442 error_propagate(errp, err); 443 return; 444 } 445 446 if (!s->boot_cpu_ptr) { 447 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 448 return; 449 } 450 451 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 452 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 453 } 454 455 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 456 NICInfo *nd = &nd_table[i]; 457 458 if (nd->used) { 459 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 460 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 461 } 462 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 463 &error_abort); 464 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 465 &error_abort); 466 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { 467 return; 468 } 469 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 470 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 471 gic_spi[gem_intr[i]]); 472 } 473 474 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 475 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 476 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 477 return; 478 } 479 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 481 gic_spi[uart_intr[i]]); 482 } 483 484 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 485 &error_abort); 486 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 487 return; 488 } 489 490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 492 493 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 494 char *bus_name; 495 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 496 Object *sdhci = OBJECT(&s->sdhci[i]); 497 498 /* Compatible with: 499 * - SD Host Controller Specification Version 3.00 500 * - SDIO Specification Version 3.0 501 * - eMMC Specification Version 4.51 502 */ 503 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { 504 return; 505 } 506 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, 507 errp)) { 508 return; 509 } 510 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { 511 return; 512 } 513 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { 514 return; 515 } 516 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 517 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 518 519 /* Alias controller SD bus to the SoC itself */ 520 bus_name = g_strdup_printf("sd-bus%d", i); 521 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 522 g_free(bus_name); 523 } 524 525 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 526 gchar *bus_name; 527 528 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 529 return; 530 } 531 532 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 533 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 534 gic_spi[spi_intr[i]]); 535 536 /* Alias controller SPI bus to the SoC itself */ 537 bus_name = g_strdup_printf("spi%d", i); 538 object_property_add_alias(OBJECT(s), bus_name, 539 OBJECT(&s->spi[i]), "spi0"); 540 g_free(bus_name); 541 } 542 543 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { 544 return; 545 } 546 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 547 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 548 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 549 550 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 551 gchar *bus_name; 552 gchar *target_bus; 553 554 /* Alias controller SPI bus to the SoC itself */ 555 bus_name = g_strdup_printf("qspi%d", i); 556 target_bus = g_strdup_printf("spi%d", i); 557 object_property_add_alias(OBJECT(s), bus_name, 558 OBJECT(&s->qspi), target_bus); 559 g_free(bus_name); 560 g_free(target_bus); 561 } 562 563 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { 564 return; 565 } 566 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 567 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 568 569 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { 570 return; 571 } 572 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 573 &error_abort); 574 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 575 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 576 577 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { 578 return; 579 } 580 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 581 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 582 583 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 584 return; 585 } 586 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 587 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 588 589 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 590 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, 591 errp)) { 592 return; 593 } 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { 595 return; 596 } 597 598 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 599 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 600 gic_spi[gdma_ch_intr[i]]); 601 } 602 603 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 604 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { 605 return; 606 } 607 608 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 609 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 610 gic_spi[adma_ch_intr[i]]); 611 } 612 } 613 614 static Property xlnx_zynqmp_props[] = { 615 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 616 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 617 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 618 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 619 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 620 MemoryRegion *), 621 DEFINE_PROP_END_OF_LIST() 622 }; 623 624 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 625 { 626 DeviceClass *dc = DEVICE_CLASS(oc); 627 628 device_class_set_props(dc, xlnx_zynqmp_props); 629 dc->realize = xlnx_zynqmp_realize; 630 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 631 dc->user_creatable = false; 632 } 633 634 static const TypeInfo xlnx_zynqmp_type_info = { 635 .name = TYPE_XLNX_ZYNQMP, 636 .parent = TYPE_DEVICE, 637 .instance_size = sizeof(XlnxZynqMPState), 638 .instance_init = xlnx_zynqmp_init, 639 .class_init = xlnx_zynqmp_class_init, 640 }; 641 642 static void xlnx_zynqmp_register_types(void) 643 { 644 type_register_static(&xlnx_zynqmp_type_info); 645 } 646 647 type_init(xlnx_zynqmp_register_types) 648