1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "hw/arm/xlnx-zynqmp.h" 22 #include "hw/intc/arm_gic_common.h" 23 #include "hw/misc/unimp.h" 24 #include "hw/boards.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/sysemu.h" 27 #include "kvm_arm.h" 28 29 #define GIC_NUM_SPI_INTR 160 30 31 #define ARM_PHYS_TIMER_PPI 30 32 #define ARM_VIRT_TIMER_PPI 27 33 #define ARM_HYP_TIMER_PPI 26 34 #define ARM_SEC_TIMER_PPI 29 35 #define GIC_MAINTENANCE_PPI 25 36 37 #define GEM_REVISION 0x40070106 38 39 #define GIC_BASE_ADDR 0xf9000000 40 #define GIC_DIST_ADDR 0xf9010000 41 #define GIC_CPU_ADDR 0xf9020000 42 #define GIC_VIFACE_ADDR 0xf9040000 43 #define GIC_VCPU_ADDR 0xf9060000 44 45 #define SATA_INTR 133 46 #define SATA_ADDR 0xFD0C0000 47 #define SATA_NUM_PORTS 2 48 49 #define QSPI_ADDR 0xff0f0000 50 #define LQSPI_ADDR 0xc0000000 51 #define QSPI_IRQ 15 52 #define QSPI_DMA_ADDR 0xff0f0800 53 #define NUM_QSPI_IRQ_LINES 2 54 55 #define DP_ADDR 0xfd4a0000 56 #define DP_IRQ 113 57 58 #define DPDMA_ADDR 0xfd4c0000 59 #define DPDMA_IRQ 116 60 61 #define APU_ADDR 0xfd5c0000 62 #define APU_SIZE 0x100 63 64 #define IPI_ADDR 0xFF300000 65 #define IPI_IRQ 64 66 67 #define RTC_ADDR 0xffa60000 68 #define RTC_IRQ 26 69 70 #define BBRAM_ADDR 0xffcd0000 71 #define BBRAM_IRQ 11 72 73 #define EFUSE_ADDR 0xffcc0000 74 #define EFUSE_IRQ 87 75 76 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 77 78 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 79 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 80 }; 81 82 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 83 57, 59, 61, 63, 84 }; 85 86 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 87 0xFF000000, 0xFF010000, 88 }; 89 90 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 91 21, 22, 92 }; 93 94 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { 95 0xFF060000, 0xFF070000, 96 }; 97 98 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { 99 23, 24, 100 }; 101 102 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 103 0xFF160000, 0xFF170000, 104 }; 105 106 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 107 48, 49, 108 }; 109 110 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 111 0xFF040000, 0xFF050000, 112 }; 113 114 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 115 19, 20, 116 }; 117 118 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 119 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 120 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 121 }; 122 123 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 124 124, 125, 126, 127, 128, 129, 130, 131 125 }; 126 127 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 128 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 129 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 130 }; 131 132 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 133 77, 78, 79, 80, 81, 82, 83, 84 134 }; 135 136 typedef struct XlnxZynqMPGICRegion { 137 int region_index; 138 uint32_t address; 139 uint32_t offset; 140 bool virt; 141 } XlnxZynqMPGICRegion; 142 143 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 144 /* Distributor */ 145 { 146 .region_index = 0, 147 .address = GIC_DIST_ADDR, 148 .offset = 0, 149 .virt = false 150 }, 151 152 /* CPU interface */ 153 { 154 .region_index = 1, 155 .address = GIC_CPU_ADDR, 156 .offset = 0, 157 .virt = false 158 }, 159 { 160 .region_index = 1, 161 .address = GIC_CPU_ADDR + 0x10000, 162 .offset = 0x1000, 163 .virt = false 164 }, 165 166 /* Virtual interface */ 167 { 168 .region_index = 2, 169 .address = GIC_VIFACE_ADDR, 170 .offset = 0, 171 .virt = true 172 }, 173 174 /* Virtual CPU interface */ 175 { 176 .region_index = 3, 177 .address = GIC_VCPU_ADDR, 178 .offset = 0, 179 .virt = true 180 }, 181 { 182 .region_index = 3, 183 .address = GIC_VCPU_ADDR + 0x10000, 184 .offset = 0x1000, 185 .virt = true 186 }, 187 }; 188 189 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 190 { 191 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 192 } 193 194 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 195 const char *boot_cpu, Error **errp) 196 { 197 int i; 198 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 199 XLNX_ZYNQMP_NUM_RPU_CPUS); 200 201 if (num_rpus <= 0) { 202 /* Don't create rpu-cluster object if there's nothing to put in it */ 203 return; 204 } 205 206 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 207 TYPE_CPU_CLUSTER); 208 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 209 210 for (i = 0; i < num_rpus; i++) { 211 const char *name; 212 213 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 214 &s->rpu_cpu[i], 215 ARM_CPU_TYPE_NAME("cortex-r5f")); 216 217 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 218 if (strcmp(name, boot_cpu)) { 219 /* 220 * Secondary CPUs start in powered-down state. 221 */ 222 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 223 "start-powered-off", true, &error_abort); 224 } else { 225 s->boot_cpu_ptr = &s->rpu_cpu[i]; 226 } 227 228 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 229 &error_abort); 230 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { 231 return; 232 } 233 } 234 235 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 236 } 237 238 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) 239 { 240 SysBusDevice *sbd; 241 242 object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, 243 sizeof(s->bbram), TYPE_XLNX_BBRAM, 244 &error_fatal, 245 "crc-zpads", "1", 246 NULL); 247 sbd = SYS_BUS_DEVICE(&s->bbram); 248 249 sysbus_realize(sbd, &error_fatal); 250 sysbus_mmio_map(sbd, 0, BBRAM_ADDR); 251 sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); 252 } 253 254 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) 255 { 256 Object *bits = OBJECT(&s->efuse); 257 Object *ctrl = OBJECT(&s->efuse_ctrl); 258 SysBusDevice *sbd; 259 260 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, 261 TYPE_XLNX_ZYNQMP_EFUSE); 262 263 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 264 sizeof(s->efuse), 265 TYPE_XLNX_EFUSE, &error_abort, 266 "efuse-nr", "3", 267 "efuse-size", "2048", 268 NULL); 269 270 qdev_realize(DEVICE(bits), NULL, &error_abort); 271 object_property_set_link(ctrl, "efuse", bits, &error_abort); 272 273 sbd = SYS_BUS_DEVICE(ctrl); 274 sysbus_realize(sbd, &error_abort); 275 sysbus_mmio_map(sbd, 0, EFUSE_ADDR); 276 sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); 277 } 278 279 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) 280 { 281 static const struct UnimpInfo { 282 const char *name; 283 hwaddr base; 284 hwaddr size; 285 } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { 286 { .name = "apu", APU_ADDR, APU_SIZE }, 287 }; 288 unsigned int nr; 289 290 for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) { 291 const struct UnimpInfo *info = &unimp_areas[nr]; 292 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 293 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 294 295 assert(info->name && info->base && info->size > 0); 296 qdev_prop_set_string(dev, "name", info->name); 297 qdev_prop_set_uint64(dev, "size", info->size); 298 object_property_add_child(OBJECT(s), info->name, OBJECT(dev)); 299 300 sysbus_realize_and_unref(sbd, &error_fatal); 301 sysbus_mmio_map(sbd, 0, info->base); 302 } 303 } 304 305 static void xlnx_zynqmp_init(Object *obj) 306 { 307 MachineState *ms = MACHINE(qdev_get_machine()); 308 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 309 int i; 310 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 311 312 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 313 TYPE_CPU_CLUSTER); 314 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 315 316 for (i = 0; i < num_apus; i++) { 317 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 318 &s->apu_cpu[i], 319 ARM_CPU_TYPE_NAME("cortex-a53")); 320 } 321 322 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 323 324 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 325 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 326 } 327 328 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 329 object_initialize_child(obj, "uart[*]", &s->uart[i], 330 TYPE_CADENCE_UART); 331 } 332 333 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 334 object_initialize_child(obj, "can[*]", &s->can[i], 335 TYPE_XLNX_ZYNQMP_CAN); 336 } 337 338 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 339 340 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 341 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 342 TYPE_SYSBUS_SDHCI); 343 } 344 345 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 346 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 347 } 348 349 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 350 351 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 352 353 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 354 355 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 356 357 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 358 359 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 360 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 361 } 362 363 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 364 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 365 } 366 367 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA); 368 object_initialize_child(obj, "qspi-irq-orgate", 369 &s->qspi_irq_orgate, TYPE_OR_IRQ); 370 } 371 372 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 373 { 374 MachineState *ms = MACHINE(qdev_get_machine()); 375 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 376 MemoryRegion *system_memory = get_system_memory(); 377 uint8_t i; 378 uint64_t ram_size; 379 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 380 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 381 ram_addr_t ddr_low_size, ddr_high_size; 382 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 383 Error *err = NULL; 384 385 ram_size = memory_region_size(s->ddr_ram); 386 387 /* 388 * Create the DDR Memory Regions. User friendly checks should happen at 389 * the board level 390 */ 391 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 392 /* 393 * The RAM size is above the maximum available for the low DDR. 394 * Create the high DDR memory region as well. 395 */ 396 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 397 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 398 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 399 400 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 401 "ddr-ram-high", s->ddr_ram, ddr_low_size, 402 ddr_high_size); 403 memory_region_add_subregion(get_system_memory(), 404 XLNX_ZYNQMP_HIGH_RAM_START, 405 &s->ddr_ram_high); 406 } else { 407 /* RAM must be non-zero */ 408 assert(ram_size); 409 ddr_low_size = ram_size; 410 } 411 412 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 413 s->ddr_ram, 0, ddr_low_size); 414 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 415 416 /* Create the four OCM banks */ 417 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 418 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 419 420 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 421 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 422 memory_region_add_subregion(get_system_memory(), 423 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 424 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 425 &s->ocm_ram[i]); 426 427 g_free(ocm_name); 428 } 429 430 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 431 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 432 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 433 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 434 qdev_prop_set_bit(DEVICE(&s->gic), 435 "has-virtualization-extensions", s->virt); 436 437 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 438 439 /* Realize APUs before realizing the GIC. KVM requires this. */ 440 for (i = 0; i < num_apus; i++) { 441 const char *name; 442 443 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 444 if (strcmp(name, boot_cpu)) { 445 /* 446 * Secondary CPUs start in powered-down state. 447 */ 448 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 449 "start-powered-off", true, &error_abort); 450 } else { 451 s->boot_cpu_ptr = &s->apu_cpu[i]; 452 } 453 454 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 455 NULL); 456 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 457 NULL); 458 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 459 GIC_BASE_ADDR, &error_abort); 460 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 461 num_apus, &error_abort); 462 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { 463 return; 464 } 465 } 466 467 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 468 return; 469 } 470 471 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 472 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 473 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 474 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 475 MemoryRegion *mr; 476 uint32_t addr = r->address; 477 int j; 478 479 if (r->virt && !s->virt) { 480 continue; 481 } 482 483 mr = sysbus_mmio_get_region(gic, r->region_index); 484 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 485 MemoryRegion *alias = &s->gic_mr[i][j]; 486 487 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 488 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 489 memory_region_add_subregion(system_memory, addr, alias); 490 491 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 492 } 493 } 494 495 for (i = 0; i < num_apus; i++) { 496 qemu_irq irq; 497 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 499 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 500 ARM_CPU_IRQ)); 501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 502 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 503 ARM_CPU_FIQ)); 504 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 505 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 506 ARM_CPU_VIRQ)); 507 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 508 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 509 ARM_CPU_VFIQ)); 510 irq = qdev_get_gpio_in(DEVICE(&s->gic), 511 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 512 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 513 irq = qdev_get_gpio_in(DEVICE(&s->gic), 514 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 515 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 516 irq = qdev_get_gpio_in(DEVICE(&s->gic), 517 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 518 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 519 irq = qdev_get_gpio_in(DEVICE(&s->gic), 520 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 521 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 522 523 if (s->virt) { 524 irq = qdev_get_gpio_in(DEVICE(&s->gic), 525 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 526 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 527 } 528 } 529 530 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 531 if (err) { 532 error_propagate(errp, err); 533 return; 534 } 535 536 if (!s->boot_cpu_ptr) { 537 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 538 return; 539 } 540 541 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 542 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 543 } 544 545 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 546 NICInfo *nd = &nd_table[i]; 547 548 /* FIXME use qdev NIC properties instead of nd_table[] */ 549 if (nd->used) { 550 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 551 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 552 } 553 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 554 &error_abort); 555 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, 556 &error_abort); 557 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 558 &error_abort); 559 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { 560 return; 561 } 562 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 563 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 564 gic_spi[gem_intr[i]]); 565 } 566 567 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 568 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 569 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 570 return; 571 } 572 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 573 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 574 gic_spi[uart_intr[i]]); 575 } 576 577 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { 578 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", 579 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); 580 581 object_property_set_link(OBJECT(&s->can[i]), "canbus", 582 OBJECT(s->canbus[i]), &error_fatal); 583 584 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); 585 if (err) { 586 error_propagate(errp, err); 587 return; 588 } 589 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); 590 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, 591 gic_spi[can_intr[i]]); 592 } 593 594 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 595 &error_abort); 596 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 597 return; 598 } 599 600 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 601 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 602 603 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 604 char *bus_name; 605 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 606 Object *sdhci = OBJECT(&s->sdhci[i]); 607 608 /* 609 * Compatible with: 610 * - SD Host Controller Specification Version 3.00 611 * - SDIO Specification Version 3.0 612 * - eMMC Specification Version 4.51 613 */ 614 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { 615 return; 616 } 617 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, 618 errp)) { 619 return; 620 } 621 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { 622 return; 623 } 624 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { 625 return; 626 } 627 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 628 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 629 630 /* Alias controller SD bus to the SoC itself */ 631 bus_name = g_strdup_printf("sd-bus%d", i); 632 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 633 g_free(bus_name); 634 } 635 636 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 637 gchar *bus_name; 638 639 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 640 return; 641 } 642 643 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 644 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 645 gic_spi[spi_intr[i]]); 646 647 /* Alias controller SPI bus to the SoC itself */ 648 bus_name = g_strdup_printf("spi%d", i); 649 object_property_add_alias(OBJECT(s), bus_name, 650 OBJECT(&s->spi[i]), "spi0"); 651 g_free(bus_name); 652 } 653 654 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { 655 return; 656 } 657 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 658 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 659 660 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { 661 return; 662 } 663 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 664 &error_abort); 665 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 666 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 667 668 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { 669 return; 670 } 671 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 672 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 673 674 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 675 return; 676 } 677 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 678 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 679 680 xlnx_zynqmp_create_bbram(s, gic_spi); 681 xlnx_zynqmp_create_efuse(s, gic_spi); 682 xlnx_zynqmp_create_unimp_mmio(s); 683 684 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 685 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, 686 errp)) { 687 return; 688 } 689 if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", 690 OBJECT(system_memory), errp)) { 691 return; 692 } 693 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { 694 return; 695 } 696 697 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 698 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 699 gic_spi[gdma_ch_intr[i]]); 700 } 701 702 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 703 if (!object_property_set_link(OBJECT(&s->adma[i]), "dma", 704 OBJECT(system_memory), errp)) { 705 return; 706 } 707 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { 708 return; 709 } 710 711 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 712 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 713 gic_spi[adma_ch_intr[i]]); 714 } 715 716 object_property_set_int(OBJECT(&s->qspi_irq_orgate), 717 "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal); 718 qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal); 719 qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]); 720 721 if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma", 722 OBJECT(system_memory), errp)) { 723 return; 724 } 725 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { 726 return; 727 } 728 729 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); 730 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, 731 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); 732 733 if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", 734 OBJECT(&s->qspi_dma), errp)) { 735 return; 736 } 737 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { 738 return; 739 } 740 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 741 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 742 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, 743 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1)); 744 745 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 746 g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i); 747 g_autofree gchar *target_bus = g_strdup_printf("spi%d", i); 748 749 /* Alias controller SPI bus to the SoC itself */ 750 object_property_add_alias(OBJECT(s), bus_name, 751 OBJECT(&s->qspi), target_bus); 752 } 753 } 754 755 static Property xlnx_zynqmp_props[] = { 756 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 757 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 758 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 759 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 760 MemoryRegion *), 761 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, 762 CanBusState *), 763 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, 764 CanBusState *), 765 DEFINE_PROP_END_OF_LIST() 766 }; 767 768 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 769 { 770 DeviceClass *dc = DEVICE_CLASS(oc); 771 772 device_class_set_props(dc, xlnx_zynqmp_props); 773 dc->realize = xlnx_zynqmp_realize; 774 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 775 dc->user_creatable = false; 776 } 777 778 static const TypeInfo xlnx_zynqmp_type_info = { 779 .name = TYPE_XLNX_ZYNQMP, 780 .parent = TYPE_DEVICE, 781 .instance_size = sizeof(XlnxZynqMPState), 782 .instance_init = xlnx_zynqmp_init, 783 .class_init = xlnx_zynqmp_class_init, 784 }; 785 786 static void xlnx_zynqmp_register_types(void) 787 { 788 type_register_static(&xlnx_zynqmp_type_info); 789 } 790 791 type_init(xlnx_zynqmp_register_types) 792