1 /* 2 * Copyright (C) 2006 InnoTek Systemberatung GmbH 3 * 4 * This file is part of VirtualBox Open Source Edition (OSE), as 5 * available from http://www.virtualbox.org. This file is free software; 6 * you can redistribute it and/or modify it under the terms of the GNU 7 * General Public License as published by the Free Software Foundation, 8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE 9 * distribution. VirtualBox OSE is distributed in the hope that it will 10 * be useful, but WITHOUT ANY WARRANTY of any kind. 11 * 12 * If you received this file as part of a commercial VirtualBox 13 * distribution, then only the terms of your commercial VirtualBox 14 * license agreement apply instead of the previous paragraph. 15 * 16 * Contributions after 2012-01-13 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "hw/audio/soundhw.h" 23 #include "audio/audio.h" 24 #include "hw/pci/pci.h" 25 #include "sysemu/dma.h" 26 27 enum { 28 AC97_Reset = 0x00, 29 AC97_Master_Volume_Mute = 0x02, 30 AC97_Headphone_Volume_Mute = 0x04, 31 AC97_Master_Volume_Mono_Mute = 0x06, 32 AC97_Master_Tone_RL = 0x08, 33 AC97_PC_BEEP_Volume_Mute = 0x0A, 34 AC97_Phone_Volume_Mute = 0x0C, 35 AC97_Mic_Volume_Mute = 0x0E, 36 AC97_Line_In_Volume_Mute = 0x10, 37 AC97_CD_Volume_Mute = 0x12, 38 AC97_Video_Volume_Mute = 0x14, 39 AC97_Aux_Volume_Mute = 0x16, 40 AC97_PCM_Out_Volume_Mute = 0x18, 41 AC97_Record_Select = 0x1A, 42 AC97_Record_Gain_Mute = 0x1C, 43 AC97_Record_Gain_Mic_Mute = 0x1E, 44 AC97_General_Purpose = 0x20, 45 AC97_3D_Control = 0x22, 46 AC97_AC_97_RESERVED = 0x24, 47 AC97_Powerdown_Ctrl_Stat = 0x26, 48 AC97_Extended_Audio_ID = 0x28, 49 AC97_Extended_Audio_Ctrl_Stat = 0x2A, 50 AC97_PCM_Front_DAC_Rate = 0x2C, 51 AC97_PCM_Surround_DAC_Rate = 0x2E, 52 AC97_PCM_LFE_DAC_Rate = 0x30, 53 AC97_PCM_LR_ADC_Rate = 0x32, 54 AC97_MIC_ADC_Rate = 0x34, 55 AC97_6Ch_Vol_C_LFE_Mute = 0x36, 56 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38, 57 AC97_Vendor_Reserved = 0x58, 58 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */ 59 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */ 60 AC97_Vendor_ID1 = 0x7c, 61 AC97_Vendor_ID2 = 0x7e 62 }; 63 64 #define SOFT_VOLUME 65 #define SR_FIFOE 16 /* rwc */ 66 #define SR_BCIS 8 /* rwc */ 67 #define SR_LVBCI 4 /* rwc */ 68 #define SR_CELV 2 /* ro */ 69 #define SR_DCH 1 /* ro */ 70 #define SR_VALID_MASK ((1 << 5) - 1) 71 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 72 #define SR_RO_MASK (SR_DCH | SR_CELV) 73 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 74 75 #define CR_IOCE 16 /* rw */ 76 #define CR_FEIE 8 /* rw */ 77 #define CR_LVBIE 4 /* rw */ 78 #define CR_RR 2 /* rw */ 79 #define CR_RPBM 1 /* rw */ 80 #define CR_VALID_MASK ((1 << 5) - 1) 81 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) 82 83 #define GC_WR 4 /* rw */ 84 #define GC_CR 2 /* rw */ 85 #define GC_VALID_MASK ((1 << 6) - 1) 86 87 #define GS_MD3 (1<<17) /* rw */ 88 #define GS_AD3 (1<<16) /* rw */ 89 #define GS_RCS (1<<15) /* rwc */ 90 #define GS_B3S12 (1<<14) /* ro */ 91 #define GS_B2S12 (1<<13) /* ro */ 92 #define GS_B1S12 (1<<12) /* ro */ 93 #define GS_S1R1 (1<<11) /* rwc */ 94 #define GS_S0R1 (1<<10) /* rwc */ 95 #define GS_S1CR (1<<9) /* ro */ 96 #define GS_S0CR (1<<8) /* ro */ 97 #define GS_MINT (1<<7) /* ro */ 98 #define GS_POINT (1<<6) /* ro */ 99 #define GS_PIINT (1<<5) /* ro */ 100 #define GS_RSRVD ((1<<4)|(1<<3)) 101 #define GS_MOINT (1<<2) /* ro */ 102 #define GS_MIINT (1<<1) /* ro */ 103 #define GS_GSCI 1 /* rwc */ 104 #define GS_RO_MASK (GS_B3S12| \ 105 GS_B2S12| \ 106 GS_B1S12| \ 107 GS_S1CR| \ 108 GS_S0CR| \ 109 GS_MINT| \ 110 GS_POINT| \ 111 GS_PIINT| \ 112 GS_RSRVD| \ 113 GS_MOINT| \ 114 GS_MIINT) 115 #define GS_VALID_MASK ((1 << 18) - 1) 116 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI) 117 118 #define BD_IOC (1<<31) 119 #define BD_BUP (1<<30) 120 121 #define EACS_VRA 1 122 #define EACS_VRM 8 123 124 #define MUTE_SHIFT 15 125 126 #define TYPE_AC97 "AC97" 127 #define AC97(obj) \ 128 OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97) 129 130 #define REC_MASK 7 131 enum { 132 REC_MIC = 0, 133 REC_CD, 134 REC_VIDEO, 135 REC_AUX, 136 REC_LINE_IN, 137 REC_STEREO_MIX, 138 REC_MONO_MIX, 139 REC_PHONE 140 }; 141 142 typedef struct BD { 143 uint32_t addr; 144 uint32_t ctl_len; 145 } BD; 146 147 typedef struct AC97BusMasterRegs { 148 uint32_t bdbar; /* rw 0 */ 149 uint8_t civ; /* ro 0 */ 150 uint8_t lvi; /* rw 0 */ 151 uint16_t sr; /* rw 1 */ 152 uint16_t picb; /* ro 0 */ 153 uint8_t piv; /* ro 0 */ 154 uint8_t cr; /* rw 0 */ 155 unsigned int bd_valid; 156 BD bd; 157 } AC97BusMasterRegs; 158 159 typedef struct AC97LinkState { 160 PCIDevice dev; 161 QEMUSoundCard card; 162 uint32_t use_broken_id; 163 uint32_t glob_cnt; 164 uint32_t glob_sta; 165 uint32_t cas; 166 uint32_t last_samp; 167 AC97BusMasterRegs bm_regs[3]; 168 uint8_t mixer_data[256]; 169 SWVoiceIn *voice_pi; 170 SWVoiceOut *voice_po; 171 SWVoiceIn *voice_mc; 172 int invalid_freq[3]; 173 uint8_t silence[128]; 174 int bup_flag; 175 MemoryRegion io_nam; 176 MemoryRegion io_nabm; 177 } AC97LinkState; 178 179 enum { 180 BUP_SET = 1, 181 BUP_LAST = 2 182 }; 183 184 #ifdef DEBUG_AC97 185 #define dolog(...) AUD_log ("ac97", __VA_ARGS__) 186 #else 187 #define dolog(...) 188 #endif 189 190 #define MKREGS(prefix, start) \ 191 enum { \ 192 prefix ## _BDBAR = start, \ 193 prefix ## _CIV = start + 4, \ 194 prefix ## _LVI = start + 5, \ 195 prefix ## _SR = start + 6, \ 196 prefix ## _PICB = start + 8, \ 197 prefix ## _PIV = start + 10, \ 198 prefix ## _CR = start + 11 \ 199 } 200 201 enum { 202 PI_INDEX = 0, 203 PO_INDEX, 204 MC_INDEX, 205 LAST_INDEX 206 }; 207 208 MKREGS (PI, PI_INDEX * 16); 209 MKREGS (PO, PO_INDEX * 16); 210 MKREGS (MC, MC_INDEX * 16); 211 212 enum { 213 GLOB_CNT = 0x2c, 214 GLOB_STA = 0x30, 215 CAS = 0x34 216 }; 217 218 #define GET_BM(index) (((index) >> 4) & 3) 219 220 static void po_callback (void *opaque, int free); 221 static void pi_callback (void *opaque, int avail); 222 static void mc_callback (void *opaque, int avail); 223 224 static void warm_reset (AC97LinkState *s) 225 { 226 (void) s; 227 } 228 229 static void cold_reset (AC97LinkState * s) 230 { 231 (void) s; 232 } 233 234 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r) 235 { 236 uint8_t b[8]; 237 238 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8); 239 r->bd_valid = 1; 240 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3; 241 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]); 242 r->picb = r->bd.ctl_len & 0xffff; 243 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 244 r->civ, r->bd.addr, r->bd.ctl_len >> 16, 245 r->bd.ctl_len & 0xffff, 246 (r->bd.ctl_len & 0xffff) << 1); 247 } 248 249 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) 250 { 251 int event = 0; 252 int level = 0; 253 uint32_t new_mask = new_sr & SR_INT_MASK; 254 uint32_t old_mask = r->sr & SR_INT_MASK; 255 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT}; 256 257 if (new_mask ^ old_mask) { 258 /** @todo is IRQ deasserted when only one of status bits is cleared? */ 259 if (!new_mask) { 260 event = 1; 261 level = 0; 262 } 263 else { 264 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) { 265 event = 1; 266 level = 1; 267 } 268 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) { 269 event = 1; 270 level = 1; 271 } 272 } 273 } 274 275 r->sr = new_sr; 276 277 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n", 278 r->sr & SR_BCIS, r->sr & SR_LVBCI, 279 r->sr, 280 event, level); 281 282 if (!event) 283 return; 284 285 if (level) { 286 s->glob_sta |= masks[r - s->bm_regs]; 287 dolog ("set irq level=1\n"); 288 pci_irq_assert(&s->dev); 289 } 290 else { 291 s->glob_sta &= ~masks[r - s->bm_regs]; 292 dolog ("set irq level=0\n"); 293 pci_irq_deassert(&s->dev); 294 } 295 } 296 297 static void voice_set_active (AC97LinkState *s, int bm_index, int on) 298 { 299 switch (bm_index) { 300 case PI_INDEX: 301 AUD_set_active_in (s->voice_pi, on); 302 break; 303 304 case PO_INDEX: 305 AUD_set_active_out (s->voice_po, on); 306 break; 307 308 case MC_INDEX: 309 AUD_set_active_in (s->voice_mc, on); 310 break; 311 312 default: 313 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index); 314 break; 315 } 316 } 317 318 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r) 319 { 320 dolog ("reset_bm_regs\n"); 321 r->bdbar = 0; 322 r->civ = 0; 323 r->lvi = 0; 324 /** todo do we need to do that? */ 325 update_sr (s, r, SR_DCH); 326 r->picb = 0; 327 r->piv = 0; 328 r->cr = r->cr & CR_DONT_CLEAR_MASK; 329 r->bd_valid = 0; 330 331 voice_set_active (s, r - s->bm_regs, 0); 332 memset (s->silence, 0, sizeof (s->silence)); 333 } 334 335 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v) 336 { 337 if (i + 2 > sizeof (s->mixer_data)) { 338 dolog ("mixer_store: index %d out of bounds %zd\n", 339 i, sizeof (s->mixer_data)); 340 return; 341 } 342 343 s->mixer_data[i + 0] = v & 0xff; 344 s->mixer_data[i + 1] = v >> 8; 345 } 346 347 static uint16_t mixer_load (AC97LinkState *s, uint32_t i) 348 { 349 uint16_t val = 0xffff; 350 351 if (i + 2 > sizeof (s->mixer_data)) { 352 dolog ("mixer_load: index %d out of bounds %zd\n", 353 i, sizeof (s->mixer_data)); 354 } 355 else { 356 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8); 357 } 358 359 return val; 360 } 361 362 static void open_voice (AC97LinkState *s, int index, int freq) 363 { 364 struct audsettings as; 365 366 as.freq = freq; 367 as.nchannels = 2; 368 as.fmt = AUDIO_FORMAT_S16; 369 as.endianness = 0; 370 371 if (freq > 0) { 372 s->invalid_freq[index] = 0; 373 switch (index) { 374 case PI_INDEX: 375 s->voice_pi = AUD_open_in ( 376 &s->card, 377 s->voice_pi, 378 "ac97.pi", 379 s, 380 pi_callback, 381 &as 382 ); 383 break; 384 385 case PO_INDEX: 386 s->voice_po = AUD_open_out ( 387 &s->card, 388 s->voice_po, 389 "ac97.po", 390 s, 391 po_callback, 392 &as 393 ); 394 break; 395 396 case MC_INDEX: 397 s->voice_mc = AUD_open_in ( 398 &s->card, 399 s->voice_mc, 400 "ac97.mc", 401 s, 402 mc_callback, 403 &as 404 ); 405 break; 406 } 407 } 408 else { 409 s->invalid_freq[index] = freq; 410 switch (index) { 411 case PI_INDEX: 412 AUD_close_in (&s->card, s->voice_pi); 413 s->voice_pi = NULL; 414 break; 415 416 case PO_INDEX: 417 AUD_close_out (&s->card, s->voice_po); 418 s->voice_po = NULL; 419 break; 420 421 case MC_INDEX: 422 AUD_close_in (&s->card, s->voice_mc); 423 s->voice_mc = NULL; 424 break; 425 } 426 } 427 } 428 429 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX]) 430 { 431 uint16_t freq; 432 433 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate); 434 open_voice (s, PI_INDEX, freq); 435 AUD_set_active_in (s->voice_pi, active[PI_INDEX]); 436 437 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate); 438 open_voice (s, PO_INDEX, freq); 439 AUD_set_active_out (s->voice_po, active[PO_INDEX]); 440 441 freq = mixer_load (s, AC97_MIC_ADC_Rate); 442 open_voice (s, MC_INDEX, freq); 443 AUD_set_active_in (s->voice_mc, active[MC_INDEX]); 444 } 445 446 static void get_volume (uint16_t vol, uint16_t mask, int inverse, 447 int *mute, uint8_t *lvol, uint8_t *rvol) 448 { 449 *mute = (vol >> MUTE_SHIFT) & 1; 450 *rvol = (255 * (vol & mask)) / mask; 451 *lvol = (255 * ((vol >> 8) & mask)) / mask; 452 453 if (inverse) { 454 *rvol = 255 - *rvol; 455 *lvol = 255 - *lvol; 456 } 457 } 458 459 static void update_combined_volume_out (AC97LinkState *s) 460 { 461 uint8_t lvol, rvol, plvol, prvol; 462 int mute, pmute; 463 464 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1, 465 &mute, &lvol, &rvol); 466 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1, 467 &pmute, &plvol, &prvol); 468 469 mute = mute | pmute; 470 lvol = (lvol * plvol) / 255; 471 rvol = (rvol * prvol) / 255; 472 473 AUD_set_volume_out (s->voice_po, mute, lvol, rvol); 474 } 475 476 static void update_volume_in (AC97LinkState *s) 477 { 478 uint8_t lvol, rvol; 479 int mute; 480 481 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0, 482 &mute, &lvol, &rvol); 483 484 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol); 485 } 486 487 static void set_volume (AC97LinkState *s, int index, uint32_t val) 488 { 489 switch (index) { 490 case AC97_Master_Volume_Mute: 491 val &= 0xbf3f; 492 mixer_store (s, index, val); 493 update_combined_volume_out (s); 494 break; 495 case AC97_PCM_Out_Volume_Mute: 496 val &= 0x9f1f; 497 mixer_store (s, index, val); 498 update_combined_volume_out (s); 499 break; 500 case AC97_Record_Gain_Mute: 501 val &= 0x8f0f; 502 mixer_store (s, index, val); 503 update_volume_in (s); 504 break; 505 } 506 } 507 508 static void record_select (AC97LinkState *s, uint32_t val) 509 { 510 uint8_t rs = val & REC_MASK; 511 uint8_t ls = (val >> 8) & REC_MASK; 512 mixer_store (s, AC97_Record_Select, rs | (ls << 8)); 513 } 514 515 static void mixer_reset (AC97LinkState *s) 516 { 517 uint8_t active[LAST_INDEX]; 518 519 dolog ("mixer_reset\n"); 520 memset (s->mixer_data, 0, sizeof (s->mixer_data)); 521 memset (active, 0, sizeof (active)); 522 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */ 523 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000); 524 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000); 525 mixer_store (s, AC97_Master_Tone_RL, 0x0000); 526 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000); 527 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000); 528 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000); 529 mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000); 530 mixer_store (s, AC97_CD_Volume_Mute , 0x0000); 531 mixer_store (s, AC97_Video_Volume_Mute , 0x0000); 532 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000); 533 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000); 534 mixer_store (s, AC97_General_Purpose , 0x0000); 535 mixer_store (s, AC97_3D_Control , 0x0000); 536 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f); 537 538 /* 539 * Sigmatel 9700 (STAC9700) 540 */ 541 mixer_store (s, AC97_Vendor_ID1 , 0x8384); 542 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */ 543 544 mixer_store (s, AC97_Extended_Audio_ID , 0x0809); 545 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009); 546 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80); 547 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80); 548 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80); 549 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80); 550 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80); 551 552 record_select (s, 0); 553 set_volume (s, AC97_Master_Volume_Mute, 0x8000); 554 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808); 555 set_volume (s, AC97_Record_Gain_Mute, 0x8808); 556 557 reset_voices (s, active); 558 } 559 560 /** 561 * Native audio mixer 562 * I/O Reads 563 */ 564 static uint32_t nam_readb (void *opaque, uint32_t addr) 565 { 566 AC97LinkState *s = opaque; 567 dolog ("U nam readb %#x\n", addr); 568 s->cas = 0; 569 return ~0U; 570 } 571 572 static uint32_t nam_readw (void *opaque, uint32_t addr) 573 { 574 AC97LinkState *s = opaque; 575 uint32_t val = ~0U; 576 uint32_t index = addr; 577 s->cas = 0; 578 val = mixer_load (s, index); 579 return val; 580 } 581 582 static uint32_t nam_readl (void *opaque, uint32_t addr) 583 { 584 AC97LinkState *s = opaque; 585 dolog ("U nam readl %#x\n", addr); 586 s->cas = 0; 587 return ~0U; 588 } 589 590 /** 591 * Native audio mixer 592 * I/O Writes 593 */ 594 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) 595 { 596 AC97LinkState *s = opaque; 597 dolog ("U nam writeb %#x <- %#x\n", addr, val); 598 s->cas = 0; 599 } 600 601 static void nam_writew (void *opaque, uint32_t addr, uint32_t val) 602 { 603 AC97LinkState *s = opaque; 604 uint32_t index = addr; 605 s->cas = 0; 606 switch (index) { 607 case AC97_Reset: 608 mixer_reset (s); 609 break; 610 case AC97_Powerdown_Ctrl_Stat: 611 val &= ~0x800f; 612 val |= mixer_load (s, index) & 0xf; 613 mixer_store (s, index, val); 614 break; 615 case AC97_PCM_Out_Volume_Mute: 616 case AC97_Master_Volume_Mute: 617 case AC97_Record_Gain_Mute: 618 set_volume (s, index, val); 619 break; 620 case AC97_Record_Select: 621 record_select (s, val); 622 break; 623 case AC97_Vendor_ID1: 624 case AC97_Vendor_ID2: 625 dolog ("Attempt to write vendor ID to %#x\n", val); 626 break; 627 case AC97_Extended_Audio_ID: 628 dolog ("Attempt to write extended audio ID to %#x\n", val); 629 break; 630 case AC97_Extended_Audio_Ctrl_Stat: 631 if (!(val & EACS_VRA)) { 632 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80); 633 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80); 634 open_voice (s, PI_INDEX, 48000); 635 open_voice (s, PO_INDEX, 48000); 636 } 637 if (!(val & EACS_VRM)) { 638 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80); 639 open_voice (s, MC_INDEX, 48000); 640 } 641 dolog ("Setting extended audio control to %#x\n", val); 642 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val); 643 break; 644 case AC97_PCM_Front_DAC_Rate: 645 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 646 mixer_store (s, index, val); 647 dolog ("Set front DAC rate to %d\n", val); 648 open_voice (s, PO_INDEX, val); 649 } 650 else { 651 dolog ("Attempt to set front DAC rate to %d, " 652 "but VRA is not set\n", 653 val); 654 } 655 break; 656 case AC97_MIC_ADC_Rate: 657 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) { 658 mixer_store (s, index, val); 659 dolog ("Set MIC ADC rate to %d\n", val); 660 open_voice (s, MC_INDEX, val); 661 } 662 else { 663 dolog ("Attempt to set MIC ADC rate to %d, " 664 "but VRM is not set\n", 665 val); 666 } 667 break; 668 case AC97_PCM_LR_ADC_Rate: 669 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { 670 mixer_store (s, index, val); 671 dolog ("Set front LR ADC rate to %d\n", val); 672 open_voice (s, PI_INDEX, val); 673 } 674 else { 675 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n", 676 val); 677 } 678 break; 679 case AC97_Headphone_Volume_Mute: 680 case AC97_Master_Volume_Mono_Mute: 681 case AC97_Master_Tone_RL: 682 case AC97_PC_BEEP_Volume_Mute: 683 case AC97_Phone_Volume_Mute: 684 case AC97_Mic_Volume_Mute: 685 case AC97_Line_In_Volume_Mute: 686 case AC97_CD_Volume_Mute: 687 case AC97_Video_Volume_Mute: 688 case AC97_Aux_Volume_Mute: 689 case AC97_Record_Gain_Mic_Mute: 690 case AC97_General_Purpose: 691 case AC97_3D_Control: 692 case AC97_Sigmatel_Analog: 693 case AC97_Sigmatel_Dac2Invert: 694 /* None of the features in these regs are emulated, so they are RO */ 695 break; 696 default: 697 dolog ("U nam writew %#x <- %#x\n", addr, val); 698 mixer_store (s, index, val); 699 break; 700 } 701 } 702 703 static void nam_writel (void *opaque, uint32_t addr, uint32_t val) 704 { 705 AC97LinkState *s = opaque; 706 dolog ("U nam writel %#x <- %#x\n", addr, val); 707 s->cas = 0; 708 } 709 710 /** 711 * Native audio bus master 712 * I/O Reads 713 */ 714 static uint32_t nabm_readb (void *opaque, uint32_t addr) 715 { 716 AC97LinkState *s = opaque; 717 AC97BusMasterRegs *r = NULL; 718 uint32_t index = addr; 719 uint32_t val = ~0U; 720 721 switch (index) { 722 case CAS: 723 dolog ("CAS %d\n", s->cas); 724 val = s->cas; 725 s->cas = 1; 726 break; 727 case PI_CIV: 728 case PO_CIV: 729 case MC_CIV: 730 r = &s->bm_regs[GET_BM (index)]; 731 val = r->civ; 732 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val); 733 break; 734 case PI_LVI: 735 case PO_LVI: 736 case MC_LVI: 737 r = &s->bm_regs[GET_BM (index)]; 738 val = r->lvi; 739 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val); 740 break; 741 case PI_PIV: 742 case PO_PIV: 743 case MC_PIV: 744 r = &s->bm_regs[GET_BM (index)]; 745 val = r->piv; 746 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val); 747 break; 748 case PI_CR: 749 case PO_CR: 750 case MC_CR: 751 r = &s->bm_regs[GET_BM (index)]; 752 val = r->cr; 753 dolog ("CR[%d] -> %#x\n", GET_BM (index), val); 754 break; 755 case PI_SR: 756 case PO_SR: 757 case MC_SR: 758 r = &s->bm_regs[GET_BM (index)]; 759 val = r->sr & 0xff; 760 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val); 761 break; 762 default: 763 dolog ("U nabm readb %#x -> %#x\n", addr, val); 764 break; 765 } 766 return val; 767 } 768 769 static uint32_t nabm_readw (void *opaque, uint32_t addr) 770 { 771 AC97LinkState *s = opaque; 772 AC97BusMasterRegs *r = NULL; 773 uint32_t index = addr; 774 uint32_t val = ~0U; 775 776 switch (index) { 777 case PI_SR: 778 case PO_SR: 779 case MC_SR: 780 r = &s->bm_regs[GET_BM (index)]; 781 val = r->sr; 782 dolog ("SR[%d] -> %#x\n", GET_BM (index), val); 783 break; 784 case PI_PICB: 785 case PO_PICB: 786 case MC_PICB: 787 r = &s->bm_regs[GET_BM (index)]; 788 val = r->picb; 789 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val); 790 break; 791 default: 792 dolog ("U nabm readw %#x -> %#x\n", addr, val); 793 break; 794 } 795 return val; 796 } 797 798 static uint32_t nabm_readl (void *opaque, uint32_t addr) 799 { 800 AC97LinkState *s = opaque; 801 AC97BusMasterRegs *r = NULL; 802 uint32_t index = addr; 803 uint32_t val = ~0U; 804 805 switch (index) { 806 case PI_BDBAR: 807 case PO_BDBAR: 808 case MC_BDBAR: 809 r = &s->bm_regs[GET_BM (index)]; 810 val = r->bdbar; 811 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val); 812 break; 813 case PI_CIV: 814 case PO_CIV: 815 case MC_CIV: 816 r = &s->bm_regs[GET_BM (index)]; 817 val = r->civ | (r->lvi << 8) | (r->sr << 16); 818 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index), 819 r->civ, r->lvi, r->sr); 820 break; 821 case PI_PICB: 822 case PO_PICB: 823 case MC_PICB: 824 r = &s->bm_regs[GET_BM (index)]; 825 val = r->picb | (r->piv << 16) | (r->cr << 24); 826 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index), 827 val, r->picb, r->piv, r->cr); 828 break; 829 case GLOB_CNT: 830 val = s->glob_cnt; 831 dolog ("glob_cnt -> %#x\n", val); 832 break; 833 case GLOB_STA: 834 val = s->glob_sta | GS_S0CR; 835 dolog ("glob_sta -> %#x\n", val); 836 break; 837 default: 838 dolog ("U nabm readl %#x -> %#x\n", addr, val); 839 break; 840 } 841 return val; 842 } 843 844 /** 845 * Native audio bus master 846 * I/O Writes 847 */ 848 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) 849 { 850 AC97LinkState *s = opaque; 851 AC97BusMasterRegs *r = NULL; 852 uint32_t index = addr; 853 switch (index) { 854 case PI_LVI: 855 case PO_LVI: 856 case MC_LVI: 857 r = &s->bm_regs[GET_BM (index)]; 858 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { 859 r->sr &= ~(SR_DCH | SR_CELV); 860 r->civ = r->piv; 861 r->piv = (r->piv + 1) % 32; 862 fetch_bd (s, r); 863 } 864 r->lvi = val % 32; 865 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val); 866 break; 867 case PI_CR: 868 case PO_CR: 869 case MC_CR: 870 r = &s->bm_regs[GET_BM (index)]; 871 if (val & CR_RR) { 872 reset_bm_regs (s, r); 873 } 874 else { 875 r->cr = val & CR_VALID_MASK; 876 if (!(r->cr & CR_RPBM)) { 877 voice_set_active (s, r - s->bm_regs, 0); 878 r->sr |= SR_DCH; 879 } 880 else { 881 r->civ = r->piv; 882 r->piv = (r->piv + 1) % 32; 883 fetch_bd (s, r); 884 r->sr &= ~SR_DCH; 885 voice_set_active (s, r - s->bm_regs, 1); 886 } 887 } 888 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr); 889 break; 890 case PI_SR: 891 case PO_SR: 892 case MC_SR: 893 r = &s->bm_regs[GET_BM (index)]; 894 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 895 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 896 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 897 break; 898 default: 899 dolog ("U nabm writeb %#x <- %#x\n", addr, val); 900 break; 901 } 902 } 903 904 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) 905 { 906 AC97LinkState *s = opaque; 907 AC97BusMasterRegs *r = NULL; 908 uint32_t index = addr; 909 switch (index) { 910 case PI_SR: 911 case PO_SR: 912 case MC_SR: 913 r = &s->bm_regs[GET_BM (index)]; 914 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK); 915 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK)); 916 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr); 917 break; 918 default: 919 dolog ("U nabm writew %#x <- %#x\n", addr, val); 920 break; 921 } 922 } 923 924 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) 925 { 926 AC97LinkState *s = opaque; 927 AC97BusMasterRegs *r = NULL; 928 uint32_t index = addr; 929 switch (index) { 930 case PI_BDBAR: 931 case PO_BDBAR: 932 case MC_BDBAR: 933 r = &s->bm_regs[GET_BM (index)]; 934 r->bdbar = val & ~3; 935 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n", 936 GET_BM (index), val, r->bdbar); 937 break; 938 case GLOB_CNT: 939 if (val & GC_WR) 940 warm_reset (s); 941 if (val & GC_CR) 942 cold_reset (s); 943 if (!(val & (GC_WR | GC_CR))) 944 s->glob_cnt = val & GC_VALID_MASK; 945 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt); 946 break; 947 case GLOB_STA: 948 s->glob_sta &= ~(val & GS_WCLEAR_MASK); 949 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; 950 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta); 951 break; 952 default: 953 dolog ("U nabm writel %#x <- %#x\n", addr, val); 954 break; 955 } 956 } 957 958 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, 959 int max, int *stop) 960 { 961 uint8_t tmpbuf[4096]; 962 uint32_t addr = r->bd.addr; 963 uint32_t temp = r->picb << 1; 964 uint32_t written = 0; 965 int to_copy = 0; 966 temp = audio_MIN (temp, max); 967 968 if (!temp) { 969 *stop = 1; 970 return 0; 971 } 972 973 while (temp) { 974 int copied; 975 to_copy = audio_MIN (temp, sizeof (tmpbuf)); 976 pci_dma_read (&s->dev, addr, tmpbuf, to_copy); 977 copied = AUD_write (s->voice_po, tmpbuf, to_copy); 978 dolog ("write_audio max=%x to_copy=%x copied=%x\n", 979 max, to_copy, copied); 980 if (!copied) { 981 *stop = 1; 982 break; 983 } 984 temp -= copied; 985 addr += copied; 986 written += copied; 987 } 988 989 if (!temp) { 990 if (to_copy < 4) { 991 dolog ("whoops\n"); 992 s->last_samp = 0; 993 } 994 else { 995 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4]; 996 } 997 } 998 999 r->bd.addr = addr; 1000 return written; 1001 } 1002 1003 static void write_bup (AC97LinkState *s, int elapsed) 1004 { 1005 dolog ("write_bup\n"); 1006 if (!(s->bup_flag & BUP_SET)) { 1007 if (s->bup_flag & BUP_LAST) { 1008 int i; 1009 uint8_t *p = s->silence; 1010 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) { 1011 *(uint32_t *) p = s->last_samp; 1012 } 1013 } 1014 else { 1015 memset (s->silence, 0, sizeof (s->silence)); 1016 } 1017 s->bup_flag |= BUP_SET; 1018 } 1019 1020 while (elapsed) { 1021 int temp = audio_MIN (elapsed, sizeof (s->silence)); 1022 while (temp) { 1023 int copied = AUD_write (s->voice_po, s->silence, temp); 1024 if (!copied) 1025 return; 1026 temp -= copied; 1027 elapsed -= copied; 1028 } 1029 } 1030 } 1031 1032 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r, 1033 int max, int *stop) 1034 { 1035 uint8_t tmpbuf[4096]; 1036 uint32_t addr = r->bd.addr; 1037 uint32_t temp = r->picb << 1; 1038 uint32_t nread = 0; 1039 int to_copy = 0; 1040 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; 1041 1042 temp = audio_MIN (temp, max); 1043 1044 if (!temp) { 1045 *stop = 1; 1046 return 0; 1047 } 1048 1049 while (temp) { 1050 int acquired; 1051 to_copy = audio_MIN (temp, sizeof (tmpbuf)); 1052 acquired = AUD_read (voice, tmpbuf, to_copy); 1053 if (!acquired) { 1054 *stop = 1; 1055 break; 1056 } 1057 pci_dma_write (&s->dev, addr, tmpbuf, acquired); 1058 temp -= acquired; 1059 addr += acquired; 1060 nread += acquired; 1061 } 1062 1063 r->bd.addr = addr; 1064 return nread; 1065 } 1066 1067 static void transfer_audio (AC97LinkState *s, int index, int elapsed) 1068 { 1069 AC97BusMasterRegs *r = &s->bm_regs[index]; 1070 int stop = 0; 1071 1072 if (s->invalid_freq[index]) { 1073 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n", 1074 index, s->invalid_freq[index]); 1075 return; 1076 } 1077 1078 if (r->sr & SR_DCH) { 1079 if (r->cr & CR_RPBM) { 1080 switch (index) { 1081 case PO_INDEX: 1082 write_bup (s, elapsed); 1083 break; 1084 } 1085 } 1086 return; 1087 } 1088 1089 while ((elapsed >> 1) && !stop) { 1090 int temp; 1091 1092 if (!r->bd_valid) { 1093 dolog ("invalid bd\n"); 1094 fetch_bd (s, r); 1095 } 1096 1097 if (!r->picb) { 1098 dolog ("fresh bd %d is empty %#x %#x\n", 1099 r->civ, r->bd.addr, r->bd.ctl_len); 1100 if (r->civ == r->lvi) { 1101 r->sr |= SR_DCH; /* CELV? */ 1102 s->bup_flag = 0; 1103 break; 1104 } 1105 r->sr &= ~SR_CELV; 1106 r->civ = r->piv; 1107 r->piv = (r->piv + 1) % 32; 1108 fetch_bd (s, r); 1109 return; 1110 } 1111 1112 switch (index) { 1113 case PO_INDEX: 1114 temp = write_audio (s, r, elapsed, &stop); 1115 elapsed -= temp; 1116 r->picb -= (temp >> 1); 1117 break; 1118 1119 case PI_INDEX: 1120 case MC_INDEX: 1121 temp = read_audio (s, r, elapsed, &stop); 1122 elapsed -= temp; 1123 r->picb -= (temp >> 1); 1124 break; 1125 } 1126 1127 if (!r->picb) { 1128 uint32_t new_sr = r->sr & ~SR_CELV; 1129 1130 if (r->bd.ctl_len & BD_IOC) { 1131 new_sr |= SR_BCIS; 1132 } 1133 1134 if (r->civ == r->lvi) { 1135 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi); 1136 1137 new_sr |= SR_LVBCI | SR_DCH | SR_CELV; 1138 stop = 1; 1139 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0; 1140 } 1141 else { 1142 r->civ = r->piv; 1143 r->piv = (r->piv + 1) % 32; 1144 fetch_bd (s, r); 1145 } 1146 1147 update_sr (s, r, new_sr); 1148 } 1149 } 1150 } 1151 1152 static void pi_callback (void *opaque, int avail) 1153 { 1154 transfer_audio (opaque, PI_INDEX, avail); 1155 } 1156 1157 static void mc_callback (void *opaque, int avail) 1158 { 1159 transfer_audio (opaque, MC_INDEX, avail); 1160 } 1161 1162 static void po_callback (void *opaque, int free) 1163 { 1164 transfer_audio (opaque, PO_INDEX, free); 1165 } 1166 1167 static const VMStateDescription vmstate_ac97_bm_regs = { 1168 .name = "ac97_bm_regs", 1169 .version_id = 1, 1170 .minimum_version_id = 1, 1171 .fields = (VMStateField[]) { 1172 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs), 1173 VMSTATE_UINT8 (civ, AC97BusMasterRegs), 1174 VMSTATE_UINT8 (lvi, AC97BusMasterRegs), 1175 VMSTATE_UINT16 (sr, AC97BusMasterRegs), 1176 VMSTATE_UINT16 (picb, AC97BusMasterRegs), 1177 VMSTATE_UINT8 (piv, AC97BusMasterRegs), 1178 VMSTATE_UINT8 (cr, AC97BusMasterRegs), 1179 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs), 1180 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs), 1181 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs), 1182 VMSTATE_END_OF_LIST () 1183 } 1184 }; 1185 1186 static int ac97_post_load (void *opaque, int version_id) 1187 { 1188 uint8_t active[LAST_INDEX]; 1189 AC97LinkState *s = opaque; 1190 1191 record_select (s, mixer_load (s, AC97_Record_Select)); 1192 set_volume (s, AC97_Master_Volume_Mute, 1193 mixer_load (s, AC97_Master_Volume_Mute)); 1194 set_volume (s, AC97_PCM_Out_Volume_Mute, 1195 mixer_load (s, AC97_PCM_Out_Volume_Mute)); 1196 set_volume (s, AC97_Record_Gain_Mute, 1197 mixer_load (s, AC97_Record_Gain_Mute)); 1198 1199 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM); 1200 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM); 1201 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM); 1202 reset_voices (s, active); 1203 1204 s->bup_flag = 0; 1205 s->last_samp = 0; 1206 return 0; 1207 } 1208 1209 static bool is_version_2 (void *opaque, int version_id) 1210 { 1211 return version_id == 2; 1212 } 1213 1214 static const VMStateDescription vmstate_ac97 = { 1215 .name = "ac97", 1216 .version_id = 3, 1217 .minimum_version_id = 2, 1218 .post_load = ac97_post_load, 1219 .fields = (VMStateField[]) { 1220 VMSTATE_PCI_DEVICE (dev, AC97LinkState), 1221 VMSTATE_UINT32 (glob_cnt, AC97LinkState), 1222 VMSTATE_UINT32 (glob_sta, AC97LinkState), 1223 VMSTATE_UINT32 (cas, AC97LinkState), 1224 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1, 1225 vmstate_ac97_bm_regs, AC97BusMasterRegs), 1226 VMSTATE_BUFFER (mixer_data, AC97LinkState), 1227 VMSTATE_UNUSED_TEST (is_version_2, 3), 1228 VMSTATE_END_OF_LIST () 1229 } 1230 }; 1231 1232 static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size) 1233 { 1234 if ((addr / size) > 256) { 1235 return -1; 1236 } 1237 1238 switch (size) { 1239 case 1: 1240 return nam_readb(opaque, addr); 1241 case 2: 1242 return nam_readw(opaque, addr); 1243 case 4: 1244 return nam_readl(opaque, addr); 1245 default: 1246 return -1; 1247 } 1248 } 1249 1250 static void nam_write(void *opaque, hwaddr addr, uint64_t val, 1251 unsigned size) 1252 { 1253 if ((addr / size) > 256) { 1254 return; 1255 } 1256 1257 switch (size) { 1258 case 1: 1259 nam_writeb(opaque, addr, val); 1260 break; 1261 case 2: 1262 nam_writew(opaque, addr, val); 1263 break; 1264 case 4: 1265 nam_writel(opaque, addr, val); 1266 break; 1267 } 1268 } 1269 1270 static const MemoryRegionOps ac97_io_nam_ops = { 1271 .read = nam_read, 1272 .write = nam_write, 1273 .impl = { 1274 .min_access_size = 1, 1275 .max_access_size = 4, 1276 }, 1277 .endianness = DEVICE_LITTLE_ENDIAN, 1278 }; 1279 1280 static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) 1281 { 1282 if ((addr / size) > 64) { 1283 return -1; 1284 } 1285 1286 switch (size) { 1287 case 1: 1288 return nabm_readb(opaque, addr); 1289 case 2: 1290 return nabm_readw(opaque, addr); 1291 case 4: 1292 return nabm_readl(opaque, addr); 1293 default: 1294 return -1; 1295 } 1296 } 1297 1298 static void nabm_write(void *opaque, hwaddr addr, uint64_t val, 1299 unsigned size) 1300 { 1301 if ((addr / size) > 64) { 1302 return; 1303 } 1304 1305 switch (size) { 1306 case 1: 1307 nabm_writeb(opaque, addr, val); 1308 break; 1309 case 2: 1310 nabm_writew(opaque, addr, val); 1311 break; 1312 case 4: 1313 nabm_writel(opaque, addr, val); 1314 break; 1315 } 1316 } 1317 1318 1319 static const MemoryRegionOps ac97_io_nabm_ops = { 1320 .read = nabm_read, 1321 .write = nabm_write, 1322 .impl = { 1323 .min_access_size = 1, 1324 .max_access_size = 4, 1325 }, 1326 .endianness = DEVICE_LITTLE_ENDIAN, 1327 }; 1328 1329 static void ac97_on_reset (DeviceState *dev) 1330 { 1331 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev); 1332 1333 reset_bm_regs (s, &s->bm_regs[0]); 1334 reset_bm_regs (s, &s->bm_regs[1]); 1335 reset_bm_regs (s, &s->bm_regs[2]); 1336 1337 /* 1338 * Reset the mixer too. The Windows XP driver seems to rely on 1339 * this. At least it wants to read the vendor id before it resets 1340 * the codec manually. 1341 */ 1342 mixer_reset (s); 1343 } 1344 1345 static void ac97_realize(PCIDevice *dev, Error **errp) 1346 { 1347 AC97LinkState *s = AC97(dev); 1348 uint8_t *c = s->dev.config; 1349 1350 /* TODO: no need to override */ 1351 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */ 1352 c[PCI_COMMAND + 1] = 0x00; 1353 1354 /* TODO: */ 1355 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */ 1356 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 1357 1358 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */ 1359 1360 /* TODO set when bar is registered. no need to override. */ 1361 /* nabmar native audio mixer base address rw */ 1362 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO; 1363 c[PCI_BASE_ADDRESS_0 + 1] = 0x00; 1364 c[PCI_BASE_ADDRESS_0 + 2] = 0x00; 1365 c[PCI_BASE_ADDRESS_0 + 3] = 0x00; 1366 1367 /* TODO set when bar is registered. no need to override. */ 1368 /* nabmbar native audio bus mastering base address rw */ 1369 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO; 1370 c[PCI_BASE_ADDRESS_0 + 5] = 0x00; 1371 c[PCI_BASE_ADDRESS_0 + 6] = 0x00; 1372 c[PCI_BASE_ADDRESS_0 + 7] = 0x00; 1373 1374 if (s->use_broken_id) { 1375 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; 1376 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80; 1377 c[PCI_SUBSYSTEM_ID] = 0x00; 1378 c[PCI_SUBSYSTEM_ID + 1] = 0x00; 1379 } 1380 1381 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */ 1382 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ 1383 1384 memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s, 1385 "ac97-nam", 1024); 1386 memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s, 1387 "ac97-nabm", 256); 1388 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); 1389 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); 1390 AUD_register_card ("ac97", &s->card); 1391 ac97_on_reset (&s->dev.qdev); 1392 } 1393 1394 static void ac97_exit(PCIDevice *dev) 1395 { 1396 AC97LinkState *s = AC97(dev); 1397 1398 AUD_close_in(&s->card, s->voice_pi); 1399 AUD_close_out(&s->card, s->voice_po); 1400 AUD_close_in(&s->card, s->voice_mc); 1401 AUD_remove_card(&s->card); 1402 } 1403 1404 static int ac97_init (PCIBus *bus) 1405 { 1406 pci_create_simple(bus, -1, TYPE_AC97); 1407 return 0; 1408 } 1409 1410 static Property ac97_properties[] = { 1411 DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0), 1412 DEFINE_PROP_END_OF_LIST (), 1413 }; 1414 1415 static void ac97_class_init (ObjectClass *klass, void *data) 1416 { 1417 DeviceClass *dc = DEVICE_CLASS (klass); 1418 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass); 1419 1420 k->realize = ac97_realize; 1421 k->exit = ac97_exit; 1422 k->vendor_id = PCI_VENDOR_ID_INTEL; 1423 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5; 1424 k->revision = 0x01; 1425 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 1426 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1427 dc->desc = "Intel 82801AA AC97 Audio"; 1428 dc->vmsd = &vmstate_ac97; 1429 dc->props = ac97_properties; 1430 dc->reset = ac97_on_reset; 1431 } 1432 1433 static const TypeInfo ac97_info = { 1434 .name = TYPE_AC97, 1435 .parent = TYPE_PCI_DEVICE, 1436 .instance_size = sizeof (AC97LinkState), 1437 .class_init = ac97_class_init, 1438 .interfaces = (InterfaceInfo[]) { 1439 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1440 { }, 1441 }, 1442 }; 1443 1444 static void ac97_register_types (void) 1445 { 1446 type_register_static (&ac97_info); 1447 pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init); 1448 } 1449 1450 type_init (ac97_register_types) 1451