1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "hw/pci/pci.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "hw/audio/audio.h" 26 #include "intel-hda.h" 27 #include "intel-hda-defs.h" 28 #include "sysemu/dma.h" 29 30 /* --------------------------------------------------------------------- */ 31 /* hda bus */ 32 33 static Property hda_props[] = { 34 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 35 DEFINE_PROP_END_OF_LIST() 36 }; 37 38 static const TypeInfo hda_codec_bus_info = { 39 .name = TYPE_HDA_BUS, 40 .parent = TYPE_BUS, 41 .instance_size = sizeof(HDACodecBus), 42 }; 43 44 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 45 hda_codec_response_func response, 46 hda_codec_xfer_func xfer) 47 { 48 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 49 bus->response = response; 50 bus->xfer = xfer; 51 } 52 53 static int hda_codec_dev_init(DeviceState *qdev) 54 { 55 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); 56 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); 57 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 58 59 if (dev->cad == -1) { 60 dev->cad = bus->next_cad; 61 } 62 if (dev->cad >= 15) { 63 return -1; 64 } 65 bus->next_cad = dev->cad + 1; 66 return cdc->init(dev); 67 } 68 69 static int hda_codec_dev_exit(DeviceState *qdev) 70 { 71 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); 72 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 73 74 if (cdc->exit) { 75 cdc->exit(dev); 76 } 77 return 0; 78 } 79 80 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 81 { 82 BusChild *kid; 83 HDACodecDevice *cdev; 84 85 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 86 DeviceState *qdev = kid->child; 87 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); 88 if (cdev->cad == cad) { 89 return cdev; 90 } 91 } 92 return NULL; 93 } 94 95 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 96 { 97 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 98 bus->response(dev, solicited, response); 99 } 100 101 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 102 uint8_t *buf, uint32_t len) 103 { 104 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 105 return bus->xfer(dev, stnr, output, buf, len); 106 } 107 108 /* --------------------------------------------------------------------- */ 109 /* intel hda emulation */ 110 111 typedef struct IntelHDAStream IntelHDAStream; 112 typedef struct IntelHDAState IntelHDAState; 113 typedef struct IntelHDAReg IntelHDAReg; 114 115 typedef struct bpl { 116 uint64_t addr; 117 uint32_t len; 118 uint32_t flags; 119 } bpl; 120 121 struct IntelHDAStream { 122 /* registers */ 123 uint32_t ctl; 124 uint32_t lpib; 125 uint32_t cbl; 126 uint32_t lvi; 127 uint32_t fmt; 128 uint32_t bdlp_lbase; 129 uint32_t bdlp_ubase; 130 131 /* state */ 132 bpl *bpl; 133 uint32_t bentries; 134 uint32_t bsize, be, bp; 135 }; 136 137 struct IntelHDAState { 138 PCIDevice pci; 139 const char *name; 140 HDACodecBus codecs; 141 142 /* registers */ 143 uint32_t g_ctl; 144 uint32_t wake_en; 145 uint32_t state_sts; 146 uint32_t int_ctl; 147 uint32_t int_sts; 148 uint32_t wall_clk; 149 150 uint32_t corb_lbase; 151 uint32_t corb_ubase; 152 uint32_t corb_rp; 153 uint32_t corb_wp; 154 uint32_t corb_ctl; 155 uint32_t corb_sts; 156 uint32_t corb_size; 157 158 uint32_t rirb_lbase; 159 uint32_t rirb_ubase; 160 uint32_t rirb_wp; 161 uint32_t rirb_cnt; 162 uint32_t rirb_ctl; 163 uint32_t rirb_sts; 164 uint32_t rirb_size; 165 166 uint32_t dp_lbase; 167 uint32_t dp_ubase; 168 169 uint32_t icw; 170 uint32_t irr; 171 uint32_t ics; 172 173 /* streams */ 174 IntelHDAStream st[8]; 175 176 /* state */ 177 MemoryRegion mmio; 178 uint32_t rirb_count; 179 int64_t wall_base_ns; 180 181 /* debug logging */ 182 const IntelHDAReg *last_reg; 183 uint32_t last_val; 184 uint32_t last_write; 185 uint32_t last_sec; 186 uint32_t repeat_count; 187 188 /* properties */ 189 uint32_t debug; 190 uint32_t msi; 191 bool old_msi_addr; 192 }; 193 194 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 195 196 #define INTEL_HDA(obj) \ 197 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC) 198 199 struct IntelHDAReg { 200 const char *name; /* register name */ 201 uint32_t size; /* size in bytes */ 202 uint32_t reset; /* reset value */ 203 uint32_t wmask; /* write mask */ 204 uint32_t wclear; /* write 1 to clear bits */ 205 uint32_t offset; /* location in IntelHDAState */ 206 uint32_t shift; /* byte access entries for dwords */ 207 uint32_t stream; 208 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 209 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 210 }; 211 212 static void intel_hda_reset(DeviceState *dev); 213 214 /* --------------------------------------------------------------------- */ 215 216 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 217 { 218 hwaddr addr; 219 220 addr = ((uint64_t)ubase << 32) | lbase; 221 return addr; 222 } 223 224 static void intel_hda_update_int_sts(IntelHDAState *d) 225 { 226 uint32_t sts = 0; 227 uint32_t i; 228 229 /* update controller status */ 230 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 231 sts |= (1 << 30); 232 } 233 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 234 sts |= (1 << 30); 235 } 236 if (d->state_sts & d->wake_en) { 237 sts |= (1 << 30); 238 } 239 240 /* update stream status */ 241 for (i = 0; i < 8; i++) { 242 /* buffer completion interrupt */ 243 if (d->st[i].ctl & (1 << 26)) { 244 sts |= (1 << i); 245 } 246 } 247 248 /* update global status */ 249 if (sts & d->int_ctl) { 250 sts |= (1U << 31); 251 } 252 253 d->int_sts = sts; 254 } 255 256 static void intel_hda_update_irq(IntelHDAState *d) 257 { 258 int msi = d->msi && msi_enabled(&d->pci); 259 int level; 260 261 intel_hda_update_int_sts(d); 262 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 263 level = 1; 264 } else { 265 level = 0; 266 } 267 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, 268 level, msi ? "msi" : "intx"); 269 if (msi) { 270 if (level) { 271 msi_notify(&d->pci, 0); 272 } 273 } else { 274 pci_set_irq(&d->pci, level); 275 } 276 } 277 278 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 279 { 280 uint32_t cad, nid, data; 281 HDACodecDevice *codec; 282 HDACodecDeviceClass *cdc; 283 284 cad = (verb >> 28) & 0x0f; 285 if (verb & (1 << 27)) { 286 /* indirect node addressing, not specified in HDA 1.0 */ 287 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); 288 return -1; 289 } 290 nid = (verb >> 20) & 0x7f; 291 data = verb & 0xfffff; 292 293 codec = hda_codec_find(&d->codecs, cad); 294 if (codec == NULL) { 295 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); 296 return -1; 297 } 298 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 299 cdc->command(codec, nid, data); 300 return 0; 301 } 302 303 static void intel_hda_corb_run(IntelHDAState *d) 304 { 305 hwaddr addr; 306 uint32_t rp, verb; 307 308 if (d->ics & ICH6_IRS_BUSY) { 309 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); 310 intel_hda_send_command(d, d->icw); 311 return; 312 } 313 314 for (;;) { 315 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 316 dprint(d, 2, "%s: !run\n", __FUNCTION__); 317 return; 318 } 319 if ((d->corb_rp & 0xff) == d->corb_wp) { 320 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); 321 return; 322 } 323 if (d->rirb_count == d->rirb_cnt) { 324 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); 325 return; 326 } 327 328 rp = (d->corb_rp + 1) & 0xff; 329 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 330 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 331 d->corb_rp = rp; 332 333 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); 334 intel_hda_send_command(d, verb); 335 } 336 } 337 338 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 339 { 340 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 341 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 342 hwaddr addr; 343 uint32_t wp, ex; 344 345 if (d->ics & ICH6_IRS_BUSY) { 346 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 347 __FUNCTION__, response, dev->cad); 348 d->irr = response; 349 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 350 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 351 return; 352 } 353 354 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 355 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); 356 return; 357 } 358 359 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 360 wp = (d->rirb_wp + 1) & 0xff; 361 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 362 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 363 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 364 d->rirb_wp = wp; 365 366 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 367 __FUNCTION__, wp, response, ex); 368 369 d->rirb_count++; 370 if (d->rirb_count == d->rirb_cnt) { 371 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); 372 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 373 d->rirb_sts |= ICH6_RBSTS_IRQ; 374 intel_hda_update_irq(d); 375 } 376 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 377 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, 378 d->rirb_count, d->rirb_cnt); 379 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 380 d->rirb_sts |= ICH6_RBSTS_IRQ; 381 intel_hda_update_irq(d); 382 } 383 } 384 } 385 386 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 387 uint8_t *buf, uint32_t len) 388 { 389 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 390 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 391 hwaddr addr; 392 uint32_t s, copy, left; 393 IntelHDAStream *st; 394 bool irq = false; 395 396 st = output ? d->st + 4 : d->st; 397 for (s = 0; s < 4; s++) { 398 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 399 st = st + s; 400 break; 401 } 402 } 403 if (s == 4) { 404 return false; 405 } 406 if (st->bpl == NULL) { 407 return false; 408 } 409 if (st->ctl & (1 << 26)) { 410 /* 411 * Wait with the next DMA xfer until the guest 412 * has acked the buffer completion interrupt 413 */ 414 return false; 415 } 416 417 left = len; 418 while (left > 0) { 419 copy = left; 420 if (copy > st->bsize - st->lpib) 421 copy = st->bsize - st->lpib; 422 if (copy > st->bpl[st->be].len - st->bp) 423 copy = st->bpl[st->be].len - st->bp; 424 425 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 426 st->be, st->bp, st->bpl[st->be].len, copy); 427 428 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); 429 st->lpib += copy; 430 st->bp += copy; 431 buf += copy; 432 left -= copy; 433 434 if (st->bpl[st->be].len == st->bp) { 435 /* bpl entry filled */ 436 if (st->bpl[st->be].flags & 0x01) { 437 irq = true; 438 } 439 st->bp = 0; 440 st->be++; 441 if (st->be == st->bentries) { 442 /* bpl wrap around */ 443 st->be = 0; 444 st->lpib = 0; 445 } 446 } 447 } 448 if (d->dp_lbase & 0x01) { 449 s = st - d->st; 450 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 451 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 452 } 453 dprint(d, 3, "dma: --\n"); 454 455 if (irq) { 456 st->ctl |= (1 << 26); /* buffer completion interrupt */ 457 intel_hda_update_irq(d); 458 } 459 return true; 460 } 461 462 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 463 { 464 hwaddr addr; 465 uint8_t buf[16]; 466 uint32_t i; 467 468 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 469 st->bentries = st->lvi +1; 470 g_free(st->bpl); 471 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 472 for (i = 0; i < st->bentries; i++, addr += 16) { 473 pci_dma_read(&d->pci, addr, buf, 16); 474 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 475 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 476 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 477 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 478 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 479 } 480 481 st->bsize = st->cbl; 482 st->lpib = 0; 483 st->be = 0; 484 st->bp = 0; 485 } 486 487 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 488 { 489 BusChild *kid; 490 HDACodecDevice *cdev; 491 492 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 493 DeviceState *qdev = kid->child; 494 HDACodecDeviceClass *cdc; 495 496 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); 497 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 498 if (cdc->stream) { 499 cdc->stream(cdev, stream, running, output); 500 } 501 } 502 } 503 504 /* --------------------------------------------------------------------- */ 505 506 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 507 { 508 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 509 intel_hda_reset(DEVICE(d)); 510 } 511 } 512 513 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 514 { 515 intel_hda_update_irq(d); 516 } 517 518 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 519 { 520 intel_hda_update_irq(d); 521 } 522 523 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 524 { 525 intel_hda_update_irq(d); 526 } 527 528 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 529 { 530 int64_t ns; 531 532 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 533 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 534 } 535 536 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 537 { 538 intel_hda_corb_run(d); 539 } 540 541 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 542 { 543 intel_hda_corb_run(d); 544 } 545 546 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 547 { 548 if (d->rirb_wp & ICH6_RIRBWP_RST) { 549 d->rirb_wp = 0; 550 } 551 } 552 553 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 554 { 555 intel_hda_update_irq(d); 556 557 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 558 /* cleared ICH6_RBSTS_IRQ */ 559 d->rirb_count = 0; 560 intel_hda_corb_run(d); 561 } 562 } 563 564 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 565 { 566 if (d->ics & ICH6_IRS_BUSY) { 567 intel_hda_corb_run(d); 568 } 569 } 570 571 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 572 { 573 bool output = reg->stream >= 4; 574 IntelHDAStream *st = d->st + reg->stream; 575 576 if (st->ctl & 0x01) { 577 /* reset */ 578 dprint(d, 1, "st #%d: reset\n", reg->stream); 579 st->ctl = SD_STS_FIFO_READY << 24; 580 } 581 if ((st->ctl & 0x02) != (old & 0x02)) { 582 uint32_t stnr = (st->ctl >> 20) & 0x0f; 583 /* run bit flipped */ 584 if (st->ctl & 0x02) { 585 /* start */ 586 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 587 reg->stream, stnr, st->cbl); 588 intel_hda_parse_bdl(d, st); 589 intel_hda_notify_codecs(d, stnr, true, output); 590 } else { 591 /* stop */ 592 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 593 intel_hda_notify_codecs(d, stnr, false, output); 594 } 595 } 596 intel_hda_update_irq(d); 597 } 598 599 /* --------------------------------------------------------------------- */ 600 601 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 602 603 static const struct IntelHDAReg regtab[] = { 604 /* global */ 605 [ ICH6_REG_GCAP ] = { 606 .name = "GCAP", 607 .size = 2, 608 .reset = 0x4401, 609 }, 610 [ ICH6_REG_VMIN ] = { 611 .name = "VMIN", 612 .size = 1, 613 }, 614 [ ICH6_REG_VMAJ ] = { 615 .name = "VMAJ", 616 .size = 1, 617 .reset = 1, 618 }, 619 [ ICH6_REG_OUTPAY ] = { 620 .name = "OUTPAY", 621 .size = 2, 622 .reset = 0x3c, 623 }, 624 [ ICH6_REG_INPAY ] = { 625 .name = "INPAY", 626 .size = 2, 627 .reset = 0x1d, 628 }, 629 [ ICH6_REG_GCTL ] = { 630 .name = "GCTL", 631 .size = 4, 632 .wmask = 0x0103, 633 .offset = offsetof(IntelHDAState, g_ctl), 634 .whandler = intel_hda_set_g_ctl, 635 }, 636 [ ICH6_REG_WAKEEN ] = { 637 .name = "WAKEEN", 638 .size = 2, 639 .wmask = 0x7fff, 640 .offset = offsetof(IntelHDAState, wake_en), 641 .whandler = intel_hda_set_wake_en, 642 }, 643 [ ICH6_REG_STATESTS ] = { 644 .name = "STATESTS", 645 .size = 2, 646 .wmask = 0x7fff, 647 .wclear = 0x7fff, 648 .offset = offsetof(IntelHDAState, state_sts), 649 .whandler = intel_hda_set_state_sts, 650 }, 651 652 /* interrupts */ 653 [ ICH6_REG_INTCTL ] = { 654 .name = "INTCTL", 655 .size = 4, 656 .wmask = 0xc00000ff, 657 .offset = offsetof(IntelHDAState, int_ctl), 658 .whandler = intel_hda_set_int_ctl, 659 }, 660 [ ICH6_REG_INTSTS ] = { 661 .name = "INTSTS", 662 .size = 4, 663 .wmask = 0xc00000ff, 664 .wclear = 0xc00000ff, 665 .offset = offsetof(IntelHDAState, int_sts), 666 }, 667 668 /* misc */ 669 [ ICH6_REG_WALLCLK ] = { 670 .name = "WALLCLK", 671 .size = 4, 672 .offset = offsetof(IntelHDAState, wall_clk), 673 .rhandler = intel_hda_get_wall_clk, 674 }, 675 [ ICH6_REG_WALLCLK + 0x2000 ] = { 676 .name = "WALLCLK(alias)", 677 .size = 4, 678 .offset = offsetof(IntelHDAState, wall_clk), 679 .rhandler = intel_hda_get_wall_clk, 680 }, 681 682 /* dma engine */ 683 [ ICH6_REG_CORBLBASE ] = { 684 .name = "CORBLBASE", 685 .size = 4, 686 .wmask = 0xffffff80, 687 .offset = offsetof(IntelHDAState, corb_lbase), 688 }, 689 [ ICH6_REG_CORBUBASE ] = { 690 .name = "CORBUBASE", 691 .size = 4, 692 .wmask = 0xffffffff, 693 .offset = offsetof(IntelHDAState, corb_ubase), 694 }, 695 [ ICH6_REG_CORBWP ] = { 696 .name = "CORBWP", 697 .size = 2, 698 .wmask = 0xff, 699 .offset = offsetof(IntelHDAState, corb_wp), 700 .whandler = intel_hda_set_corb_wp, 701 }, 702 [ ICH6_REG_CORBRP ] = { 703 .name = "CORBRP", 704 .size = 2, 705 .wmask = 0x80ff, 706 .offset = offsetof(IntelHDAState, corb_rp), 707 }, 708 [ ICH6_REG_CORBCTL ] = { 709 .name = "CORBCTL", 710 .size = 1, 711 .wmask = 0x03, 712 .offset = offsetof(IntelHDAState, corb_ctl), 713 .whandler = intel_hda_set_corb_ctl, 714 }, 715 [ ICH6_REG_CORBSTS ] = { 716 .name = "CORBSTS", 717 .size = 1, 718 .wmask = 0x01, 719 .wclear = 0x01, 720 .offset = offsetof(IntelHDAState, corb_sts), 721 }, 722 [ ICH6_REG_CORBSIZE ] = { 723 .name = "CORBSIZE", 724 .size = 1, 725 .reset = 0x42, 726 .offset = offsetof(IntelHDAState, corb_size), 727 }, 728 [ ICH6_REG_RIRBLBASE ] = { 729 .name = "RIRBLBASE", 730 .size = 4, 731 .wmask = 0xffffff80, 732 .offset = offsetof(IntelHDAState, rirb_lbase), 733 }, 734 [ ICH6_REG_RIRBUBASE ] = { 735 .name = "RIRBUBASE", 736 .size = 4, 737 .wmask = 0xffffffff, 738 .offset = offsetof(IntelHDAState, rirb_ubase), 739 }, 740 [ ICH6_REG_RIRBWP ] = { 741 .name = "RIRBWP", 742 .size = 2, 743 .wmask = 0x8000, 744 .offset = offsetof(IntelHDAState, rirb_wp), 745 .whandler = intel_hda_set_rirb_wp, 746 }, 747 [ ICH6_REG_RINTCNT ] = { 748 .name = "RINTCNT", 749 .size = 2, 750 .wmask = 0xff, 751 .offset = offsetof(IntelHDAState, rirb_cnt), 752 }, 753 [ ICH6_REG_RIRBCTL ] = { 754 .name = "RIRBCTL", 755 .size = 1, 756 .wmask = 0x07, 757 .offset = offsetof(IntelHDAState, rirb_ctl), 758 }, 759 [ ICH6_REG_RIRBSTS ] = { 760 .name = "RIRBSTS", 761 .size = 1, 762 .wmask = 0x05, 763 .wclear = 0x05, 764 .offset = offsetof(IntelHDAState, rirb_sts), 765 .whandler = intel_hda_set_rirb_sts, 766 }, 767 [ ICH6_REG_RIRBSIZE ] = { 768 .name = "RIRBSIZE", 769 .size = 1, 770 .reset = 0x42, 771 .offset = offsetof(IntelHDAState, rirb_size), 772 }, 773 774 [ ICH6_REG_DPLBASE ] = { 775 .name = "DPLBASE", 776 .size = 4, 777 .wmask = 0xffffff81, 778 .offset = offsetof(IntelHDAState, dp_lbase), 779 }, 780 [ ICH6_REG_DPUBASE ] = { 781 .name = "DPUBASE", 782 .size = 4, 783 .wmask = 0xffffffff, 784 .offset = offsetof(IntelHDAState, dp_ubase), 785 }, 786 787 [ ICH6_REG_IC ] = { 788 .name = "ICW", 789 .size = 4, 790 .wmask = 0xffffffff, 791 .offset = offsetof(IntelHDAState, icw), 792 }, 793 [ ICH6_REG_IR ] = { 794 .name = "IRR", 795 .size = 4, 796 .offset = offsetof(IntelHDAState, irr), 797 }, 798 [ ICH6_REG_IRS ] = { 799 .name = "ICS", 800 .size = 2, 801 .wmask = 0x0003, 802 .wclear = 0x0002, 803 .offset = offsetof(IntelHDAState, ics), 804 .whandler = intel_hda_set_ics, 805 }, 806 807 #define HDA_STREAM(_t, _i) \ 808 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 809 .stream = _i, \ 810 .name = _t stringify(_i) " CTL", \ 811 .size = 4, \ 812 .wmask = 0x1cff001f, \ 813 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 814 .whandler = intel_hda_set_st_ctl, \ 815 }, \ 816 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 817 .stream = _i, \ 818 .name = _t stringify(_i) " CTL(stnr)", \ 819 .size = 1, \ 820 .shift = 16, \ 821 .wmask = 0x00ff0000, \ 822 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 823 .whandler = intel_hda_set_st_ctl, \ 824 }, \ 825 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 826 .stream = _i, \ 827 .name = _t stringify(_i) " CTL(sts)", \ 828 .size = 1, \ 829 .shift = 24, \ 830 .wmask = 0x1c000000, \ 831 .wclear = 0x1c000000, \ 832 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 833 .whandler = intel_hda_set_st_ctl, \ 834 .reset = SD_STS_FIFO_READY << 24 \ 835 }, \ 836 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 837 .stream = _i, \ 838 .name = _t stringify(_i) " LPIB", \ 839 .size = 4, \ 840 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 841 }, \ 842 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \ 843 .stream = _i, \ 844 .name = _t stringify(_i) " LPIB(alias)", \ 845 .size = 4, \ 846 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 847 }, \ 848 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 849 .stream = _i, \ 850 .name = _t stringify(_i) " CBL", \ 851 .size = 4, \ 852 .wmask = 0xffffffff, \ 853 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 854 }, \ 855 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 856 .stream = _i, \ 857 .name = _t stringify(_i) " LVI", \ 858 .size = 2, \ 859 .wmask = 0x00ff, \ 860 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 861 }, \ 862 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 863 .stream = _i, \ 864 .name = _t stringify(_i) " FIFOS", \ 865 .size = 2, \ 866 .reset = HDA_BUFFER_SIZE, \ 867 }, \ 868 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 869 .stream = _i, \ 870 .name = _t stringify(_i) " FMT", \ 871 .size = 2, \ 872 .wmask = 0x7f7f, \ 873 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 874 }, \ 875 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 876 .stream = _i, \ 877 .name = _t stringify(_i) " BDLPL", \ 878 .size = 4, \ 879 .wmask = 0xffffff80, \ 880 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 881 }, \ 882 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 883 .stream = _i, \ 884 .name = _t stringify(_i) " BDLPU", \ 885 .size = 4, \ 886 .wmask = 0xffffffff, \ 887 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 888 }, \ 889 890 HDA_STREAM("IN", 0) 891 HDA_STREAM("IN", 1) 892 HDA_STREAM("IN", 2) 893 HDA_STREAM("IN", 3) 894 895 HDA_STREAM("OUT", 4) 896 HDA_STREAM("OUT", 5) 897 HDA_STREAM("OUT", 6) 898 HDA_STREAM("OUT", 7) 899 900 }; 901 902 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 903 { 904 const IntelHDAReg *reg; 905 906 if (addr >= ARRAY_SIZE(regtab)) { 907 goto noreg; 908 } 909 reg = regtab+addr; 910 if (reg->name == NULL) { 911 goto noreg; 912 } 913 return reg; 914 915 noreg: 916 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 917 return NULL; 918 } 919 920 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 921 { 922 uint8_t *addr = (void*)d; 923 924 addr += reg->offset; 925 return (uint32_t*)addr; 926 } 927 928 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 929 uint32_t wmask) 930 { 931 uint32_t *addr; 932 uint32_t old; 933 934 if (!reg) { 935 return; 936 } 937 938 if (d->debug) { 939 time_t now = time(NULL); 940 if (d->last_write && d->last_reg == reg && d->last_val == val) { 941 d->repeat_count++; 942 if (d->last_sec != now) { 943 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 944 d->last_sec = now; 945 d->repeat_count = 0; 946 } 947 } else { 948 if (d->repeat_count) { 949 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 950 } 951 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 952 d->last_write = 1; 953 d->last_reg = reg; 954 d->last_val = val; 955 d->last_sec = now; 956 d->repeat_count = 0; 957 } 958 } 959 assert(reg->offset != 0); 960 961 addr = intel_hda_reg_addr(d, reg); 962 old = *addr; 963 964 if (reg->shift) { 965 val <<= reg->shift; 966 wmask <<= reg->shift; 967 } 968 wmask &= reg->wmask; 969 *addr &= ~wmask; 970 *addr |= wmask & val; 971 *addr &= ~(val & reg->wclear); 972 973 if (reg->whandler) { 974 reg->whandler(d, reg, old); 975 } 976 } 977 978 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 979 uint32_t rmask) 980 { 981 uint32_t *addr, ret; 982 983 if (!reg) { 984 return 0; 985 } 986 987 if (reg->rhandler) { 988 reg->rhandler(d, reg); 989 } 990 991 if (reg->offset == 0) { 992 /* constant read-only register */ 993 ret = reg->reset; 994 } else { 995 addr = intel_hda_reg_addr(d, reg); 996 ret = *addr; 997 if (reg->shift) { 998 ret >>= reg->shift; 999 } 1000 ret &= rmask; 1001 } 1002 if (d->debug) { 1003 time_t now = time(NULL); 1004 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1005 d->repeat_count++; 1006 if (d->last_sec != now) { 1007 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1008 d->last_sec = now; 1009 d->repeat_count = 0; 1010 } 1011 } else { 1012 if (d->repeat_count) { 1013 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1014 } 1015 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1016 d->last_write = 0; 1017 d->last_reg = reg; 1018 d->last_val = ret; 1019 d->last_sec = now; 1020 d->repeat_count = 0; 1021 } 1022 } 1023 return ret; 1024 } 1025 1026 static void intel_hda_regs_reset(IntelHDAState *d) 1027 { 1028 uint32_t *addr; 1029 int i; 1030 1031 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1032 if (regtab[i].name == NULL) { 1033 continue; 1034 } 1035 if (regtab[i].offset == 0) { 1036 continue; 1037 } 1038 addr = intel_hda_reg_addr(d, regtab + i); 1039 *addr = regtab[i].reset; 1040 } 1041 } 1042 1043 /* --------------------------------------------------------------------- */ 1044 1045 static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 1046 { 1047 IntelHDAState *d = opaque; 1048 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1049 1050 intel_hda_reg_write(d, reg, val, 0xff); 1051 } 1052 1053 static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 1054 { 1055 IntelHDAState *d = opaque; 1056 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1057 1058 intel_hda_reg_write(d, reg, val, 0xffff); 1059 } 1060 1061 static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 1062 { 1063 IntelHDAState *d = opaque; 1064 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1065 1066 intel_hda_reg_write(d, reg, val, 0xffffffff); 1067 } 1068 1069 static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr) 1070 { 1071 IntelHDAState *d = opaque; 1072 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1073 1074 return intel_hda_reg_read(d, reg, 0xff); 1075 } 1076 1077 static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr) 1078 { 1079 IntelHDAState *d = opaque; 1080 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1081 1082 return intel_hda_reg_read(d, reg, 0xffff); 1083 } 1084 1085 static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr) 1086 { 1087 IntelHDAState *d = opaque; 1088 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1089 1090 return intel_hda_reg_read(d, reg, 0xffffffff); 1091 } 1092 1093 static const MemoryRegionOps intel_hda_mmio_ops = { 1094 .old_mmio = { 1095 .read = { 1096 intel_hda_mmio_readb, 1097 intel_hda_mmio_readw, 1098 intel_hda_mmio_readl, 1099 }, 1100 .write = { 1101 intel_hda_mmio_writeb, 1102 intel_hda_mmio_writew, 1103 intel_hda_mmio_writel, 1104 }, 1105 }, 1106 .endianness = DEVICE_NATIVE_ENDIAN, 1107 }; 1108 1109 /* --------------------------------------------------------------------- */ 1110 1111 static void intel_hda_reset(DeviceState *dev) 1112 { 1113 BusChild *kid; 1114 IntelHDAState *d = INTEL_HDA(dev); 1115 HDACodecDevice *cdev; 1116 1117 intel_hda_regs_reset(d); 1118 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1119 1120 /* reset codecs */ 1121 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1122 DeviceState *qdev = kid->child; 1123 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); 1124 device_reset(DEVICE(cdev)); 1125 d->state_sts |= (1 << cdev->cad); 1126 } 1127 intel_hda_update_irq(d); 1128 } 1129 1130 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1131 { 1132 IntelHDAState *d = INTEL_HDA(pci); 1133 uint8_t *conf = d->pci.config; 1134 1135 d->name = object_get_typename(OBJECT(d)); 1136 1137 pci_config_set_interrupt_pin(conf, 1); 1138 1139 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1140 conf[0x40] = 0x01; 1141 1142 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1143 "intel-hda", 0x4000); 1144 pci_register_bar(&d->pci, 0, 0, &d->mmio); 1145 if (d->msi) { 1146 msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1, true, false); 1147 } 1148 1149 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1150 intel_hda_response, intel_hda_xfer); 1151 } 1152 1153 static void intel_hda_exit(PCIDevice *pci) 1154 { 1155 IntelHDAState *d = INTEL_HDA(pci); 1156 1157 msi_uninit(&d->pci); 1158 } 1159 1160 static int intel_hda_post_load(void *opaque, int version) 1161 { 1162 IntelHDAState* d = opaque; 1163 int i; 1164 1165 dprint(d, 1, "%s\n", __FUNCTION__); 1166 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1167 if (d->st[i].ctl & 0x02) { 1168 intel_hda_parse_bdl(d, &d->st[i]); 1169 } 1170 } 1171 intel_hda_update_irq(d); 1172 return 0; 1173 } 1174 1175 static const VMStateDescription vmstate_intel_hda_stream = { 1176 .name = "intel-hda-stream", 1177 .version_id = 1, 1178 .fields = (VMStateField[]) { 1179 VMSTATE_UINT32(ctl, IntelHDAStream), 1180 VMSTATE_UINT32(lpib, IntelHDAStream), 1181 VMSTATE_UINT32(cbl, IntelHDAStream), 1182 VMSTATE_UINT32(lvi, IntelHDAStream), 1183 VMSTATE_UINT32(fmt, IntelHDAStream), 1184 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1185 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1186 VMSTATE_END_OF_LIST() 1187 } 1188 }; 1189 1190 static const VMStateDescription vmstate_intel_hda = { 1191 .name = "intel-hda", 1192 .version_id = 1, 1193 .post_load = intel_hda_post_load, 1194 .fields = (VMStateField[]) { 1195 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1196 1197 /* registers */ 1198 VMSTATE_UINT32(g_ctl, IntelHDAState), 1199 VMSTATE_UINT32(wake_en, IntelHDAState), 1200 VMSTATE_UINT32(state_sts, IntelHDAState), 1201 VMSTATE_UINT32(int_ctl, IntelHDAState), 1202 VMSTATE_UINT32(int_sts, IntelHDAState), 1203 VMSTATE_UINT32(wall_clk, IntelHDAState), 1204 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1205 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1206 VMSTATE_UINT32(corb_rp, IntelHDAState), 1207 VMSTATE_UINT32(corb_wp, IntelHDAState), 1208 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1209 VMSTATE_UINT32(corb_sts, IntelHDAState), 1210 VMSTATE_UINT32(corb_size, IntelHDAState), 1211 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1212 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1213 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1214 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1215 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1216 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1217 VMSTATE_UINT32(rirb_size, IntelHDAState), 1218 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1219 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1220 VMSTATE_UINT32(icw, IntelHDAState), 1221 VMSTATE_UINT32(irr, IntelHDAState), 1222 VMSTATE_UINT32(ics, IntelHDAState), 1223 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1224 vmstate_intel_hda_stream, 1225 IntelHDAStream), 1226 1227 /* additional state info */ 1228 VMSTATE_UINT32(rirb_count, IntelHDAState), 1229 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1230 1231 VMSTATE_END_OF_LIST() 1232 } 1233 }; 1234 1235 static Property intel_hda_properties[] = { 1236 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1237 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), 1238 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1239 DEFINE_PROP_END_OF_LIST(), 1240 }; 1241 1242 static void intel_hda_class_init(ObjectClass *klass, void *data) 1243 { 1244 DeviceClass *dc = DEVICE_CLASS(klass); 1245 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1246 1247 k->realize = intel_hda_realize; 1248 k->exit = intel_hda_exit; 1249 k->vendor_id = PCI_VENDOR_ID_INTEL; 1250 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1251 dc->reset = intel_hda_reset; 1252 dc->vmsd = &vmstate_intel_hda; 1253 dc->props = intel_hda_properties; 1254 } 1255 1256 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1257 { 1258 DeviceClass *dc = DEVICE_CLASS(klass); 1259 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1260 1261 k->device_id = 0x2668; 1262 k->revision = 1; 1263 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1264 dc->desc = "Intel HD Audio Controller (ich6)"; 1265 } 1266 1267 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1268 { 1269 DeviceClass *dc = DEVICE_CLASS(klass); 1270 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1271 1272 k->device_id = 0x293e; 1273 k->revision = 3; 1274 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1275 dc->desc = "Intel HD Audio Controller (ich9)"; 1276 } 1277 1278 static const TypeInfo intel_hda_info = { 1279 .name = TYPE_INTEL_HDA_GENERIC, 1280 .parent = TYPE_PCI_DEVICE, 1281 .instance_size = sizeof(IntelHDAState), 1282 .class_init = intel_hda_class_init, 1283 .abstract = true, 1284 }; 1285 1286 static const TypeInfo intel_hda_info_ich6 = { 1287 .name = "intel-hda", 1288 .parent = TYPE_INTEL_HDA_GENERIC, 1289 .class_init = intel_hda_class_init_ich6, 1290 }; 1291 1292 static const TypeInfo intel_hda_info_ich9 = { 1293 .name = "ich9-intel-hda", 1294 .parent = TYPE_INTEL_HDA_GENERIC, 1295 .class_init = intel_hda_class_init_ich9, 1296 }; 1297 1298 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1299 { 1300 DeviceClass *k = DEVICE_CLASS(klass); 1301 k->init = hda_codec_dev_init; 1302 k->exit = hda_codec_dev_exit; 1303 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1304 k->bus_type = TYPE_HDA_BUS; 1305 k->props = hda_props; 1306 } 1307 1308 static const TypeInfo hda_codec_device_type_info = { 1309 .name = TYPE_HDA_CODEC_DEVICE, 1310 .parent = TYPE_DEVICE, 1311 .instance_size = sizeof(HDACodecDevice), 1312 .abstract = true, 1313 .class_size = sizeof(HDACodecDeviceClass), 1314 .class_init = hda_codec_device_class_init, 1315 }; 1316 1317 /* 1318 * create intel hda controller with codec attached to it, 1319 * so '-soundhw hda' works. 1320 */ 1321 static int intel_hda_and_codec_init(PCIBus *bus) 1322 { 1323 DeviceState *controller; 1324 BusState *hdabus; 1325 DeviceState *codec; 1326 1327 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1328 hdabus = QLIST_FIRST(&controller->child_bus); 1329 codec = qdev_create(hdabus, "hda-duplex"); 1330 qdev_init_nofail(codec); 1331 return 0; 1332 } 1333 1334 static void intel_hda_register_types(void) 1335 { 1336 type_register_static(&hda_codec_bus_info); 1337 type_register_static(&intel_hda_info); 1338 type_register_static(&intel_hda_info_ich6); 1339 type_register_static(&intel_hda_info_ich9); 1340 type_register_static(&hda_codec_device_type_info); 1341 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1342 } 1343 1344 type_init(intel_hda_register_types) 1345