1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/ssi/ssi.h" 29 #include "migration/vmstate.h" 30 #include "qemu/bitops.h" 31 #include "qemu/log.h" 32 #include "qemu/module.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "trace.h" 36 #include "qom/object.h" 37 38 /* Fields for FlashPartInfo->flags */ 39 40 /* erase capabilities */ 41 #define ER_4K 1 42 #define ER_32K 2 43 /* set to allow the page program command to write 0s back to 1. Useful for 44 * modelling EEPROM with SPI flash command set 45 */ 46 #define EEPROM 0x100 47 48 /* 16 MiB max in 3 byte address mode */ 49 #define MAX_3BYTES_SIZE 0x1000000 50 51 #define SPI_NOR_MAX_ID_LEN 6 52 53 typedef struct FlashPartInfo { 54 const char *part_name; 55 /* 56 * This array stores the ID bytes. 57 * The first three bytes are the JEDIC ID. 58 * JEDEC ID zero means "no ID" (mostly older chips). 59 */ 60 uint8_t id[SPI_NOR_MAX_ID_LEN]; 61 uint8_t id_len; 62 /* there is confusion between manufacturers as to what a sector is. In this 63 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 64 * command (opcode 0xd8). 65 */ 66 uint32_t sector_size; 67 uint32_t n_sectors; 68 uint32_t page_size; 69 uint16_t flags; 70 /* 71 * Big sized spi nor are often stacked devices, thus sometime 72 * replace chip erase with die erase. 73 * This field inform how many die is in the chip. 74 */ 75 uint8_t die_cnt; 76 } FlashPartInfo; 77 78 /* adapted from linux */ 79 /* Used when the "_ext_id" is two bytes at most */ 80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 81 .part_name = _part_name,\ 82 .id = {\ 83 ((_jedec_id) >> 16) & 0xff,\ 84 ((_jedec_id) >> 8) & 0xff,\ 85 (_jedec_id) & 0xff,\ 86 ((_ext_id) >> 8) & 0xff,\ 87 (_ext_id) & 0xff,\ 88 },\ 89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 90 .sector_size = (_sector_size),\ 91 .n_sectors = (_n_sectors),\ 92 .page_size = 256,\ 93 .flags = (_flags),\ 94 .die_cnt = 0 95 96 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 97 .part_name = _part_name,\ 98 .id = {\ 99 ((_jedec_id) >> 16) & 0xff,\ 100 ((_jedec_id) >> 8) & 0xff,\ 101 (_jedec_id) & 0xff,\ 102 ((_ext_id) >> 16) & 0xff,\ 103 ((_ext_id) >> 8) & 0xff,\ 104 (_ext_id) & 0xff,\ 105 },\ 106 .id_len = 6,\ 107 .sector_size = (_sector_size),\ 108 .n_sectors = (_n_sectors),\ 109 .page_size = 256,\ 110 .flags = (_flags),\ 111 .die_cnt = 0 112 113 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 114 _flags, _die_cnt)\ 115 .part_name = _part_name,\ 116 .id = {\ 117 ((_jedec_id) >> 16) & 0xff,\ 118 ((_jedec_id) >> 8) & 0xff,\ 119 (_jedec_id) & 0xff,\ 120 ((_ext_id) >> 8) & 0xff,\ 121 (_ext_id) & 0xff,\ 122 },\ 123 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 124 .sector_size = (_sector_size),\ 125 .n_sectors = (_n_sectors),\ 126 .page_size = 256,\ 127 .flags = (_flags),\ 128 .die_cnt = _die_cnt 129 130 #define JEDEC_NUMONYX 0x20 131 #define JEDEC_WINBOND 0xEF 132 #define JEDEC_SPANSION 0x01 133 134 /* Numonyx (Micron) Configuration register macros */ 135 #define VCFG_DUMMY 0x1 136 #define VCFG_WRAP_SEQUENTIAL 0x2 137 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 138 #define NVCFG_XIP_MODE_MASK (7 << 9) 139 #define VCFG_XIP_MODE_DISABLED (1 << 3) 140 #define CFG_DUMMY_CLK_LEN 4 141 #define NVCFG_DUMMY_CLK_POS 12 142 #define VCFG_DUMMY_CLK_POS 4 143 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 144 #define EVCFG_VPP_ACCELERATOR (1 << 3) 145 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 146 #define NVCFG_DUAL_IO_MASK (1 << 2) 147 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 148 #define NVCFG_QUAD_IO_MASK (1 << 3) 149 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 150 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 151 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 152 153 /* Numonyx (Micron) Flag Status Register macros */ 154 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 155 #define FSR_FLASH_READY (1 << 7) 156 157 /* Spansion configuration registers macros. */ 158 #define SPANSION_QUAD_CFG_POS 0 159 #define SPANSION_QUAD_CFG_LEN 1 160 #define SPANSION_DUMMY_CLK_POS 0 161 #define SPANSION_DUMMY_CLK_LEN 4 162 #define SPANSION_ADDR_LEN_POS 7 163 #define SPANSION_ADDR_LEN_LEN 1 164 165 /* 166 * Spansion read mode command length in bytes, 167 * the mode is currently not supported. 168 */ 169 170 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 171 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 172 173 static const FlashPartInfo known_devices[] = { 174 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 175 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 176 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 177 178 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 179 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 180 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 181 182 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 183 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 184 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 185 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 186 187 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 188 189 /* Atmel EEPROMS - it is assumed, that don't care bit in command 190 * is set to 0. Block protection is not supported. 191 */ 192 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 193 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 194 195 /* EON -- en25xxx */ 196 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 197 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 198 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 199 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 200 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 201 202 /* GigaDevice */ 203 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 204 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 205 206 /* Intel/Numonyx -- xxxs33b */ 207 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 208 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 209 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 210 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 211 212 /* Macronix */ 213 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 214 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 215 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 216 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 217 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 218 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 219 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 220 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 221 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) }, 222 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 223 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 224 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 225 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 226 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 227 228 /* Micron */ 229 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 230 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 231 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 232 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 233 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 234 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 235 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 236 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 237 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 238 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 239 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 240 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 241 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 242 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 243 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 244 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 245 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 246 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 247 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 248 249 /* Spansion -- single (large) sector size only, at least 250 * for the chips listed here (without boot sectors). 251 */ 252 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 253 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 254 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 255 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 256 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 257 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 258 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 259 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 260 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 261 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 262 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 263 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 264 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 265 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 266 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 267 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 268 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 269 270 /* Spansion -- boot sectors support */ 271 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 272 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 273 274 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 275 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 276 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 277 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 278 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 279 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 280 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 281 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 282 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 283 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 284 285 /* ST Microelectronics -- newer production may have feature updates */ 286 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 287 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 288 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 289 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 290 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 291 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 292 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 293 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 294 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 295 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 296 297 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 298 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 299 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 300 301 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 302 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 303 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 304 305 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 306 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 307 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 308 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 309 310 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 311 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 312 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 313 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 314 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 315 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 316 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 317 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 318 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 319 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 320 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 321 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 322 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 323 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 324 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, 325 }; 326 327 typedef enum { 328 NOP = 0, 329 WRSR = 0x1, 330 WRDI = 0x4, 331 RDSR = 0x5, 332 WREN = 0x6, 333 BRRD = 0x16, 334 BRWR = 0x17, 335 JEDEC_READ = 0x9f, 336 BULK_ERASE_60 = 0x60, 337 BULK_ERASE = 0xc7, 338 READ_FSR = 0x70, 339 RDCR = 0x15, 340 341 READ = 0x03, 342 READ4 = 0x13, 343 FAST_READ = 0x0b, 344 FAST_READ4 = 0x0c, 345 DOR = 0x3b, 346 DOR4 = 0x3c, 347 QOR = 0x6b, 348 QOR4 = 0x6c, 349 DIOR = 0xbb, 350 DIOR4 = 0xbc, 351 QIOR = 0xeb, 352 QIOR4 = 0xec, 353 354 PP = 0x02, 355 PP4 = 0x12, 356 PP4_4 = 0x3e, 357 DPP = 0xa2, 358 QPP = 0x32, 359 QPP_4 = 0x34, 360 RDID_90 = 0x90, 361 RDID_AB = 0xab, 362 363 ERASE_4K = 0x20, 364 ERASE4_4K = 0x21, 365 ERASE_32K = 0x52, 366 ERASE4_32K = 0x5c, 367 ERASE_SECTOR = 0xd8, 368 ERASE4_SECTOR = 0xdc, 369 370 EN_4BYTE_ADDR = 0xB7, 371 EX_4BYTE_ADDR = 0xE9, 372 373 EXTEND_ADDR_READ = 0xC8, 374 EXTEND_ADDR_WRITE = 0xC5, 375 376 RESET_ENABLE = 0x66, 377 RESET_MEMORY = 0x99, 378 379 /* 380 * Micron: 0x35 - enable QPI 381 * Spansion: 0x35 - read control register 382 */ 383 RDCR_EQIO = 0x35, 384 RSTQIO = 0xf5, 385 386 RNVCR = 0xB5, 387 WNVCR = 0xB1, 388 389 RVCR = 0x85, 390 WVCR = 0x81, 391 392 REVCR = 0x65, 393 WEVCR = 0x61, 394 395 DIE_ERASE = 0xC4, 396 } FlashCMD; 397 398 typedef enum { 399 STATE_IDLE, 400 STATE_PAGE_PROGRAM, 401 STATE_READ, 402 STATE_COLLECTING_DATA, 403 STATE_COLLECTING_VAR_LEN_DATA, 404 STATE_READING_DATA, 405 } CMDState; 406 407 typedef enum { 408 MAN_SPANSION, 409 MAN_MACRONIX, 410 MAN_NUMONYX, 411 MAN_WINBOND, 412 MAN_SST, 413 MAN_GENERIC, 414 } Manufacturer; 415 416 typedef enum { 417 MODE_STD = 0, 418 MODE_DIO = 1, 419 MODE_QIO = 2 420 } SPIMode; 421 422 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 423 424 struct Flash { 425 SSIPeripheral parent_obj; 426 427 BlockBackend *blk; 428 429 uint8_t *storage; 430 uint32_t size; 431 int page_size; 432 433 uint8_t state; 434 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 435 uint32_t len; 436 uint32_t pos; 437 bool data_read_loop; 438 uint8_t needed_bytes; 439 uint8_t cmd_in_progress; 440 uint32_t cur_addr; 441 uint32_t nonvolatile_cfg; 442 /* Configuration register for Macronix */ 443 uint32_t volatile_cfg; 444 uint32_t enh_volatile_cfg; 445 /* Spansion cfg registers. */ 446 uint8_t spansion_cr1nv; 447 uint8_t spansion_cr2nv; 448 uint8_t spansion_cr3nv; 449 uint8_t spansion_cr4nv; 450 uint8_t spansion_cr1v; 451 uint8_t spansion_cr2v; 452 uint8_t spansion_cr3v; 453 uint8_t spansion_cr4v; 454 bool write_enable; 455 bool four_bytes_address_mode; 456 bool reset_enable; 457 bool quad_enable; 458 uint8_t ear; 459 460 int64_t dirty_page; 461 462 const FlashPartInfo *pi; 463 464 }; 465 466 struct M25P80Class { 467 SSIPeripheralClass parent_class; 468 FlashPartInfo *pi; 469 }; 470 471 #define TYPE_M25P80 "m25p80-generic" 472 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 473 474 static inline Manufacturer get_man(Flash *s) 475 { 476 switch (s->pi->id[0]) { 477 case 0x20: 478 return MAN_NUMONYX; 479 case 0xEF: 480 return MAN_WINBOND; 481 case 0x01: 482 return MAN_SPANSION; 483 case 0xC2: 484 return MAN_MACRONIX; 485 case 0xBF: 486 return MAN_SST; 487 default: 488 return MAN_GENERIC; 489 } 490 } 491 492 static void blk_sync_complete(void *opaque, int ret) 493 { 494 QEMUIOVector *iov = opaque; 495 496 qemu_iovec_destroy(iov); 497 g_free(iov); 498 499 /* do nothing. Masters do not directly interact with the backing store, 500 * only the working copy so no mutexing required. 501 */ 502 } 503 504 static void flash_sync_page(Flash *s, int page) 505 { 506 QEMUIOVector *iov; 507 508 if (!s->blk || blk_is_read_only(s->blk)) { 509 return; 510 } 511 512 iov = g_new(QEMUIOVector, 1); 513 qemu_iovec_init(iov, 1); 514 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 515 s->pi->page_size); 516 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 517 blk_sync_complete, iov); 518 } 519 520 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 521 { 522 QEMUIOVector *iov; 523 524 if (!s->blk || blk_is_read_only(s->blk)) { 525 return; 526 } 527 528 assert(!(len % BDRV_SECTOR_SIZE)); 529 iov = g_new(QEMUIOVector, 1); 530 qemu_iovec_init(iov, 1); 531 qemu_iovec_add(iov, s->storage + off, len); 532 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 533 } 534 535 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 536 { 537 uint32_t len; 538 uint8_t capa_to_assert = 0; 539 540 switch (cmd) { 541 case ERASE_4K: 542 case ERASE4_4K: 543 len = 4 * KiB; 544 capa_to_assert = ER_4K; 545 break; 546 case ERASE_32K: 547 case ERASE4_32K: 548 len = 32 * KiB; 549 capa_to_assert = ER_32K; 550 break; 551 case ERASE_SECTOR: 552 case ERASE4_SECTOR: 553 len = s->pi->sector_size; 554 break; 555 case BULK_ERASE: 556 len = s->size; 557 break; 558 case DIE_ERASE: 559 if (s->pi->die_cnt) { 560 len = s->size / s->pi->die_cnt; 561 offset = offset & (~(len - 1)); 562 } else { 563 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 564 " by device\n"); 565 return; 566 } 567 break; 568 default: 569 abort(); 570 } 571 572 trace_m25p80_flash_erase(s, offset, len); 573 574 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 575 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 576 " device\n", len); 577 } 578 579 if (!s->write_enable) { 580 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 581 return; 582 } 583 memset(s->storage + offset, 0xff, len); 584 flash_sync_area(s, offset, len); 585 } 586 587 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 588 { 589 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 590 flash_sync_page(s, s->dirty_page); 591 s->dirty_page = newpage; 592 } 593 } 594 595 static inline 596 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 597 { 598 uint32_t page = addr / s->pi->page_size; 599 uint8_t prev = s->storage[s->cur_addr]; 600 601 if (!s->write_enable) { 602 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 603 } 604 605 if ((prev ^ data) & data) { 606 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 607 } 608 609 if (s->pi->flags & EEPROM) { 610 s->storage[s->cur_addr] = data; 611 } else { 612 s->storage[s->cur_addr] &= data; 613 } 614 615 flash_sync_dirty(s, page); 616 s->dirty_page = page; 617 } 618 619 static inline int get_addr_length(Flash *s) 620 { 621 /* check if eeprom is in use */ 622 if (s->pi->flags == EEPROM) { 623 return 2; 624 } 625 626 switch (s->cmd_in_progress) { 627 case PP4: 628 case PP4_4: 629 case QPP_4: 630 case READ4: 631 case QIOR4: 632 case ERASE4_4K: 633 case ERASE4_32K: 634 case ERASE4_SECTOR: 635 case FAST_READ4: 636 case DOR4: 637 case QOR4: 638 case DIOR4: 639 return 4; 640 default: 641 return s->four_bytes_address_mode ? 4 : 3; 642 } 643 } 644 645 static void complete_collecting_data(Flash *s) 646 { 647 int i, n; 648 649 n = get_addr_length(s); 650 s->cur_addr = (n == 3 ? s->ear : 0); 651 for (i = 0; i < n; ++i) { 652 s->cur_addr <<= 8; 653 s->cur_addr |= s->data[i]; 654 } 655 656 s->cur_addr &= s->size - 1; 657 658 s->state = STATE_IDLE; 659 660 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 661 s->cur_addr); 662 663 switch (s->cmd_in_progress) { 664 case DPP: 665 case QPP: 666 case QPP_4: 667 case PP: 668 case PP4: 669 case PP4_4: 670 s->state = STATE_PAGE_PROGRAM; 671 break; 672 case READ: 673 case READ4: 674 case FAST_READ: 675 case FAST_READ4: 676 case DOR: 677 case DOR4: 678 case QOR: 679 case QOR4: 680 case DIOR: 681 case DIOR4: 682 case QIOR: 683 case QIOR4: 684 s->state = STATE_READ; 685 break; 686 case ERASE_4K: 687 case ERASE4_4K: 688 case ERASE_32K: 689 case ERASE4_32K: 690 case ERASE_SECTOR: 691 case ERASE4_SECTOR: 692 case DIE_ERASE: 693 flash_erase(s, s->cur_addr, s->cmd_in_progress); 694 break; 695 case WRSR: 696 switch (get_man(s)) { 697 case MAN_SPANSION: 698 s->quad_enable = !!(s->data[1] & 0x02); 699 break; 700 case MAN_MACRONIX: 701 s->quad_enable = extract32(s->data[0], 6, 1); 702 if (s->len > 1) { 703 s->volatile_cfg = s->data[1]; 704 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 705 } 706 break; 707 default: 708 break; 709 } 710 if (s->write_enable) { 711 s->write_enable = false; 712 } 713 break; 714 case BRWR: 715 case EXTEND_ADDR_WRITE: 716 s->ear = s->data[0]; 717 break; 718 case WNVCR: 719 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 720 break; 721 case WVCR: 722 s->volatile_cfg = s->data[0]; 723 break; 724 case WEVCR: 725 s->enh_volatile_cfg = s->data[0]; 726 break; 727 case RDID_90: 728 case RDID_AB: 729 if (get_man(s) == MAN_SST) { 730 if (s->cur_addr <= 1) { 731 if (s->cur_addr) { 732 s->data[0] = s->pi->id[2]; 733 s->data[1] = s->pi->id[0]; 734 } else { 735 s->data[0] = s->pi->id[0]; 736 s->data[1] = s->pi->id[2]; 737 } 738 s->pos = 0; 739 s->len = 2; 740 s->data_read_loop = true; 741 s->state = STATE_READING_DATA; 742 } else { 743 qemu_log_mask(LOG_GUEST_ERROR, 744 "M25P80: Invalid read id address\n"); 745 } 746 } else { 747 qemu_log_mask(LOG_GUEST_ERROR, 748 "M25P80: Read id (command 0x90/0xAB) is not supported" 749 " by device\n"); 750 } 751 break; 752 default: 753 break; 754 } 755 } 756 757 static void reset_memory(Flash *s) 758 { 759 s->cmd_in_progress = NOP; 760 s->cur_addr = 0; 761 s->ear = 0; 762 s->four_bytes_address_mode = false; 763 s->len = 0; 764 s->needed_bytes = 0; 765 s->pos = 0; 766 s->state = STATE_IDLE; 767 s->write_enable = false; 768 s->reset_enable = false; 769 s->quad_enable = false; 770 771 switch (get_man(s)) { 772 case MAN_NUMONYX: 773 s->volatile_cfg = 0; 774 s->volatile_cfg |= VCFG_DUMMY; 775 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 776 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 777 == NVCFG_XIP_MODE_DISABLED) { 778 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 779 } 780 s->volatile_cfg |= deposit32(s->volatile_cfg, 781 VCFG_DUMMY_CLK_POS, 782 CFG_DUMMY_CLK_LEN, 783 extract32(s->nonvolatile_cfg, 784 NVCFG_DUMMY_CLK_POS, 785 CFG_DUMMY_CLK_LEN) 786 ); 787 788 s->enh_volatile_cfg = 0; 789 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 790 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 791 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 792 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 793 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 794 } 795 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 796 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 797 } 798 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 799 s->four_bytes_address_mode = true; 800 } 801 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 802 s->ear = s->size / MAX_3BYTES_SIZE - 1; 803 } 804 break; 805 case MAN_MACRONIX: 806 s->volatile_cfg = 0x7; 807 break; 808 case MAN_SPANSION: 809 s->spansion_cr1v = s->spansion_cr1nv; 810 s->spansion_cr2v = s->spansion_cr2nv; 811 s->spansion_cr3v = s->spansion_cr3nv; 812 s->spansion_cr4v = s->spansion_cr4nv; 813 s->quad_enable = extract32(s->spansion_cr1v, 814 SPANSION_QUAD_CFG_POS, 815 SPANSION_QUAD_CFG_LEN 816 ); 817 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 818 SPANSION_ADDR_LEN_POS, 819 SPANSION_ADDR_LEN_LEN 820 ); 821 break; 822 default: 823 break; 824 } 825 826 trace_m25p80_reset_done(s); 827 } 828 829 static uint8_t numonyx_mode(Flash *s) 830 { 831 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 832 return MODE_QIO; 833 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 834 return MODE_DIO; 835 } else { 836 return MODE_STD; 837 } 838 } 839 840 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 841 { 842 uint8_t num_dummies; 843 uint8_t mode; 844 assert(get_man(s) == MAN_NUMONYX); 845 846 mode = numonyx_mode(s); 847 num_dummies = extract32(s->volatile_cfg, 4, 4); 848 849 if (num_dummies == 0x0 || num_dummies == 0xf) { 850 switch (s->cmd_in_progress) { 851 case QIOR: 852 case QIOR4: 853 num_dummies = 10; 854 break; 855 default: 856 num_dummies = (mode == MODE_QIO) ? 10 : 8; 857 break; 858 } 859 } 860 861 return num_dummies; 862 } 863 864 static void decode_fast_read_cmd(Flash *s) 865 { 866 s->needed_bytes = get_addr_length(s); 867 switch (get_man(s)) { 868 /* Dummy cycles - modeled with bytes writes instead of bits */ 869 case MAN_WINBOND: 870 s->needed_bytes += 8; 871 break; 872 case MAN_NUMONYX: 873 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 874 break; 875 case MAN_MACRONIX: 876 if (extract32(s->volatile_cfg, 6, 2) == 1) { 877 s->needed_bytes += 6; 878 } else { 879 s->needed_bytes += 8; 880 } 881 break; 882 case MAN_SPANSION: 883 s->needed_bytes += extract32(s->spansion_cr2v, 884 SPANSION_DUMMY_CLK_POS, 885 SPANSION_DUMMY_CLK_LEN 886 ); 887 break; 888 default: 889 break; 890 } 891 s->pos = 0; 892 s->len = 0; 893 s->state = STATE_COLLECTING_DATA; 894 } 895 896 static void decode_dio_read_cmd(Flash *s) 897 { 898 s->needed_bytes = get_addr_length(s); 899 /* Dummy cycles modeled with bytes writes instead of bits */ 900 switch (get_man(s)) { 901 case MAN_WINBOND: 902 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 903 break; 904 case MAN_SPANSION: 905 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 906 s->needed_bytes += extract32(s->spansion_cr2v, 907 SPANSION_DUMMY_CLK_POS, 908 SPANSION_DUMMY_CLK_LEN 909 ); 910 break; 911 case MAN_NUMONYX: 912 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 913 break; 914 case MAN_MACRONIX: 915 switch (extract32(s->volatile_cfg, 6, 2)) { 916 case 1: 917 s->needed_bytes += 6; 918 break; 919 case 2: 920 s->needed_bytes += 8; 921 break; 922 default: 923 s->needed_bytes += 4; 924 break; 925 } 926 break; 927 default: 928 break; 929 } 930 s->pos = 0; 931 s->len = 0; 932 s->state = STATE_COLLECTING_DATA; 933 } 934 935 static void decode_qio_read_cmd(Flash *s) 936 { 937 s->needed_bytes = get_addr_length(s); 938 /* Dummy cycles modeled with bytes writes instead of bits */ 939 switch (get_man(s)) { 940 case MAN_WINBOND: 941 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 942 s->needed_bytes += 4; 943 break; 944 case MAN_SPANSION: 945 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 946 s->needed_bytes += extract32(s->spansion_cr2v, 947 SPANSION_DUMMY_CLK_POS, 948 SPANSION_DUMMY_CLK_LEN 949 ); 950 break; 951 case MAN_NUMONYX: 952 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 953 break; 954 case MAN_MACRONIX: 955 switch (extract32(s->volatile_cfg, 6, 2)) { 956 case 1: 957 s->needed_bytes += 4; 958 break; 959 case 2: 960 s->needed_bytes += 8; 961 break; 962 default: 963 s->needed_bytes += 6; 964 break; 965 } 966 break; 967 default: 968 break; 969 } 970 s->pos = 0; 971 s->len = 0; 972 s->state = STATE_COLLECTING_DATA; 973 } 974 975 static void decode_new_cmd(Flash *s, uint32_t value) 976 { 977 int i; 978 979 s->cmd_in_progress = value; 980 trace_m25p80_command_decoded(s, value); 981 982 if (value != RESET_MEMORY) { 983 s->reset_enable = false; 984 } 985 986 switch (value) { 987 988 case ERASE_4K: 989 case ERASE4_4K: 990 case ERASE_32K: 991 case ERASE4_32K: 992 case ERASE_SECTOR: 993 case ERASE4_SECTOR: 994 case PP: 995 case PP4: 996 case DIE_ERASE: 997 case RDID_90: 998 case RDID_AB: 999 s->needed_bytes = get_addr_length(s); 1000 s->pos = 0; 1001 s->len = 0; 1002 s->state = STATE_COLLECTING_DATA; 1003 break; 1004 case READ: 1005 case READ4: 1006 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1007 s->needed_bytes = get_addr_length(s); 1008 s->pos = 0; 1009 s->len = 0; 1010 s->state = STATE_COLLECTING_DATA; 1011 } else { 1012 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1013 "DIO or QIO mode\n", s->cmd_in_progress); 1014 } 1015 break; 1016 case DPP: 1017 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1018 s->needed_bytes = get_addr_length(s); 1019 s->pos = 0; 1020 s->len = 0; 1021 s->state = STATE_COLLECTING_DATA; 1022 } else { 1023 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1024 "QIO mode\n", s->cmd_in_progress); 1025 } 1026 break; 1027 case QPP: 1028 case QPP_4: 1029 case PP4_4: 1030 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1031 s->needed_bytes = get_addr_length(s); 1032 s->pos = 0; 1033 s->len = 0; 1034 s->state = STATE_COLLECTING_DATA; 1035 } else { 1036 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1037 "DIO mode\n", s->cmd_in_progress); 1038 } 1039 break; 1040 1041 case FAST_READ: 1042 case FAST_READ4: 1043 decode_fast_read_cmd(s); 1044 break; 1045 case DOR: 1046 case DOR4: 1047 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1048 decode_fast_read_cmd(s); 1049 } else { 1050 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1051 "QIO mode\n", s->cmd_in_progress); 1052 } 1053 break; 1054 case QOR: 1055 case QOR4: 1056 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1057 decode_fast_read_cmd(s); 1058 } else { 1059 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1060 "DIO mode\n", s->cmd_in_progress); 1061 } 1062 break; 1063 1064 case DIOR: 1065 case DIOR4: 1066 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1067 decode_dio_read_cmd(s); 1068 } else { 1069 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1070 "QIO mode\n", s->cmd_in_progress); 1071 } 1072 break; 1073 1074 case QIOR: 1075 case QIOR4: 1076 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1077 decode_qio_read_cmd(s); 1078 } else { 1079 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1080 "DIO mode\n", s->cmd_in_progress); 1081 } 1082 break; 1083 1084 case WRSR: 1085 if (s->write_enable) { 1086 switch (get_man(s)) { 1087 case MAN_SPANSION: 1088 s->needed_bytes = 2; 1089 s->state = STATE_COLLECTING_DATA; 1090 break; 1091 case MAN_MACRONIX: 1092 s->needed_bytes = 2; 1093 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1094 break; 1095 default: 1096 s->needed_bytes = 1; 1097 s->state = STATE_COLLECTING_DATA; 1098 } 1099 s->pos = 0; 1100 } 1101 break; 1102 1103 case WRDI: 1104 s->write_enable = false; 1105 break; 1106 case WREN: 1107 s->write_enable = true; 1108 break; 1109 1110 case RDSR: 1111 s->data[0] = (!!s->write_enable) << 1; 1112 if (get_man(s) == MAN_MACRONIX) { 1113 s->data[0] |= (!!s->quad_enable) << 6; 1114 } 1115 s->pos = 0; 1116 s->len = 1; 1117 s->data_read_loop = true; 1118 s->state = STATE_READING_DATA; 1119 break; 1120 1121 case READ_FSR: 1122 s->data[0] = FSR_FLASH_READY; 1123 if (s->four_bytes_address_mode) { 1124 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1125 } 1126 s->pos = 0; 1127 s->len = 1; 1128 s->data_read_loop = true; 1129 s->state = STATE_READING_DATA; 1130 break; 1131 1132 case JEDEC_READ: 1133 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1134 trace_m25p80_populated_jedec(s); 1135 for (i = 0; i < s->pi->id_len; i++) { 1136 s->data[i] = s->pi->id[i]; 1137 } 1138 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1139 s->data[i] = 0; 1140 } 1141 1142 s->len = SPI_NOR_MAX_ID_LEN; 1143 s->pos = 0; 1144 s->state = STATE_READING_DATA; 1145 } else { 1146 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1147 "in DIO or QIO mode\n"); 1148 } 1149 break; 1150 1151 case RDCR: 1152 s->data[0] = s->volatile_cfg & 0xFF; 1153 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1154 s->pos = 0; 1155 s->len = 1; 1156 s->state = STATE_READING_DATA; 1157 break; 1158 1159 case BULK_ERASE_60: 1160 case BULK_ERASE: 1161 if (s->write_enable) { 1162 trace_m25p80_chip_erase(s); 1163 flash_erase(s, 0, BULK_ERASE); 1164 } else { 1165 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1166 "protect!\n"); 1167 } 1168 break; 1169 case NOP: 1170 break; 1171 case EN_4BYTE_ADDR: 1172 s->four_bytes_address_mode = true; 1173 break; 1174 case EX_4BYTE_ADDR: 1175 s->four_bytes_address_mode = false; 1176 break; 1177 case BRRD: 1178 case EXTEND_ADDR_READ: 1179 s->data[0] = s->ear; 1180 s->pos = 0; 1181 s->len = 1; 1182 s->state = STATE_READING_DATA; 1183 break; 1184 case BRWR: 1185 case EXTEND_ADDR_WRITE: 1186 if (s->write_enable) { 1187 s->needed_bytes = 1; 1188 s->pos = 0; 1189 s->len = 0; 1190 s->state = STATE_COLLECTING_DATA; 1191 } 1192 break; 1193 case RNVCR: 1194 s->data[0] = s->nonvolatile_cfg & 0xFF; 1195 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1196 s->pos = 0; 1197 s->len = 2; 1198 s->state = STATE_READING_DATA; 1199 break; 1200 case WNVCR: 1201 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1202 s->needed_bytes = 2; 1203 s->pos = 0; 1204 s->len = 0; 1205 s->state = STATE_COLLECTING_DATA; 1206 } 1207 break; 1208 case RVCR: 1209 s->data[0] = s->volatile_cfg & 0xFF; 1210 s->pos = 0; 1211 s->len = 1; 1212 s->state = STATE_READING_DATA; 1213 break; 1214 case WVCR: 1215 if (s->write_enable) { 1216 s->needed_bytes = 1; 1217 s->pos = 0; 1218 s->len = 0; 1219 s->state = STATE_COLLECTING_DATA; 1220 } 1221 break; 1222 case REVCR: 1223 s->data[0] = s->enh_volatile_cfg & 0xFF; 1224 s->pos = 0; 1225 s->len = 1; 1226 s->state = STATE_READING_DATA; 1227 break; 1228 case WEVCR: 1229 if (s->write_enable) { 1230 s->needed_bytes = 1; 1231 s->pos = 0; 1232 s->len = 0; 1233 s->state = STATE_COLLECTING_DATA; 1234 } 1235 break; 1236 case RESET_ENABLE: 1237 s->reset_enable = true; 1238 break; 1239 case RESET_MEMORY: 1240 if (s->reset_enable) { 1241 reset_memory(s); 1242 } 1243 break; 1244 case RDCR_EQIO: 1245 switch (get_man(s)) { 1246 case MAN_SPANSION: 1247 s->data[0] = (!!s->quad_enable) << 1; 1248 s->pos = 0; 1249 s->len = 1; 1250 s->state = STATE_READING_DATA; 1251 break; 1252 case MAN_MACRONIX: 1253 s->quad_enable = true; 1254 break; 1255 default: 1256 break; 1257 } 1258 break; 1259 case RSTQIO: 1260 s->quad_enable = false; 1261 break; 1262 default: 1263 s->pos = 0; 1264 s->len = 1; 1265 s->state = STATE_READING_DATA; 1266 s->data_read_loop = true; 1267 s->data[0] = 0; 1268 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1269 break; 1270 } 1271 } 1272 1273 static int m25p80_cs(SSIPeripheral *ss, bool select) 1274 { 1275 Flash *s = M25P80(ss); 1276 1277 if (select) { 1278 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1279 complete_collecting_data(s); 1280 } 1281 s->len = 0; 1282 s->pos = 0; 1283 s->state = STATE_IDLE; 1284 flash_sync_dirty(s, -1); 1285 s->data_read_loop = false; 1286 } 1287 1288 trace_m25p80_select(s, select ? "de" : ""); 1289 1290 return 0; 1291 } 1292 1293 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1294 { 1295 Flash *s = M25P80(ss); 1296 uint32_t r = 0; 1297 1298 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1299 s->cur_addr, (uint8_t)tx); 1300 1301 switch (s->state) { 1302 1303 case STATE_PAGE_PROGRAM: 1304 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1305 flash_write8(s, s->cur_addr, (uint8_t)tx); 1306 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1307 break; 1308 1309 case STATE_READ: 1310 r = s->storage[s->cur_addr]; 1311 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1312 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1313 break; 1314 1315 case STATE_COLLECTING_DATA: 1316 case STATE_COLLECTING_VAR_LEN_DATA: 1317 1318 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1319 qemu_log_mask(LOG_GUEST_ERROR, 1320 "M25P80: Write overrun internal data buffer. " 1321 "SPI controller (QEMU emulator or guest driver) " 1322 "is misbehaving\n"); 1323 s->len = s->pos = 0; 1324 s->state = STATE_IDLE; 1325 break; 1326 } 1327 1328 s->data[s->len] = (uint8_t)tx; 1329 s->len++; 1330 1331 if (s->len == s->needed_bytes) { 1332 complete_collecting_data(s); 1333 } 1334 break; 1335 1336 case STATE_READING_DATA: 1337 1338 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1339 qemu_log_mask(LOG_GUEST_ERROR, 1340 "M25P80: Read overrun internal data buffer. " 1341 "SPI controller (QEMU emulator or guest driver) " 1342 "is misbehaving\n"); 1343 s->len = s->pos = 0; 1344 s->state = STATE_IDLE; 1345 break; 1346 } 1347 1348 r = s->data[s->pos]; 1349 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1350 s->pos++; 1351 if (s->pos == s->len) { 1352 s->pos = 0; 1353 if (!s->data_read_loop) { 1354 s->state = STATE_IDLE; 1355 } 1356 } 1357 break; 1358 1359 default: 1360 case STATE_IDLE: 1361 decode_new_cmd(s, (uint8_t)tx); 1362 break; 1363 } 1364 1365 return r; 1366 } 1367 1368 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1369 { 1370 Flash *s = M25P80(ss); 1371 M25P80Class *mc = M25P80_GET_CLASS(s); 1372 int ret; 1373 1374 s->pi = mc->pi; 1375 1376 s->size = s->pi->sector_size * s->pi->n_sectors; 1377 s->dirty_page = -1; 1378 1379 if (s->blk) { 1380 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1381 (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); 1382 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1383 if (ret < 0) { 1384 return; 1385 } 1386 1387 trace_m25p80_binding(s); 1388 s->storage = blk_blockalign(s->blk, s->size); 1389 1390 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1391 error_setg(errp, "failed to read the initial flash content"); 1392 return; 1393 } 1394 } else { 1395 trace_m25p80_binding_no_bdrv(s); 1396 s->storage = blk_blockalign(NULL, s->size); 1397 memset(s->storage, 0xFF, s->size); 1398 } 1399 } 1400 1401 static void m25p80_reset(DeviceState *d) 1402 { 1403 Flash *s = M25P80(d); 1404 1405 reset_memory(s); 1406 } 1407 1408 static int m25p80_pre_save(void *opaque) 1409 { 1410 flash_sync_dirty((Flash *)opaque, -1); 1411 1412 return 0; 1413 } 1414 1415 static Property m25p80_properties[] = { 1416 /* This is default value for Micron flash */ 1417 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1418 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1419 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1420 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1421 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1422 DEFINE_PROP_DRIVE("drive", Flash, blk), 1423 DEFINE_PROP_END_OF_LIST(), 1424 }; 1425 1426 static int m25p80_pre_load(void *opaque) 1427 { 1428 Flash *s = (Flash *)opaque; 1429 1430 s->data_read_loop = false; 1431 return 0; 1432 } 1433 1434 static bool m25p80_data_read_loop_needed(void *opaque) 1435 { 1436 Flash *s = (Flash *)opaque; 1437 1438 return s->data_read_loop; 1439 } 1440 1441 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1442 .name = "m25p80/data_read_loop", 1443 .version_id = 1, 1444 .minimum_version_id = 1, 1445 .needed = m25p80_data_read_loop_needed, 1446 .fields = (VMStateField[]) { 1447 VMSTATE_BOOL(data_read_loop, Flash), 1448 VMSTATE_END_OF_LIST() 1449 } 1450 }; 1451 1452 static const VMStateDescription vmstate_m25p80 = { 1453 .name = "m25p80", 1454 .version_id = 0, 1455 .minimum_version_id = 0, 1456 .pre_save = m25p80_pre_save, 1457 .pre_load = m25p80_pre_load, 1458 .fields = (VMStateField[]) { 1459 VMSTATE_UINT8(state, Flash), 1460 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1461 VMSTATE_UINT32(len, Flash), 1462 VMSTATE_UINT32(pos, Flash), 1463 VMSTATE_UINT8(needed_bytes, Flash), 1464 VMSTATE_UINT8(cmd_in_progress, Flash), 1465 VMSTATE_UINT32(cur_addr, Flash), 1466 VMSTATE_BOOL(write_enable, Flash), 1467 VMSTATE_BOOL(reset_enable, Flash), 1468 VMSTATE_UINT8(ear, Flash), 1469 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1470 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1471 VMSTATE_UINT32(volatile_cfg, Flash), 1472 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1473 VMSTATE_BOOL(quad_enable, Flash), 1474 VMSTATE_UINT8(spansion_cr1nv, Flash), 1475 VMSTATE_UINT8(spansion_cr2nv, Flash), 1476 VMSTATE_UINT8(spansion_cr3nv, Flash), 1477 VMSTATE_UINT8(spansion_cr4nv, Flash), 1478 VMSTATE_END_OF_LIST() 1479 }, 1480 .subsections = (const VMStateDescription * []) { 1481 &vmstate_m25p80_data_read_loop, 1482 NULL 1483 } 1484 }; 1485 1486 static void m25p80_class_init(ObjectClass *klass, void *data) 1487 { 1488 DeviceClass *dc = DEVICE_CLASS(klass); 1489 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1490 M25P80Class *mc = M25P80_CLASS(klass); 1491 1492 k->realize = m25p80_realize; 1493 k->transfer = m25p80_transfer8; 1494 k->set_cs = m25p80_cs; 1495 k->cs_polarity = SSI_CS_LOW; 1496 dc->vmsd = &vmstate_m25p80; 1497 device_class_set_props(dc, m25p80_properties); 1498 dc->reset = m25p80_reset; 1499 mc->pi = data; 1500 } 1501 1502 static const TypeInfo m25p80_info = { 1503 .name = TYPE_M25P80, 1504 .parent = TYPE_SSI_PERIPHERAL, 1505 .instance_size = sizeof(Flash), 1506 .class_size = sizeof(M25P80Class), 1507 .abstract = true, 1508 }; 1509 1510 static void m25p80_register_types(void) 1511 { 1512 int i; 1513 1514 type_register_static(&m25p80_info); 1515 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1516 TypeInfo ti = { 1517 .name = known_devices[i].part_name, 1518 .parent = TYPE_M25P80, 1519 .class_init = m25p80_class_init, 1520 .class_data = (void *)&known_devices[i], 1521 }; 1522 type_register(&ti); 1523 } 1524 } 1525 1526 type_init(m25p80_register_types) 1527