1 /* 2 * CFI parallel flash with AMD command set emulation 3 * 4 * Copyright (c) 2005 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /* 21 * For now, this code can emulate flashes of 1, 2 or 4 bytes width. 22 * Supported commands/modes are: 23 * - flash read 24 * - flash write 25 * - flash ID read 26 * - sector erase 27 * - chip erase 28 * - unlock bypass command 29 * - CFI queries 30 * 31 * It does not support flash interleaving. 32 * It does not implement software data protection as found in many real chips 33 */ 34 35 #include "qemu/osdep.h" 36 #include "hw/block/block.h" 37 #include "hw/block/flash.h" 38 #include "hw/qdev-properties.h" 39 #include "qapi/error.h" 40 #include "qemu/bitmap.h" 41 #include "qemu/timer.h" 42 #include "sysemu/block-backend.h" 43 #include "qemu/host-utils.h" 44 #include "qemu/module.h" 45 #include "hw/sysbus.h" 46 #include "migration/vmstate.h" 47 #include "trace.h" 48 49 #define PFLASH_DEBUG false 50 #define DPRINTF(fmt, ...) \ 51 do { \ 52 if (PFLASH_DEBUG) { \ 53 fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \ 54 } \ 55 } while (0) 56 57 #define PFLASH_LAZY_ROMD_THRESHOLD 42 58 59 /* 60 * The size of the cfi_table indirectly depends on this and the start of the 61 * PRI table directly depends on it. 4 is the maximum size (and also what 62 * seems common) without changing the PRT table address. 63 */ 64 #define PFLASH_MAX_ERASE_REGIONS 4 65 66 /* Special write cycles for CFI queries. */ 67 enum { 68 WCYCLE_CFI = 7, 69 WCYCLE_AUTOSELECT_CFI = 8, 70 }; 71 72 struct PFlashCFI02 { 73 /*< private >*/ 74 SysBusDevice parent_obj; 75 /*< public >*/ 76 77 BlockBackend *blk; 78 uint32_t uniform_nb_blocs; 79 uint32_t uniform_sector_len; 80 uint32_t total_sectors; 81 uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; 82 uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; 83 uint32_t chip_len; 84 uint8_t mappings; 85 uint8_t width; 86 uint8_t be; 87 int wcycle; /* if 0, the flash is read normally */ 88 int bypass; 89 int ro; 90 uint8_t cmd; 91 uint8_t status; 92 /* FIXME: implement array device properties */ 93 uint16_t ident0; 94 uint16_t ident1; 95 uint16_t ident2; 96 uint16_t ident3; 97 uint16_t unlock_addr0; 98 uint16_t unlock_addr1; 99 uint8_t cfi_table[0x4d]; 100 QEMUTimer timer; 101 /* The device replicates the flash memory across its memory space. Emulate 102 * that by having a container (.mem) filled with an array of aliases 103 * (.mem_mappings) pointing to the flash memory (.orig_mem). 104 */ 105 MemoryRegion mem; 106 MemoryRegion *mem_mappings; /* array; one per mapping */ 107 MemoryRegion orig_mem; 108 int rom_mode; 109 int read_counter; /* used for lazy switch-back to rom mode */ 110 int sectors_to_erase; 111 uint64_t erase_time_remaining; 112 unsigned long *sector_erase_map; 113 char *name; 114 void *storage; 115 }; 116 117 /* 118 * Toggle status bit DQ7. 119 */ 120 static inline void toggle_dq7(PFlashCFI02 *pfl) 121 { 122 pfl->status ^= 0x80; 123 } 124 125 /* 126 * Set status bit DQ7 to bit 7 of value. 127 */ 128 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) 129 { 130 pfl->status &= 0x7F; 131 pfl->status |= value & 0x80; 132 } 133 134 /* 135 * Toggle status bit DQ6. 136 */ 137 static inline void toggle_dq6(PFlashCFI02 *pfl) 138 { 139 pfl->status ^= 0x40; 140 } 141 142 /* 143 * Turn on DQ3. 144 */ 145 static inline void assert_dq3(PFlashCFI02 *pfl) 146 { 147 pfl->status |= 0x08; 148 } 149 150 /* 151 * Turn off DQ3. 152 */ 153 static inline void reset_dq3(PFlashCFI02 *pfl) 154 { 155 pfl->status &= ~0x08; 156 } 157 158 /* 159 * Toggle status bit DQ2. 160 */ 161 static inline void toggle_dq2(PFlashCFI02 *pfl) 162 { 163 pfl->status ^= 0x04; 164 } 165 166 /* 167 * Set up replicated mappings of the same region. 168 */ 169 static void pflash_setup_mappings(PFlashCFI02 *pfl) 170 { 171 unsigned i; 172 hwaddr size = memory_region_size(&pfl->orig_mem); 173 174 memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); 175 pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); 176 for (i = 0; i < pfl->mappings; ++i) { 177 memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), 178 "pflash-alias", &pfl->orig_mem, 0, size); 179 memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); 180 } 181 } 182 183 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) 184 { 185 memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); 186 pfl->rom_mode = rom_mode; 187 } 188 189 static size_t pflash_regions_count(PFlashCFI02 *pfl) 190 { 191 return pfl->cfi_table[0x2c]; 192 } 193 194 /* 195 * Returns the time it takes to erase the number of sectors scheduled for 196 * erasure based on CFI address 0x21 which is "Typical timeout per individual 197 * block erase 2^N ms." 198 */ 199 static uint64_t pflash_erase_time(PFlashCFI02 *pfl) 200 { 201 /* 202 * If there are no sectors to erase (which can happen if all of the sectors 203 * to be erased are protected), then erase takes 100 us. Protected sectors 204 * aren't supported so this should never happen. 205 */ 206 return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US; 207 } 208 209 /* 210 * Returns true if the device is currently in erase suspend mode. 211 */ 212 static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl) 213 { 214 return pfl->erase_time_remaining > 0; 215 } 216 217 static void pflash_timer(void *opaque) 218 { 219 PFlashCFI02 *pfl = opaque; 220 221 trace_pflash_timer_expired(pfl->cmd); 222 if (pfl->cmd == 0x30) { 223 /* 224 * Sector erase. If DQ3 is 0 when the timer expires, then the 50 225 * us erase timeout has expired so we need to start the timer for the 226 * sector erase algorithm. Otherwise, the erase completed and we should 227 * go back to read array mode. 228 */ 229 if ((pfl->status & 0x08) == 0) { 230 assert_dq3(pfl); 231 uint64_t timeout = pflash_erase_time(pfl); 232 timer_mod(&pfl->timer, 233 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); 234 DPRINTF("%s: erase timeout fired; erasing %d sectors\n", 235 __func__, pfl->sectors_to_erase); 236 return; 237 } 238 DPRINTF("%s: sector erase complete\n", __func__); 239 bitmap_zero(pfl->sector_erase_map, pfl->total_sectors); 240 pfl->sectors_to_erase = 0; 241 reset_dq3(pfl); 242 } 243 244 /* Reset flash */ 245 toggle_dq7(pfl); 246 if (pfl->bypass) { 247 pfl->wcycle = 2; 248 } else { 249 pflash_register_memory(pfl, 1); 250 pfl->wcycle = 0; 251 } 252 pfl->cmd = 0; 253 } 254 255 /* 256 * Read data from flash. 257 */ 258 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, 259 unsigned int width) 260 { 261 uint8_t *p = (uint8_t *)pfl->storage + offset; 262 uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); 263 trace_pflash_data_read(offset, width, ret); 264 return ret; 265 } 266 267 typedef struct { 268 uint32_t len; 269 uint32_t num; 270 } SectorInfo; 271 272 /* 273 * offset should be a byte offset of the QEMU device and _not_ a device 274 * offset. 275 */ 276 static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset) 277 { 278 assert(offset < pfl->chip_len); 279 hwaddr addr = 0; 280 uint32_t sector_num = 0; 281 for (int i = 0; i < pflash_regions_count(pfl); ++i) { 282 uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i]; 283 if (addr <= offset && offset < addr + region_size) { 284 return (SectorInfo) { 285 .len = pfl->sector_len[i], 286 .num = sector_num + (offset - addr) / pfl->sector_len[i], 287 }; 288 } 289 sector_num += pfl->nb_blocs[i]; 290 addr += region_size; 291 } 292 abort(); 293 } 294 295 /* 296 * Returns true if the offset refers to a flash sector that is currently being 297 * erased. 298 */ 299 static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset) 300 { 301 long sector_num = pflash_sector_info(pfl, offset).num; 302 return test_bit(sector_num, pfl->sector_erase_map); 303 } 304 305 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) 306 { 307 PFlashCFI02 *pfl = opaque; 308 hwaddr boff; 309 uint64_t ret; 310 311 /* Lazy reset to ROMD mode after a certain amount of read accesses */ 312 if (!pfl->rom_mode && pfl->wcycle == 0 && 313 ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { 314 pflash_register_memory(pfl, 1); 315 } 316 offset &= pfl->chip_len - 1; 317 boff = offset & 0xFF; 318 if (pfl->width == 2) { 319 boff = boff >> 1; 320 } else if (pfl->width == 4) { 321 boff = boff >> 2; 322 } 323 switch (pfl->cmd) { 324 default: 325 /* This should never happen : reset state & treat it as a read*/ 326 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); 327 pfl->wcycle = 0; 328 pfl->cmd = 0; 329 /* fall through to the read code */ 330 case 0x80: /* Erase (unlock) */ 331 /* We accept reads during second unlock sequence... */ 332 case 0x00: 333 if (pflash_erase_suspend_mode(pfl) && 334 pflash_sector_is_erasing(pfl, offset)) { 335 /* Toggle bit 2, but not 6. */ 336 toggle_dq2(pfl); 337 /* Status register read */ 338 ret = pfl->status; 339 DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); 340 break; 341 } 342 /* Flash area read */ 343 ret = pflash_data_read(pfl, offset, width); 344 break; 345 case 0x90: /* flash ID read */ 346 switch (boff) { 347 case 0x00: 348 case 0x01: 349 ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; 350 break; 351 case 0x02: 352 ret = 0x00; /* Pretend all sectors are unprotected */ 353 break; 354 case 0x0E: 355 case 0x0F: 356 ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; 357 if (ret != (uint8_t)-1) { 358 break; 359 } 360 /* Fall through to data read. */ 361 default: 362 ret = pflash_data_read(pfl, offset, width); 363 } 364 DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret); 365 break; 366 case 0x10: /* Chip Erase */ 367 case 0x30: /* Sector Erase */ 368 /* Toggle bit 2 during erase, but not program. */ 369 toggle_dq2(pfl); 370 /* fall through */ 371 case 0xA0: /* Program */ 372 /* Toggle bit 6 */ 373 toggle_dq6(pfl); 374 /* Status register read */ 375 ret = pfl->status; 376 DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); 377 break; 378 case 0x98: 379 /* CFI query mode */ 380 if (boff < sizeof(pfl->cfi_table)) { 381 ret = pfl->cfi_table[boff]; 382 } else { 383 ret = 0; 384 } 385 break; 386 } 387 trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle); 388 389 return ret; 390 } 391 392 /* update flash content on disk */ 393 static void pflash_update(PFlashCFI02 *pfl, int offset, int size) 394 { 395 int offset_end; 396 if (pfl->blk) { 397 offset_end = offset + size; 398 /* widen to sector boundaries */ 399 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); 400 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); 401 blk_pwrite(pfl->blk, offset, pfl->storage + offset, 402 offset_end - offset, 0); 403 } 404 } 405 406 static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset) 407 { 408 SectorInfo sector_info = pflash_sector_info(pfl, offset); 409 uint64_t sector_len = sector_info.len; 410 offset &= ~(sector_len - 1); 411 DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n", 412 __func__, pfl->width * 2, offset, 413 pfl->width * 2, offset + sector_len - 1); 414 if (!pfl->ro) { 415 uint8_t *p = pfl->storage; 416 memset(p + offset, 0xff, sector_len); 417 pflash_update(pfl, offset, sector_len); 418 } 419 set_dq7(pfl, 0x00); 420 ++pfl->sectors_to_erase; 421 set_bit(sector_info.num, pfl->sector_erase_map); 422 /* Set (or reset) the 50 us timer for additional erase commands. */ 423 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); 424 } 425 426 static void pflash_write(void *opaque, hwaddr offset, uint64_t value, 427 unsigned int width) 428 { 429 PFlashCFI02 *pfl = opaque; 430 hwaddr boff; 431 uint8_t *p; 432 uint8_t cmd; 433 434 trace_pflash_io_write(offset, width, value, pfl->wcycle); 435 cmd = value; 436 if (pfl->cmd != 0xA0) { 437 /* Reset does nothing during chip erase and sector erase. */ 438 if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) { 439 if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) { 440 /* Return to autoselect mode. */ 441 pfl->wcycle = 3; 442 pfl->cmd = 0x90; 443 return; 444 } 445 goto reset_flash; 446 } 447 } 448 offset &= pfl->chip_len - 1; 449 450 boff = offset; 451 if (pfl->width == 2) { 452 boff = boff >> 1; 453 } else if (pfl->width == 4) { 454 boff = boff >> 2; 455 } 456 /* Only the least-significant 11 bits are used in most cases. */ 457 boff &= 0x7FF; 458 switch (pfl->wcycle) { 459 case 0: 460 /* Set the device in I/O access mode if required */ 461 if (pfl->rom_mode) 462 pflash_register_memory(pfl, 0); 463 pfl->read_counter = 0; 464 /* We're in read mode */ 465 check_unlock0: 466 if (boff == 0x55 && cmd == 0x98) { 467 /* Enter CFI query mode */ 468 pfl->wcycle = WCYCLE_CFI; 469 pfl->cmd = 0x98; 470 return; 471 } 472 /* Handle erase resume in erase suspend mode, otherwise reset. */ 473 if (cmd == 0x30) { /* Erase Resume */ 474 if (pflash_erase_suspend_mode(pfl)) { 475 /* Resume the erase. */ 476 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 477 pfl->erase_time_remaining); 478 pfl->erase_time_remaining = 0; 479 pfl->wcycle = 6; 480 pfl->cmd = 0x30; 481 set_dq7(pfl, 0x00); 482 assert_dq3(pfl); 483 return; 484 } 485 goto reset_flash; 486 } 487 /* Ignore erase suspend. */ 488 if (cmd == 0xB0) { /* Erase Suspend */ 489 return; 490 } 491 if (boff != pfl->unlock_addr0 || cmd != 0xAA) { 492 DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", 493 __func__, boff, cmd, pfl->unlock_addr0); 494 goto reset_flash; 495 } 496 DPRINTF("%s: unlock sequence started\n", __func__); 497 break; 498 case 1: 499 /* We started an unlock sequence */ 500 check_unlock1: 501 if (boff != pfl->unlock_addr1 || cmd != 0x55) { 502 DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, 503 boff, cmd); 504 goto reset_flash; 505 } 506 DPRINTF("%s: unlock sequence done\n", __func__); 507 break; 508 case 2: 509 /* We finished an unlock sequence */ 510 if (!pfl->bypass && boff != pfl->unlock_addr0) { 511 DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, 512 boff, cmd); 513 goto reset_flash; 514 } 515 switch (cmd) { 516 case 0x20: 517 pfl->bypass = 1; 518 goto do_bypass; 519 case 0x80: /* Erase */ 520 case 0x90: /* Autoselect */ 521 case 0xA0: /* Program */ 522 pfl->cmd = cmd; 523 DPRINTF("%s: starting command %02x\n", __func__, cmd); 524 break; 525 default: 526 DPRINTF("%s: unknown command %02x\n", __func__, cmd); 527 goto reset_flash; 528 } 529 break; 530 case 3: 531 switch (pfl->cmd) { 532 case 0x80: /* Erase */ 533 /* We need another unlock sequence */ 534 goto check_unlock0; 535 case 0xA0: /* Program */ 536 if (pflash_erase_suspend_mode(pfl) && 537 pflash_sector_is_erasing(pfl, offset)) { 538 /* Ignore writes to erasing sectors. */ 539 if (pfl->bypass) { 540 goto do_bypass; 541 } 542 goto reset_flash; 543 } 544 trace_pflash_data_write(offset, width, value, 0); 545 if (!pfl->ro) { 546 p = (uint8_t *)pfl->storage + offset; 547 if (pfl->be) { 548 uint64_t current = ldn_be_p(p, width); 549 stn_be_p(p, width, current & value); 550 } else { 551 uint64_t current = ldn_le_p(p, width); 552 stn_le_p(p, width, current & value); 553 } 554 pflash_update(pfl, offset, width); 555 } 556 /* 557 * While programming, status bit DQ7 should hold the opposite 558 * value from how it was programmed. 559 */ 560 set_dq7(pfl, ~value); 561 /* Let's pretend write is immediate */ 562 if (pfl->bypass) 563 goto do_bypass; 564 goto reset_flash; 565 case 0x90: /* Autoselect */ 566 if (pfl->bypass && cmd == 0x00) { 567 /* Unlock bypass reset */ 568 goto reset_flash; 569 } 570 /* 571 * We can enter CFI query mode from autoselect mode, but we must 572 * return to autoselect mode after a reset. 573 */ 574 if (boff == 0x55 && cmd == 0x98) { 575 /* Enter autoselect CFI query mode */ 576 pfl->wcycle = WCYCLE_AUTOSELECT_CFI; 577 pfl->cmd = 0x98; 578 return; 579 } 580 /* fall through */ 581 default: 582 DPRINTF("%s: invalid write for command %02x\n", 583 __func__, pfl->cmd); 584 goto reset_flash; 585 } 586 case 4: 587 switch (pfl->cmd) { 588 case 0xA0: /* Program */ 589 /* Ignore writes while flash data write is occurring */ 590 /* As we suppose write is immediate, this should never happen */ 591 return; 592 case 0x80: /* Erase */ 593 goto check_unlock1; 594 default: 595 /* Should never happen */ 596 DPRINTF("%s: invalid command state %02x (wc 4)\n", 597 __func__, pfl->cmd); 598 goto reset_flash; 599 } 600 break; 601 case 5: 602 if (pflash_erase_suspend_mode(pfl)) { 603 /* Erasing is not supported in erase suspend mode. */ 604 goto reset_flash; 605 } 606 switch (cmd) { 607 case 0x10: /* Chip Erase */ 608 if (boff != pfl->unlock_addr0) { 609 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", 610 __func__, offset); 611 goto reset_flash; 612 } 613 /* Chip erase */ 614 DPRINTF("%s: start chip erase\n", __func__); 615 if (!pfl->ro) { 616 memset(pfl->storage, 0xff, pfl->chip_len); 617 pflash_update(pfl, 0, pfl->chip_len); 618 } 619 set_dq7(pfl, 0x00); 620 /* Wait the time specified at CFI address 0x22. */ 621 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 622 (1ULL << pfl->cfi_table[0x22]) * SCALE_MS); 623 break; 624 case 0x30: /* Sector erase */ 625 pflash_sector_erase(pfl, offset); 626 break; 627 default: 628 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); 629 goto reset_flash; 630 } 631 pfl->cmd = cmd; 632 break; 633 case 6: 634 switch (pfl->cmd) { 635 case 0x10: /* Chip Erase */ 636 /* Ignore writes during chip erase */ 637 return; 638 case 0x30: /* Sector erase */ 639 if (cmd == 0xB0) { 640 /* 641 * If erase suspend happens during the erase timeout (so DQ3 is 642 * 0), then the device suspends erasing immediately. Set the 643 * remaining time to be the total time to erase. Otherwise, 644 * there is a maximum amount of time it can take to enter 645 * suspend mode. Let's ignore that and suspend immediately and 646 * set the remaining time to the actual time remaining on the 647 * timer. 648 */ 649 if ((pfl->status & 0x08) == 0) { 650 pfl->erase_time_remaining = pflash_erase_time(pfl); 651 } else { 652 int64_t delta = timer_expire_time_ns(&pfl->timer) - 653 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 654 /* Make sure we have a positive time remaining. */ 655 pfl->erase_time_remaining = delta <= 0 ? 1 : delta; 656 } 657 reset_dq3(pfl); 658 timer_del(&pfl->timer); 659 pfl->wcycle = 0; 660 pfl->cmd = 0; 661 return; 662 } 663 /* 664 * If DQ3 is 0, additional sector erase commands can be 665 * written and anything else (other than an erase suspend) resets 666 * the device. 667 */ 668 if ((pfl->status & 0x08) == 0) { 669 if (cmd == 0x30) { 670 pflash_sector_erase(pfl, offset); 671 } else { 672 goto reset_flash; 673 } 674 } 675 /* Ignore writes during the actual erase. */ 676 return; 677 default: 678 /* Should never happen */ 679 DPRINTF("%s: invalid command state %02x (wc 6)\n", 680 __func__, pfl->cmd); 681 goto reset_flash; 682 } 683 break; 684 /* Special values for CFI queries */ 685 case WCYCLE_CFI: 686 case WCYCLE_AUTOSELECT_CFI: 687 DPRINTF("%s: invalid write in CFI query mode\n", __func__); 688 goto reset_flash; 689 default: 690 /* Should never happen */ 691 DPRINTF("%s: invalid write state (wc 7)\n", __func__); 692 goto reset_flash; 693 } 694 pfl->wcycle++; 695 696 return; 697 698 /* Reset flash */ 699 reset_flash: 700 trace_pflash_reset(); 701 pfl->bypass = 0; 702 pfl->wcycle = 0; 703 pfl->cmd = 0; 704 return; 705 706 do_bypass: 707 pfl->wcycle = 2; 708 pfl->cmd = 0; 709 } 710 711 static const MemoryRegionOps pflash_cfi02_ops = { 712 .read = pflash_read, 713 .write = pflash_write, 714 .valid.min_access_size = 1, 715 .valid.max_access_size = 4, 716 .endianness = DEVICE_NATIVE_ENDIAN, 717 }; 718 719 static void pflash_cfi02_realize(DeviceState *dev, Error **errp) 720 { 721 PFlashCFI02 *pfl = PFLASH_CFI02(dev); 722 int ret; 723 Error *local_err = NULL; 724 725 if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) { 726 error_setg(errp, "attribute \"sector-length\" not specified or zero."); 727 return; 728 } 729 if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) { 730 error_setg(errp, "attribute \"num-blocks\" not specified or zero."); 731 return; 732 } 733 if (pfl->name == NULL) { 734 error_setg(errp, "attribute \"name\" not specified."); 735 return; 736 } 737 738 int nb_regions; 739 pfl->chip_len = 0; 740 pfl->total_sectors = 0; 741 for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) { 742 if (pfl->nb_blocs[nb_regions] == 0) { 743 break; 744 } 745 pfl->total_sectors += pfl->nb_blocs[nb_regions]; 746 uint64_t sector_len_per_device = pfl->sector_len[nb_regions]; 747 748 /* 749 * The size of each flash sector must be a power of 2 and it must be 750 * aligned at the same power of 2. 751 */ 752 if (sector_len_per_device & 0xff || 753 sector_len_per_device >= (1 << 24) || 754 !is_power_of_2(sector_len_per_device)) 755 { 756 error_setg(errp, "unsupported configuration: " 757 "sector length[%d] per device = %" PRIx64 ".", 758 nb_regions, sector_len_per_device); 759 return; 760 } 761 if (pfl->chip_len & (sector_len_per_device - 1)) { 762 error_setg(errp, "unsupported configuration: " 763 "flash region %d not correctly aligned.", 764 nb_regions); 765 return; 766 } 767 768 pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] * 769 pfl->nb_blocs[nb_regions]; 770 } 771 772 uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs * 773 pfl->uniform_sector_len; 774 if (nb_regions == 0) { 775 nb_regions = 1; 776 pfl->nb_blocs[0] = pfl->uniform_nb_blocs; 777 pfl->sector_len[0] = pfl->uniform_sector_len; 778 pfl->chip_len = uniform_len; 779 pfl->total_sectors = pfl->uniform_nb_blocs; 780 } else if (uniform_len != 0 && uniform_len != pfl->chip_len) { 781 error_setg(errp, "\"num-blocks\"*\"sector-length\" " 782 "different from \"num-blocks0\"*\'sector-length0\" + ... + " 783 "\"num-blocks3\"*\"sector-length3\""); 784 return; 785 } 786 787 memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), 788 &pflash_cfi02_ops, pfl, pfl->name, 789 pfl->chip_len, &local_err); 790 if (local_err) { 791 error_propagate(errp, local_err); 792 return; 793 } 794 795 pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); 796 797 if (pfl->blk) { 798 uint64_t perm; 799 pfl->ro = blk_is_read_only(pfl->blk); 800 perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); 801 ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); 802 if (ret < 0) { 803 return; 804 } 805 } else { 806 pfl->ro = 0; 807 } 808 809 if (pfl->blk) { 810 if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, 811 pfl->chip_len, errp)) { 812 vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); 813 return; 814 } 815 } 816 817 /* Only 11 bits are used in the comparison. */ 818 pfl->unlock_addr0 &= 0x7FF; 819 pfl->unlock_addr1 &= 0x7FF; 820 821 /* Allocate memory for a bitmap for sectors being erased. */ 822 pfl->sector_erase_map = bitmap_new(pfl->total_sectors); 823 824 pflash_setup_mappings(pfl); 825 pfl->rom_mode = 1; 826 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); 827 828 timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); 829 pfl->wcycle = 0; 830 pfl->cmd = 0; 831 pfl->status = 0; 832 833 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ 834 const uint16_t pri_ofs = 0x40; 835 /* Standard "QRY" string */ 836 pfl->cfi_table[0x10] = 'Q'; 837 pfl->cfi_table[0x11] = 'R'; 838 pfl->cfi_table[0x12] = 'Y'; 839 /* Command set (AMD/Fujitsu) */ 840 pfl->cfi_table[0x13] = 0x02; 841 pfl->cfi_table[0x14] = 0x00; 842 /* Primary extended table address */ 843 pfl->cfi_table[0x15] = pri_ofs; 844 pfl->cfi_table[0x16] = pri_ofs >> 8; 845 /* Alternate command set (none) */ 846 pfl->cfi_table[0x17] = 0x00; 847 pfl->cfi_table[0x18] = 0x00; 848 /* Alternate extended table (none) */ 849 pfl->cfi_table[0x19] = 0x00; 850 pfl->cfi_table[0x1A] = 0x00; 851 /* Vcc min */ 852 pfl->cfi_table[0x1B] = 0x27; 853 /* Vcc max */ 854 pfl->cfi_table[0x1C] = 0x36; 855 /* Vpp min (no Vpp pin) */ 856 pfl->cfi_table[0x1D] = 0x00; 857 /* Vpp max (no Vpp pin) */ 858 pfl->cfi_table[0x1E] = 0x00; 859 /* Timeout per single byte/word write (128 ms) */ 860 pfl->cfi_table[0x1F] = 0x07; 861 /* Timeout for min size buffer write (NA) */ 862 pfl->cfi_table[0x20] = 0x00; 863 /* Typical timeout for block erase (512 ms) */ 864 pfl->cfi_table[0x21] = 0x09; 865 /* Typical timeout for full chip erase (4096 ms) */ 866 pfl->cfi_table[0x22] = 0x0C; 867 /* Reserved */ 868 pfl->cfi_table[0x23] = 0x01; 869 /* Max timeout for buffer write (NA) */ 870 pfl->cfi_table[0x24] = 0x00; 871 /* Max timeout for block erase */ 872 pfl->cfi_table[0x25] = 0x0A; 873 /* Max timeout for chip erase */ 874 pfl->cfi_table[0x26] = 0x0D; 875 /* Device size */ 876 pfl->cfi_table[0x27] = ctz32(pfl->chip_len); 877 /* Flash device interface (8 & 16 bits) */ 878 pfl->cfi_table[0x28] = 0x02; 879 pfl->cfi_table[0x29] = 0x00; 880 /* Max number of bytes in multi-bytes write */ 881 /* XXX: disable buffered write as it's not supported */ 882 // pfl->cfi_table[0x2A] = 0x05; 883 pfl->cfi_table[0x2A] = 0x00; 884 pfl->cfi_table[0x2B] = 0x00; 885 /* Number of erase block regions */ 886 pfl->cfi_table[0x2c] = nb_regions; 887 /* Erase block regions */ 888 for (int i = 0; i < nb_regions; ++i) { 889 uint32_t sector_len_per_device = pfl->sector_len[i]; 890 pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1; 891 pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8; 892 pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8; 893 pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16; 894 } 895 assert(0x2c + 4 * nb_regions < pri_ofs); 896 897 /* Extended */ 898 pfl->cfi_table[0x00 + pri_ofs] = 'P'; 899 pfl->cfi_table[0x01 + pri_ofs] = 'R'; 900 pfl->cfi_table[0x02 + pri_ofs] = 'I'; 901 902 /* Extended version 1.0 */ 903 pfl->cfi_table[0x03 + pri_ofs] = '1'; 904 pfl->cfi_table[0x04 + pri_ofs] = '0'; 905 906 /* Address sensitive unlock required. */ 907 pfl->cfi_table[0x05 + pri_ofs] = 0x00; 908 /* Erase suspend to read/write. */ 909 pfl->cfi_table[0x06 + pri_ofs] = 0x02; 910 /* Sector protect not supported. */ 911 pfl->cfi_table[0x07 + pri_ofs] = 0x00; 912 /* Temporary sector unprotect not supported. */ 913 pfl->cfi_table[0x08 + pri_ofs] = 0x00; 914 915 /* Sector protect/unprotect scheme. */ 916 pfl->cfi_table[0x09 + pri_ofs] = 0x00; 917 918 /* Simultaneous operation not supported. */ 919 pfl->cfi_table[0x0a + pri_ofs] = 0x00; 920 /* Burst mode not supported. */ 921 pfl->cfi_table[0x0b + pri_ofs] = 0x00; 922 /* Page mode not supported. */ 923 pfl->cfi_table[0x0c + pri_ofs] = 0x00; 924 assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); 925 } 926 927 static Property pflash_cfi02_properties[] = { 928 DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), 929 DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0), 930 DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0), 931 DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0), 932 DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0), 933 DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0), 934 DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0), 935 DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0), 936 DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0), 937 DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0), 938 DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0), 939 DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), 940 DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), 941 DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), 942 DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), 943 DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), 944 DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), 945 DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), 946 DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), 947 DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), 948 DEFINE_PROP_STRING("name", PFlashCFI02, name), 949 DEFINE_PROP_END_OF_LIST(), 950 }; 951 952 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp) 953 { 954 PFlashCFI02 *pfl = PFLASH_CFI02(dev); 955 timer_del(&pfl->timer); 956 g_free(pfl->sector_erase_map); 957 } 958 959 static void pflash_cfi02_class_init(ObjectClass *klass, void *data) 960 { 961 DeviceClass *dc = DEVICE_CLASS(klass); 962 963 dc->realize = pflash_cfi02_realize; 964 dc->unrealize = pflash_cfi02_unrealize; 965 device_class_set_props(dc, pflash_cfi02_properties); 966 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 967 } 968 969 static const TypeInfo pflash_cfi02_info = { 970 .name = TYPE_PFLASH_CFI02, 971 .parent = TYPE_SYS_BUS_DEVICE, 972 .instance_size = sizeof(PFlashCFI02), 973 .class_init = pflash_cfi02_class_init, 974 }; 975 976 static void pflash_cfi02_register_types(void) 977 { 978 type_register_static(&pflash_cfi02_info); 979 } 980 981 type_init(pflash_cfi02_register_types) 982 983 PFlashCFI02 *pflash_cfi02_register(hwaddr base, 984 const char *name, 985 hwaddr size, 986 BlockBackend *blk, 987 uint32_t sector_len, 988 int nb_mappings, int width, 989 uint16_t id0, uint16_t id1, 990 uint16_t id2, uint16_t id3, 991 uint16_t unlock_addr0, 992 uint16_t unlock_addr1, 993 int be) 994 { 995 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); 996 997 if (blk) { 998 qdev_prop_set_drive(dev, "drive", blk, &error_abort); 999 } 1000 assert(size % sector_len == 0); 1001 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); 1002 qdev_prop_set_uint32(dev, "sector-length", sector_len); 1003 qdev_prop_set_uint8(dev, "width", width); 1004 qdev_prop_set_uint8(dev, "mappings", nb_mappings); 1005 qdev_prop_set_uint8(dev, "big-endian", !!be); 1006 qdev_prop_set_uint16(dev, "id0", id0); 1007 qdev_prop_set_uint16(dev, "id1", id1); 1008 qdev_prop_set_uint16(dev, "id2", id2); 1009 qdev_prop_set_uint16(dev, "id3", id3); 1010 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); 1011 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); 1012 qdev_prop_set_string(dev, "name", name); 1013 qdev_init_nofail(dev); 1014 1015 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1016 return PFLASH_CFI02(dev); 1017 } 1018