1 /* 2 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/sysbus.h" 28 #include "qemu/module.h" 29 #include "hw/char/escc.h" 30 #include "ui/console.h" 31 #include "trace.h" 32 33 /* 34 * Chipset docs: 35 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual", 36 * http://www.zilog.com/docs/serial/scc_escc_um.pdf 37 * 38 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001 39 * (Slave I/O), also produced as NCR89C105. See 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 41 * 42 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips, 43 * mouse and keyboard ports don't implement all functions and they are 44 * only asynchronous. There is no DMA. 45 * 46 * Z85C30 is also used on PowerMacs. There are some small differences 47 * between Sparc version (sunzilog) and PowerMac (pmac): 48 * Offset between control and data registers 49 * There is some kind of lockup bug, but we can ignore it 50 * CTS is inverted 51 * DMA on pmac using DBDMA chip 52 * pmac can do IRDA and faster rates, sunzilog can only do 38400 53 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz 54 */ 55 56 /* 57 * Modifications: 58 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented 59 * serial mouse queue. 60 * Implemented serial mouse protocol. 61 * 62 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic 63 */ 64 65 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a') 66 67 #define SERIAL_CTRL 0 68 #define SERIAL_DATA 1 69 70 #define W_CMD 0 71 #define CMD_PTR_MASK 0x07 72 #define CMD_CMD_MASK 0x38 73 #define CMD_HI 0x08 74 #define CMD_CLR_TXINT 0x28 75 #define CMD_CLR_IUS 0x38 76 #define W_INTR 1 77 #define INTR_INTALL 0x01 78 #define INTR_TXINT 0x02 79 #define INTR_RXMODEMSK 0x18 80 #define INTR_RXINT1ST 0x08 81 #define INTR_RXINTALL 0x10 82 #define W_IVEC 2 83 #define W_RXCTRL 3 84 #define RXCTRL_RXEN 0x01 85 #define W_TXCTRL1 4 86 #define TXCTRL1_PAREN 0x01 87 #define TXCTRL1_PAREV 0x02 88 #define TXCTRL1_1STOP 0x04 89 #define TXCTRL1_1HSTOP 0x08 90 #define TXCTRL1_2STOP 0x0c 91 #define TXCTRL1_STPMSK 0x0c 92 #define TXCTRL1_CLK1X 0x00 93 #define TXCTRL1_CLK16X 0x40 94 #define TXCTRL1_CLK32X 0x80 95 #define TXCTRL1_CLK64X 0xc0 96 #define TXCTRL1_CLKMSK 0xc0 97 #define W_TXCTRL2 5 98 #define TXCTRL2_TXEN 0x08 99 #define TXCTRL2_BITMSK 0x60 100 #define TXCTRL2_5BITS 0x00 101 #define TXCTRL2_7BITS 0x20 102 #define TXCTRL2_6BITS 0x40 103 #define TXCTRL2_8BITS 0x60 104 #define W_SYNC1 6 105 #define W_SYNC2 7 106 #define W_TXBUF 8 107 #define W_MINTR 9 108 #define MINTR_STATUSHI 0x10 109 #define MINTR_RST_MASK 0xc0 110 #define MINTR_RST_B 0x40 111 #define MINTR_RST_A 0x80 112 #define MINTR_RST_ALL 0xc0 113 #define W_MISC1 10 114 #define W_CLOCK 11 115 #define CLOCK_TRXC 0x08 116 #define W_BRGLO 12 117 #define W_BRGHI 13 118 #define W_MISC2 14 119 #define MISC2_PLLDIS 0x30 120 #define W_EXTINT 15 121 #define EXTINT_DCD 0x08 122 #define EXTINT_SYNCINT 0x10 123 #define EXTINT_CTSINT 0x20 124 #define EXTINT_TXUNDRN 0x40 125 #define EXTINT_BRKINT 0x80 126 127 #define R_STATUS 0 128 #define STATUS_RXAV 0x01 129 #define STATUS_ZERO 0x02 130 #define STATUS_TXEMPTY 0x04 131 #define STATUS_DCD 0x08 132 #define STATUS_SYNC 0x10 133 #define STATUS_CTS 0x20 134 #define STATUS_TXUNDRN 0x40 135 #define STATUS_BRK 0x80 136 #define R_SPEC 1 137 #define SPEC_ALLSENT 0x01 138 #define SPEC_BITS8 0x06 139 #define R_IVEC 2 140 #define IVEC_TXINTB 0x00 141 #define IVEC_LONOINT 0x06 142 #define IVEC_LORXINTA 0x0c 143 #define IVEC_LORXINTB 0x04 144 #define IVEC_LOTXINTA 0x08 145 #define IVEC_HINOINT 0x60 146 #define IVEC_HIRXINTA 0x30 147 #define IVEC_HIRXINTB 0x20 148 #define IVEC_HITXINTA 0x10 149 #define R_INTR 3 150 #define INTR_EXTINTB 0x01 151 #define INTR_TXINTB 0x02 152 #define INTR_RXINTB 0x04 153 #define INTR_EXTINTA 0x08 154 #define INTR_TXINTA 0x10 155 #define INTR_RXINTA 0x20 156 #define R_IPEN 4 157 #define R_TXCTRL1 5 158 #define R_TXCTRL2 6 159 #define R_BC 7 160 #define R_RXBUF 8 161 #define R_RXCTRL 9 162 #define R_MISC 10 163 #define R_MISC1 11 164 #define R_BRGLO 12 165 #define R_BRGHI 13 166 #define R_MISC1I 14 167 #define R_EXTINT 15 168 169 static void handle_kbd_command(ESCCChannelState *s, int val); 170 static int serial_can_receive(void *opaque); 171 static void serial_receive_byte(ESCCChannelState *s, int ch); 172 173 static void clear_queue(void *opaque) 174 { 175 ESCCChannelState *s = opaque; 176 ESCCSERIOQueue *q = &s->queue; 177 q->rptr = q->wptr = q->count = 0; 178 } 179 180 static void put_queue(void *opaque, int b) 181 { 182 ESCCChannelState *s = opaque; 183 ESCCSERIOQueue *q = &s->queue; 184 185 trace_escc_put_queue(CHN_C(s), b); 186 if (q->count >= ESCC_SERIO_QUEUE_SIZE) { 187 return; 188 } 189 q->data[q->wptr] = b; 190 if (++q->wptr == ESCC_SERIO_QUEUE_SIZE) { 191 q->wptr = 0; 192 } 193 q->count++; 194 serial_receive_byte(s, 0); 195 } 196 197 static uint32_t get_queue(void *opaque) 198 { 199 ESCCChannelState *s = opaque; 200 ESCCSERIOQueue *q = &s->queue; 201 int val; 202 203 if (q->count == 0) { 204 return 0; 205 } else { 206 val = q->data[q->rptr]; 207 if (++q->rptr == ESCC_SERIO_QUEUE_SIZE) { 208 q->rptr = 0; 209 } 210 q->count--; 211 } 212 trace_escc_get_queue(CHN_C(s), val); 213 if (q->count > 0) 214 serial_receive_byte(s, 0); 215 return val; 216 } 217 218 static int escc_update_irq_chn(ESCCChannelState *s) 219 { 220 if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) || 221 // tx ints enabled, pending 222 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || 223 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && 224 s->rxint == 1) || // rx ints enabled, pending 225 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && 226 (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p 227 return 1; 228 } 229 return 0; 230 } 231 232 static void escc_update_irq(ESCCChannelState *s) 233 { 234 int irq; 235 236 irq = escc_update_irq_chn(s); 237 irq |= escc_update_irq_chn(s->otherchn); 238 239 trace_escc_update_irq(irq); 240 qemu_set_irq(s->irq, irq); 241 } 242 243 static void escc_reset_chn(ESCCChannelState *s) 244 { 245 int i; 246 247 s->reg = 0; 248 for (i = 0; i < ESCC_SERIAL_REGS; i++) { 249 s->rregs[i] = 0; 250 s->wregs[i] = 0; 251 } 252 s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity 253 s->wregs[W_MINTR] = MINTR_RST_ALL; 254 s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC 255 s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled 256 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | 257 EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts 258 if (s->disabled) 259 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | 260 STATUS_CTS | STATUS_TXUNDRN; 261 else 262 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; 263 s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; 264 265 s->rx = s->tx = 0; 266 s->rxint = s->txint = 0; 267 s->rxint_under_svc = s->txint_under_svc = 0; 268 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; 269 clear_queue(s); 270 } 271 272 static void escc_reset(DeviceState *d) 273 { 274 ESCCState *s = ESCC(d); 275 276 escc_reset_chn(&s->chn[0]); 277 escc_reset_chn(&s->chn[1]); 278 } 279 280 static inline void set_rxint(ESCCChannelState *s) 281 { 282 s->rxint = 1; 283 /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower priority 284 than chn_a rx/tx/special_condition service*/ 285 s->rxint_under_svc = 1; 286 if (s->chn == escc_chn_a) { 287 s->rregs[R_INTR] |= INTR_RXINTA; 288 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 289 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; 290 else 291 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; 292 } else { 293 s->otherchn->rregs[R_INTR] |= INTR_RXINTB; 294 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 295 s->rregs[R_IVEC] = IVEC_HIRXINTB; 296 else 297 s->rregs[R_IVEC] = IVEC_LORXINTB; 298 } 299 escc_update_irq(s); 300 } 301 302 static inline void set_txint(ESCCChannelState *s) 303 { 304 s->txint = 1; 305 if (!s->rxint_under_svc) { 306 s->txint_under_svc = 1; 307 if (s->chn == escc_chn_a) { 308 if (s->wregs[W_INTR] & INTR_TXINT) { 309 s->rregs[R_INTR] |= INTR_TXINTA; 310 } 311 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 312 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; 313 else 314 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; 315 } else { 316 s->rregs[R_IVEC] = IVEC_TXINTB; 317 if (s->wregs[W_INTR] & INTR_TXINT) { 318 s->otherchn->rregs[R_INTR] |= INTR_TXINTB; 319 } 320 } 321 escc_update_irq(s); 322 } 323 } 324 325 static inline void clr_rxint(ESCCChannelState *s) 326 { 327 s->rxint = 0; 328 s->rxint_under_svc = 0; 329 if (s->chn == escc_chn_a) { 330 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 331 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; 332 else 333 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; 334 s->rregs[R_INTR] &= ~INTR_RXINTA; 335 } else { 336 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 337 s->rregs[R_IVEC] = IVEC_HINOINT; 338 else 339 s->rregs[R_IVEC] = IVEC_LONOINT; 340 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; 341 } 342 if (s->txint) 343 set_txint(s); 344 escc_update_irq(s); 345 } 346 347 static inline void clr_txint(ESCCChannelState *s) 348 { 349 s->txint = 0; 350 s->txint_under_svc = 0; 351 if (s->chn == escc_chn_a) { 352 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 353 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; 354 else 355 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; 356 s->rregs[R_INTR] &= ~INTR_TXINTA; 357 } else { 358 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; 359 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 360 s->rregs[R_IVEC] = IVEC_HINOINT; 361 else 362 s->rregs[R_IVEC] = IVEC_LONOINT; 363 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; 364 } 365 if (s->rxint) 366 set_rxint(s); 367 escc_update_irq(s); 368 } 369 370 static void escc_update_parameters(ESCCChannelState *s) 371 { 372 int speed, parity, data_bits, stop_bits; 373 QEMUSerialSetParams ssp; 374 375 if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != escc_serial) 376 return; 377 378 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { 379 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) 380 parity = 'E'; 381 else 382 parity = 'O'; 383 } else { 384 parity = 'N'; 385 } 386 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) 387 stop_bits = 2; 388 else 389 stop_bits = 1; 390 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { 391 case TXCTRL2_5BITS: 392 data_bits = 5; 393 break; 394 case TXCTRL2_7BITS: 395 data_bits = 7; 396 break; 397 case TXCTRL2_6BITS: 398 data_bits = 6; 399 break; 400 default: 401 case TXCTRL2_8BITS: 402 data_bits = 8; 403 break; 404 } 405 speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); 406 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) { 407 case TXCTRL1_CLK1X: 408 break; 409 case TXCTRL1_CLK16X: 410 speed /= 16; 411 break; 412 case TXCTRL1_CLK32X: 413 speed /= 32; 414 break; 415 default: 416 case TXCTRL1_CLK64X: 417 speed /= 64; 418 break; 419 } 420 ssp.speed = speed; 421 ssp.parity = parity; 422 ssp.data_bits = data_bits; 423 ssp.stop_bits = stop_bits; 424 trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits); 425 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 426 } 427 428 static void escc_mem_write(void *opaque, hwaddr addr, 429 uint64_t val, unsigned size) 430 { 431 ESCCState *serial = opaque; 432 ESCCChannelState *s; 433 uint32_t saddr; 434 int newreg, channel; 435 436 val &= 0xff; 437 saddr = (addr >> serial->it_shift) & 1; 438 channel = (addr >> (serial->it_shift + 1)) & 1; 439 s = &serial->chn[channel]; 440 switch (saddr) { 441 case SERIAL_CTRL: 442 trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff); 443 newreg = 0; 444 switch (s->reg) { 445 case W_CMD: 446 newreg = val & CMD_PTR_MASK; 447 val &= CMD_CMD_MASK; 448 switch (val) { 449 case CMD_HI: 450 newreg |= CMD_HI; 451 break; 452 case CMD_CLR_TXINT: 453 clr_txint(s); 454 break; 455 case CMD_CLR_IUS: 456 if (s->rxint_under_svc) { 457 s->rxint_under_svc = 0; 458 if (s->txint) { 459 set_txint(s); 460 } 461 } else if (s->txint_under_svc) { 462 s->txint_under_svc = 0; 463 } 464 escc_update_irq(s); 465 break; 466 default: 467 break; 468 } 469 break; 470 case W_INTR ... W_RXCTRL: 471 case W_SYNC1 ... W_TXBUF: 472 case W_MISC1 ... W_CLOCK: 473 case W_MISC2 ... W_EXTINT: 474 s->wregs[s->reg] = val; 475 break; 476 case W_TXCTRL1: 477 case W_TXCTRL2: 478 s->wregs[s->reg] = val; 479 escc_update_parameters(s); 480 break; 481 case W_BRGLO: 482 case W_BRGHI: 483 s->wregs[s->reg] = val; 484 s->rregs[s->reg] = val; 485 escc_update_parameters(s); 486 break; 487 case W_MINTR: 488 switch (val & MINTR_RST_MASK) { 489 case 0: 490 default: 491 break; 492 case MINTR_RST_B: 493 escc_reset_chn(&serial->chn[0]); 494 return; 495 case MINTR_RST_A: 496 escc_reset_chn(&serial->chn[1]); 497 return; 498 case MINTR_RST_ALL: 499 escc_reset(DEVICE(serial)); 500 return; 501 } 502 break; 503 default: 504 break; 505 } 506 if (s->reg == 0) 507 s->reg = newreg; 508 else 509 s->reg = 0; 510 break; 511 case SERIAL_DATA: 512 trace_escc_mem_writeb_data(CHN_C(s), val); 513 /* 514 * Lower the irq when data is written to the Tx buffer and no other 515 * interrupts are currently pending. The irq will be raised again once 516 * the Tx buffer becomes empty below. 517 */ 518 s->txint = 0; 519 escc_update_irq(s); 520 s->tx = val; 521 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled 522 if (qemu_chr_fe_backend_connected(&s->chr)) { 523 /* XXX this blocks entire thread. Rewrite to use 524 * qemu_chr_fe_write and background I/O callbacks */ 525 qemu_chr_fe_write_all(&s->chr, &s->tx, 1); 526 } else if (s->type == escc_kbd && !s->disabled) { 527 handle_kbd_command(s, val); 528 } 529 } 530 s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty 531 s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent 532 set_txint(s); 533 break; 534 default: 535 break; 536 } 537 } 538 539 static uint64_t escc_mem_read(void *opaque, hwaddr addr, 540 unsigned size) 541 { 542 ESCCState *serial = opaque; 543 ESCCChannelState *s; 544 uint32_t saddr; 545 uint32_t ret; 546 int channel; 547 548 saddr = (addr >> serial->it_shift) & 1; 549 channel = (addr >> (serial->it_shift + 1)) & 1; 550 s = &serial->chn[channel]; 551 switch (saddr) { 552 case SERIAL_CTRL: 553 trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]); 554 ret = s->rregs[s->reg]; 555 s->reg = 0; 556 return ret; 557 case SERIAL_DATA: 558 s->rregs[R_STATUS] &= ~STATUS_RXAV; 559 clr_rxint(s); 560 if (s->type == escc_kbd || s->type == escc_mouse) { 561 ret = get_queue(s); 562 } else { 563 ret = s->rx; 564 } 565 trace_escc_mem_readb_data(CHN_C(s), ret); 566 qemu_chr_fe_accept_input(&s->chr); 567 return ret; 568 default: 569 break; 570 } 571 return 0; 572 } 573 574 static const MemoryRegionOps escc_mem_ops = { 575 .read = escc_mem_read, 576 .write = escc_mem_write, 577 .endianness = DEVICE_NATIVE_ENDIAN, 578 .valid = { 579 .min_access_size = 1, 580 .max_access_size = 1, 581 }, 582 }; 583 584 static int serial_can_receive(void *opaque) 585 { 586 ESCCChannelState *s = opaque; 587 int ret; 588 589 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled 590 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) 591 // char already available 592 ret = 0; 593 else 594 ret = 1; 595 return ret; 596 } 597 598 static void serial_receive_byte(ESCCChannelState *s, int ch) 599 { 600 trace_escc_serial_receive_byte(CHN_C(s), ch); 601 s->rregs[R_STATUS] |= STATUS_RXAV; 602 s->rx = ch; 603 set_rxint(s); 604 } 605 606 static void serial_receive_break(ESCCChannelState *s) 607 { 608 s->rregs[R_STATUS] |= STATUS_BRK; 609 escc_update_irq(s); 610 } 611 612 static void serial_receive1(void *opaque, const uint8_t *buf, int size) 613 { 614 ESCCChannelState *s = opaque; 615 serial_receive_byte(s, buf[0]); 616 } 617 618 static void serial_event(void *opaque, int event) 619 { 620 ESCCChannelState *s = opaque; 621 if (event == CHR_EVENT_BREAK) 622 serial_receive_break(s); 623 } 624 625 static const VMStateDescription vmstate_escc_chn = { 626 .name ="escc_chn", 627 .version_id = 2, 628 .minimum_version_id = 1, 629 .fields = (VMStateField[]) { 630 VMSTATE_UINT32(vmstate_dummy, ESCCChannelState), 631 VMSTATE_UINT32(reg, ESCCChannelState), 632 VMSTATE_UINT32(rxint, ESCCChannelState), 633 VMSTATE_UINT32(txint, ESCCChannelState), 634 VMSTATE_UINT32(rxint_under_svc, ESCCChannelState), 635 VMSTATE_UINT32(txint_under_svc, ESCCChannelState), 636 VMSTATE_UINT8(rx, ESCCChannelState), 637 VMSTATE_UINT8(tx, ESCCChannelState), 638 VMSTATE_BUFFER(wregs, ESCCChannelState), 639 VMSTATE_BUFFER(rregs, ESCCChannelState), 640 VMSTATE_END_OF_LIST() 641 } 642 }; 643 644 static const VMStateDescription vmstate_escc = { 645 .name ="escc", 646 .version_id = 2, 647 .minimum_version_id = 1, 648 .fields = (VMStateField[]) { 649 VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn, 650 ESCCChannelState), 651 VMSTATE_END_OF_LIST() 652 } 653 }; 654 655 static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src, 656 InputEvent *evt) 657 { 658 ESCCChannelState *s = (ESCCChannelState *)dev; 659 int qcode, keycode; 660 InputKeyEvent *key; 661 662 assert(evt->type == INPUT_EVENT_KIND_KEY); 663 key = evt->u.key.data; 664 qcode = qemu_input_key_value_to_qcode(key->key); 665 trace_escc_sunkbd_event_in(qcode, QKeyCode_str(qcode), 666 key->down); 667 668 if (qcode == Q_KEY_CODE_CAPS_LOCK) { 669 if (key->down) { 670 s->caps_lock_mode ^= 1; 671 if (s->caps_lock_mode == 2) { 672 return; /* Drop second press */ 673 } 674 } else { 675 s->caps_lock_mode ^= 2; 676 if (s->caps_lock_mode == 3) { 677 return; /* Drop first release */ 678 } 679 } 680 } 681 682 if (qcode == Q_KEY_CODE_NUM_LOCK) { 683 if (key->down) { 684 s->num_lock_mode ^= 1; 685 if (s->num_lock_mode == 2) { 686 return; /* Drop second press */ 687 } 688 } else { 689 s->num_lock_mode ^= 2; 690 if (s->num_lock_mode == 3) { 691 return; /* Drop first release */ 692 } 693 } 694 } 695 696 if (qcode > qemu_input_map_qcode_to_sun_len) { 697 return; 698 } 699 700 keycode = qemu_input_map_qcode_to_sun[qcode]; 701 if (!key->down) { 702 keycode |= 0x80; 703 } 704 trace_escc_sunkbd_event_out(keycode); 705 put_queue(s, keycode); 706 } 707 708 static QemuInputHandler sunkbd_handler = { 709 .name = "sun keyboard", 710 .mask = INPUT_EVENT_MASK_KEY, 711 .event = sunkbd_handle_event, 712 }; 713 714 static void handle_kbd_command(ESCCChannelState *s, int val) 715 { 716 trace_escc_kbd_command(val); 717 if (s->led_mode) { // Ignore led byte 718 s->led_mode = 0; 719 return; 720 } 721 switch (val) { 722 case 1: // Reset, return type code 723 clear_queue(s); 724 put_queue(s, 0xff); 725 put_queue(s, 4); // Type 4 726 put_queue(s, 0x7f); 727 break; 728 case 0xe: // Set leds 729 s->led_mode = 1; 730 break; 731 case 7: // Query layout 732 case 0xf: 733 clear_queue(s); 734 put_queue(s, 0xfe); 735 put_queue(s, 0x21); /* en-us layout */ 736 break; 737 default: 738 break; 739 } 740 } 741 742 static void sunmouse_event(void *opaque, 743 int dx, int dy, int dz, int buttons_state) 744 { 745 ESCCChannelState *s = opaque; 746 int ch; 747 748 trace_escc_sunmouse_event(dx, dy, buttons_state); 749 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */ 750 751 if (buttons_state & MOUSE_EVENT_LBUTTON) 752 ch ^= 0x4; 753 if (buttons_state & MOUSE_EVENT_MBUTTON) 754 ch ^= 0x2; 755 if (buttons_state & MOUSE_EVENT_RBUTTON) 756 ch ^= 0x1; 757 758 put_queue(s, ch); 759 760 ch = dx; 761 762 if (ch > 127) 763 ch = 127; 764 else if (ch < -127) 765 ch = -127; 766 767 put_queue(s, ch & 0xff); 768 769 ch = -dy; 770 771 if (ch > 127) 772 ch = 127; 773 else if (ch < -127) 774 ch = -127; 775 776 put_queue(s, ch & 0xff); 777 778 // MSC protocol specify two extra motion bytes 779 780 put_queue(s, 0); 781 put_queue(s, 0); 782 } 783 784 static void escc_init1(Object *obj) 785 { 786 ESCCState *s = ESCC(obj); 787 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 788 unsigned int i; 789 790 for (i = 0; i < 2; i++) { 791 sysbus_init_irq(dev, &s->chn[i].irq); 792 s->chn[i].chn = 1 - i; 793 } 794 s->chn[0].otherchn = &s->chn[1]; 795 s->chn[1].otherchn = &s->chn[0]; 796 797 sysbus_init_mmio(dev, &s->mmio); 798 } 799 800 static void escc_realize(DeviceState *dev, Error **errp) 801 { 802 ESCCState *s = ESCC(dev); 803 unsigned int i; 804 805 s->chn[0].disabled = s->disabled; 806 s->chn[1].disabled = s->disabled; 807 808 memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc", 809 ESCC_SIZE << s->it_shift); 810 811 for (i = 0; i < 2; i++) { 812 if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) { 813 s->chn[i].clock = s->frequency / 2; 814 qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive, 815 serial_receive1, serial_event, NULL, 816 &s->chn[i], NULL, true); 817 } 818 } 819 820 if (s->chn[0].type == escc_mouse) { 821 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, 822 "QEMU Sun Mouse"); 823 } 824 if (s->chn[1].type == escc_kbd) { 825 s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]), 826 &sunkbd_handler); 827 } 828 } 829 830 static Property escc_properties[] = { 831 DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), 832 DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), 833 DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), 834 DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), 835 DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), 836 DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr), 837 DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr), 838 DEFINE_PROP_END_OF_LIST(), 839 }; 840 841 static void escc_class_init(ObjectClass *klass, void *data) 842 { 843 DeviceClass *dc = DEVICE_CLASS(klass); 844 845 dc->reset = escc_reset; 846 dc->realize = escc_realize; 847 dc->vmsd = &vmstate_escc; 848 dc->props = escc_properties; 849 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 850 } 851 852 static const TypeInfo escc_info = { 853 .name = TYPE_ESCC, 854 .parent = TYPE_SYS_BUS_DEVICE, 855 .instance_size = sizeof(ESCCState), 856 .instance_init = escc_init1, 857 .class_init = escc_class_init, 858 }; 859 860 static void escc_register_types(void) 861 { 862 type_register_static(&escc_info); 863 } 864 865 type_init(escc_register_types) 866