19944d320SPaolo Bonzini /*
29944d320SPaolo Bonzini * Exynos4210 UART Emulation
39944d320SPaolo Bonzini *
49944d320SPaolo Bonzini * Copyright (C) 2011 Samsung Electronics Co Ltd.
59944d320SPaolo Bonzini * Maksim Kozlov, <m.kozlov@samsung.com>
69944d320SPaolo Bonzini *
79944d320SPaolo Bonzini * This program is free software; you can redistribute it and/or modify it
89944d320SPaolo Bonzini * under the terms of the GNU General Public License as published by the
99944d320SPaolo Bonzini * Free Software Foundation; either version 2 of the License, or
109944d320SPaolo Bonzini * (at your option) any later version.
119944d320SPaolo Bonzini *
129944d320SPaolo Bonzini * This program is distributed in the hope that it will be useful, but WITHOUT
139944d320SPaolo Bonzini * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
149944d320SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
159944d320SPaolo Bonzini * for more details.
169944d320SPaolo Bonzini *
179944d320SPaolo Bonzini * You should have received a copy of the GNU General Public License along
189944d320SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>.
199944d320SPaolo Bonzini *
209944d320SPaolo Bonzini */
219944d320SPaolo Bonzini
228ef94f0bSPeter Maydell #include "qemu/osdep.h"
239944d320SPaolo Bonzini #include "hw/sysbus.h"
24d6454270SMarkus Armbruster #include "migration/vmstate.h"
253e80f690SMarkus Armbruster #include "qapi/error.h"
26c525436eSMarkus Armbruster #include "qemu/error-report.h"
270b8fa32fSMarkus Armbruster #include "qemu/module.h"
283a5d3a6fSGuenter Roeck #include "qemu/timer.h"
294d43a603SMarc-André Lureau #include "chardev/char-fe.h"
307566c6efSMarc-André Lureau #include "chardev/char-serial.h"
319944d320SPaolo Bonzini
329944d320SPaolo Bonzini #include "hw/arm/exynos4210.h"
3364552b6bSMarkus Armbruster #include "hw/irq.h"
34a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h"
35ce35e229SEduardo Habkost #include "hw/qdev-properties-system.h"
369944d320SPaolo Bonzini
376804d230SGuenter Roeck #include "trace.h"
38db1015e9SEduardo Habkost #include "qom/object.h"
399944d320SPaolo Bonzini
409944d320SPaolo Bonzini /*
419944d320SPaolo Bonzini * Offsets for UART registers relative to SFR base address
429944d320SPaolo Bonzini * for UARTn
439944d320SPaolo Bonzini *
449944d320SPaolo Bonzini */
459944d320SPaolo Bonzini #define ULCON 0x0000 /* Line Control */
469944d320SPaolo Bonzini #define UCON 0x0004 /* Control */
479944d320SPaolo Bonzini #define UFCON 0x0008 /* FIFO Control */
489944d320SPaolo Bonzini #define UMCON 0x000C /* Modem Control */
499944d320SPaolo Bonzini #define UTRSTAT 0x0010 /* Tx/Rx Status */
509944d320SPaolo Bonzini #define UERSTAT 0x0014 /* UART Error Status */
519944d320SPaolo Bonzini #define UFSTAT 0x0018 /* FIFO Status */
529944d320SPaolo Bonzini #define UMSTAT 0x001C /* Modem Status */
539944d320SPaolo Bonzini #define UTXH 0x0020 /* Transmit Buffer */
549944d320SPaolo Bonzini #define URXH 0x0024 /* Receive Buffer */
559944d320SPaolo Bonzini #define UBRDIV 0x0028 /* Baud Rate Divisor */
569944d320SPaolo Bonzini #define UFRACVAL 0x002C /* Divisor Fractional Value */
579944d320SPaolo Bonzini #define UINTP 0x0030 /* Interrupt Pending */
589944d320SPaolo Bonzini #define UINTSP 0x0034 /* Interrupt Source Pending */
599944d320SPaolo Bonzini #define UINTM 0x0038 /* Interrupt Mask */
609944d320SPaolo Bonzini
619944d320SPaolo Bonzini /*
629944d320SPaolo Bonzini * for indexing register in the uint32_t array
639944d320SPaolo Bonzini *
649944d320SPaolo Bonzini * 'reg' - register offset (see offsets definitions above)
659944d320SPaolo Bonzini *
669944d320SPaolo Bonzini */
679944d320SPaolo Bonzini #define I_(reg) (reg / sizeof(uint32_t))
689944d320SPaolo Bonzini
699944d320SPaolo Bonzini typedef struct Exynos4210UartReg {
709944d320SPaolo Bonzini const char *name; /* the only reason is the debug output */
719944d320SPaolo Bonzini hwaddr offset;
729944d320SPaolo Bonzini uint32_t reset_value;
739944d320SPaolo Bonzini } Exynos4210UartReg;
749944d320SPaolo Bonzini
7575c6d92eSKrzysztof Kozlowski static const Exynos4210UartReg exynos4210_uart_regs[] = {
769944d320SPaolo Bonzini {"ULCON", ULCON, 0x00000000},
779944d320SPaolo Bonzini {"UCON", UCON, 0x00003000},
789944d320SPaolo Bonzini {"UFCON", UFCON, 0x00000000},
799944d320SPaolo Bonzini {"UMCON", UMCON, 0x00000000},
809944d320SPaolo Bonzini {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
819944d320SPaolo Bonzini {"UERSTAT", UERSTAT, 0x00000000}, /* RO */
829944d320SPaolo Bonzini {"UFSTAT", UFSTAT, 0x00000000}, /* RO */
839944d320SPaolo Bonzini {"UMSTAT", UMSTAT, 0x00000000}, /* RO */
849944d320SPaolo Bonzini {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
859944d320SPaolo Bonzini {"URXH", URXH, 0x00000000}, /* RO */
869944d320SPaolo Bonzini {"UBRDIV", UBRDIV, 0x00000000},
879944d320SPaolo Bonzini {"UFRACVAL", UFRACVAL, 0x00000000},
889944d320SPaolo Bonzini {"UINTP", UINTP, 0x00000000},
899944d320SPaolo Bonzini {"UINTSP", UINTSP, 0x00000000},
909944d320SPaolo Bonzini {"UINTM", UINTM, 0x00000000},
919944d320SPaolo Bonzini };
929944d320SPaolo Bonzini
939944d320SPaolo Bonzini #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
949944d320SPaolo Bonzini
959944d320SPaolo Bonzini /* UART FIFO Control */
969944d320SPaolo Bonzini #define UFCON_FIFO_ENABLE 0x1
979944d320SPaolo Bonzini #define UFCON_Rx_FIFO_RESET 0x2
989944d320SPaolo Bonzini #define UFCON_Tx_FIFO_RESET 0x4
999944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
1009944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
1019944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
1029944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
1039944d320SPaolo Bonzini
1049944d320SPaolo Bonzini /* Uart FIFO Status */
1059944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_COUNT 0xff
1069944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_FULL 0x100
1079944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_ERROR 0x200
1089944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
1099944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
1109944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL_SHIFT 24
1119944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
1129944d320SPaolo Bonzini
1139944d320SPaolo Bonzini /* UART Interrupt Source Pending */
1149944d320SPaolo Bonzini #define UINTSP_RXD 0x1 /* Receive interrupt */
1159944d320SPaolo Bonzini #define UINTSP_ERROR 0x2 /* Error interrupt */
1169944d320SPaolo Bonzini #define UINTSP_TXD 0x4 /* Transmit interrupt */
1179944d320SPaolo Bonzini #define UINTSP_MODEM 0x8 /* Modem interrupt */
1189944d320SPaolo Bonzini
1199944d320SPaolo Bonzini /* UART Line Control */
1209944d320SPaolo Bonzini #define ULCON_IR_MODE_SHIFT 6
1219944d320SPaolo Bonzini #define ULCON_PARITY_SHIFT 3
1229944d320SPaolo Bonzini #define ULCON_STOP_BIT_SHIFT 1
1239944d320SPaolo Bonzini
1249944d320SPaolo Bonzini /* UART Tx/Rx Status */
1253a5d3a6fSGuenter Roeck #define UTRSTAT_Rx_TIMEOUT 0x8
1269944d320SPaolo Bonzini #define UTRSTAT_TRANSMITTER_EMPTY 0x4
1279944d320SPaolo Bonzini #define UTRSTAT_Tx_BUFFER_EMPTY 0x2
1289944d320SPaolo Bonzini #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
1299944d320SPaolo Bonzini
1309944d320SPaolo Bonzini /* UART Error Status */
1319944d320SPaolo Bonzini #define UERSTAT_OVERRUN 0x1
1329944d320SPaolo Bonzini #define UERSTAT_PARITY 0x2
1339944d320SPaolo Bonzini #define UERSTAT_FRAME 0x4
1349944d320SPaolo Bonzini #define UERSTAT_BREAK 0x8
1359944d320SPaolo Bonzini
1369944d320SPaolo Bonzini typedef struct {
1379944d320SPaolo Bonzini uint8_t *data;
1389944d320SPaolo Bonzini uint32_t sp, rp; /* store and retrieve pointers */
1399944d320SPaolo Bonzini uint32_t size;
1409944d320SPaolo Bonzini } Exynos4210UartFIFO;
1419944d320SPaolo Bonzini
14261149ff6SAndreas Färber #define TYPE_EXYNOS4210_UART "exynos4210.uart"
1438063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210UartState, EXYNOS4210_UART)
14461149ff6SAndreas Färber
145db1015e9SEduardo Habkost struct Exynos4210UartState {
14661149ff6SAndreas Färber SysBusDevice parent_obj;
14761149ff6SAndreas Färber
1489944d320SPaolo Bonzini MemoryRegion iomem;
1499944d320SPaolo Bonzini
1509944d320SPaolo Bonzini uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
1519944d320SPaolo Bonzini Exynos4210UartFIFO rx;
1529944d320SPaolo Bonzini Exynos4210UartFIFO tx;
1539944d320SPaolo Bonzini
1543a5d3a6fSGuenter Roeck QEMUTimer *fifo_timeout_timer;
1553a5d3a6fSGuenter Roeck uint64_t wordtime; /* word time in ns */
1563a5d3a6fSGuenter Roeck
157becdfa00SMarc-André Lureau CharBackend chr;
1589944d320SPaolo Bonzini qemu_irq irq;
1593c77412bSGuenter Roeck qemu_irq dmairq;
1609944d320SPaolo Bonzini
1619944d320SPaolo Bonzini uint32_t channel;
1629944d320SPaolo Bonzini
163db1015e9SEduardo Habkost };
1649944d320SPaolo Bonzini
1659944d320SPaolo Bonzini
1666804d230SGuenter Roeck /* Used only for tracing */
exynos4210_uart_regname(hwaddr offset)1679944d320SPaolo Bonzini static const char *exynos4210_uart_regname(hwaddr offset)
1689944d320SPaolo Bonzini {
1699944d320SPaolo Bonzini
1709944d320SPaolo Bonzini int i;
1719944d320SPaolo Bonzini
172c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
1739944d320SPaolo Bonzini if (offset == exynos4210_uart_regs[i].offset) {
1749944d320SPaolo Bonzini return exynos4210_uart_regs[i].name;
1759944d320SPaolo Bonzini }
1769944d320SPaolo Bonzini }
1779944d320SPaolo Bonzini
1789944d320SPaolo Bonzini return NULL;
1799944d320SPaolo Bonzini }
1809944d320SPaolo Bonzini
1819944d320SPaolo Bonzini
fifo_store(Exynos4210UartFIFO * q,uint8_t ch)1829944d320SPaolo Bonzini static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
1839944d320SPaolo Bonzini {
1849944d320SPaolo Bonzini q->data[q->sp] = ch;
1859944d320SPaolo Bonzini q->sp = (q->sp + 1) % q->size;
1869944d320SPaolo Bonzini }
1879944d320SPaolo Bonzini
fifo_retrieve(Exynos4210UartFIFO * q)1889944d320SPaolo Bonzini static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
1899944d320SPaolo Bonzini {
1909944d320SPaolo Bonzini uint8_t ret = q->data[q->rp];
1919944d320SPaolo Bonzini q->rp = (q->rp + 1) % q->size;
1929944d320SPaolo Bonzini return ret;
1939944d320SPaolo Bonzini }
1949944d320SPaolo Bonzini
fifo_elements_number(const Exynos4210UartFIFO * q)19575c6d92eSKrzysztof Kozlowski static int fifo_elements_number(const Exynos4210UartFIFO *q)
1969944d320SPaolo Bonzini {
1979944d320SPaolo Bonzini if (q->sp < q->rp) {
1989944d320SPaolo Bonzini return q->size - q->rp + q->sp;
1999944d320SPaolo Bonzini }
2009944d320SPaolo Bonzini
2019944d320SPaolo Bonzini return q->sp - q->rp;
2029944d320SPaolo Bonzini }
2039944d320SPaolo Bonzini
fifo_empty_elements_number(const Exynos4210UartFIFO * q)20475c6d92eSKrzysztof Kozlowski static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
2059944d320SPaolo Bonzini {
2069944d320SPaolo Bonzini return q->size - fifo_elements_number(q);
2079944d320SPaolo Bonzini }
2089944d320SPaolo Bonzini
fifo_reset(Exynos4210UartFIFO * q)2099944d320SPaolo Bonzini static void fifo_reset(Exynos4210UartFIFO *q)
2109944d320SPaolo Bonzini {
2119944d320SPaolo Bonzini g_free(q->data);
2129944d320SPaolo Bonzini q->data = NULL;
2139944d320SPaolo Bonzini
2140a553c12SMarkus Armbruster q->data = g_malloc0(q->size);
2159944d320SPaolo Bonzini
2169944d320SPaolo Bonzini q->sp = 0;
2179944d320SPaolo Bonzini q->rp = 0;
2189944d320SPaolo Bonzini }
2199944d320SPaolo Bonzini
exynos4210_uart_FIFO_trigger_level(uint32_t channel,uint32_t reg)2203a5d3a6fSGuenter Roeck static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel,
2213a5d3a6fSGuenter Roeck uint32_t reg)
2229944d320SPaolo Bonzini {
2233a5d3a6fSGuenter Roeck uint32_t level;
2249944d320SPaolo Bonzini
2253a5d3a6fSGuenter Roeck switch (channel) {
2269944d320SPaolo Bonzini case 0:
2279944d320SPaolo Bonzini level = reg * 32;
2289944d320SPaolo Bonzini break;
2299944d320SPaolo Bonzini case 1:
2309944d320SPaolo Bonzini case 4:
2319944d320SPaolo Bonzini level = reg * 8;
2329944d320SPaolo Bonzini break;
2339944d320SPaolo Bonzini case 2:
2349944d320SPaolo Bonzini case 3:
2359944d320SPaolo Bonzini level = reg * 2;
2369944d320SPaolo Bonzini break;
2379944d320SPaolo Bonzini default:
2389944d320SPaolo Bonzini level = 0;
2393a5d3a6fSGuenter Roeck trace_exynos_uart_channel_error(channel);
2403a5d3a6fSGuenter Roeck break;
2413a5d3a6fSGuenter Roeck }
2423a5d3a6fSGuenter Roeck return level;
2439944d320SPaolo Bonzini }
2449944d320SPaolo Bonzini
2453a5d3a6fSGuenter Roeck static uint32_t
exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState * s)2463a5d3a6fSGuenter Roeck exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
2473a5d3a6fSGuenter Roeck {
2483a5d3a6fSGuenter Roeck uint32_t reg;
2493a5d3a6fSGuenter Roeck
2503a5d3a6fSGuenter Roeck reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
2513a5d3a6fSGuenter Roeck UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
2523a5d3a6fSGuenter Roeck
2533a5d3a6fSGuenter Roeck return exynos4210_uart_FIFO_trigger_level(s->channel, reg);
2543a5d3a6fSGuenter Roeck }
2553a5d3a6fSGuenter Roeck
2563a5d3a6fSGuenter Roeck static uint32_t
exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState * s)2573a5d3a6fSGuenter Roeck exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s)
2583a5d3a6fSGuenter Roeck {
2593a5d3a6fSGuenter Roeck uint32_t reg;
2603a5d3a6fSGuenter Roeck
2613a5d3a6fSGuenter Roeck reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >>
2623a5d3a6fSGuenter Roeck UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1;
2633a5d3a6fSGuenter Roeck
2643a5d3a6fSGuenter Roeck return exynos4210_uart_FIFO_trigger_level(s->channel, reg);
2659944d320SPaolo Bonzini }
2669944d320SPaolo Bonzini
2673c77412bSGuenter Roeck /*
2683c77412bSGuenter Roeck * Update Rx DMA busy signal if Rx DMA is enabled. For simplicity,
2693c77412bSGuenter Roeck * mark DMA as busy if DMA is enabled and the receive buffer is empty.
2703c77412bSGuenter Roeck */
exynos4210_uart_update_dmabusy(Exynos4210UartState * s)2713c77412bSGuenter Roeck static void exynos4210_uart_update_dmabusy(Exynos4210UartState *s)
2723c77412bSGuenter Roeck {
2733c77412bSGuenter Roeck bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02;
2743c77412bSGuenter Roeck uint32_t count = fifo_elements_number(&s->rx);
2753c77412bSGuenter Roeck
2763c77412bSGuenter Roeck if (rx_dma_enabled && !count) {
2773c77412bSGuenter Roeck qemu_irq_raise(s->dmairq);
2783c77412bSGuenter Roeck trace_exynos_uart_dmabusy(s->channel);
2793c77412bSGuenter Roeck } else {
2803c77412bSGuenter Roeck qemu_irq_lower(s->dmairq);
2813c77412bSGuenter Roeck trace_exynos_uart_dmaready(s->channel);
2823c77412bSGuenter Roeck }
2833c77412bSGuenter Roeck }
2843c77412bSGuenter Roeck
exynos4210_uart_update_irq(Exynos4210UartState * s)2859944d320SPaolo Bonzini static void exynos4210_uart_update_irq(Exynos4210UartState *s)
2869944d320SPaolo Bonzini {
2879944d320SPaolo Bonzini /*
2889944d320SPaolo Bonzini * The Tx interrupt is always requested if the number of data in the
2899944d320SPaolo Bonzini * transmit FIFO is smaller than the trigger level.
2909944d320SPaolo Bonzini */
2919944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
2929944d320SPaolo Bonzini uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
2939944d320SPaolo Bonzini UFSTAT_Tx_FIFO_COUNT_SHIFT;
2949944d320SPaolo Bonzini
2959944d320SPaolo Bonzini if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
2969944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD;
2979944d320SPaolo Bonzini }
2983a5d3a6fSGuenter Roeck
2993a5d3a6fSGuenter Roeck /*
3003a5d3a6fSGuenter Roeck * Rx interrupt if trigger level is reached or if rx timeout
3013a5d3a6fSGuenter Roeck * interrupt is disabled and there is data in the receive buffer
3023a5d3a6fSGuenter Roeck */
3033a5d3a6fSGuenter Roeck count = fifo_elements_number(&s->rx);
3043a5d3a6fSGuenter Roeck if ((count && !(s->reg[I_(UCON)] & 0x80)) ||
3053a5d3a6fSGuenter Roeck count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) {
3063c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s);
3073a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD;
3083a5d3a6fSGuenter Roeck timer_del(s->fifo_timeout_timer);
3093a5d3a6fSGuenter Roeck }
3103a5d3a6fSGuenter Roeck } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) {
3113c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s);
3123a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD;
3139944d320SPaolo Bonzini }
3149944d320SPaolo Bonzini
3159944d320SPaolo Bonzini s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
3169944d320SPaolo Bonzini
3179944d320SPaolo Bonzini if (s->reg[I_(UINTP)]) {
3189944d320SPaolo Bonzini qemu_irq_raise(s->irq);
3196804d230SGuenter Roeck trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]);
3209944d320SPaolo Bonzini } else {
3219944d320SPaolo Bonzini qemu_irq_lower(s->irq);
3226804d230SGuenter Roeck trace_exynos_uart_irq_lowered(s->channel);
3239944d320SPaolo Bonzini }
3249944d320SPaolo Bonzini }
3259944d320SPaolo Bonzini
exynos4210_uart_timeout_int(void * opaque)3263a5d3a6fSGuenter Roeck static void exynos4210_uart_timeout_int(void *opaque)
3273a5d3a6fSGuenter Roeck {
3283a5d3a6fSGuenter Roeck Exynos4210UartState *s = opaque;
3293a5d3a6fSGuenter Roeck
3303a5d3a6fSGuenter Roeck trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)],
3313a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)]);
3323a5d3a6fSGuenter Roeck
3333a5d3a6fSGuenter Roeck if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) ||
3343a5d3a6fSGuenter Roeck (s->reg[I_(UCON)] & (1 << 11))) {
3353a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD;
3363a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT;
3373c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s);
3383a5d3a6fSGuenter Roeck exynos4210_uart_update_irq(s);
3393a5d3a6fSGuenter Roeck }
3403a5d3a6fSGuenter Roeck }
3413a5d3a6fSGuenter Roeck
exynos4210_uart_update_parameters(Exynos4210UartState * s)3429944d320SPaolo Bonzini static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
3439944d320SPaolo Bonzini {
344e62694a0SPeter Maydell int speed, parity, data_bits, stop_bits;
3459944d320SPaolo Bonzini QEMUSerialSetParams ssp;
3469944d320SPaolo Bonzini uint64_t uclk_rate;
3479944d320SPaolo Bonzini
3489944d320SPaolo Bonzini if (s->reg[I_(UBRDIV)] == 0) {
3499944d320SPaolo Bonzini return;
3509944d320SPaolo Bonzini }
3519944d320SPaolo Bonzini
3529944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x20) {
3539944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x28) {
3549944d320SPaolo Bonzini parity = 'E';
3559944d320SPaolo Bonzini } else {
3569944d320SPaolo Bonzini parity = 'O';
3579944d320SPaolo Bonzini }
3589944d320SPaolo Bonzini } else {
3599944d320SPaolo Bonzini parity = 'N';
3609944d320SPaolo Bonzini }
3619944d320SPaolo Bonzini
3629944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x4) {
3639944d320SPaolo Bonzini stop_bits = 2;
3649944d320SPaolo Bonzini } else {
3659944d320SPaolo Bonzini stop_bits = 1;
3669944d320SPaolo Bonzini }
3679944d320SPaolo Bonzini
3689944d320SPaolo Bonzini data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
3699944d320SPaolo Bonzini
3709944d320SPaolo Bonzini uclk_rate = 24000000;
3719944d320SPaolo Bonzini
3729944d320SPaolo Bonzini speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
3739944d320SPaolo Bonzini (s->reg[I_(UFRACVAL)] & 0x7) + 16);
3749944d320SPaolo Bonzini
3759944d320SPaolo Bonzini ssp.speed = speed;
3769944d320SPaolo Bonzini ssp.parity = parity;
3779944d320SPaolo Bonzini ssp.data_bits = data_bits;
3789944d320SPaolo Bonzini ssp.stop_bits = stop_bits;
3799944d320SPaolo Bonzini
3803a5d3a6fSGuenter Roeck s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed;
3813a5d3a6fSGuenter Roeck
3825345fdb4SMarc-André Lureau qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
3839944d320SPaolo Bonzini
3846804d230SGuenter Roeck trace_exynos_uart_update_params(
3853a5d3a6fSGuenter Roeck s->channel, speed, parity, data_bits, stop_bits, s->wordtime);
3863a5d3a6fSGuenter Roeck }
3873a5d3a6fSGuenter Roeck
exynos4210_uart_rx_timeout_set(Exynos4210UartState * s)3883a5d3a6fSGuenter Roeck static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s)
3893a5d3a6fSGuenter Roeck {
3903a5d3a6fSGuenter Roeck if (s->reg[I_(UCON)] & 0x80) {
3913a5d3a6fSGuenter Roeck uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime;
3923a5d3a6fSGuenter Roeck
3933a5d3a6fSGuenter Roeck timer_mod(s->fifo_timeout_timer,
3943a5d3a6fSGuenter Roeck qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
3953a5d3a6fSGuenter Roeck } else {
3963a5d3a6fSGuenter Roeck timer_del(s->fifo_timeout_timer);
3973a5d3a6fSGuenter Roeck }
3989944d320SPaolo Bonzini }
3999944d320SPaolo Bonzini
exynos4210_uart_write(void * opaque,hwaddr offset,uint64_t val,unsigned size)4009944d320SPaolo Bonzini static void exynos4210_uart_write(void *opaque, hwaddr offset,
4019944d320SPaolo Bonzini uint64_t val, unsigned size)
4029944d320SPaolo Bonzini {
4039944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque;
4049944d320SPaolo Bonzini uint8_t ch;
4059944d320SPaolo Bonzini
4066804d230SGuenter Roeck trace_exynos_uart_write(s->channel, offset,
4076804d230SGuenter Roeck exynos4210_uart_regname(offset), val);
4089944d320SPaolo Bonzini
4099944d320SPaolo Bonzini switch (offset) {
4109944d320SPaolo Bonzini case ULCON:
4119944d320SPaolo Bonzini case UBRDIV:
4129944d320SPaolo Bonzini case UFRACVAL:
4139944d320SPaolo Bonzini s->reg[I_(offset)] = val;
4149944d320SPaolo Bonzini exynos4210_uart_update_parameters(s);
4159944d320SPaolo Bonzini break;
4169944d320SPaolo Bonzini case UFCON:
4179944d320SPaolo Bonzini s->reg[I_(UFCON)] = val;
4189944d320SPaolo Bonzini if (val & UFCON_Rx_FIFO_RESET) {
4199944d320SPaolo Bonzini fifo_reset(&s->rx);
4209944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
4216804d230SGuenter Roeck trace_exynos_uart_rx_fifo_reset(s->channel);
4229944d320SPaolo Bonzini }
4239944d320SPaolo Bonzini if (val & UFCON_Tx_FIFO_RESET) {
4249944d320SPaolo Bonzini fifo_reset(&s->tx);
4259944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
4266804d230SGuenter Roeck trace_exynos_uart_tx_fifo_reset(s->channel);
4279944d320SPaolo Bonzini }
4289944d320SPaolo Bonzini break;
4299944d320SPaolo Bonzini
4309944d320SPaolo Bonzini case UTXH:
43130650701SAnton Nefedov if (qemu_chr_fe_backend_connected(&s->chr)) {
4329944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
4339944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY);
4349944d320SPaolo Bonzini ch = (uint8_t)val;
4356ab3fc32SDaniel P. Berrange /* XXX this blocks entire thread. Rewrite to use
4366ab3fc32SDaniel P. Berrange * qemu_chr_fe_write and background I/O callbacks */
4375345fdb4SMarc-André Lureau qemu_chr_fe_write_all(&s->chr, &ch, 1);
4386804d230SGuenter Roeck trace_exynos_uart_tx(s->channel, ch);
4399944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
4409944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY;
4419944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD;
4429944d320SPaolo Bonzini exynos4210_uart_update_irq(s);
4439944d320SPaolo Bonzini }
4449944d320SPaolo Bonzini break;
4459944d320SPaolo Bonzini
4469944d320SPaolo Bonzini case UINTP:
4479944d320SPaolo Bonzini s->reg[I_(UINTP)] &= ~val;
4489944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val;
4496804d230SGuenter Roeck trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]);
4509944d320SPaolo Bonzini exynos4210_uart_update_irq(s);
4519944d320SPaolo Bonzini break;
4529944d320SPaolo Bonzini case UTRSTAT:
4533a5d3a6fSGuenter Roeck if (val & UTRSTAT_Rx_TIMEOUT) {
4543a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT;
4553a5d3a6fSGuenter Roeck }
4563a5d3a6fSGuenter Roeck break;
4579944d320SPaolo Bonzini case UERSTAT:
4589944d320SPaolo Bonzini case UFSTAT:
4599944d320SPaolo Bonzini case UMSTAT:
4609944d320SPaolo Bonzini case URXH:
4616804d230SGuenter Roeck trace_exynos_uart_ro_write(
4629944d320SPaolo Bonzini s->channel, exynos4210_uart_regname(offset), offset);
4639944d320SPaolo Bonzini break;
4649944d320SPaolo Bonzini case UINTSP:
4659944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val;
4669944d320SPaolo Bonzini break;
4679944d320SPaolo Bonzini case UINTM:
4689944d320SPaolo Bonzini s->reg[I_(UINTM)] = val;
4699944d320SPaolo Bonzini exynos4210_uart_update_irq(s);
4709944d320SPaolo Bonzini break;
4719944d320SPaolo Bonzini case UCON:
4729944d320SPaolo Bonzini case UMCON:
4739944d320SPaolo Bonzini default:
4749944d320SPaolo Bonzini s->reg[I_(offset)] = val;
4759944d320SPaolo Bonzini break;
4769944d320SPaolo Bonzini }
4779944d320SPaolo Bonzini }
4783a5d3a6fSGuenter Roeck
exynos4210_uart_read(void * opaque,hwaddr offset,unsigned size)4799944d320SPaolo Bonzini static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
4809944d320SPaolo Bonzini unsigned size)
4819944d320SPaolo Bonzini {
4829944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque;
4839944d320SPaolo Bonzini uint32_t res;
4849944d320SPaolo Bonzini
4859944d320SPaolo Bonzini switch (offset) {
4869944d320SPaolo Bonzini case UERSTAT: /* Read Only */
4879944d320SPaolo Bonzini res = s->reg[I_(UERSTAT)];
4889944d320SPaolo Bonzini s->reg[I_(UERSTAT)] = 0;
4896804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset,
4906804d230SGuenter Roeck exynos4210_uart_regname(offset), res);
4919944d320SPaolo Bonzini return res;
4929944d320SPaolo Bonzini case UFSTAT: /* Read Only */
4939944d320SPaolo Bonzini s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
4949944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) == 0) {
4959944d320SPaolo Bonzini s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
4969944d320SPaolo Bonzini s->reg[I_(UFSTAT)] &= ~0xff;
4979944d320SPaolo Bonzini }
4986804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset,
4996804d230SGuenter Roeck exynos4210_uart_regname(offset),
5006804d230SGuenter Roeck s->reg[I_(UFSTAT)]);
5019944d320SPaolo Bonzini return s->reg[I_(UFSTAT)];
5029944d320SPaolo Bonzini case URXH:
5039944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
5049944d320SPaolo Bonzini if (fifo_elements_number(&s->rx)) {
5059944d320SPaolo Bonzini res = fifo_retrieve(&s->rx);
5066804d230SGuenter Roeck trace_exynos_uart_rx(s->channel, res);
5079944d320SPaolo Bonzini if (!fifo_elements_number(&s->rx)) {
5089944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
5099944d320SPaolo Bonzini } else {
5109944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
5119944d320SPaolo Bonzini }
5129944d320SPaolo Bonzini } else {
5136804d230SGuenter Roeck trace_exynos_uart_rx_error(s->channel);
5149944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR;
5159944d320SPaolo Bonzini exynos4210_uart_update_irq(s);
5169944d320SPaolo Bonzini res = 0;
5179944d320SPaolo Bonzini }
5189944d320SPaolo Bonzini } else {
5199944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
5209944d320SPaolo Bonzini res = s->reg[I_(URXH)];
5219944d320SPaolo Bonzini }
522f2c0fb93SIris Johnson qemu_chr_fe_accept_input(&s->chr);
5233c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s);
5246804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset,
5256804d230SGuenter Roeck exynos4210_uart_regname(offset), res);
5269944d320SPaolo Bonzini return res;
5279944d320SPaolo Bonzini case UTXH:
5286804d230SGuenter Roeck trace_exynos_uart_wo_read(s->channel, exynos4210_uart_regname(offset),
5296804d230SGuenter Roeck offset);
5309944d320SPaolo Bonzini break;
5319944d320SPaolo Bonzini default:
5326804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset,
5336804d230SGuenter Roeck exynos4210_uart_regname(offset),
5346804d230SGuenter Roeck s->reg[I_(offset)]);
5359944d320SPaolo Bonzini return s->reg[I_(offset)];
5369944d320SPaolo Bonzini }
5379944d320SPaolo Bonzini
5386804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset),
5396804d230SGuenter Roeck 0);
5409944d320SPaolo Bonzini return 0;
5419944d320SPaolo Bonzini }
5429944d320SPaolo Bonzini
5439944d320SPaolo Bonzini static const MemoryRegionOps exynos4210_uart_ops = {
5449944d320SPaolo Bonzini .read = exynos4210_uart_read,
5459944d320SPaolo Bonzini .write = exynos4210_uart_write,
5469944d320SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN,
5479944d320SPaolo Bonzini .valid = {
5489944d320SPaolo Bonzini .max_access_size = 4,
5499944d320SPaolo Bonzini .unaligned = false
5509944d320SPaolo Bonzini },
5519944d320SPaolo Bonzini };
5529944d320SPaolo Bonzini
exynos4210_uart_can_receive(void * opaque)5539944d320SPaolo Bonzini static int exynos4210_uart_can_receive(void *opaque)
5549944d320SPaolo Bonzini {
5559944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque;
5569944d320SPaolo Bonzini
55740b4c2aeSIris Johnson if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
5589944d320SPaolo Bonzini return fifo_empty_elements_number(&s->rx);
55940b4c2aeSIris Johnson } else {
56040b4c2aeSIris Johnson return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY);
56140b4c2aeSIris Johnson }
5629944d320SPaolo Bonzini }
5639944d320SPaolo Bonzini
exynos4210_uart_receive(void * opaque,const uint8_t * buf,int size)5649944d320SPaolo Bonzini static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
5659944d320SPaolo Bonzini {
5669944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque;
5679944d320SPaolo Bonzini int i;
5689944d320SPaolo Bonzini
5699944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
5709944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) < size) {
5713a5d3a6fSGuenter Roeck size = fifo_empty_elements_number(&s->rx);
5729944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR;
5733a5d3a6fSGuenter Roeck }
5749944d320SPaolo Bonzini for (i = 0; i < size; i++) {
5759944d320SPaolo Bonzini fifo_store(&s->rx, buf[i]);
5769944d320SPaolo Bonzini }
5773a5d3a6fSGuenter Roeck exynos4210_uart_rx_timeout_set(s);
5789944d320SPaolo Bonzini } else {
5799944d320SPaolo Bonzini s->reg[I_(URXH)] = buf[0];
5809944d320SPaolo Bonzini }
5813a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
5829944d320SPaolo Bonzini
5839944d320SPaolo Bonzini exynos4210_uart_update_irq(s);
5849944d320SPaolo Bonzini }
5859944d320SPaolo Bonzini
5869944d320SPaolo Bonzini
exynos4210_uart_event(void * opaque,QEMUChrEvent event)587083b266fSPhilippe Mathieu-Daudé static void exynos4210_uart_event(void *opaque, QEMUChrEvent event)
5889944d320SPaolo Bonzini {
5899944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque;
5909944d320SPaolo Bonzini
5919944d320SPaolo Bonzini if (event == CHR_EVENT_BREAK) {
5929944d320SPaolo Bonzini /* When the RxDn is held in logic 0, then a null byte is pushed into the
5939944d320SPaolo Bonzini * fifo */
5949944d320SPaolo Bonzini fifo_store(&s->rx, '\0');
5959944d320SPaolo Bonzini s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
5969944d320SPaolo Bonzini exynos4210_uart_update_irq(s);
5979944d320SPaolo Bonzini }
5989944d320SPaolo Bonzini }
5999944d320SPaolo Bonzini
6009944d320SPaolo Bonzini
exynos4210_uart_reset(DeviceState * dev)6019944d320SPaolo Bonzini static void exynos4210_uart_reset(DeviceState *dev)
6029944d320SPaolo Bonzini {
60361149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev);
6049944d320SPaolo Bonzini int i;
6059944d320SPaolo Bonzini
606c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
6079944d320SPaolo Bonzini s->reg[I_(exynos4210_uart_regs[i].offset)] =
6089944d320SPaolo Bonzini exynos4210_uart_regs[i].reset_value;
6099944d320SPaolo Bonzini }
6109944d320SPaolo Bonzini
6119944d320SPaolo Bonzini fifo_reset(&s->rx);
6129944d320SPaolo Bonzini fifo_reset(&s->tx);
6139944d320SPaolo Bonzini
6146804d230SGuenter Roeck trace_exynos_uart_rxsize(s->channel, s->rx.size);
6159944d320SPaolo Bonzini }
6169944d320SPaolo Bonzini
exynos4210_uart_post_load(void * opaque,int version_id)617c9d3396dSGuenter Roeck static int exynos4210_uart_post_load(void *opaque, int version_id)
618c9d3396dSGuenter Roeck {
619c9d3396dSGuenter Roeck Exynos4210UartState *s = (Exynos4210UartState *)opaque;
620c9d3396dSGuenter Roeck
621c9d3396dSGuenter Roeck exynos4210_uart_update_parameters(s);
6223a5d3a6fSGuenter Roeck exynos4210_uart_rx_timeout_set(s);
623c9d3396dSGuenter Roeck
624c9d3396dSGuenter Roeck return 0;
625c9d3396dSGuenter Roeck }
626c9d3396dSGuenter Roeck
6279944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart_fifo = {
6289944d320SPaolo Bonzini .name = "exynos4210.uart.fifo",
6299944d320SPaolo Bonzini .version_id = 1,
6309944d320SPaolo Bonzini .minimum_version_id = 1,
631*2f6cab05SRichard Henderson .fields = (const VMStateField[]) {
6329944d320SPaolo Bonzini VMSTATE_UINT32(sp, Exynos4210UartFIFO),
6339944d320SPaolo Bonzini VMSTATE_UINT32(rp, Exynos4210UartFIFO),
63459046ec2SHalil Pasic VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size),
6359944d320SPaolo Bonzini VMSTATE_END_OF_LIST()
6369944d320SPaolo Bonzini }
6379944d320SPaolo Bonzini };
6389944d320SPaolo Bonzini
6399944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart = {
6409944d320SPaolo Bonzini .name = "exynos4210.uart",
6419944d320SPaolo Bonzini .version_id = 1,
6429944d320SPaolo Bonzini .minimum_version_id = 1,
643617dff09SPeter Maydell .post_load = exynos4210_uart_post_load,
644*2f6cab05SRichard Henderson .fields = (const VMStateField[]) {
6459944d320SPaolo Bonzini VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
6469944d320SPaolo Bonzini vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
6479944d320SPaolo Bonzini VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
6489944d320SPaolo Bonzini EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
6499944d320SPaolo Bonzini VMSTATE_END_OF_LIST()
6509944d320SPaolo Bonzini }
6519944d320SPaolo Bonzini };
6529944d320SPaolo Bonzini
exynos4210_uart_create(hwaddr addr,int fifo_size,int channel,Chardev * chr,qemu_irq irq)6539944d320SPaolo Bonzini DeviceState *exynos4210_uart_create(hwaddr addr,
6549944d320SPaolo Bonzini int fifo_size,
6559944d320SPaolo Bonzini int channel,
6560ec7b3e7SMarc-André Lureau Chardev *chr,
6579944d320SPaolo Bonzini qemu_irq irq)
6589944d320SPaolo Bonzini {
6599944d320SPaolo Bonzini DeviceState *dev;
6609944d320SPaolo Bonzini SysBusDevice *bus;
6619944d320SPaolo Bonzini
6623e80f690SMarkus Armbruster dev = qdev_new(TYPE_EXYNOS4210_UART);
6639944d320SPaolo Bonzini
6649944d320SPaolo Bonzini qdev_prop_set_chr(dev, "chardev", chr);
6659944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "channel", channel);
6669944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "rx-size", fifo_size);
6679944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "tx-size", fifo_size);
6689944d320SPaolo Bonzini
6699944d320SPaolo Bonzini bus = SYS_BUS_DEVICE(dev);
6703c6ef471SMarkus Armbruster sysbus_realize_and_unref(bus, &error_fatal);
6719944d320SPaolo Bonzini if (addr != (hwaddr)-1) {
6729944d320SPaolo Bonzini sysbus_mmio_map(bus, 0, addr);
6739944d320SPaolo Bonzini }
6749944d320SPaolo Bonzini sysbus_connect_irq(bus, 0, irq);
6759944d320SPaolo Bonzini
6769944d320SPaolo Bonzini return dev;
6779944d320SPaolo Bonzini }
6789944d320SPaolo Bonzini
exynos4210_uart_init(Object * obj)6795b982482Sxiaoqiang zhao static void exynos4210_uart_init(Object *obj)
6809944d320SPaolo Bonzini {
6815b982482Sxiaoqiang zhao SysBusDevice *dev = SYS_BUS_DEVICE(obj);
68261149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev);
6839944d320SPaolo Bonzini
6843a5d3a6fSGuenter Roeck s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600;
6853a5d3a6fSGuenter Roeck
6869944d320SPaolo Bonzini /* memory mapping */
6875b982482Sxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,
688300b1fc6SPaolo Bonzini "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
6899944d320SPaolo Bonzini sysbus_init_mmio(dev, &s->iomem);
6909944d320SPaolo Bonzini
6919944d320SPaolo Bonzini sysbus_init_irq(dev, &s->irq);
6923c77412bSGuenter Roeck sysbus_init_irq(dev, &s->dmairq);
6935b982482Sxiaoqiang zhao }
6945b982482Sxiaoqiang zhao
exynos4210_uart_realize(DeviceState * dev,Error ** errp)6955b982482Sxiaoqiang zhao static void exynos4210_uart_realize(DeviceState *dev, Error **errp)
6965b982482Sxiaoqiang zhao {
6975b982482Sxiaoqiang zhao Exynos4210UartState *s = EXYNOS4210_UART(dev);
6989944d320SPaolo Bonzini
6998bbc394cSChen Qun s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
7008bbc394cSChen Qun exynos4210_uart_timeout_int, s);
7018bbc394cSChen Qun
7025345fdb4SMarc-André Lureau qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
7035345fdb4SMarc-André Lureau exynos4210_uart_receive, exynos4210_uart_event,
70481517ba3SAnton Nefedov NULL, s, NULL, true);
7059944d320SPaolo Bonzini }
7069944d320SPaolo Bonzini
7079944d320SPaolo Bonzini static Property exynos4210_uart_properties[] = {
7089944d320SPaolo Bonzini DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
7099944d320SPaolo Bonzini DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
7109944d320SPaolo Bonzini DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
7119944d320SPaolo Bonzini DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
7129944d320SPaolo Bonzini DEFINE_PROP_END_OF_LIST(),
7139944d320SPaolo Bonzini };
7149944d320SPaolo Bonzini
exynos4210_uart_class_init(ObjectClass * klass,void * data)7159944d320SPaolo Bonzini static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
7169944d320SPaolo Bonzini {
7179944d320SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass);
7189944d320SPaolo Bonzini
7195b982482Sxiaoqiang zhao dc->realize = exynos4210_uart_realize;
7209944d320SPaolo Bonzini dc->reset = exynos4210_uart_reset;
7214f67d30bSMarc-André Lureau device_class_set_props(dc, exynos4210_uart_properties);
7229944d320SPaolo Bonzini dc->vmsd = &vmstate_exynos4210_uart;
7239944d320SPaolo Bonzini }
7249944d320SPaolo Bonzini
7259944d320SPaolo Bonzini static const TypeInfo exynos4210_uart_info = {
72661149ff6SAndreas Färber .name = TYPE_EXYNOS4210_UART,
7279944d320SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE,
7289944d320SPaolo Bonzini .instance_size = sizeof(Exynos4210UartState),
7295b982482Sxiaoqiang zhao .instance_init = exynos4210_uart_init,
7309944d320SPaolo Bonzini .class_init = exynos4210_uart_class_init,
7319944d320SPaolo Bonzini };
7329944d320SPaolo Bonzini
exynos4210_uart_register(void)7339944d320SPaolo Bonzini static void exynos4210_uart_register(void)
7349944d320SPaolo Bonzini {
7359944d320SPaolo Bonzini type_register_static(&exynos4210_uart_info);
7369944d320SPaolo Bonzini }
7379944d320SPaolo Bonzini
7389944d320SPaolo Bonzini type_init(exynos4210_uart_register)
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