19944d320SPaolo Bonzini /* 29944d320SPaolo Bonzini * Exynos4210 UART Emulation 39944d320SPaolo Bonzini * 49944d320SPaolo Bonzini * Copyright (C) 2011 Samsung Electronics Co Ltd. 59944d320SPaolo Bonzini * Maksim Kozlov, <m.kozlov@samsung.com> 69944d320SPaolo Bonzini * 79944d320SPaolo Bonzini * This program is free software; you can redistribute it and/or modify it 89944d320SPaolo Bonzini * under the terms of the GNU General Public License as published by the 99944d320SPaolo Bonzini * Free Software Foundation; either version 2 of the License, or 109944d320SPaolo Bonzini * (at your option) any later version. 119944d320SPaolo Bonzini * 129944d320SPaolo Bonzini * This program is distributed in the hope that it will be useful, but WITHOUT 139944d320SPaolo Bonzini * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 149944d320SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 159944d320SPaolo Bonzini * for more details. 169944d320SPaolo Bonzini * 179944d320SPaolo Bonzini * You should have received a copy of the GNU General Public License along 189944d320SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 199944d320SPaolo Bonzini * 209944d320SPaolo Bonzini */ 219944d320SPaolo Bonzini 228ef94f0bSPeter Maydell #include "qemu/osdep.h" 239944d320SPaolo Bonzini #include "hw/sysbus.h" 24d6454270SMarkus Armbruster #include "migration/vmstate.h" 25c525436eSMarkus Armbruster #include "qemu/error-report.h" 260b8fa32fSMarkus Armbruster #include "qemu/module.h" 27*3a5d3a6fSGuenter Roeck #include "qemu/timer.h" 284d43a603SMarc-André Lureau #include "chardev/char-fe.h" 297566c6efSMarc-André Lureau #include "chardev/char-serial.h" 309944d320SPaolo Bonzini 319944d320SPaolo Bonzini #include "hw/arm/exynos4210.h" 3264552b6bSMarkus Armbruster #include "hw/irq.h" 33a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 349944d320SPaolo Bonzini 356804d230SGuenter Roeck #include "trace.h" 369944d320SPaolo Bonzini 379944d320SPaolo Bonzini /* 389944d320SPaolo Bonzini * Offsets for UART registers relative to SFR base address 399944d320SPaolo Bonzini * for UARTn 409944d320SPaolo Bonzini * 419944d320SPaolo Bonzini */ 429944d320SPaolo Bonzini #define ULCON 0x0000 /* Line Control */ 439944d320SPaolo Bonzini #define UCON 0x0004 /* Control */ 449944d320SPaolo Bonzini #define UFCON 0x0008 /* FIFO Control */ 459944d320SPaolo Bonzini #define UMCON 0x000C /* Modem Control */ 469944d320SPaolo Bonzini #define UTRSTAT 0x0010 /* Tx/Rx Status */ 479944d320SPaolo Bonzini #define UERSTAT 0x0014 /* UART Error Status */ 489944d320SPaolo Bonzini #define UFSTAT 0x0018 /* FIFO Status */ 499944d320SPaolo Bonzini #define UMSTAT 0x001C /* Modem Status */ 509944d320SPaolo Bonzini #define UTXH 0x0020 /* Transmit Buffer */ 519944d320SPaolo Bonzini #define URXH 0x0024 /* Receive Buffer */ 529944d320SPaolo Bonzini #define UBRDIV 0x0028 /* Baud Rate Divisor */ 539944d320SPaolo Bonzini #define UFRACVAL 0x002C /* Divisor Fractional Value */ 549944d320SPaolo Bonzini #define UINTP 0x0030 /* Interrupt Pending */ 559944d320SPaolo Bonzini #define UINTSP 0x0034 /* Interrupt Source Pending */ 569944d320SPaolo Bonzini #define UINTM 0x0038 /* Interrupt Mask */ 579944d320SPaolo Bonzini 589944d320SPaolo Bonzini /* 599944d320SPaolo Bonzini * for indexing register in the uint32_t array 609944d320SPaolo Bonzini * 619944d320SPaolo Bonzini * 'reg' - register offset (see offsets definitions above) 629944d320SPaolo Bonzini * 639944d320SPaolo Bonzini */ 649944d320SPaolo Bonzini #define I_(reg) (reg / sizeof(uint32_t)) 659944d320SPaolo Bonzini 669944d320SPaolo Bonzini typedef struct Exynos4210UartReg { 679944d320SPaolo Bonzini const char *name; /* the only reason is the debug output */ 689944d320SPaolo Bonzini hwaddr offset; 699944d320SPaolo Bonzini uint32_t reset_value; 709944d320SPaolo Bonzini } Exynos4210UartReg; 719944d320SPaolo Bonzini 7275c6d92eSKrzysztof Kozlowski static const Exynos4210UartReg exynos4210_uart_regs[] = { 739944d320SPaolo Bonzini {"ULCON", ULCON, 0x00000000}, 749944d320SPaolo Bonzini {"UCON", UCON, 0x00003000}, 759944d320SPaolo Bonzini {"UFCON", UFCON, 0x00000000}, 769944d320SPaolo Bonzini {"UMCON", UMCON, 0x00000000}, 779944d320SPaolo Bonzini {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 789944d320SPaolo Bonzini {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 799944d320SPaolo Bonzini {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 809944d320SPaolo Bonzini {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 819944d320SPaolo Bonzini {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 829944d320SPaolo Bonzini {"URXH", URXH, 0x00000000}, /* RO */ 839944d320SPaolo Bonzini {"UBRDIV", UBRDIV, 0x00000000}, 849944d320SPaolo Bonzini {"UFRACVAL", UFRACVAL, 0x00000000}, 859944d320SPaolo Bonzini {"UINTP", UINTP, 0x00000000}, 869944d320SPaolo Bonzini {"UINTSP", UINTSP, 0x00000000}, 879944d320SPaolo Bonzini {"UINTM", UINTM, 0x00000000}, 889944d320SPaolo Bonzini }; 899944d320SPaolo Bonzini 909944d320SPaolo Bonzini #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 919944d320SPaolo Bonzini 929944d320SPaolo Bonzini /* UART FIFO Control */ 939944d320SPaolo Bonzini #define UFCON_FIFO_ENABLE 0x1 949944d320SPaolo Bonzini #define UFCON_Rx_FIFO_RESET 0x2 959944d320SPaolo Bonzini #define UFCON_Tx_FIFO_RESET 0x4 969944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 979944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 989944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 999944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 1009944d320SPaolo Bonzini 1019944d320SPaolo Bonzini /* Uart FIFO Status */ 1029944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_COUNT 0xff 1039944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_FULL 0x100 1049944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_ERROR 0x200 1059944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 1069944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 1079944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 1089944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 1099944d320SPaolo Bonzini 1109944d320SPaolo Bonzini /* UART Interrupt Source Pending */ 1119944d320SPaolo Bonzini #define UINTSP_RXD 0x1 /* Receive interrupt */ 1129944d320SPaolo Bonzini #define UINTSP_ERROR 0x2 /* Error interrupt */ 1139944d320SPaolo Bonzini #define UINTSP_TXD 0x4 /* Transmit interrupt */ 1149944d320SPaolo Bonzini #define UINTSP_MODEM 0x8 /* Modem interrupt */ 1159944d320SPaolo Bonzini 1169944d320SPaolo Bonzini /* UART Line Control */ 1179944d320SPaolo Bonzini #define ULCON_IR_MODE_SHIFT 6 1189944d320SPaolo Bonzini #define ULCON_PARITY_SHIFT 3 1199944d320SPaolo Bonzini #define ULCON_STOP_BIT_SHIFT 1 1209944d320SPaolo Bonzini 1219944d320SPaolo Bonzini /* UART Tx/Rx Status */ 122*3a5d3a6fSGuenter Roeck #define UTRSTAT_Rx_TIMEOUT 0x8 1239944d320SPaolo Bonzini #define UTRSTAT_TRANSMITTER_EMPTY 0x4 1249944d320SPaolo Bonzini #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 1259944d320SPaolo Bonzini #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 1269944d320SPaolo Bonzini 1279944d320SPaolo Bonzini /* UART Error Status */ 1289944d320SPaolo Bonzini #define UERSTAT_OVERRUN 0x1 1299944d320SPaolo Bonzini #define UERSTAT_PARITY 0x2 1309944d320SPaolo Bonzini #define UERSTAT_FRAME 0x4 1319944d320SPaolo Bonzini #define UERSTAT_BREAK 0x8 1329944d320SPaolo Bonzini 1339944d320SPaolo Bonzini typedef struct { 1349944d320SPaolo Bonzini uint8_t *data; 1359944d320SPaolo Bonzini uint32_t sp, rp; /* store and retrieve pointers */ 1369944d320SPaolo Bonzini uint32_t size; 1379944d320SPaolo Bonzini } Exynos4210UartFIFO; 1389944d320SPaolo Bonzini 13961149ff6SAndreas Färber #define TYPE_EXYNOS4210_UART "exynos4210.uart" 14061149ff6SAndreas Färber #define EXYNOS4210_UART(obj) \ 14161149ff6SAndreas Färber OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 14261149ff6SAndreas Färber 14361149ff6SAndreas Färber typedef struct Exynos4210UartState { 14461149ff6SAndreas Färber SysBusDevice parent_obj; 14561149ff6SAndreas Färber 1469944d320SPaolo Bonzini MemoryRegion iomem; 1479944d320SPaolo Bonzini 1489944d320SPaolo Bonzini uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 1499944d320SPaolo Bonzini Exynos4210UartFIFO rx; 1509944d320SPaolo Bonzini Exynos4210UartFIFO tx; 1519944d320SPaolo Bonzini 152*3a5d3a6fSGuenter Roeck QEMUTimer *fifo_timeout_timer; 153*3a5d3a6fSGuenter Roeck uint64_t wordtime; /* word time in ns */ 154*3a5d3a6fSGuenter Roeck 155becdfa00SMarc-André Lureau CharBackend chr; 1569944d320SPaolo Bonzini qemu_irq irq; 1579944d320SPaolo Bonzini 1589944d320SPaolo Bonzini uint32_t channel; 1599944d320SPaolo Bonzini 1609944d320SPaolo Bonzini } Exynos4210UartState; 1619944d320SPaolo Bonzini 1629944d320SPaolo Bonzini 1636804d230SGuenter Roeck /* Used only for tracing */ 1649944d320SPaolo Bonzini static const char *exynos4210_uart_regname(hwaddr offset) 1659944d320SPaolo Bonzini { 1669944d320SPaolo Bonzini 1679944d320SPaolo Bonzini int i; 1689944d320SPaolo Bonzini 169c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 1709944d320SPaolo Bonzini if (offset == exynos4210_uart_regs[i].offset) { 1719944d320SPaolo Bonzini return exynos4210_uart_regs[i].name; 1729944d320SPaolo Bonzini } 1739944d320SPaolo Bonzini } 1749944d320SPaolo Bonzini 1759944d320SPaolo Bonzini return NULL; 1769944d320SPaolo Bonzini } 1779944d320SPaolo Bonzini 1789944d320SPaolo Bonzini 1799944d320SPaolo Bonzini static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 1809944d320SPaolo Bonzini { 1819944d320SPaolo Bonzini q->data[q->sp] = ch; 1829944d320SPaolo Bonzini q->sp = (q->sp + 1) % q->size; 1839944d320SPaolo Bonzini } 1849944d320SPaolo Bonzini 1859944d320SPaolo Bonzini static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 1869944d320SPaolo Bonzini { 1879944d320SPaolo Bonzini uint8_t ret = q->data[q->rp]; 1889944d320SPaolo Bonzini q->rp = (q->rp + 1) % q->size; 1899944d320SPaolo Bonzini return ret; 1909944d320SPaolo Bonzini } 1919944d320SPaolo Bonzini 19275c6d92eSKrzysztof Kozlowski static int fifo_elements_number(const Exynos4210UartFIFO *q) 1939944d320SPaolo Bonzini { 1949944d320SPaolo Bonzini if (q->sp < q->rp) { 1959944d320SPaolo Bonzini return q->size - q->rp + q->sp; 1969944d320SPaolo Bonzini } 1979944d320SPaolo Bonzini 1989944d320SPaolo Bonzini return q->sp - q->rp; 1999944d320SPaolo Bonzini } 2009944d320SPaolo Bonzini 20175c6d92eSKrzysztof Kozlowski static int fifo_empty_elements_number(const Exynos4210UartFIFO *q) 2029944d320SPaolo Bonzini { 2039944d320SPaolo Bonzini return q->size - fifo_elements_number(q); 2049944d320SPaolo Bonzini } 2059944d320SPaolo Bonzini 2069944d320SPaolo Bonzini static void fifo_reset(Exynos4210UartFIFO *q) 2079944d320SPaolo Bonzini { 2089944d320SPaolo Bonzini g_free(q->data); 2099944d320SPaolo Bonzini q->data = NULL; 2109944d320SPaolo Bonzini 2119944d320SPaolo Bonzini q->data = (uint8_t *)g_malloc0(q->size); 2129944d320SPaolo Bonzini 2139944d320SPaolo Bonzini q->sp = 0; 2149944d320SPaolo Bonzini q->rp = 0; 2159944d320SPaolo Bonzini } 2169944d320SPaolo Bonzini 217*3a5d3a6fSGuenter Roeck static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel, 218*3a5d3a6fSGuenter Roeck uint32_t reg) 2199944d320SPaolo Bonzini { 220*3a5d3a6fSGuenter Roeck uint32_t level; 2219944d320SPaolo Bonzini 222*3a5d3a6fSGuenter Roeck switch (channel) { 2239944d320SPaolo Bonzini case 0: 2249944d320SPaolo Bonzini level = reg * 32; 2259944d320SPaolo Bonzini break; 2269944d320SPaolo Bonzini case 1: 2279944d320SPaolo Bonzini case 4: 2289944d320SPaolo Bonzini level = reg * 8; 2299944d320SPaolo Bonzini break; 2309944d320SPaolo Bonzini case 2: 2319944d320SPaolo Bonzini case 3: 2329944d320SPaolo Bonzini level = reg * 2; 2339944d320SPaolo Bonzini break; 2349944d320SPaolo Bonzini default: 2359944d320SPaolo Bonzini level = 0; 236*3a5d3a6fSGuenter Roeck trace_exynos_uart_channel_error(channel); 237*3a5d3a6fSGuenter Roeck break; 238*3a5d3a6fSGuenter Roeck } 239*3a5d3a6fSGuenter Roeck return level; 2409944d320SPaolo Bonzini } 2419944d320SPaolo Bonzini 242*3a5d3a6fSGuenter Roeck static uint32_t 243*3a5d3a6fSGuenter Roeck exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s) 244*3a5d3a6fSGuenter Roeck { 245*3a5d3a6fSGuenter Roeck uint32_t reg; 246*3a5d3a6fSGuenter Roeck 247*3a5d3a6fSGuenter Roeck reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 248*3a5d3a6fSGuenter Roeck UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 249*3a5d3a6fSGuenter Roeck 250*3a5d3a6fSGuenter Roeck return exynos4210_uart_FIFO_trigger_level(s->channel, reg); 251*3a5d3a6fSGuenter Roeck } 252*3a5d3a6fSGuenter Roeck 253*3a5d3a6fSGuenter Roeck static uint32_t 254*3a5d3a6fSGuenter Roeck exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s) 255*3a5d3a6fSGuenter Roeck { 256*3a5d3a6fSGuenter Roeck uint32_t reg; 257*3a5d3a6fSGuenter Roeck 258*3a5d3a6fSGuenter Roeck reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >> 259*3a5d3a6fSGuenter Roeck UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1; 260*3a5d3a6fSGuenter Roeck 261*3a5d3a6fSGuenter Roeck return exynos4210_uart_FIFO_trigger_level(s->channel, reg); 2629944d320SPaolo Bonzini } 2639944d320SPaolo Bonzini 2649944d320SPaolo Bonzini static void exynos4210_uart_update_irq(Exynos4210UartState *s) 2659944d320SPaolo Bonzini { 2669944d320SPaolo Bonzini /* 2679944d320SPaolo Bonzini * The Tx interrupt is always requested if the number of data in the 2689944d320SPaolo Bonzini * transmit FIFO is smaller than the trigger level. 2699944d320SPaolo Bonzini */ 2709944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 2719944d320SPaolo Bonzini uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 2729944d320SPaolo Bonzini UFSTAT_Tx_FIFO_COUNT_SHIFT; 2739944d320SPaolo Bonzini 2749944d320SPaolo Bonzini if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 2759944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD; 2769944d320SPaolo Bonzini } 277*3a5d3a6fSGuenter Roeck 278*3a5d3a6fSGuenter Roeck /* 279*3a5d3a6fSGuenter Roeck * Rx interrupt if trigger level is reached or if rx timeout 280*3a5d3a6fSGuenter Roeck * interrupt is disabled and there is data in the receive buffer 281*3a5d3a6fSGuenter Roeck */ 282*3a5d3a6fSGuenter Roeck count = fifo_elements_number(&s->rx); 283*3a5d3a6fSGuenter Roeck if ((count && !(s->reg[I_(UCON)] & 0x80)) || 284*3a5d3a6fSGuenter Roeck count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) { 285*3a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD; 286*3a5d3a6fSGuenter Roeck timer_del(s->fifo_timeout_timer); 287*3a5d3a6fSGuenter Roeck } 288*3a5d3a6fSGuenter Roeck } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) { 289*3a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD; 2909944d320SPaolo Bonzini } 2919944d320SPaolo Bonzini 2929944d320SPaolo Bonzini s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 2939944d320SPaolo Bonzini 2949944d320SPaolo Bonzini if (s->reg[I_(UINTP)]) { 2959944d320SPaolo Bonzini qemu_irq_raise(s->irq); 2966804d230SGuenter Roeck trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]); 2979944d320SPaolo Bonzini } else { 2989944d320SPaolo Bonzini qemu_irq_lower(s->irq); 2996804d230SGuenter Roeck trace_exynos_uart_irq_lowered(s->channel); 3009944d320SPaolo Bonzini } 3019944d320SPaolo Bonzini } 3029944d320SPaolo Bonzini 303*3a5d3a6fSGuenter Roeck static void exynos4210_uart_timeout_int(void *opaque) 304*3a5d3a6fSGuenter Roeck { 305*3a5d3a6fSGuenter Roeck Exynos4210UartState *s = opaque; 306*3a5d3a6fSGuenter Roeck 307*3a5d3a6fSGuenter Roeck trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)], 308*3a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)]); 309*3a5d3a6fSGuenter Roeck 310*3a5d3a6fSGuenter Roeck if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) || 311*3a5d3a6fSGuenter Roeck (s->reg[I_(UCON)] & (1 << 11))) { 312*3a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD; 313*3a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT; 314*3a5d3a6fSGuenter Roeck exynos4210_uart_update_irq(s); 315*3a5d3a6fSGuenter Roeck } 316*3a5d3a6fSGuenter Roeck } 317*3a5d3a6fSGuenter Roeck 3189944d320SPaolo Bonzini static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 3199944d320SPaolo Bonzini { 320e62694a0SPeter Maydell int speed, parity, data_bits, stop_bits; 3219944d320SPaolo Bonzini QEMUSerialSetParams ssp; 3229944d320SPaolo Bonzini uint64_t uclk_rate; 3239944d320SPaolo Bonzini 3249944d320SPaolo Bonzini if (s->reg[I_(UBRDIV)] == 0) { 3259944d320SPaolo Bonzini return; 3269944d320SPaolo Bonzini } 3279944d320SPaolo Bonzini 3289944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x20) { 3299944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x28) { 3309944d320SPaolo Bonzini parity = 'E'; 3319944d320SPaolo Bonzini } else { 3329944d320SPaolo Bonzini parity = 'O'; 3339944d320SPaolo Bonzini } 3349944d320SPaolo Bonzini } else { 3359944d320SPaolo Bonzini parity = 'N'; 3369944d320SPaolo Bonzini } 3379944d320SPaolo Bonzini 3389944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x4) { 3399944d320SPaolo Bonzini stop_bits = 2; 3409944d320SPaolo Bonzini } else { 3419944d320SPaolo Bonzini stop_bits = 1; 3429944d320SPaolo Bonzini } 3439944d320SPaolo Bonzini 3449944d320SPaolo Bonzini data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 3459944d320SPaolo Bonzini 3469944d320SPaolo Bonzini uclk_rate = 24000000; 3479944d320SPaolo Bonzini 3489944d320SPaolo Bonzini speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 3499944d320SPaolo Bonzini (s->reg[I_(UFRACVAL)] & 0x7) + 16); 3509944d320SPaolo Bonzini 3519944d320SPaolo Bonzini ssp.speed = speed; 3529944d320SPaolo Bonzini ssp.parity = parity; 3539944d320SPaolo Bonzini ssp.data_bits = data_bits; 3549944d320SPaolo Bonzini ssp.stop_bits = stop_bits; 3559944d320SPaolo Bonzini 356*3a5d3a6fSGuenter Roeck s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed; 357*3a5d3a6fSGuenter Roeck 3585345fdb4SMarc-André Lureau qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 3599944d320SPaolo Bonzini 3606804d230SGuenter Roeck trace_exynos_uart_update_params( 361*3a5d3a6fSGuenter Roeck s->channel, speed, parity, data_bits, stop_bits, s->wordtime); 362*3a5d3a6fSGuenter Roeck } 363*3a5d3a6fSGuenter Roeck 364*3a5d3a6fSGuenter Roeck static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s) 365*3a5d3a6fSGuenter Roeck { 366*3a5d3a6fSGuenter Roeck if (s->reg[I_(UCON)] & 0x80) { 367*3a5d3a6fSGuenter Roeck uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime; 368*3a5d3a6fSGuenter Roeck 369*3a5d3a6fSGuenter Roeck timer_mod(s->fifo_timeout_timer, 370*3a5d3a6fSGuenter Roeck qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); 371*3a5d3a6fSGuenter Roeck } else { 372*3a5d3a6fSGuenter Roeck timer_del(s->fifo_timeout_timer); 373*3a5d3a6fSGuenter Roeck } 3749944d320SPaolo Bonzini } 3759944d320SPaolo Bonzini 3769944d320SPaolo Bonzini static void exynos4210_uart_write(void *opaque, hwaddr offset, 3779944d320SPaolo Bonzini uint64_t val, unsigned size) 3789944d320SPaolo Bonzini { 3799944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 3809944d320SPaolo Bonzini uint8_t ch; 3819944d320SPaolo Bonzini 3826804d230SGuenter Roeck trace_exynos_uart_write(s->channel, offset, 3836804d230SGuenter Roeck exynos4210_uart_regname(offset), val); 3849944d320SPaolo Bonzini 3859944d320SPaolo Bonzini switch (offset) { 3869944d320SPaolo Bonzini case ULCON: 3879944d320SPaolo Bonzini case UBRDIV: 3889944d320SPaolo Bonzini case UFRACVAL: 3899944d320SPaolo Bonzini s->reg[I_(offset)] = val; 3909944d320SPaolo Bonzini exynos4210_uart_update_parameters(s); 3919944d320SPaolo Bonzini break; 3929944d320SPaolo Bonzini case UFCON: 3939944d320SPaolo Bonzini s->reg[I_(UFCON)] = val; 3949944d320SPaolo Bonzini if (val & UFCON_Rx_FIFO_RESET) { 3959944d320SPaolo Bonzini fifo_reset(&s->rx); 3969944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 3976804d230SGuenter Roeck trace_exynos_uart_rx_fifo_reset(s->channel); 3989944d320SPaolo Bonzini } 3999944d320SPaolo Bonzini if (val & UFCON_Tx_FIFO_RESET) { 4009944d320SPaolo Bonzini fifo_reset(&s->tx); 4019944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 4026804d230SGuenter Roeck trace_exynos_uart_tx_fifo_reset(s->channel); 4039944d320SPaolo Bonzini } 4049944d320SPaolo Bonzini break; 4059944d320SPaolo Bonzini 4069944d320SPaolo Bonzini case UTXH: 40730650701SAnton Nefedov if (qemu_chr_fe_backend_connected(&s->chr)) { 4089944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 4099944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY); 4109944d320SPaolo Bonzini ch = (uint8_t)val; 4116ab3fc32SDaniel P. Berrange /* XXX this blocks entire thread. Rewrite to use 4126ab3fc32SDaniel P. Berrange * qemu_chr_fe_write and background I/O callbacks */ 4135345fdb4SMarc-André Lureau qemu_chr_fe_write_all(&s->chr, &ch, 1); 4146804d230SGuenter Roeck trace_exynos_uart_tx(s->channel, ch); 4159944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 4169944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY; 4179944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD; 4189944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4199944d320SPaolo Bonzini } 4209944d320SPaolo Bonzini break; 4219944d320SPaolo Bonzini 4229944d320SPaolo Bonzini case UINTP: 4239944d320SPaolo Bonzini s->reg[I_(UINTP)] &= ~val; 4249944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val; 4256804d230SGuenter Roeck trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]); 4269944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4279944d320SPaolo Bonzini break; 4289944d320SPaolo Bonzini case UTRSTAT: 429*3a5d3a6fSGuenter Roeck if (val & UTRSTAT_Rx_TIMEOUT) { 430*3a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT; 431*3a5d3a6fSGuenter Roeck } 432*3a5d3a6fSGuenter Roeck break; 4339944d320SPaolo Bonzini case UERSTAT: 4349944d320SPaolo Bonzini case UFSTAT: 4359944d320SPaolo Bonzini case UMSTAT: 4369944d320SPaolo Bonzini case URXH: 4376804d230SGuenter Roeck trace_exynos_uart_ro_write( 4389944d320SPaolo Bonzini s->channel, exynos4210_uart_regname(offset), offset); 4399944d320SPaolo Bonzini break; 4409944d320SPaolo Bonzini case UINTSP: 4419944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val; 4429944d320SPaolo Bonzini break; 4439944d320SPaolo Bonzini case UINTM: 4449944d320SPaolo Bonzini s->reg[I_(UINTM)] = val; 4459944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4469944d320SPaolo Bonzini break; 4479944d320SPaolo Bonzini case UCON: 4489944d320SPaolo Bonzini case UMCON: 4499944d320SPaolo Bonzini default: 4509944d320SPaolo Bonzini s->reg[I_(offset)] = val; 4519944d320SPaolo Bonzini break; 4529944d320SPaolo Bonzini } 4539944d320SPaolo Bonzini } 454*3a5d3a6fSGuenter Roeck 4559944d320SPaolo Bonzini static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 4569944d320SPaolo Bonzini unsigned size) 4579944d320SPaolo Bonzini { 4589944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 4599944d320SPaolo Bonzini uint32_t res; 4609944d320SPaolo Bonzini 4619944d320SPaolo Bonzini switch (offset) { 4629944d320SPaolo Bonzini case UERSTAT: /* Read Only */ 4639944d320SPaolo Bonzini res = s->reg[I_(UERSTAT)]; 4649944d320SPaolo Bonzini s->reg[I_(UERSTAT)] = 0; 4656804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 4666804d230SGuenter Roeck exynos4210_uart_regname(offset), res); 4679944d320SPaolo Bonzini return res; 4689944d320SPaolo Bonzini case UFSTAT: /* Read Only */ 4699944d320SPaolo Bonzini s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 4709944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) == 0) { 4719944d320SPaolo Bonzini s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 4729944d320SPaolo Bonzini s->reg[I_(UFSTAT)] &= ~0xff; 4739944d320SPaolo Bonzini } 4746804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 4756804d230SGuenter Roeck exynos4210_uart_regname(offset), 4766804d230SGuenter Roeck s->reg[I_(UFSTAT)]); 4779944d320SPaolo Bonzini return s->reg[I_(UFSTAT)]; 4789944d320SPaolo Bonzini case URXH: 4799944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 4809944d320SPaolo Bonzini if (fifo_elements_number(&s->rx)) { 4819944d320SPaolo Bonzini res = fifo_retrieve(&s->rx); 4826804d230SGuenter Roeck trace_exynos_uart_rx(s->channel, res); 4839944d320SPaolo Bonzini if (!fifo_elements_number(&s->rx)) { 4849944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 4859944d320SPaolo Bonzini } else { 4869944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 4879944d320SPaolo Bonzini } 4889944d320SPaolo Bonzini } else { 4896804d230SGuenter Roeck trace_exynos_uart_rx_error(s->channel); 4909944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR; 4919944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4929944d320SPaolo Bonzini res = 0; 4939944d320SPaolo Bonzini } 4949944d320SPaolo Bonzini } else { 4959944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 4969944d320SPaolo Bonzini res = s->reg[I_(URXH)]; 4979944d320SPaolo Bonzini } 4986804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 4996804d230SGuenter Roeck exynos4210_uart_regname(offset), res); 5009944d320SPaolo Bonzini return res; 5019944d320SPaolo Bonzini case UTXH: 5026804d230SGuenter Roeck trace_exynos_uart_wo_read(s->channel, exynos4210_uart_regname(offset), 5036804d230SGuenter Roeck offset); 5049944d320SPaolo Bonzini break; 5059944d320SPaolo Bonzini default: 5066804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 5076804d230SGuenter Roeck exynos4210_uart_regname(offset), 5086804d230SGuenter Roeck s->reg[I_(offset)]); 5099944d320SPaolo Bonzini return s->reg[I_(offset)]; 5109944d320SPaolo Bonzini } 5119944d320SPaolo Bonzini 5126804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset), 5136804d230SGuenter Roeck 0); 5149944d320SPaolo Bonzini return 0; 5159944d320SPaolo Bonzini } 5169944d320SPaolo Bonzini 5179944d320SPaolo Bonzini static const MemoryRegionOps exynos4210_uart_ops = { 5189944d320SPaolo Bonzini .read = exynos4210_uart_read, 5199944d320SPaolo Bonzini .write = exynos4210_uart_write, 5209944d320SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 5219944d320SPaolo Bonzini .valid = { 5229944d320SPaolo Bonzini .max_access_size = 4, 5239944d320SPaolo Bonzini .unaligned = false 5249944d320SPaolo Bonzini }, 5259944d320SPaolo Bonzini }; 5269944d320SPaolo Bonzini 5279944d320SPaolo Bonzini static int exynos4210_uart_can_receive(void *opaque) 5289944d320SPaolo Bonzini { 5299944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5309944d320SPaolo Bonzini 5319944d320SPaolo Bonzini return fifo_empty_elements_number(&s->rx); 5329944d320SPaolo Bonzini } 5339944d320SPaolo Bonzini 5349944d320SPaolo Bonzini static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 5359944d320SPaolo Bonzini { 5369944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5379944d320SPaolo Bonzini int i; 5389944d320SPaolo Bonzini 5399944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 5409944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) < size) { 541*3a5d3a6fSGuenter Roeck size = fifo_empty_elements_number(&s->rx); 5429944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR; 543*3a5d3a6fSGuenter Roeck } 5449944d320SPaolo Bonzini for (i = 0; i < size; i++) { 5459944d320SPaolo Bonzini fifo_store(&s->rx, buf[i]); 5469944d320SPaolo Bonzini } 547*3a5d3a6fSGuenter Roeck exynos4210_uart_rx_timeout_set(s); 5489944d320SPaolo Bonzini } else { 5499944d320SPaolo Bonzini s->reg[I_(URXH)] = buf[0]; 5509944d320SPaolo Bonzini } 551*3a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 5529944d320SPaolo Bonzini 5539944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5549944d320SPaolo Bonzini } 5559944d320SPaolo Bonzini 5569944d320SPaolo Bonzini 557083b266fSPhilippe Mathieu-Daudé static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) 5589944d320SPaolo Bonzini { 5599944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5609944d320SPaolo Bonzini 5619944d320SPaolo Bonzini if (event == CHR_EVENT_BREAK) { 5629944d320SPaolo Bonzini /* When the RxDn is held in logic 0, then a null byte is pushed into the 5639944d320SPaolo Bonzini * fifo */ 5649944d320SPaolo Bonzini fifo_store(&s->rx, '\0'); 5659944d320SPaolo Bonzini s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 5669944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5679944d320SPaolo Bonzini } 5689944d320SPaolo Bonzini } 5699944d320SPaolo Bonzini 5709944d320SPaolo Bonzini 5719944d320SPaolo Bonzini static void exynos4210_uart_reset(DeviceState *dev) 5729944d320SPaolo Bonzini { 57361149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev); 5749944d320SPaolo Bonzini int i; 5759944d320SPaolo Bonzini 576c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 5779944d320SPaolo Bonzini s->reg[I_(exynos4210_uart_regs[i].offset)] = 5789944d320SPaolo Bonzini exynos4210_uart_regs[i].reset_value; 5799944d320SPaolo Bonzini } 5809944d320SPaolo Bonzini 5819944d320SPaolo Bonzini fifo_reset(&s->rx); 5829944d320SPaolo Bonzini fifo_reset(&s->tx); 5839944d320SPaolo Bonzini 5846804d230SGuenter Roeck trace_exynos_uart_rxsize(s->channel, s->rx.size); 5859944d320SPaolo Bonzini } 5869944d320SPaolo Bonzini 587c9d3396dSGuenter Roeck static int exynos4210_uart_post_load(void *opaque, int version_id) 588c9d3396dSGuenter Roeck { 589c9d3396dSGuenter Roeck Exynos4210UartState *s = (Exynos4210UartState *)opaque; 590c9d3396dSGuenter Roeck 591c9d3396dSGuenter Roeck exynos4210_uart_update_parameters(s); 592*3a5d3a6fSGuenter Roeck exynos4210_uart_rx_timeout_set(s); 593c9d3396dSGuenter Roeck 594c9d3396dSGuenter Roeck return 0; 595c9d3396dSGuenter Roeck } 596c9d3396dSGuenter Roeck 5979944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart_fifo = { 5989944d320SPaolo Bonzini .name = "exynos4210.uart.fifo", 5999944d320SPaolo Bonzini .version_id = 1, 6009944d320SPaolo Bonzini .minimum_version_id = 1, 601c9d3396dSGuenter Roeck .post_load = exynos4210_uart_post_load, 6029944d320SPaolo Bonzini .fields = (VMStateField[]) { 6039944d320SPaolo Bonzini VMSTATE_UINT32(sp, Exynos4210UartFIFO), 6049944d320SPaolo Bonzini VMSTATE_UINT32(rp, Exynos4210UartFIFO), 60559046ec2SHalil Pasic VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size), 6069944d320SPaolo Bonzini VMSTATE_END_OF_LIST() 6079944d320SPaolo Bonzini } 6089944d320SPaolo Bonzini }; 6099944d320SPaolo Bonzini 6109944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart = { 6119944d320SPaolo Bonzini .name = "exynos4210.uart", 6129944d320SPaolo Bonzini .version_id = 1, 6139944d320SPaolo Bonzini .minimum_version_id = 1, 6149944d320SPaolo Bonzini .fields = (VMStateField[]) { 6159944d320SPaolo Bonzini VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 6169944d320SPaolo Bonzini vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 6179944d320SPaolo Bonzini VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 6189944d320SPaolo Bonzini EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 6199944d320SPaolo Bonzini VMSTATE_END_OF_LIST() 6209944d320SPaolo Bonzini } 6219944d320SPaolo Bonzini }; 6229944d320SPaolo Bonzini 6239944d320SPaolo Bonzini DeviceState *exynos4210_uart_create(hwaddr addr, 6249944d320SPaolo Bonzini int fifo_size, 6259944d320SPaolo Bonzini int channel, 6260ec7b3e7SMarc-André Lureau Chardev *chr, 6279944d320SPaolo Bonzini qemu_irq irq) 6289944d320SPaolo Bonzini { 6299944d320SPaolo Bonzini DeviceState *dev; 6309944d320SPaolo Bonzini SysBusDevice *bus; 6319944d320SPaolo Bonzini 63261149ff6SAndreas Färber dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 6339944d320SPaolo Bonzini 6349944d320SPaolo Bonzini qdev_prop_set_chr(dev, "chardev", chr); 6359944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "channel", channel); 6369944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "rx-size", fifo_size); 6379944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "tx-size", fifo_size); 6389944d320SPaolo Bonzini 6399944d320SPaolo Bonzini bus = SYS_BUS_DEVICE(dev); 6409944d320SPaolo Bonzini qdev_init_nofail(dev); 6419944d320SPaolo Bonzini if (addr != (hwaddr)-1) { 6429944d320SPaolo Bonzini sysbus_mmio_map(bus, 0, addr); 6439944d320SPaolo Bonzini } 6449944d320SPaolo Bonzini sysbus_connect_irq(bus, 0, irq); 6459944d320SPaolo Bonzini 6469944d320SPaolo Bonzini return dev; 6479944d320SPaolo Bonzini } 6489944d320SPaolo Bonzini 6495b982482Sxiaoqiang zhao static void exynos4210_uart_init(Object *obj) 6509944d320SPaolo Bonzini { 6515b982482Sxiaoqiang zhao SysBusDevice *dev = SYS_BUS_DEVICE(obj); 65261149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev); 6539944d320SPaolo Bonzini 654*3a5d3a6fSGuenter Roeck s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 655*3a5d3a6fSGuenter Roeck exynos4210_uart_timeout_int, s); 656*3a5d3a6fSGuenter Roeck s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600; 657*3a5d3a6fSGuenter Roeck 6589944d320SPaolo Bonzini /* memory mapping */ 6595b982482Sxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s, 660300b1fc6SPaolo Bonzini "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 6619944d320SPaolo Bonzini sysbus_init_mmio(dev, &s->iomem); 6629944d320SPaolo Bonzini 6639944d320SPaolo Bonzini sysbus_init_irq(dev, &s->irq); 6645b982482Sxiaoqiang zhao } 6655b982482Sxiaoqiang zhao 6665b982482Sxiaoqiang zhao static void exynos4210_uart_realize(DeviceState *dev, Error **errp) 6675b982482Sxiaoqiang zhao { 6685b982482Sxiaoqiang zhao Exynos4210UartState *s = EXYNOS4210_UART(dev); 6699944d320SPaolo Bonzini 6705345fdb4SMarc-André Lureau qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, 6715345fdb4SMarc-André Lureau exynos4210_uart_receive, exynos4210_uart_event, 67281517ba3SAnton Nefedov NULL, s, NULL, true); 6739944d320SPaolo Bonzini } 6749944d320SPaolo Bonzini 6759944d320SPaolo Bonzini static Property exynos4210_uart_properties[] = { 6769944d320SPaolo Bonzini DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 6779944d320SPaolo Bonzini DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 6789944d320SPaolo Bonzini DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 6799944d320SPaolo Bonzini DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 6809944d320SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 6819944d320SPaolo Bonzini }; 6829944d320SPaolo Bonzini 6839944d320SPaolo Bonzini static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 6849944d320SPaolo Bonzini { 6859944d320SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 6869944d320SPaolo Bonzini 6875b982482Sxiaoqiang zhao dc->realize = exynos4210_uart_realize; 6889944d320SPaolo Bonzini dc->reset = exynos4210_uart_reset; 6899944d320SPaolo Bonzini dc->props = exynos4210_uart_properties; 6909944d320SPaolo Bonzini dc->vmsd = &vmstate_exynos4210_uart; 6919944d320SPaolo Bonzini } 6929944d320SPaolo Bonzini 6939944d320SPaolo Bonzini static const TypeInfo exynos4210_uart_info = { 69461149ff6SAndreas Färber .name = TYPE_EXYNOS4210_UART, 6959944d320SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 6969944d320SPaolo Bonzini .instance_size = sizeof(Exynos4210UartState), 6975b982482Sxiaoqiang zhao .instance_init = exynos4210_uart_init, 6989944d320SPaolo Bonzini .class_init = exynos4210_uart_class_init, 6999944d320SPaolo Bonzini }; 7009944d320SPaolo Bonzini 7019944d320SPaolo Bonzini static void exynos4210_uart_register(void) 7029944d320SPaolo Bonzini { 7039944d320SPaolo Bonzini type_register_static(&exynos4210_uart_info); 7049944d320SPaolo Bonzini } 7059944d320SPaolo Bonzini 7069944d320SPaolo Bonzini type_init(exynos4210_uart_register) 707