19944d320SPaolo Bonzini /* 29944d320SPaolo Bonzini * Exynos4210 UART Emulation 39944d320SPaolo Bonzini * 49944d320SPaolo Bonzini * Copyright (C) 2011 Samsung Electronics Co Ltd. 59944d320SPaolo Bonzini * Maksim Kozlov, <m.kozlov@samsung.com> 69944d320SPaolo Bonzini * 79944d320SPaolo Bonzini * This program is free software; you can redistribute it and/or modify it 89944d320SPaolo Bonzini * under the terms of the GNU General Public License as published by the 99944d320SPaolo Bonzini * Free Software Foundation; either version 2 of the License, or 109944d320SPaolo Bonzini * (at your option) any later version. 119944d320SPaolo Bonzini * 129944d320SPaolo Bonzini * This program is distributed in the hope that it will be useful, but WITHOUT 139944d320SPaolo Bonzini * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 149944d320SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 159944d320SPaolo Bonzini * for more details. 169944d320SPaolo Bonzini * 179944d320SPaolo Bonzini * You should have received a copy of the GNU General Public License along 189944d320SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 199944d320SPaolo Bonzini * 209944d320SPaolo Bonzini */ 219944d320SPaolo Bonzini 228ef94f0bSPeter Maydell #include "qemu/osdep.h" 239944d320SPaolo Bonzini #include "hw/sysbus.h" 24d6454270SMarkus Armbruster #include "migration/vmstate.h" 253e80f690SMarkus Armbruster #include "qapi/error.h" 26c525436eSMarkus Armbruster #include "qemu/error-report.h" 270b8fa32fSMarkus Armbruster #include "qemu/module.h" 283a5d3a6fSGuenter Roeck #include "qemu/timer.h" 294d43a603SMarc-André Lureau #include "chardev/char-fe.h" 307566c6efSMarc-André Lureau #include "chardev/char-serial.h" 319944d320SPaolo Bonzini 329944d320SPaolo Bonzini #include "hw/arm/exynos4210.h" 3364552b6bSMarkus Armbruster #include "hw/irq.h" 34a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 359944d320SPaolo Bonzini 366804d230SGuenter Roeck #include "trace.h" 37db1015e9SEduardo Habkost #include "qom/object.h" 389944d320SPaolo Bonzini 399944d320SPaolo Bonzini /* 409944d320SPaolo Bonzini * Offsets for UART registers relative to SFR base address 419944d320SPaolo Bonzini * for UARTn 429944d320SPaolo Bonzini * 439944d320SPaolo Bonzini */ 449944d320SPaolo Bonzini #define ULCON 0x0000 /* Line Control */ 459944d320SPaolo Bonzini #define UCON 0x0004 /* Control */ 469944d320SPaolo Bonzini #define UFCON 0x0008 /* FIFO Control */ 479944d320SPaolo Bonzini #define UMCON 0x000C /* Modem Control */ 489944d320SPaolo Bonzini #define UTRSTAT 0x0010 /* Tx/Rx Status */ 499944d320SPaolo Bonzini #define UERSTAT 0x0014 /* UART Error Status */ 509944d320SPaolo Bonzini #define UFSTAT 0x0018 /* FIFO Status */ 519944d320SPaolo Bonzini #define UMSTAT 0x001C /* Modem Status */ 529944d320SPaolo Bonzini #define UTXH 0x0020 /* Transmit Buffer */ 539944d320SPaolo Bonzini #define URXH 0x0024 /* Receive Buffer */ 549944d320SPaolo Bonzini #define UBRDIV 0x0028 /* Baud Rate Divisor */ 559944d320SPaolo Bonzini #define UFRACVAL 0x002C /* Divisor Fractional Value */ 569944d320SPaolo Bonzini #define UINTP 0x0030 /* Interrupt Pending */ 579944d320SPaolo Bonzini #define UINTSP 0x0034 /* Interrupt Source Pending */ 589944d320SPaolo Bonzini #define UINTM 0x0038 /* Interrupt Mask */ 599944d320SPaolo Bonzini 609944d320SPaolo Bonzini /* 619944d320SPaolo Bonzini * for indexing register in the uint32_t array 629944d320SPaolo Bonzini * 639944d320SPaolo Bonzini * 'reg' - register offset (see offsets definitions above) 649944d320SPaolo Bonzini * 659944d320SPaolo Bonzini */ 669944d320SPaolo Bonzini #define I_(reg) (reg / sizeof(uint32_t)) 679944d320SPaolo Bonzini 689944d320SPaolo Bonzini typedef struct Exynos4210UartReg { 699944d320SPaolo Bonzini const char *name; /* the only reason is the debug output */ 709944d320SPaolo Bonzini hwaddr offset; 719944d320SPaolo Bonzini uint32_t reset_value; 729944d320SPaolo Bonzini } Exynos4210UartReg; 739944d320SPaolo Bonzini 7475c6d92eSKrzysztof Kozlowski static const Exynos4210UartReg exynos4210_uart_regs[] = { 759944d320SPaolo Bonzini {"ULCON", ULCON, 0x00000000}, 769944d320SPaolo Bonzini {"UCON", UCON, 0x00003000}, 779944d320SPaolo Bonzini {"UFCON", UFCON, 0x00000000}, 789944d320SPaolo Bonzini {"UMCON", UMCON, 0x00000000}, 799944d320SPaolo Bonzini {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 809944d320SPaolo Bonzini {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 819944d320SPaolo Bonzini {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 829944d320SPaolo Bonzini {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 839944d320SPaolo Bonzini {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 849944d320SPaolo Bonzini {"URXH", URXH, 0x00000000}, /* RO */ 859944d320SPaolo Bonzini {"UBRDIV", UBRDIV, 0x00000000}, 869944d320SPaolo Bonzini {"UFRACVAL", UFRACVAL, 0x00000000}, 879944d320SPaolo Bonzini {"UINTP", UINTP, 0x00000000}, 889944d320SPaolo Bonzini {"UINTSP", UINTSP, 0x00000000}, 899944d320SPaolo Bonzini {"UINTM", UINTM, 0x00000000}, 909944d320SPaolo Bonzini }; 919944d320SPaolo Bonzini 929944d320SPaolo Bonzini #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 939944d320SPaolo Bonzini 949944d320SPaolo Bonzini /* UART FIFO Control */ 959944d320SPaolo Bonzini #define UFCON_FIFO_ENABLE 0x1 969944d320SPaolo Bonzini #define UFCON_Rx_FIFO_RESET 0x2 979944d320SPaolo Bonzini #define UFCON_Tx_FIFO_RESET 0x4 989944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 999944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 1009944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 1019944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 1029944d320SPaolo Bonzini 1039944d320SPaolo Bonzini /* Uart FIFO Status */ 1049944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_COUNT 0xff 1059944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_FULL 0x100 1069944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_ERROR 0x200 1079944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 1089944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 1099944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 1109944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 1119944d320SPaolo Bonzini 1129944d320SPaolo Bonzini /* UART Interrupt Source Pending */ 1139944d320SPaolo Bonzini #define UINTSP_RXD 0x1 /* Receive interrupt */ 1149944d320SPaolo Bonzini #define UINTSP_ERROR 0x2 /* Error interrupt */ 1159944d320SPaolo Bonzini #define UINTSP_TXD 0x4 /* Transmit interrupt */ 1169944d320SPaolo Bonzini #define UINTSP_MODEM 0x8 /* Modem interrupt */ 1179944d320SPaolo Bonzini 1189944d320SPaolo Bonzini /* UART Line Control */ 1199944d320SPaolo Bonzini #define ULCON_IR_MODE_SHIFT 6 1209944d320SPaolo Bonzini #define ULCON_PARITY_SHIFT 3 1219944d320SPaolo Bonzini #define ULCON_STOP_BIT_SHIFT 1 1229944d320SPaolo Bonzini 1239944d320SPaolo Bonzini /* UART Tx/Rx Status */ 1243a5d3a6fSGuenter Roeck #define UTRSTAT_Rx_TIMEOUT 0x8 1259944d320SPaolo Bonzini #define UTRSTAT_TRANSMITTER_EMPTY 0x4 1269944d320SPaolo Bonzini #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 1279944d320SPaolo Bonzini #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 1289944d320SPaolo Bonzini 1299944d320SPaolo Bonzini /* UART Error Status */ 1309944d320SPaolo Bonzini #define UERSTAT_OVERRUN 0x1 1319944d320SPaolo Bonzini #define UERSTAT_PARITY 0x2 1329944d320SPaolo Bonzini #define UERSTAT_FRAME 0x4 1339944d320SPaolo Bonzini #define UERSTAT_BREAK 0x8 1349944d320SPaolo Bonzini 1359944d320SPaolo Bonzini typedef struct { 1369944d320SPaolo Bonzini uint8_t *data; 1379944d320SPaolo Bonzini uint32_t sp, rp; /* store and retrieve pointers */ 1389944d320SPaolo Bonzini uint32_t size; 1399944d320SPaolo Bonzini } Exynos4210UartFIFO; 1409944d320SPaolo Bonzini 14161149ff6SAndreas Färber #define TYPE_EXYNOS4210_UART "exynos4210.uart" 142*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210UartState, EXYNOS4210_UART) 14361149ff6SAndreas Färber 144db1015e9SEduardo Habkost struct Exynos4210UartState { 14561149ff6SAndreas Färber SysBusDevice parent_obj; 14661149ff6SAndreas Färber 1479944d320SPaolo Bonzini MemoryRegion iomem; 1489944d320SPaolo Bonzini 1499944d320SPaolo Bonzini uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 1509944d320SPaolo Bonzini Exynos4210UartFIFO rx; 1519944d320SPaolo Bonzini Exynos4210UartFIFO tx; 1529944d320SPaolo Bonzini 1533a5d3a6fSGuenter Roeck QEMUTimer *fifo_timeout_timer; 1543a5d3a6fSGuenter Roeck uint64_t wordtime; /* word time in ns */ 1553a5d3a6fSGuenter Roeck 156becdfa00SMarc-André Lureau CharBackend chr; 1579944d320SPaolo Bonzini qemu_irq irq; 1583c77412bSGuenter Roeck qemu_irq dmairq; 1599944d320SPaolo Bonzini 1609944d320SPaolo Bonzini uint32_t channel; 1619944d320SPaolo Bonzini 162db1015e9SEduardo Habkost }; 1639944d320SPaolo Bonzini 1649944d320SPaolo Bonzini 1656804d230SGuenter Roeck /* Used only for tracing */ 1669944d320SPaolo Bonzini static const char *exynos4210_uart_regname(hwaddr offset) 1679944d320SPaolo Bonzini { 1689944d320SPaolo Bonzini 1699944d320SPaolo Bonzini int i; 1709944d320SPaolo Bonzini 171c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 1729944d320SPaolo Bonzini if (offset == exynos4210_uart_regs[i].offset) { 1739944d320SPaolo Bonzini return exynos4210_uart_regs[i].name; 1749944d320SPaolo Bonzini } 1759944d320SPaolo Bonzini } 1769944d320SPaolo Bonzini 1779944d320SPaolo Bonzini return NULL; 1789944d320SPaolo Bonzini } 1799944d320SPaolo Bonzini 1809944d320SPaolo Bonzini 1819944d320SPaolo Bonzini static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 1829944d320SPaolo Bonzini { 1839944d320SPaolo Bonzini q->data[q->sp] = ch; 1849944d320SPaolo Bonzini q->sp = (q->sp + 1) % q->size; 1859944d320SPaolo Bonzini } 1869944d320SPaolo Bonzini 1879944d320SPaolo Bonzini static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 1889944d320SPaolo Bonzini { 1899944d320SPaolo Bonzini uint8_t ret = q->data[q->rp]; 1909944d320SPaolo Bonzini q->rp = (q->rp + 1) % q->size; 1919944d320SPaolo Bonzini return ret; 1929944d320SPaolo Bonzini } 1939944d320SPaolo Bonzini 19475c6d92eSKrzysztof Kozlowski static int fifo_elements_number(const Exynos4210UartFIFO *q) 1959944d320SPaolo Bonzini { 1969944d320SPaolo Bonzini if (q->sp < q->rp) { 1979944d320SPaolo Bonzini return q->size - q->rp + q->sp; 1989944d320SPaolo Bonzini } 1999944d320SPaolo Bonzini 2009944d320SPaolo Bonzini return q->sp - q->rp; 2019944d320SPaolo Bonzini } 2029944d320SPaolo Bonzini 20375c6d92eSKrzysztof Kozlowski static int fifo_empty_elements_number(const Exynos4210UartFIFO *q) 2049944d320SPaolo Bonzini { 2059944d320SPaolo Bonzini return q->size - fifo_elements_number(q); 2069944d320SPaolo Bonzini } 2079944d320SPaolo Bonzini 2089944d320SPaolo Bonzini static void fifo_reset(Exynos4210UartFIFO *q) 2099944d320SPaolo Bonzini { 2109944d320SPaolo Bonzini g_free(q->data); 2119944d320SPaolo Bonzini q->data = NULL; 2129944d320SPaolo Bonzini 2139944d320SPaolo Bonzini q->data = (uint8_t *)g_malloc0(q->size); 2149944d320SPaolo Bonzini 2159944d320SPaolo Bonzini q->sp = 0; 2169944d320SPaolo Bonzini q->rp = 0; 2179944d320SPaolo Bonzini } 2189944d320SPaolo Bonzini 2193a5d3a6fSGuenter Roeck static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel, 2203a5d3a6fSGuenter Roeck uint32_t reg) 2219944d320SPaolo Bonzini { 2223a5d3a6fSGuenter Roeck uint32_t level; 2239944d320SPaolo Bonzini 2243a5d3a6fSGuenter Roeck switch (channel) { 2259944d320SPaolo Bonzini case 0: 2269944d320SPaolo Bonzini level = reg * 32; 2279944d320SPaolo Bonzini break; 2289944d320SPaolo Bonzini case 1: 2299944d320SPaolo Bonzini case 4: 2309944d320SPaolo Bonzini level = reg * 8; 2319944d320SPaolo Bonzini break; 2329944d320SPaolo Bonzini case 2: 2339944d320SPaolo Bonzini case 3: 2349944d320SPaolo Bonzini level = reg * 2; 2359944d320SPaolo Bonzini break; 2369944d320SPaolo Bonzini default: 2379944d320SPaolo Bonzini level = 0; 2383a5d3a6fSGuenter Roeck trace_exynos_uart_channel_error(channel); 2393a5d3a6fSGuenter Roeck break; 2403a5d3a6fSGuenter Roeck } 2413a5d3a6fSGuenter Roeck return level; 2429944d320SPaolo Bonzini } 2439944d320SPaolo Bonzini 2443a5d3a6fSGuenter Roeck static uint32_t 2453a5d3a6fSGuenter Roeck exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s) 2463a5d3a6fSGuenter Roeck { 2473a5d3a6fSGuenter Roeck uint32_t reg; 2483a5d3a6fSGuenter Roeck 2493a5d3a6fSGuenter Roeck reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 2503a5d3a6fSGuenter Roeck UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 2513a5d3a6fSGuenter Roeck 2523a5d3a6fSGuenter Roeck return exynos4210_uart_FIFO_trigger_level(s->channel, reg); 2533a5d3a6fSGuenter Roeck } 2543a5d3a6fSGuenter Roeck 2553a5d3a6fSGuenter Roeck static uint32_t 2563a5d3a6fSGuenter Roeck exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s) 2573a5d3a6fSGuenter Roeck { 2583a5d3a6fSGuenter Roeck uint32_t reg; 2593a5d3a6fSGuenter Roeck 2603a5d3a6fSGuenter Roeck reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >> 2613a5d3a6fSGuenter Roeck UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1; 2623a5d3a6fSGuenter Roeck 2633a5d3a6fSGuenter Roeck return exynos4210_uart_FIFO_trigger_level(s->channel, reg); 2649944d320SPaolo Bonzini } 2659944d320SPaolo Bonzini 2663c77412bSGuenter Roeck /* 2673c77412bSGuenter Roeck * Update Rx DMA busy signal if Rx DMA is enabled. For simplicity, 2683c77412bSGuenter Roeck * mark DMA as busy if DMA is enabled and the receive buffer is empty. 2693c77412bSGuenter Roeck */ 2703c77412bSGuenter Roeck static void exynos4210_uart_update_dmabusy(Exynos4210UartState *s) 2713c77412bSGuenter Roeck { 2723c77412bSGuenter Roeck bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02; 2733c77412bSGuenter Roeck uint32_t count = fifo_elements_number(&s->rx); 2743c77412bSGuenter Roeck 2753c77412bSGuenter Roeck if (rx_dma_enabled && !count) { 2763c77412bSGuenter Roeck qemu_irq_raise(s->dmairq); 2773c77412bSGuenter Roeck trace_exynos_uart_dmabusy(s->channel); 2783c77412bSGuenter Roeck } else { 2793c77412bSGuenter Roeck qemu_irq_lower(s->dmairq); 2803c77412bSGuenter Roeck trace_exynos_uart_dmaready(s->channel); 2813c77412bSGuenter Roeck } 2823c77412bSGuenter Roeck } 2833c77412bSGuenter Roeck 2849944d320SPaolo Bonzini static void exynos4210_uart_update_irq(Exynos4210UartState *s) 2859944d320SPaolo Bonzini { 2869944d320SPaolo Bonzini /* 2879944d320SPaolo Bonzini * The Tx interrupt is always requested if the number of data in the 2889944d320SPaolo Bonzini * transmit FIFO is smaller than the trigger level. 2899944d320SPaolo Bonzini */ 2909944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 2919944d320SPaolo Bonzini uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 2929944d320SPaolo Bonzini UFSTAT_Tx_FIFO_COUNT_SHIFT; 2939944d320SPaolo Bonzini 2949944d320SPaolo Bonzini if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 2959944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD; 2969944d320SPaolo Bonzini } 2973a5d3a6fSGuenter Roeck 2983a5d3a6fSGuenter Roeck /* 2993a5d3a6fSGuenter Roeck * Rx interrupt if trigger level is reached or if rx timeout 3003a5d3a6fSGuenter Roeck * interrupt is disabled and there is data in the receive buffer 3013a5d3a6fSGuenter Roeck */ 3023a5d3a6fSGuenter Roeck count = fifo_elements_number(&s->rx); 3033a5d3a6fSGuenter Roeck if ((count && !(s->reg[I_(UCON)] & 0x80)) || 3043a5d3a6fSGuenter Roeck count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) { 3053c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s); 3063a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD; 3073a5d3a6fSGuenter Roeck timer_del(s->fifo_timeout_timer); 3083a5d3a6fSGuenter Roeck } 3093a5d3a6fSGuenter Roeck } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) { 3103c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s); 3113a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD; 3129944d320SPaolo Bonzini } 3139944d320SPaolo Bonzini 3149944d320SPaolo Bonzini s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 3159944d320SPaolo Bonzini 3169944d320SPaolo Bonzini if (s->reg[I_(UINTP)]) { 3179944d320SPaolo Bonzini qemu_irq_raise(s->irq); 3186804d230SGuenter Roeck trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]); 3199944d320SPaolo Bonzini } else { 3209944d320SPaolo Bonzini qemu_irq_lower(s->irq); 3216804d230SGuenter Roeck trace_exynos_uart_irq_lowered(s->channel); 3229944d320SPaolo Bonzini } 3239944d320SPaolo Bonzini } 3249944d320SPaolo Bonzini 3253a5d3a6fSGuenter Roeck static void exynos4210_uart_timeout_int(void *opaque) 3263a5d3a6fSGuenter Roeck { 3273a5d3a6fSGuenter Roeck Exynos4210UartState *s = opaque; 3283a5d3a6fSGuenter Roeck 3293a5d3a6fSGuenter Roeck trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)], 3303a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)]); 3313a5d3a6fSGuenter Roeck 3323a5d3a6fSGuenter Roeck if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) || 3333a5d3a6fSGuenter Roeck (s->reg[I_(UCON)] & (1 << 11))) { 3343a5d3a6fSGuenter Roeck s->reg[I_(UINTSP)] |= UINTSP_RXD; 3353a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT; 3363c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s); 3373a5d3a6fSGuenter Roeck exynos4210_uart_update_irq(s); 3383a5d3a6fSGuenter Roeck } 3393a5d3a6fSGuenter Roeck } 3403a5d3a6fSGuenter Roeck 3419944d320SPaolo Bonzini static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 3429944d320SPaolo Bonzini { 343e62694a0SPeter Maydell int speed, parity, data_bits, stop_bits; 3449944d320SPaolo Bonzini QEMUSerialSetParams ssp; 3459944d320SPaolo Bonzini uint64_t uclk_rate; 3469944d320SPaolo Bonzini 3479944d320SPaolo Bonzini if (s->reg[I_(UBRDIV)] == 0) { 3489944d320SPaolo Bonzini return; 3499944d320SPaolo Bonzini } 3509944d320SPaolo Bonzini 3519944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x20) { 3529944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x28) { 3539944d320SPaolo Bonzini parity = 'E'; 3549944d320SPaolo Bonzini } else { 3559944d320SPaolo Bonzini parity = 'O'; 3569944d320SPaolo Bonzini } 3579944d320SPaolo Bonzini } else { 3589944d320SPaolo Bonzini parity = 'N'; 3599944d320SPaolo Bonzini } 3609944d320SPaolo Bonzini 3619944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x4) { 3629944d320SPaolo Bonzini stop_bits = 2; 3639944d320SPaolo Bonzini } else { 3649944d320SPaolo Bonzini stop_bits = 1; 3659944d320SPaolo Bonzini } 3669944d320SPaolo Bonzini 3679944d320SPaolo Bonzini data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 3689944d320SPaolo Bonzini 3699944d320SPaolo Bonzini uclk_rate = 24000000; 3709944d320SPaolo Bonzini 3719944d320SPaolo Bonzini speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 3729944d320SPaolo Bonzini (s->reg[I_(UFRACVAL)] & 0x7) + 16); 3739944d320SPaolo Bonzini 3749944d320SPaolo Bonzini ssp.speed = speed; 3759944d320SPaolo Bonzini ssp.parity = parity; 3769944d320SPaolo Bonzini ssp.data_bits = data_bits; 3779944d320SPaolo Bonzini ssp.stop_bits = stop_bits; 3789944d320SPaolo Bonzini 3793a5d3a6fSGuenter Roeck s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed; 3803a5d3a6fSGuenter Roeck 3815345fdb4SMarc-André Lureau qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 3829944d320SPaolo Bonzini 3836804d230SGuenter Roeck trace_exynos_uart_update_params( 3843a5d3a6fSGuenter Roeck s->channel, speed, parity, data_bits, stop_bits, s->wordtime); 3853a5d3a6fSGuenter Roeck } 3863a5d3a6fSGuenter Roeck 3873a5d3a6fSGuenter Roeck static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s) 3883a5d3a6fSGuenter Roeck { 3893a5d3a6fSGuenter Roeck if (s->reg[I_(UCON)] & 0x80) { 3903a5d3a6fSGuenter Roeck uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime; 3913a5d3a6fSGuenter Roeck 3923a5d3a6fSGuenter Roeck timer_mod(s->fifo_timeout_timer, 3933a5d3a6fSGuenter Roeck qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); 3943a5d3a6fSGuenter Roeck } else { 3953a5d3a6fSGuenter Roeck timer_del(s->fifo_timeout_timer); 3963a5d3a6fSGuenter Roeck } 3979944d320SPaolo Bonzini } 3989944d320SPaolo Bonzini 3999944d320SPaolo Bonzini static void exynos4210_uart_write(void *opaque, hwaddr offset, 4009944d320SPaolo Bonzini uint64_t val, unsigned size) 4019944d320SPaolo Bonzini { 4029944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 4039944d320SPaolo Bonzini uint8_t ch; 4049944d320SPaolo Bonzini 4056804d230SGuenter Roeck trace_exynos_uart_write(s->channel, offset, 4066804d230SGuenter Roeck exynos4210_uart_regname(offset), val); 4079944d320SPaolo Bonzini 4089944d320SPaolo Bonzini switch (offset) { 4099944d320SPaolo Bonzini case ULCON: 4109944d320SPaolo Bonzini case UBRDIV: 4119944d320SPaolo Bonzini case UFRACVAL: 4129944d320SPaolo Bonzini s->reg[I_(offset)] = val; 4139944d320SPaolo Bonzini exynos4210_uart_update_parameters(s); 4149944d320SPaolo Bonzini break; 4159944d320SPaolo Bonzini case UFCON: 4169944d320SPaolo Bonzini s->reg[I_(UFCON)] = val; 4179944d320SPaolo Bonzini if (val & UFCON_Rx_FIFO_RESET) { 4189944d320SPaolo Bonzini fifo_reset(&s->rx); 4199944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 4206804d230SGuenter Roeck trace_exynos_uart_rx_fifo_reset(s->channel); 4219944d320SPaolo Bonzini } 4229944d320SPaolo Bonzini if (val & UFCON_Tx_FIFO_RESET) { 4239944d320SPaolo Bonzini fifo_reset(&s->tx); 4249944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 4256804d230SGuenter Roeck trace_exynos_uart_tx_fifo_reset(s->channel); 4269944d320SPaolo Bonzini } 4279944d320SPaolo Bonzini break; 4289944d320SPaolo Bonzini 4299944d320SPaolo Bonzini case UTXH: 43030650701SAnton Nefedov if (qemu_chr_fe_backend_connected(&s->chr)) { 4319944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 4329944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY); 4339944d320SPaolo Bonzini ch = (uint8_t)val; 4346ab3fc32SDaniel P. Berrange /* XXX this blocks entire thread. Rewrite to use 4356ab3fc32SDaniel P. Berrange * qemu_chr_fe_write and background I/O callbacks */ 4365345fdb4SMarc-André Lureau qemu_chr_fe_write_all(&s->chr, &ch, 1); 4376804d230SGuenter Roeck trace_exynos_uart_tx(s->channel, ch); 4389944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 4399944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY; 4409944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD; 4419944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4429944d320SPaolo Bonzini } 4439944d320SPaolo Bonzini break; 4449944d320SPaolo Bonzini 4459944d320SPaolo Bonzini case UINTP: 4469944d320SPaolo Bonzini s->reg[I_(UINTP)] &= ~val; 4479944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val; 4486804d230SGuenter Roeck trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]); 4499944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4509944d320SPaolo Bonzini break; 4519944d320SPaolo Bonzini case UTRSTAT: 4523a5d3a6fSGuenter Roeck if (val & UTRSTAT_Rx_TIMEOUT) { 4533a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT; 4543a5d3a6fSGuenter Roeck } 4553a5d3a6fSGuenter Roeck break; 4569944d320SPaolo Bonzini case UERSTAT: 4579944d320SPaolo Bonzini case UFSTAT: 4589944d320SPaolo Bonzini case UMSTAT: 4599944d320SPaolo Bonzini case URXH: 4606804d230SGuenter Roeck trace_exynos_uart_ro_write( 4619944d320SPaolo Bonzini s->channel, exynos4210_uart_regname(offset), offset); 4629944d320SPaolo Bonzini break; 4639944d320SPaolo Bonzini case UINTSP: 4649944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val; 4659944d320SPaolo Bonzini break; 4669944d320SPaolo Bonzini case UINTM: 4679944d320SPaolo Bonzini s->reg[I_(UINTM)] = val; 4689944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4699944d320SPaolo Bonzini break; 4709944d320SPaolo Bonzini case UCON: 4719944d320SPaolo Bonzini case UMCON: 4729944d320SPaolo Bonzini default: 4739944d320SPaolo Bonzini s->reg[I_(offset)] = val; 4749944d320SPaolo Bonzini break; 4759944d320SPaolo Bonzini } 4769944d320SPaolo Bonzini } 4773a5d3a6fSGuenter Roeck 4789944d320SPaolo Bonzini static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 4799944d320SPaolo Bonzini unsigned size) 4809944d320SPaolo Bonzini { 4819944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 4829944d320SPaolo Bonzini uint32_t res; 4839944d320SPaolo Bonzini 4849944d320SPaolo Bonzini switch (offset) { 4859944d320SPaolo Bonzini case UERSTAT: /* Read Only */ 4869944d320SPaolo Bonzini res = s->reg[I_(UERSTAT)]; 4879944d320SPaolo Bonzini s->reg[I_(UERSTAT)] = 0; 4886804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 4896804d230SGuenter Roeck exynos4210_uart_regname(offset), res); 4909944d320SPaolo Bonzini return res; 4919944d320SPaolo Bonzini case UFSTAT: /* Read Only */ 4929944d320SPaolo Bonzini s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 4939944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) == 0) { 4949944d320SPaolo Bonzini s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 4959944d320SPaolo Bonzini s->reg[I_(UFSTAT)] &= ~0xff; 4969944d320SPaolo Bonzini } 4976804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 4986804d230SGuenter Roeck exynos4210_uart_regname(offset), 4996804d230SGuenter Roeck s->reg[I_(UFSTAT)]); 5009944d320SPaolo Bonzini return s->reg[I_(UFSTAT)]; 5019944d320SPaolo Bonzini case URXH: 5029944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 5039944d320SPaolo Bonzini if (fifo_elements_number(&s->rx)) { 5049944d320SPaolo Bonzini res = fifo_retrieve(&s->rx); 5056804d230SGuenter Roeck trace_exynos_uart_rx(s->channel, res); 5069944d320SPaolo Bonzini if (!fifo_elements_number(&s->rx)) { 5079944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 5089944d320SPaolo Bonzini } else { 5099944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 5109944d320SPaolo Bonzini } 5119944d320SPaolo Bonzini } else { 5126804d230SGuenter Roeck trace_exynos_uart_rx_error(s->channel); 5139944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR; 5149944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5159944d320SPaolo Bonzini res = 0; 5169944d320SPaolo Bonzini } 5179944d320SPaolo Bonzini } else { 5189944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 5199944d320SPaolo Bonzini res = s->reg[I_(URXH)]; 5209944d320SPaolo Bonzini } 5213c77412bSGuenter Roeck exynos4210_uart_update_dmabusy(s); 5226804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 5236804d230SGuenter Roeck exynos4210_uart_regname(offset), res); 5249944d320SPaolo Bonzini return res; 5259944d320SPaolo Bonzini case UTXH: 5266804d230SGuenter Roeck trace_exynos_uart_wo_read(s->channel, exynos4210_uart_regname(offset), 5276804d230SGuenter Roeck offset); 5289944d320SPaolo Bonzini break; 5299944d320SPaolo Bonzini default: 5306804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, 5316804d230SGuenter Roeck exynos4210_uart_regname(offset), 5326804d230SGuenter Roeck s->reg[I_(offset)]); 5339944d320SPaolo Bonzini return s->reg[I_(offset)]; 5349944d320SPaolo Bonzini } 5359944d320SPaolo Bonzini 5366804d230SGuenter Roeck trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset), 5376804d230SGuenter Roeck 0); 5389944d320SPaolo Bonzini return 0; 5399944d320SPaolo Bonzini } 5409944d320SPaolo Bonzini 5419944d320SPaolo Bonzini static const MemoryRegionOps exynos4210_uart_ops = { 5429944d320SPaolo Bonzini .read = exynos4210_uart_read, 5439944d320SPaolo Bonzini .write = exynos4210_uart_write, 5449944d320SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 5459944d320SPaolo Bonzini .valid = { 5469944d320SPaolo Bonzini .max_access_size = 4, 5479944d320SPaolo Bonzini .unaligned = false 5489944d320SPaolo Bonzini }, 5499944d320SPaolo Bonzini }; 5509944d320SPaolo Bonzini 5519944d320SPaolo Bonzini static int exynos4210_uart_can_receive(void *opaque) 5529944d320SPaolo Bonzini { 5539944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5549944d320SPaolo Bonzini 5559944d320SPaolo Bonzini return fifo_empty_elements_number(&s->rx); 5569944d320SPaolo Bonzini } 5579944d320SPaolo Bonzini 5589944d320SPaolo Bonzini static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 5599944d320SPaolo Bonzini { 5609944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5619944d320SPaolo Bonzini int i; 5629944d320SPaolo Bonzini 5639944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 5649944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) < size) { 5653a5d3a6fSGuenter Roeck size = fifo_empty_elements_number(&s->rx); 5669944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR; 5673a5d3a6fSGuenter Roeck } 5689944d320SPaolo Bonzini for (i = 0; i < size; i++) { 5699944d320SPaolo Bonzini fifo_store(&s->rx, buf[i]); 5709944d320SPaolo Bonzini } 5713a5d3a6fSGuenter Roeck exynos4210_uart_rx_timeout_set(s); 5729944d320SPaolo Bonzini } else { 5739944d320SPaolo Bonzini s->reg[I_(URXH)] = buf[0]; 5749944d320SPaolo Bonzini } 5753a5d3a6fSGuenter Roeck s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 5769944d320SPaolo Bonzini 5779944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5789944d320SPaolo Bonzini } 5799944d320SPaolo Bonzini 5809944d320SPaolo Bonzini 581083b266fSPhilippe Mathieu-Daudé static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) 5829944d320SPaolo Bonzini { 5839944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5849944d320SPaolo Bonzini 5859944d320SPaolo Bonzini if (event == CHR_EVENT_BREAK) { 5869944d320SPaolo Bonzini /* When the RxDn is held in logic 0, then a null byte is pushed into the 5879944d320SPaolo Bonzini * fifo */ 5889944d320SPaolo Bonzini fifo_store(&s->rx, '\0'); 5899944d320SPaolo Bonzini s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 5909944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5919944d320SPaolo Bonzini } 5929944d320SPaolo Bonzini } 5939944d320SPaolo Bonzini 5949944d320SPaolo Bonzini 5959944d320SPaolo Bonzini static void exynos4210_uart_reset(DeviceState *dev) 5969944d320SPaolo Bonzini { 59761149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev); 5989944d320SPaolo Bonzini int i; 5999944d320SPaolo Bonzini 600c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 6019944d320SPaolo Bonzini s->reg[I_(exynos4210_uart_regs[i].offset)] = 6029944d320SPaolo Bonzini exynos4210_uart_regs[i].reset_value; 6039944d320SPaolo Bonzini } 6049944d320SPaolo Bonzini 6059944d320SPaolo Bonzini fifo_reset(&s->rx); 6069944d320SPaolo Bonzini fifo_reset(&s->tx); 6079944d320SPaolo Bonzini 6086804d230SGuenter Roeck trace_exynos_uart_rxsize(s->channel, s->rx.size); 6099944d320SPaolo Bonzini } 6109944d320SPaolo Bonzini 611c9d3396dSGuenter Roeck static int exynos4210_uart_post_load(void *opaque, int version_id) 612c9d3396dSGuenter Roeck { 613c9d3396dSGuenter Roeck Exynos4210UartState *s = (Exynos4210UartState *)opaque; 614c9d3396dSGuenter Roeck 615c9d3396dSGuenter Roeck exynos4210_uart_update_parameters(s); 6163a5d3a6fSGuenter Roeck exynos4210_uart_rx_timeout_set(s); 617c9d3396dSGuenter Roeck 618c9d3396dSGuenter Roeck return 0; 619c9d3396dSGuenter Roeck } 620c9d3396dSGuenter Roeck 6219944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart_fifo = { 6229944d320SPaolo Bonzini .name = "exynos4210.uart.fifo", 6239944d320SPaolo Bonzini .version_id = 1, 6249944d320SPaolo Bonzini .minimum_version_id = 1, 625c9d3396dSGuenter Roeck .post_load = exynos4210_uart_post_load, 6269944d320SPaolo Bonzini .fields = (VMStateField[]) { 6279944d320SPaolo Bonzini VMSTATE_UINT32(sp, Exynos4210UartFIFO), 6289944d320SPaolo Bonzini VMSTATE_UINT32(rp, Exynos4210UartFIFO), 62959046ec2SHalil Pasic VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size), 6309944d320SPaolo Bonzini VMSTATE_END_OF_LIST() 6319944d320SPaolo Bonzini } 6329944d320SPaolo Bonzini }; 6339944d320SPaolo Bonzini 6349944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart = { 6359944d320SPaolo Bonzini .name = "exynos4210.uart", 6369944d320SPaolo Bonzini .version_id = 1, 6379944d320SPaolo Bonzini .minimum_version_id = 1, 6389944d320SPaolo Bonzini .fields = (VMStateField[]) { 6399944d320SPaolo Bonzini VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 6409944d320SPaolo Bonzini vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 6419944d320SPaolo Bonzini VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 6429944d320SPaolo Bonzini EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 6439944d320SPaolo Bonzini VMSTATE_END_OF_LIST() 6449944d320SPaolo Bonzini } 6459944d320SPaolo Bonzini }; 6469944d320SPaolo Bonzini 6479944d320SPaolo Bonzini DeviceState *exynos4210_uart_create(hwaddr addr, 6489944d320SPaolo Bonzini int fifo_size, 6499944d320SPaolo Bonzini int channel, 6500ec7b3e7SMarc-André Lureau Chardev *chr, 6519944d320SPaolo Bonzini qemu_irq irq) 6529944d320SPaolo Bonzini { 6539944d320SPaolo Bonzini DeviceState *dev; 6549944d320SPaolo Bonzini SysBusDevice *bus; 6559944d320SPaolo Bonzini 6563e80f690SMarkus Armbruster dev = qdev_new(TYPE_EXYNOS4210_UART); 6579944d320SPaolo Bonzini 6589944d320SPaolo Bonzini qdev_prop_set_chr(dev, "chardev", chr); 6599944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "channel", channel); 6609944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "rx-size", fifo_size); 6619944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "tx-size", fifo_size); 6629944d320SPaolo Bonzini 6639944d320SPaolo Bonzini bus = SYS_BUS_DEVICE(dev); 6643c6ef471SMarkus Armbruster sysbus_realize_and_unref(bus, &error_fatal); 6659944d320SPaolo Bonzini if (addr != (hwaddr)-1) { 6669944d320SPaolo Bonzini sysbus_mmio_map(bus, 0, addr); 6679944d320SPaolo Bonzini } 6689944d320SPaolo Bonzini sysbus_connect_irq(bus, 0, irq); 6699944d320SPaolo Bonzini 6709944d320SPaolo Bonzini return dev; 6719944d320SPaolo Bonzini } 6729944d320SPaolo Bonzini 6735b982482Sxiaoqiang zhao static void exynos4210_uart_init(Object *obj) 6749944d320SPaolo Bonzini { 6755b982482Sxiaoqiang zhao SysBusDevice *dev = SYS_BUS_DEVICE(obj); 67661149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev); 6779944d320SPaolo Bonzini 6783a5d3a6fSGuenter Roeck s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600; 6793a5d3a6fSGuenter Roeck 6809944d320SPaolo Bonzini /* memory mapping */ 6815b982482Sxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s, 682300b1fc6SPaolo Bonzini "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 6839944d320SPaolo Bonzini sysbus_init_mmio(dev, &s->iomem); 6849944d320SPaolo Bonzini 6859944d320SPaolo Bonzini sysbus_init_irq(dev, &s->irq); 6863c77412bSGuenter Roeck sysbus_init_irq(dev, &s->dmairq); 6875b982482Sxiaoqiang zhao } 6885b982482Sxiaoqiang zhao 6895b982482Sxiaoqiang zhao static void exynos4210_uart_realize(DeviceState *dev, Error **errp) 6905b982482Sxiaoqiang zhao { 6915b982482Sxiaoqiang zhao Exynos4210UartState *s = EXYNOS4210_UART(dev); 6929944d320SPaolo Bonzini 6938bbc394cSChen Qun s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 6948bbc394cSChen Qun exynos4210_uart_timeout_int, s); 6958bbc394cSChen Qun 6965345fdb4SMarc-André Lureau qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, 6975345fdb4SMarc-André Lureau exynos4210_uart_receive, exynos4210_uart_event, 69881517ba3SAnton Nefedov NULL, s, NULL, true); 6999944d320SPaolo Bonzini } 7009944d320SPaolo Bonzini 7019944d320SPaolo Bonzini static Property exynos4210_uart_properties[] = { 7029944d320SPaolo Bonzini DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 7039944d320SPaolo Bonzini DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 7049944d320SPaolo Bonzini DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 7059944d320SPaolo Bonzini DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 7069944d320SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 7079944d320SPaolo Bonzini }; 7089944d320SPaolo Bonzini 7099944d320SPaolo Bonzini static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 7109944d320SPaolo Bonzini { 7119944d320SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 7129944d320SPaolo Bonzini 7135b982482Sxiaoqiang zhao dc->realize = exynos4210_uart_realize; 7149944d320SPaolo Bonzini dc->reset = exynos4210_uart_reset; 7154f67d30bSMarc-André Lureau device_class_set_props(dc, exynos4210_uart_properties); 7169944d320SPaolo Bonzini dc->vmsd = &vmstate_exynos4210_uart; 7179944d320SPaolo Bonzini } 7189944d320SPaolo Bonzini 7199944d320SPaolo Bonzini static const TypeInfo exynos4210_uart_info = { 72061149ff6SAndreas Färber .name = TYPE_EXYNOS4210_UART, 7219944d320SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 7229944d320SPaolo Bonzini .instance_size = sizeof(Exynos4210UartState), 7235b982482Sxiaoqiang zhao .instance_init = exynos4210_uart_init, 7249944d320SPaolo Bonzini .class_init = exynos4210_uart_class_init, 7259944d320SPaolo Bonzini }; 7269944d320SPaolo Bonzini 7279944d320SPaolo Bonzini static void exynos4210_uart_register(void) 7289944d320SPaolo Bonzini { 7299944d320SPaolo Bonzini type_register_static(&exynos4210_uart_info); 7309944d320SPaolo Bonzini } 7319944d320SPaolo Bonzini 7329944d320SPaolo Bonzini type_init(exynos4210_uart_register) 733