19944d320SPaolo Bonzini /* 29944d320SPaolo Bonzini * Exynos4210 UART Emulation 39944d320SPaolo Bonzini * 49944d320SPaolo Bonzini * Copyright (C) 2011 Samsung Electronics Co Ltd. 59944d320SPaolo Bonzini * Maksim Kozlov, <m.kozlov@samsung.com> 69944d320SPaolo Bonzini * 79944d320SPaolo Bonzini * This program is free software; you can redistribute it and/or modify it 89944d320SPaolo Bonzini * under the terms of the GNU General Public License as published by the 99944d320SPaolo Bonzini * Free Software Foundation; either version 2 of the License, or 109944d320SPaolo Bonzini * (at your option) any later version. 119944d320SPaolo Bonzini * 129944d320SPaolo Bonzini * This program is distributed in the hope that it will be useful, but WITHOUT 139944d320SPaolo Bonzini * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 149944d320SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 159944d320SPaolo Bonzini * for more details. 169944d320SPaolo Bonzini * 179944d320SPaolo Bonzini * You should have received a copy of the GNU General Public License along 189944d320SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 199944d320SPaolo Bonzini * 209944d320SPaolo Bonzini */ 219944d320SPaolo Bonzini 229944d320SPaolo Bonzini #include "hw/sysbus.h" 23*c525436eSMarkus Armbruster #include "qemu/error-report.h" 249944d320SPaolo Bonzini #include "sysemu/sysemu.h" 25dccfcd0eSPaolo Bonzini #include "sysemu/char.h" 269944d320SPaolo Bonzini 279944d320SPaolo Bonzini #include "hw/arm/exynos4210.h" 289944d320SPaolo Bonzini 299944d320SPaolo Bonzini #undef DEBUG_UART 309944d320SPaolo Bonzini #undef DEBUG_UART_EXTEND 319944d320SPaolo Bonzini #undef DEBUG_IRQ 329944d320SPaolo Bonzini #undef DEBUG_Rx_DATA 339944d320SPaolo Bonzini #undef DEBUG_Tx_DATA 349944d320SPaolo Bonzini 359944d320SPaolo Bonzini #define DEBUG_UART 0 369944d320SPaolo Bonzini #define DEBUG_UART_EXTEND 0 379944d320SPaolo Bonzini #define DEBUG_IRQ 0 389944d320SPaolo Bonzini #define DEBUG_Rx_DATA 0 399944d320SPaolo Bonzini #define DEBUG_Tx_DATA 0 409944d320SPaolo Bonzini 419944d320SPaolo Bonzini #if DEBUG_UART 429944d320SPaolo Bonzini #define PRINT_DEBUG(fmt, args...) \ 439944d320SPaolo Bonzini do { \ 449944d320SPaolo Bonzini fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 459944d320SPaolo Bonzini } while (0) 469944d320SPaolo Bonzini 479944d320SPaolo Bonzini #if DEBUG_UART_EXTEND 489944d320SPaolo Bonzini #define PRINT_DEBUG_EXTEND(fmt, args...) \ 499944d320SPaolo Bonzini do { \ 509944d320SPaolo Bonzini fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 519944d320SPaolo Bonzini } while (0) 529944d320SPaolo Bonzini #else 539944d320SPaolo Bonzini #define PRINT_DEBUG_EXTEND(fmt, args...) \ 549944d320SPaolo Bonzini do {} while (0) 559944d320SPaolo Bonzini #endif /* EXTEND */ 569944d320SPaolo Bonzini 579944d320SPaolo Bonzini #else 589944d320SPaolo Bonzini #define PRINT_DEBUG(fmt, args...) \ 599944d320SPaolo Bonzini do {} while (0) 609944d320SPaolo Bonzini #define PRINT_DEBUG_EXTEND(fmt, args...) \ 619944d320SPaolo Bonzini do {} while (0) 629944d320SPaolo Bonzini #endif 639944d320SPaolo Bonzini 649944d320SPaolo Bonzini #define PRINT_ERROR(fmt, args...) \ 659944d320SPaolo Bonzini do { \ 669944d320SPaolo Bonzini fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ 679944d320SPaolo Bonzini } while (0) 689944d320SPaolo Bonzini 699944d320SPaolo Bonzini /* 709944d320SPaolo Bonzini * Offsets for UART registers relative to SFR base address 719944d320SPaolo Bonzini * for UARTn 729944d320SPaolo Bonzini * 739944d320SPaolo Bonzini */ 749944d320SPaolo Bonzini #define ULCON 0x0000 /* Line Control */ 759944d320SPaolo Bonzini #define UCON 0x0004 /* Control */ 769944d320SPaolo Bonzini #define UFCON 0x0008 /* FIFO Control */ 779944d320SPaolo Bonzini #define UMCON 0x000C /* Modem Control */ 789944d320SPaolo Bonzini #define UTRSTAT 0x0010 /* Tx/Rx Status */ 799944d320SPaolo Bonzini #define UERSTAT 0x0014 /* UART Error Status */ 809944d320SPaolo Bonzini #define UFSTAT 0x0018 /* FIFO Status */ 819944d320SPaolo Bonzini #define UMSTAT 0x001C /* Modem Status */ 829944d320SPaolo Bonzini #define UTXH 0x0020 /* Transmit Buffer */ 839944d320SPaolo Bonzini #define URXH 0x0024 /* Receive Buffer */ 849944d320SPaolo Bonzini #define UBRDIV 0x0028 /* Baud Rate Divisor */ 859944d320SPaolo Bonzini #define UFRACVAL 0x002C /* Divisor Fractional Value */ 869944d320SPaolo Bonzini #define UINTP 0x0030 /* Interrupt Pending */ 879944d320SPaolo Bonzini #define UINTSP 0x0034 /* Interrupt Source Pending */ 889944d320SPaolo Bonzini #define UINTM 0x0038 /* Interrupt Mask */ 899944d320SPaolo Bonzini 909944d320SPaolo Bonzini /* 919944d320SPaolo Bonzini * for indexing register in the uint32_t array 929944d320SPaolo Bonzini * 939944d320SPaolo Bonzini * 'reg' - register offset (see offsets definitions above) 949944d320SPaolo Bonzini * 959944d320SPaolo Bonzini */ 969944d320SPaolo Bonzini #define I_(reg) (reg / sizeof(uint32_t)) 979944d320SPaolo Bonzini 989944d320SPaolo Bonzini typedef struct Exynos4210UartReg { 999944d320SPaolo Bonzini const char *name; /* the only reason is the debug output */ 1009944d320SPaolo Bonzini hwaddr offset; 1019944d320SPaolo Bonzini uint32_t reset_value; 1029944d320SPaolo Bonzini } Exynos4210UartReg; 1039944d320SPaolo Bonzini 1049944d320SPaolo Bonzini static Exynos4210UartReg exynos4210_uart_regs[] = { 1059944d320SPaolo Bonzini {"ULCON", ULCON, 0x00000000}, 1069944d320SPaolo Bonzini {"UCON", UCON, 0x00003000}, 1079944d320SPaolo Bonzini {"UFCON", UFCON, 0x00000000}, 1089944d320SPaolo Bonzini {"UMCON", UMCON, 0x00000000}, 1099944d320SPaolo Bonzini {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ 1109944d320SPaolo Bonzini {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ 1119944d320SPaolo Bonzini {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ 1129944d320SPaolo Bonzini {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ 1139944d320SPaolo Bonzini {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ 1149944d320SPaolo Bonzini {"URXH", URXH, 0x00000000}, /* RO */ 1159944d320SPaolo Bonzini {"UBRDIV", UBRDIV, 0x00000000}, 1169944d320SPaolo Bonzini {"UFRACVAL", UFRACVAL, 0x00000000}, 1179944d320SPaolo Bonzini {"UINTP", UINTP, 0x00000000}, 1189944d320SPaolo Bonzini {"UINTSP", UINTSP, 0x00000000}, 1199944d320SPaolo Bonzini {"UINTM", UINTM, 0x00000000}, 1209944d320SPaolo Bonzini }; 1219944d320SPaolo Bonzini 1229944d320SPaolo Bonzini #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C 1239944d320SPaolo Bonzini 1249944d320SPaolo Bonzini /* UART FIFO Control */ 1259944d320SPaolo Bonzini #define UFCON_FIFO_ENABLE 0x1 1269944d320SPaolo Bonzini #define UFCON_Rx_FIFO_RESET 0x2 1279944d320SPaolo Bonzini #define UFCON_Tx_FIFO_RESET 0x4 1289944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 1299944d320SPaolo Bonzini #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) 1309944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 1319944d320SPaolo Bonzini #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) 1329944d320SPaolo Bonzini 1339944d320SPaolo Bonzini /* Uart FIFO Status */ 1349944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_COUNT 0xff 1359944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_FULL 0x100 1369944d320SPaolo Bonzini #define UFSTAT_Rx_FIFO_ERROR 0x200 1379944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 1389944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) 1399944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 1409944d320SPaolo Bonzini #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) 1419944d320SPaolo Bonzini 1429944d320SPaolo Bonzini /* UART Interrupt Source Pending */ 1439944d320SPaolo Bonzini #define UINTSP_RXD 0x1 /* Receive interrupt */ 1449944d320SPaolo Bonzini #define UINTSP_ERROR 0x2 /* Error interrupt */ 1459944d320SPaolo Bonzini #define UINTSP_TXD 0x4 /* Transmit interrupt */ 1469944d320SPaolo Bonzini #define UINTSP_MODEM 0x8 /* Modem interrupt */ 1479944d320SPaolo Bonzini 1489944d320SPaolo Bonzini /* UART Line Control */ 1499944d320SPaolo Bonzini #define ULCON_IR_MODE_SHIFT 6 1509944d320SPaolo Bonzini #define ULCON_PARITY_SHIFT 3 1519944d320SPaolo Bonzini #define ULCON_STOP_BIT_SHIFT 1 1529944d320SPaolo Bonzini 1539944d320SPaolo Bonzini /* UART Tx/Rx Status */ 1549944d320SPaolo Bonzini #define UTRSTAT_TRANSMITTER_EMPTY 0x4 1559944d320SPaolo Bonzini #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 1569944d320SPaolo Bonzini #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 1579944d320SPaolo Bonzini 1589944d320SPaolo Bonzini /* UART Error Status */ 1599944d320SPaolo Bonzini #define UERSTAT_OVERRUN 0x1 1609944d320SPaolo Bonzini #define UERSTAT_PARITY 0x2 1619944d320SPaolo Bonzini #define UERSTAT_FRAME 0x4 1629944d320SPaolo Bonzini #define UERSTAT_BREAK 0x8 1639944d320SPaolo Bonzini 1649944d320SPaolo Bonzini typedef struct { 1659944d320SPaolo Bonzini uint8_t *data; 1669944d320SPaolo Bonzini uint32_t sp, rp; /* store and retrieve pointers */ 1679944d320SPaolo Bonzini uint32_t size; 1689944d320SPaolo Bonzini } Exynos4210UartFIFO; 1699944d320SPaolo Bonzini 17061149ff6SAndreas Färber #define TYPE_EXYNOS4210_UART "exynos4210.uart" 17161149ff6SAndreas Färber #define EXYNOS4210_UART(obj) \ 17261149ff6SAndreas Färber OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) 17361149ff6SAndreas Färber 17461149ff6SAndreas Färber typedef struct Exynos4210UartState { 17561149ff6SAndreas Färber SysBusDevice parent_obj; 17661149ff6SAndreas Färber 1779944d320SPaolo Bonzini MemoryRegion iomem; 1789944d320SPaolo Bonzini 1799944d320SPaolo Bonzini uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; 1809944d320SPaolo Bonzini Exynos4210UartFIFO rx; 1819944d320SPaolo Bonzini Exynos4210UartFIFO tx; 1829944d320SPaolo Bonzini 1839944d320SPaolo Bonzini CharDriverState *chr; 1849944d320SPaolo Bonzini qemu_irq irq; 1859944d320SPaolo Bonzini 1869944d320SPaolo Bonzini uint32_t channel; 1879944d320SPaolo Bonzini 1889944d320SPaolo Bonzini } Exynos4210UartState; 1899944d320SPaolo Bonzini 1909944d320SPaolo Bonzini 1919944d320SPaolo Bonzini #if DEBUG_UART 1929944d320SPaolo Bonzini /* Used only for debugging inside PRINT_DEBUG_... macros */ 1939944d320SPaolo Bonzini static const char *exynos4210_uart_regname(hwaddr offset) 1949944d320SPaolo Bonzini { 1959944d320SPaolo Bonzini 1969944d320SPaolo Bonzini int i; 1979944d320SPaolo Bonzini 198c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 1999944d320SPaolo Bonzini if (offset == exynos4210_uart_regs[i].offset) { 2009944d320SPaolo Bonzini return exynos4210_uart_regs[i].name; 2019944d320SPaolo Bonzini } 2029944d320SPaolo Bonzini } 2039944d320SPaolo Bonzini 2049944d320SPaolo Bonzini return NULL; 2059944d320SPaolo Bonzini } 2069944d320SPaolo Bonzini #endif 2079944d320SPaolo Bonzini 2089944d320SPaolo Bonzini 2099944d320SPaolo Bonzini static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) 2109944d320SPaolo Bonzini { 2119944d320SPaolo Bonzini q->data[q->sp] = ch; 2129944d320SPaolo Bonzini q->sp = (q->sp + 1) % q->size; 2139944d320SPaolo Bonzini } 2149944d320SPaolo Bonzini 2159944d320SPaolo Bonzini static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) 2169944d320SPaolo Bonzini { 2179944d320SPaolo Bonzini uint8_t ret = q->data[q->rp]; 2189944d320SPaolo Bonzini q->rp = (q->rp + 1) % q->size; 2199944d320SPaolo Bonzini return ret; 2209944d320SPaolo Bonzini } 2219944d320SPaolo Bonzini 2229944d320SPaolo Bonzini static int fifo_elements_number(Exynos4210UartFIFO *q) 2239944d320SPaolo Bonzini { 2249944d320SPaolo Bonzini if (q->sp < q->rp) { 2259944d320SPaolo Bonzini return q->size - q->rp + q->sp; 2269944d320SPaolo Bonzini } 2279944d320SPaolo Bonzini 2289944d320SPaolo Bonzini return q->sp - q->rp; 2299944d320SPaolo Bonzini } 2309944d320SPaolo Bonzini 2319944d320SPaolo Bonzini static int fifo_empty_elements_number(Exynos4210UartFIFO *q) 2329944d320SPaolo Bonzini { 2339944d320SPaolo Bonzini return q->size - fifo_elements_number(q); 2349944d320SPaolo Bonzini } 2359944d320SPaolo Bonzini 2369944d320SPaolo Bonzini static void fifo_reset(Exynos4210UartFIFO *q) 2379944d320SPaolo Bonzini { 2389944d320SPaolo Bonzini g_free(q->data); 2399944d320SPaolo Bonzini q->data = NULL; 2409944d320SPaolo Bonzini 2419944d320SPaolo Bonzini q->data = (uint8_t *)g_malloc0(q->size); 2429944d320SPaolo Bonzini 2439944d320SPaolo Bonzini q->sp = 0; 2449944d320SPaolo Bonzini q->rp = 0; 2459944d320SPaolo Bonzini } 2469944d320SPaolo Bonzini 2479944d320SPaolo Bonzini static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s) 2489944d320SPaolo Bonzini { 2499944d320SPaolo Bonzini uint32_t level = 0; 2509944d320SPaolo Bonzini uint32_t reg; 2519944d320SPaolo Bonzini 2529944d320SPaolo Bonzini reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> 2539944d320SPaolo Bonzini UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; 2549944d320SPaolo Bonzini 2559944d320SPaolo Bonzini switch (s->channel) { 2569944d320SPaolo Bonzini case 0: 2579944d320SPaolo Bonzini level = reg * 32; 2589944d320SPaolo Bonzini break; 2599944d320SPaolo Bonzini case 1: 2609944d320SPaolo Bonzini case 4: 2619944d320SPaolo Bonzini level = reg * 8; 2629944d320SPaolo Bonzini break; 2639944d320SPaolo Bonzini case 2: 2649944d320SPaolo Bonzini case 3: 2659944d320SPaolo Bonzini level = reg * 2; 2669944d320SPaolo Bonzini break; 2679944d320SPaolo Bonzini default: 2689944d320SPaolo Bonzini level = 0; 2699944d320SPaolo Bonzini PRINT_ERROR("Wrong UART channel number: %d\n", s->channel); 2709944d320SPaolo Bonzini } 2719944d320SPaolo Bonzini 2729944d320SPaolo Bonzini return level; 2739944d320SPaolo Bonzini } 2749944d320SPaolo Bonzini 2759944d320SPaolo Bonzini static void exynos4210_uart_update_irq(Exynos4210UartState *s) 2769944d320SPaolo Bonzini { 2779944d320SPaolo Bonzini /* 2789944d320SPaolo Bonzini * The Tx interrupt is always requested if the number of data in the 2799944d320SPaolo Bonzini * transmit FIFO is smaller than the trigger level. 2809944d320SPaolo Bonzini */ 2819944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 2829944d320SPaolo Bonzini 2839944d320SPaolo Bonzini uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> 2849944d320SPaolo Bonzini UFSTAT_Tx_FIFO_COUNT_SHIFT; 2859944d320SPaolo Bonzini 2869944d320SPaolo Bonzini if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { 2879944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD; 2889944d320SPaolo Bonzini } 2899944d320SPaolo Bonzini } 2909944d320SPaolo Bonzini 2919944d320SPaolo Bonzini s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; 2929944d320SPaolo Bonzini 2939944d320SPaolo Bonzini if (s->reg[I_(UINTP)]) { 2949944d320SPaolo Bonzini qemu_irq_raise(s->irq); 2959944d320SPaolo Bonzini 2969944d320SPaolo Bonzini #if DEBUG_IRQ 2979944d320SPaolo Bonzini fprintf(stderr, "UART%d: IRQ has been raised: %08x\n", 2989944d320SPaolo Bonzini s->channel, s->reg[I_(UINTP)]); 2999944d320SPaolo Bonzini #endif 3009944d320SPaolo Bonzini 3019944d320SPaolo Bonzini } else { 3029944d320SPaolo Bonzini qemu_irq_lower(s->irq); 3039944d320SPaolo Bonzini } 3049944d320SPaolo Bonzini } 3059944d320SPaolo Bonzini 3069944d320SPaolo Bonzini static void exynos4210_uart_update_parameters(Exynos4210UartState *s) 3079944d320SPaolo Bonzini { 3089944d320SPaolo Bonzini int speed, parity, data_bits, stop_bits, frame_size; 3099944d320SPaolo Bonzini QEMUSerialSetParams ssp; 3109944d320SPaolo Bonzini uint64_t uclk_rate; 3119944d320SPaolo Bonzini 3129944d320SPaolo Bonzini if (s->reg[I_(UBRDIV)] == 0) { 3139944d320SPaolo Bonzini return; 3149944d320SPaolo Bonzini } 3159944d320SPaolo Bonzini 3169944d320SPaolo Bonzini frame_size = 1; /* start bit */ 3179944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x20) { 3189944d320SPaolo Bonzini frame_size++; /* parity bit */ 3199944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x28) { 3209944d320SPaolo Bonzini parity = 'E'; 3219944d320SPaolo Bonzini } else { 3229944d320SPaolo Bonzini parity = 'O'; 3239944d320SPaolo Bonzini } 3249944d320SPaolo Bonzini } else { 3259944d320SPaolo Bonzini parity = 'N'; 3269944d320SPaolo Bonzini } 3279944d320SPaolo Bonzini 3289944d320SPaolo Bonzini if (s->reg[I_(ULCON)] & 0x4) { 3299944d320SPaolo Bonzini stop_bits = 2; 3309944d320SPaolo Bonzini } else { 3319944d320SPaolo Bonzini stop_bits = 1; 3329944d320SPaolo Bonzini } 3339944d320SPaolo Bonzini 3349944d320SPaolo Bonzini data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; 3359944d320SPaolo Bonzini 3369944d320SPaolo Bonzini frame_size += data_bits + stop_bits; 3379944d320SPaolo Bonzini 3389944d320SPaolo Bonzini uclk_rate = 24000000; 3399944d320SPaolo Bonzini 3409944d320SPaolo Bonzini speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + 3419944d320SPaolo Bonzini (s->reg[I_(UFRACVAL)] & 0x7) + 16); 3429944d320SPaolo Bonzini 3439944d320SPaolo Bonzini ssp.speed = speed; 3449944d320SPaolo Bonzini ssp.parity = parity; 3459944d320SPaolo Bonzini ssp.data_bits = data_bits; 3469944d320SPaolo Bonzini ssp.stop_bits = stop_bits; 3479944d320SPaolo Bonzini 3489944d320SPaolo Bonzini qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 3499944d320SPaolo Bonzini 3509944d320SPaolo Bonzini PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n", 3519944d320SPaolo Bonzini s->channel, speed, parity, data_bits, stop_bits); 3529944d320SPaolo Bonzini } 3539944d320SPaolo Bonzini 3549944d320SPaolo Bonzini static void exynos4210_uart_write(void *opaque, hwaddr offset, 3559944d320SPaolo Bonzini uint64_t val, unsigned size) 3569944d320SPaolo Bonzini { 3579944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 3589944d320SPaolo Bonzini uint8_t ch; 3599944d320SPaolo Bonzini 3609944d320SPaolo Bonzini PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel, 3619944d320SPaolo Bonzini offset, exynos4210_uart_regname(offset), (long long unsigned int)val); 3629944d320SPaolo Bonzini 3639944d320SPaolo Bonzini switch (offset) { 3649944d320SPaolo Bonzini case ULCON: 3659944d320SPaolo Bonzini case UBRDIV: 3669944d320SPaolo Bonzini case UFRACVAL: 3679944d320SPaolo Bonzini s->reg[I_(offset)] = val; 3689944d320SPaolo Bonzini exynos4210_uart_update_parameters(s); 3699944d320SPaolo Bonzini break; 3709944d320SPaolo Bonzini case UFCON: 3719944d320SPaolo Bonzini s->reg[I_(UFCON)] = val; 3729944d320SPaolo Bonzini if (val & UFCON_Rx_FIFO_RESET) { 3739944d320SPaolo Bonzini fifo_reset(&s->rx); 3749944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; 3759944d320SPaolo Bonzini PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel); 3769944d320SPaolo Bonzini } 3779944d320SPaolo Bonzini if (val & UFCON_Tx_FIFO_RESET) { 3789944d320SPaolo Bonzini fifo_reset(&s->tx); 3799944d320SPaolo Bonzini s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; 3809944d320SPaolo Bonzini PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel); 3819944d320SPaolo Bonzini } 3829944d320SPaolo Bonzini break; 3839944d320SPaolo Bonzini 3849944d320SPaolo Bonzini case UTXH: 3859944d320SPaolo Bonzini if (s->chr) { 3869944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | 3879944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY); 3889944d320SPaolo Bonzini ch = (uint8_t)val; 3899944d320SPaolo Bonzini qemu_chr_fe_write(s->chr, &ch, 1); 3909944d320SPaolo Bonzini #if DEBUG_Tx_DATA 3919944d320SPaolo Bonzini fprintf(stderr, "%c", ch); 3929944d320SPaolo Bonzini #endif 3939944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | 3949944d320SPaolo Bonzini UTRSTAT_Tx_BUFFER_EMPTY; 3959944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_TXD; 3969944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 3979944d320SPaolo Bonzini } 3989944d320SPaolo Bonzini break; 3999944d320SPaolo Bonzini 4009944d320SPaolo Bonzini case UINTP: 4019944d320SPaolo Bonzini s->reg[I_(UINTP)] &= ~val; 4029944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val; 4039944d320SPaolo Bonzini PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n", 4049944d320SPaolo Bonzini s->channel, offset, s->reg[I_(UINTP)]); 4059944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4069944d320SPaolo Bonzini break; 4079944d320SPaolo Bonzini case UTRSTAT: 4089944d320SPaolo Bonzini case UERSTAT: 4099944d320SPaolo Bonzini case UFSTAT: 4109944d320SPaolo Bonzini case UMSTAT: 4119944d320SPaolo Bonzini case URXH: 4129944d320SPaolo Bonzini PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n", 4139944d320SPaolo Bonzini s->channel, exynos4210_uart_regname(offset), offset); 4149944d320SPaolo Bonzini break; 4159944d320SPaolo Bonzini case UINTSP: 4169944d320SPaolo Bonzini s->reg[I_(UINTSP)] &= ~val; 4179944d320SPaolo Bonzini break; 4189944d320SPaolo Bonzini case UINTM: 4199944d320SPaolo Bonzini s->reg[I_(UINTM)] = val; 4209944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4219944d320SPaolo Bonzini break; 4229944d320SPaolo Bonzini case UCON: 4239944d320SPaolo Bonzini case UMCON: 4249944d320SPaolo Bonzini default: 4259944d320SPaolo Bonzini s->reg[I_(offset)] = val; 4269944d320SPaolo Bonzini break; 4279944d320SPaolo Bonzini } 4289944d320SPaolo Bonzini } 4299944d320SPaolo Bonzini static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, 4309944d320SPaolo Bonzini unsigned size) 4319944d320SPaolo Bonzini { 4329944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 4339944d320SPaolo Bonzini uint32_t res; 4349944d320SPaolo Bonzini 4359944d320SPaolo Bonzini switch (offset) { 4369944d320SPaolo Bonzini case UERSTAT: /* Read Only */ 4379944d320SPaolo Bonzini res = s->reg[I_(UERSTAT)]; 4389944d320SPaolo Bonzini s->reg[I_(UERSTAT)] = 0; 4399944d320SPaolo Bonzini return res; 4409944d320SPaolo Bonzini case UFSTAT: /* Read Only */ 4419944d320SPaolo Bonzini s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; 4429944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) == 0) { 4439944d320SPaolo Bonzini s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; 4449944d320SPaolo Bonzini s->reg[I_(UFSTAT)] &= ~0xff; 4459944d320SPaolo Bonzini } 4469944d320SPaolo Bonzini return s->reg[I_(UFSTAT)]; 4479944d320SPaolo Bonzini case URXH: 4489944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 4499944d320SPaolo Bonzini if (fifo_elements_number(&s->rx)) { 4509944d320SPaolo Bonzini res = fifo_retrieve(&s->rx); 4519944d320SPaolo Bonzini #if DEBUG_Rx_DATA 4529944d320SPaolo Bonzini fprintf(stderr, "%c", res); 4539944d320SPaolo Bonzini #endif 4549944d320SPaolo Bonzini if (!fifo_elements_number(&s->rx)) { 4559944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 4569944d320SPaolo Bonzini } else { 4579944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 4589944d320SPaolo Bonzini } 4599944d320SPaolo Bonzini } else { 4609944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR; 4619944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 4629944d320SPaolo Bonzini res = 0; 4639944d320SPaolo Bonzini } 4649944d320SPaolo Bonzini } else { 4659944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; 4669944d320SPaolo Bonzini res = s->reg[I_(URXH)]; 4679944d320SPaolo Bonzini } 4689944d320SPaolo Bonzini return res; 4699944d320SPaolo Bonzini case UTXH: 4709944d320SPaolo Bonzini PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n", 4719944d320SPaolo Bonzini s->channel, exynos4210_uart_regname(offset), offset); 4729944d320SPaolo Bonzini break; 4739944d320SPaolo Bonzini default: 4749944d320SPaolo Bonzini return s->reg[I_(offset)]; 4759944d320SPaolo Bonzini } 4769944d320SPaolo Bonzini 4779944d320SPaolo Bonzini return 0; 4789944d320SPaolo Bonzini } 4799944d320SPaolo Bonzini 4809944d320SPaolo Bonzini static const MemoryRegionOps exynos4210_uart_ops = { 4819944d320SPaolo Bonzini .read = exynos4210_uart_read, 4829944d320SPaolo Bonzini .write = exynos4210_uart_write, 4839944d320SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 4849944d320SPaolo Bonzini .valid = { 4859944d320SPaolo Bonzini .max_access_size = 4, 4869944d320SPaolo Bonzini .unaligned = false 4879944d320SPaolo Bonzini }, 4889944d320SPaolo Bonzini }; 4899944d320SPaolo Bonzini 4909944d320SPaolo Bonzini static int exynos4210_uart_can_receive(void *opaque) 4919944d320SPaolo Bonzini { 4929944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 4939944d320SPaolo Bonzini 4949944d320SPaolo Bonzini return fifo_empty_elements_number(&s->rx); 4959944d320SPaolo Bonzini } 4969944d320SPaolo Bonzini 4979944d320SPaolo Bonzini 4989944d320SPaolo Bonzini static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) 4999944d320SPaolo Bonzini { 5009944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5019944d320SPaolo Bonzini int i; 5029944d320SPaolo Bonzini 5039944d320SPaolo Bonzini if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { 5049944d320SPaolo Bonzini if (fifo_empty_elements_number(&s->rx) < size) { 5059944d320SPaolo Bonzini for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { 5069944d320SPaolo Bonzini fifo_store(&s->rx, buf[i]); 5079944d320SPaolo Bonzini } 5089944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_ERROR; 5099944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 5109944d320SPaolo Bonzini } else { 5119944d320SPaolo Bonzini for (i = 0; i < size; i++) { 5129944d320SPaolo Bonzini fifo_store(&s->rx, buf[i]); 5139944d320SPaolo Bonzini } 5149944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 5159944d320SPaolo Bonzini } 5169944d320SPaolo Bonzini /* XXX: Around here we maybe should check Rx trigger level */ 5179944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_RXD; 5189944d320SPaolo Bonzini } else { 5199944d320SPaolo Bonzini s->reg[I_(URXH)] = buf[0]; 5209944d320SPaolo Bonzini s->reg[I_(UINTSP)] |= UINTSP_RXD; 5219944d320SPaolo Bonzini s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; 5229944d320SPaolo Bonzini } 5239944d320SPaolo Bonzini 5249944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5259944d320SPaolo Bonzini } 5269944d320SPaolo Bonzini 5279944d320SPaolo Bonzini 5289944d320SPaolo Bonzini static void exynos4210_uart_event(void *opaque, int event) 5299944d320SPaolo Bonzini { 5309944d320SPaolo Bonzini Exynos4210UartState *s = (Exynos4210UartState *)opaque; 5319944d320SPaolo Bonzini 5329944d320SPaolo Bonzini if (event == CHR_EVENT_BREAK) { 5339944d320SPaolo Bonzini /* When the RxDn is held in logic 0, then a null byte is pushed into the 5349944d320SPaolo Bonzini * fifo */ 5359944d320SPaolo Bonzini fifo_store(&s->rx, '\0'); 5369944d320SPaolo Bonzini s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; 5379944d320SPaolo Bonzini exynos4210_uart_update_irq(s); 5389944d320SPaolo Bonzini } 5399944d320SPaolo Bonzini } 5409944d320SPaolo Bonzini 5419944d320SPaolo Bonzini 5429944d320SPaolo Bonzini static void exynos4210_uart_reset(DeviceState *dev) 5439944d320SPaolo Bonzini { 54461149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev); 5459944d320SPaolo Bonzini int i; 5469944d320SPaolo Bonzini 547c46b07f0SStefan Weil for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { 5489944d320SPaolo Bonzini s->reg[I_(exynos4210_uart_regs[i].offset)] = 5499944d320SPaolo Bonzini exynos4210_uart_regs[i].reset_value; 5509944d320SPaolo Bonzini } 5519944d320SPaolo Bonzini 5529944d320SPaolo Bonzini fifo_reset(&s->rx); 5539944d320SPaolo Bonzini fifo_reset(&s->tx); 5549944d320SPaolo Bonzini 5559944d320SPaolo Bonzini PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); 5569944d320SPaolo Bonzini } 5579944d320SPaolo Bonzini 5589944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart_fifo = { 5599944d320SPaolo Bonzini .name = "exynos4210.uart.fifo", 5609944d320SPaolo Bonzini .version_id = 1, 5619944d320SPaolo Bonzini .minimum_version_id = 1, 5629944d320SPaolo Bonzini .fields = (VMStateField[]) { 5639944d320SPaolo Bonzini VMSTATE_UINT32(sp, Exynos4210UartFIFO), 5649944d320SPaolo Bonzini VMSTATE_UINT32(rp, Exynos4210UartFIFO), 5659944d320SPaolo Bonzini VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size), 5669944d320SPaolo Bonzini VMSTATE_END_OF_LIST() 5679944d320SPaolo Bonzini } 5689944d320SPaolo Bonzini }; 5699944d320SPaolo Bonzini 5709944d320SPaolo Bonzini static const VMStateDescription vmstate_exynos4210_uart = { 5719944d320SPaolo Bonzini .name = "exynos4210.uart", 5729944d320SPaolo Bonzini .version_id = 1, 5739944d320SPaolo Bonzini .minimum_version_id = 1, 5749944d320SPaolo Bonzini .fields = (VMStateField[]) { 5759944d320SPaolo Bonzini VMSTATE_STRUCT(rx, Exynos4210UartState, 1, 5769944d320SPaolo Bonzini vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), 5779944d320SPaolo Bonzini VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, 5789944d320SPaolo Bonzini EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), 5799944d320SPaolo Bonzini VMSTATE_END_OF_LIST() 5809944d320SPaolo Bonzini } 5819944d320SPaolo Bonzini }; 5829944d320SPaolo Bonzini 5839944d320SPaolo Bonzini DeviceState *exynos4210_uart_create(hwaddr addr, 5849944d320SPaolo Bonzini int fifo_size, 5859944d320SPaolo Bonzini int channel, 5869944d320SPaolo Bonzini CharDriverState *chr, 5879944d320SPaolo Bonzini qemu_irq irq) 5889944d320SPaolo Bonzini { 5899944d320SPaolo Bonzini DeviceState *dev; 5909944d320SPaolo Bonzini SysBusDevice *bus; 5919944d320SPaolo Bonzini 5929944d320SPaolo Bonzini const char chr_name[] = "serial"; 5939944d320SPaolo Bonzini char label[ARRAY_SIZE(chr_name) + 1]; 5949944d320SPaolo Bonzini 59561149ff6SAndreas Färber dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 5969944d320SPaolo Bonzini 5979944d320SPaolo Bonzini if (!chr) { 5989944d320SPaolo Bonzini if (channel >= MAX_SERIAL_PORTS) { 599*c525436eSMarkus Armbruster error_report("Only %d serial ports are supported by QEMU", 6009944d320SPaolo Bonzini MAX_SERIAL_PORTS); 601*c525436eSMarkus Armbruster exit(1); 6029944d320SPaolo Bonzini } 6039944d320SPaolo Bonzini chr = serial_hds[channel]; 6049944d320SPaolo Bonzini if (!chr) { 6059944d320SPaolo Bonzini snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel); 6069944d320SPaolo Bonzini chr = qemu_chr_new(label, "null", NULL); 6079944d320SPaolo Bonzini if (!(chr)) { 608*c525436eSMarkus Armbruster error_report("Can't assign serial port to UART%d", channel); 609*c525436eSMarkus Armbruster exit(1); 6109944d320SPaolo Bonzini } 6119944d320SPaolo Bonzini } 6129944d320SPaolo Bonzini } 6139944d320SPaolo Bonzini 6149944d320SPaolo Bonzini qdev_prop_set_chr(dev, "chardev", chr); 6159944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "channel", channel); 6169944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "rx-size", fifo_size); 6179944d320SPaolo Bonzini qdev_prop_set_uint32(dev, "tx-size", fifo_size); 6189944d320SPaolo Bonzini 6199944d320SPaolo Bonzini bus = SYS_BUS_DEVICE(dev); 6209944d320SPaolo Bonzini qdev_init_nofail(dev); 6219944d320SPaolo Bonzini if (addr != (hwaddr)-1) { 6229944d320SPaolo Bonzini sysbus_mmio_map(bus, 0, addr); 6239944d320SPaolo Bonzini } 6249944d320SPaolo Bonzini sysbus_connect_irq(bus, 0, irq); 6259944d320SPaolo Bonzini 6269944d320SPaolo Bonzini return dev; 6279944d320SPaolo Bonzini } 6289944d320SPaolo Bonzini 6299944d320SPaolo Bonzini static int exynos4210_uart_init(SysBusDevice *dev) 6309944d320SPaolo Bonzini { 63161149ff6SAndreas Färber Exynos4210UartState *s = EXYNOS4210_UART(dev); 6329944d320SPaolo Bonzini 6339944d320SPaolo Bonzini /* memory mapping */ 634300b1fc6SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s, 635300b1fc6SPaolo Bonzini "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); 6369944d320SPaolo Bonzini sysbus_init_mmio(dev, &s->iomem); 6379944d320SPaolo Bonzini 6389944d320SPaolo Bonzini sysbus_init_irq(dev, &s->irq); 6399944d320SPaolo Bonzini 6409944d320SPaolo Bonzini qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive, 6419944d320SPaolo Bonzini exynos4210_uart_receive, exynos4210_uart_event, s); 6429944d320SPaolo Bonzini 6439944d320SPaolo Bonzini return 0; 6449944d320SPaolo Bonzini } 6459944d320SPaolo Bonzini 6469944d320SPaolo Bonzini static Property exynos4210_uart_properties[] = { 6479944d320SPaolo Bonzini DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), 6489944d320SPaolo Bonzini DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), 6499944d320SPaolo Bonzini DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), 6509944d320SPaolo Bonzini DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), 6519944d320SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 6529944d320SPaolo Bonzini }; 6539944d320SPaolo Bonzini 6549944d320SPaolo Bonzini static void exynos4210_uart_class_init(ObjectClass *klass, void *data) 6559944d320SPaolo Bonzini { 6569944d320SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 6579944d320SPaolo Bonzini SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 6589944d320SPaolo Bonzini 6599944d320SPaolo Bonzini k->init = exynos4210_uart_init; 6609944d320SPaolo Bonzini dc->reset = exynos4210_uart_reset; 6619944d320SPaolo Bonzini dc->props = exynos4210_uart_properties; 6629944d320SPaolo Bonzini dc->vmsd = &vmstate_exynos4210_uart; 6639944d320SPaolo Bonzini } 6649944d320SPaolo Bonzini 6659944d320SPaolo Bonzini static const TypeInfo exynos4210_uart_info = { 66661149ff6SAndreas Färber .name = TYPE_EXYNOS4210_UART, 6679944d320SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 6689944d320SPaolo Bonzini .instance_size = sizeof(Exynos4210UartState), 6699944d320SPaolo Bonzini .class_init = exynos4210_uart_class_init, 6709944d320SPaolo Bonzini }; 6719944d320SPaolo Bonzini 6729944d320SPaolo Bonzini static void exynos4210_uart_register(void) 6739944d320SPaolo Bonzini { 6749944d320SPaolo Bonzini type_register_static(&exynos4210_uart_info); 6759944d320SPaolo Bonzini } 6769944d320SPaolo Bonzini 6779944d320SPaolo Bonzini type_init(exynos4210_uart_register) 678