1 /* 2 * IMX31 UARTS 3 * 4 * Copyright (c) 2008 OKL 5 * Originally Written by Hans Jiang 6 * Copyright (c) 2011 NICTA Pty Ltd. 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This is a `bare-bones' implementation of the IMX series serial ports. 13 * TODO: 14 * -- implement FIFOs. The real hardware has 32 word transmit 15 * and receive FIFOs; we currently use a 1-char buffer 16 * -- implement DMA 17 * -- implement BAUD-rate and modem lines, for when the backend 18 * is a real serial device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/char/imx_serial.h" 23 #include "hw/irq.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 28 #ifndef DEBUG_IMX_UART 29 #define DEBUG_IMX_UART 0 30 #endif 31 32 #define DPRINTF(fmt, args...) \ 33 do { \ 34 if (DEBUG_IMX_UART) { \ 35 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \ 36 __func__, ##args); \ 37 } \ 38 } while (0) 39 40 static const VMStateDescription vmstate_imx_serial = { 41 .name = TYPE_IMX_SERIAL, 42 .version_id = 2, 43 .minimum_version_id = 2, 44 .fields = (VMStateField[]) { 45 VMSTATE_INT32(readbuff, IMXSerialState), 46 VMSTATE_UINT32(usr1, IMXSerialState), 47 VMSTATE_UINT32(usr2, IMXSerialState), 48 VMSTATE_UINT32(ucr1, IMXSerialState), 49 VMSTATE_UINT32(uts1, IMXSerialState), 50 VMSTATE_UINT32(onems, IMXSerialState), 51 VMSTATE_UINT32(ufcr, IMXSerialState), 52 VMSTATE_UINT32(ubmr, IMXSerialState), 53 VMSTATE_UINT32(ubrc, IMXSerialState), 54 VMSTATE_UINT32(ucr3, IMXSerialState), 55 VMSTATE_UINT32(ucr4, IMXSerialState), 56 VMSTATE_END_OF_LIST() 57 }, 58 }; 59 60 static void imx_update(IMXSerialState *s) 61 { 62 uint32_t usr1; 63 uint32_t usr2; 64 uint32_t mask; 65 66 /* 67 * Lucky for us TRDY and RRDY has the same offset in both USR1 and 68 * UCR1, so we can get away with something as simple as the 69 * following: 70 */ 71 usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); 72 /* 73 * Bits that we want in USR2 are not as conveniently laid out, 74 * unfortunately. 75 */ 76 mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; 77 /* 78 * TCEN and TXDC are both bit 3 79 * RDR and DREN are both bit 0 80 */ 81 mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN); 82 83 usr2 = s->usr2 & mask; 84 85 qemu_set_irq(s->irq, usr1 || usr2); 86 } 87 88 static void imx_serial_reset(IMXSerialState *s) 89 { 90 91 s->usr1 = USR1_TRDY | USR1_RXDS; 92 /* 93 * Fake attachment of a terminal: assert RTS. 94 */ 95 s->usr1 |= USR1_RTSS; 96 s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN; 97 s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY; 98 s->ucr1 = 0; 99 s->ucr2 = UCR2_SRST; 100 s->ucr3 = 0x700; 101 s->ubmr = 0; 102 s->ubrc = 4; 103 s->readbuff = URXD_ERR; 104 } 105 106 static void imx_serial_reset_at_boot(DeviceState *dev) 107 { 108 IMXSerialState *s = IMX_SERIAL(dev); 109 110 imx_serial_reset(s); 111 112 /* 113 * enable the uart on boot, so messages from the linux decompresser 114 * are visible. On real hardware this is done by the boot rom 115 * before anything else is loaded. 116 */ 117 s->ucr1 = UCR1_UARTEN; 118 s->ucr2 = UCR2_TXEN; 119 120 } 121 122 static uint64_t imx_serial_read(void *opaque, hwaddr offset, 123 unsigned size) 124 { 125 IMXSerialState *s = (IMXSerialState *)opaque; 126 uint32_t c; 127 128 DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); 129 130 switch (offset >> 2) { 131 case 0x0: /* URXD */ 132 c = s->readbuff; 133 if (!(s->uts1 & UTS1_RXEMPTY)) { 134 /* Character is valid */ 135 c |= URXD_CHARRDY; 136 s->usr1 &= ~USR1_RRDY; 137 s->usr2 &= ~USR2_RDR; 138 s->uts1 |= UTS1_RXEMPTY; 139 imx_update(s); 140 qemu_chr_fe_accept_input(&s->chr); 141 } 142 return c; 143 144 case 0x20: /* UCR1 */ 145 return s->ucr1; 146 147 case 0x21: /* UCR2 */ 148 return s->ucr2; 149 150 case 0x25: /* USR1 */ 151 return s->usr1; 152 153 case 0x26: /* USR2 */ 154 return s->usr2; 155 156 case 0x2A: /* BRM Modulator */ 157 return s->ubmr; 158 159 case 0x2B: /* Baud Rate Count */ 160 return s->ubrc; 161 162 case 0x2d: /* Test register */ 163 return s->uts1; 164 165 case 0x24: /* UFCR */ 166 return s->ufcr; 167 168 case 0x2c: 169 return s->onems; 170 171 case 0x22: /* UCR3 */ 172 return s->ucr3; 173 174 case 0x23: /* UCR4 */ 175 return s->ucr4; 176 177 case 0x29: /* BRM Incremental */ 178 return 0x0; /* TODO */ 179 180 default: 181 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 182 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 183 return 0; 184 } 185 } 186 187 static void imx_serial_write(void *opaque, hwaddr offset, 188 uint64_t value, unsigned size) 189 { 190 IMXSerialState *s = (IMXSerialState *)opaque; 191 Chardev *chr = qemu_chr_fe_get_driver(&s->chr); 192 unsigned char ch; 193 194 DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", 195 offset, (unsigned int)value, chr ? chr->label : "NODEV"); 196 197 switch (offset >> 2) { 198 case 0x10: /* UTXD */ 199 ch = value; 200 if (s->ucr2 & UCR2_TXEN) { 201 /* XXX this blocks entire thread. Rewrite to use 202 * qemu_chr_fe_write and background I/O callbacks */ 203 qemu_chr_fe_write_all(&s->chr, &ch, 1); 204 s->usr1 &= ~USR1_TRDY; 205 s->usr2 &= ~USR2_TXDC; 206 imx_update(s); 207 s->usr1 |= USR1_TRDY; 208 s->usr2 |= USR2_TXDC; 209 imx_update(s); 210 } 211 break; 212 213 case 0x20: /* UCR1 */ 214 s->ucr1 = value & 0xffff; 215 216 DPRINTF("write(ucr1=%x)\n", (unsigned int)value); 217 218 imx_update(s); 219 break; 220 221 case 0x21: /* UCR2 */ 222 /* 223 * Only a few bits in control register 2 are implemented as yet. 224 * If it's intended to use a real serial device as a back-end, this 225 * register will have to be implemented more fully. 226 */ 227 if (!(value & UCR2_SRST)) { 228 imx_serial_reset(s); 229 imx_update(s); 230 value |= UCR2_SRST; 231 } 232 if (value & UCR2_RXEN) { 233 if (!(s->ucr2 & UCR2_RXEN)) { 234 qemu_chr_fe_accept_input(&s->chr); 235 } 236 } 237 s->ucr2 = value & 0xffff; 238 break; 239 240 case 0x25: /* USR1 */ 241 value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM | 242 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER; 243 s->usr1 &= ~value; 244 break; 245 246 case 0x26: /* USR2 */ 247 /* 248 * Writing 1 to some bits clears them; all other 249 * values are ignored 250 */ 251 value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST | 252 USR2_RIDELT | USR2_IRINT | USR2_WAKE | 253 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE; 254 s->usr2 &= ~value; 255 break; 256 257 /* 258 * Linux expects to see what it writes to these registers 259 * We don't currently alter the baud rate 260 */ 261 case 0x29: /* UBIR */ 262 s->ubrc = value & 0xffff; 263 break; 264 265 case 0x2a: /* UBMR */ 266 s->ubmr = value & 0xffff; 267 break; 268 269 case 0x2c: /* One ms reg */ 270 s->onems = value & 0xffff; 271 break; 272 273 case 0x24: /* FIFO control register */ 274 s->ufcr = value & 0xffff; 275 break; 276 277 case 0x22: /* UCR3 */ 278 s->ucr3 = value & 0xffff; 279 break; 280 281 case 0x23: /* UCR4 */ 282 s->ucr4 = value & 0xffff; 283 imx_update(s); 284 break; 285 286 case 0x2d: /* UTS1 */ 287 qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" 288 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 289 /* TODO */ 290 break; 291 292 default: 293 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 294 HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); 295 } 296 } 297 298 static int imx_can_receive(void *opaque) 299 { 300 IMXSerialState *s = (IMXSerialState *)opaque; 301 return !(s->usr1 & USR1_RRDY); 302 } 303 304 static void imx_put_data(void *opaque, uint32_t value) 305 { 306 IMXSerialState *s = (IMXSerialState *)opaque; 307 308 DPRINTF("received char\n"); 309 310 s->usr1 |= USR1_RRDY; 311 s->usr2 |= USR2_RDR; 312 s->uts1 &= ~UTS1_RXEMPTY; 313 s->readbuff = value; 314 if (value & URXD_BRK) { 315 s->usr2 |= USR2_BRCD; 316 } 317 imx_update(s); 318 } 319 320 static void imx_receive(void *opaque, const uint8_t *buf, int size) 321 { 322 imx_put_data(opaque, *buf); 323 } 324 325 static void imx_event(void *opaque, int event) 326 { 327 if (event == CHR_EVENT_BREAK) { 328 imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); 329 } 330 } 331 332 333 static const struct MemoryRegionOps imx_serial_ops = { 334 .read = imx_serial_read, 335 .write = imx_serial_write, 336 .endianness = DEVICE_NATIVE_ENDIAN, 337 }; 338 339 static void imx_serial_realize(DeviceState *dev, Error **errp) 340 { 341 IMXSerialState *s = IMX_SERIAL(dev); 342 343 DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); 344 345 qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, 346 imx_event, NULL, s, NULL, true); 347 } 348 349 static void imx_serial_init(Object *obj) 350 { 351 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 352 IMXSerialState *s = IMX_SERIAL(obj); 353 354 memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s, 355 TYPE_IMX_SERIAL, 0x1000); 356 sysbus_init_mmio(sbd, &s->iomem); 357 sysbus_init_irq(sbd, &s->irq); 358 } 359 360 static Property imx_serial_properties[] = { 361 DEFINE_PROP_CHR("chardev", IMXSerialState, chr), 362 DEFINE_PROP_END_OF_LIST(), 363 }; 364 365 static void imx_serial_class_init(ObjectClass *klass, void *data) 366 { 367 DeviceClass *dc = DEVICE_CLASS(klass); 368 369 dc->realize = imx_serial_realize; 370 dc->vmsd = &vmstate_imx_serial; 371 dc->reset = imx_serial_reset_at_boot; 372 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 373 dc->desc = "i.MX series UART"; 374 dc->props = imx_serial_properties; 375 } 376 377 static const TypeInfo imx_serial_info = { 378 .name = TYPE_IMX_SERIAL, 379 .parent = TYPE_SYS_BUS_DEVICE, 380 .instance_size = sizeof(IMXSerialState), 381 .instance_init = imx_serial_init, 382 .class_init = imx_serial_class_init, 383 }; 384 385 static void imx_serial_register_types(void) 386 { 387 type_register_static(&imx_serial_info); 388 } 389 390 type_init(imx_serial_register_types) 391