1 /* 2 * nRF51 SoC UART emulation 3 * 4 * See nRF51 Series Reference Manual, "29 Universal Asynchronous 5 * Receiver/Transmitter" for hardware specifications: 6 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf 7 * 8 * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 or 12 * (at your option) any later version. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qemu/log.h" 17 #include "qemu/module.h" 18 #include "hw/char/nrf51_uart.h" 19 #include "hw/irq.h" 20 #include "migration/vmstate.h" 21 #include "trace.h" 22 23 static void nrf51_uart_update_irq(NRF51UARTState *s) 24 { 25 bool irq = false; 26 27 irq |= (s->reg[R_UART_RXDRDY] && 28 (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK)); 29 irq |= (s->reg[R_UART_TXDRDY] && 30 (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK)); 31 irq |= (s->reg[R_UART_ERROR] && 32 (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK)); 33 irq |= (s->reg[R_UART_RXTO] && 34 (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK)); 35 36 qemu_set_irq(s->irq, irq); 37 } 38 39 static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) 40 { 41 NRF51UARTState *s = NRF51_UART(opaque); 42 uint64_t r; 43 44 if (!s->enabled) { 45 return 0; 46 } 47 48 switch (addr) { 49 case A_UART_RXD: 50 r = s->rx_fifo[s->rx_fifo_pos]; 51 if (s->rx_started && s->rx_fifo_len) { 52 s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH; 53 s->rx_fifo_len--; 54 if (s->rx_fifo_len) { 55 s->reg[R_UART_RXDRDY] = 1; 56 nrf51_uart_update_irq(s); 57 } 58 qemu_chr_fe_accept_input(&s->chr); 59 } 60 break; 61 case A_UART_INTENSET: 62 case A_UART_INTENCLR: 63 case A_UART_INTEN: 64 r = s->reg[R_UART_INTEN]; 65 break; 66 default: 67 r = s->reg[addr / 4]; 68 break; 69 } 70 71 trace_nrf51_uart_read(addr, r, size); 72 73 return r; 74 } 75 76 static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque) 77 { 78 NRF51UARTState *s = NRF51_UART(opaque); 79 int r; 80 uint8_t c = s->reg[R_UART_TXD]; 81 82 s->watch_tag = 0; 83 84 r = qemu_chr_fe_write(&s->chr, &c, 1); 85 if (r <= 0) { 86 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 87 uart_transmit, s); 88 if (!s->watch_tag) { 89 /* The hardware has no transmit error reporting, 90 * so silently drop the byte 91 */ 92 goto buffer_drained; 93 } 94 return FALSE; 95 } 96 97 buffer_drained: 98 s->reg[R_UART_TXDRDY] = 1; 99 s->pending_tx_byte = false; 100 return FALSE; 101 } 102 103 static void uart_cancel_transmit(NRF51UARTState *s) 104 { 105 if (s->watch_tag) { 106 g_source_remove(s->watch_tag); 107 s->watch_tag = 0; 108 } 109 } 110 111 static void uart_write(void *opaque, hwaddr addr, 112 uint64_t value, unsigned int size) 113 { 114 NRF51UARTState *s = NRF51_UART(opaque); 115 116 trace_nrf51_uart_write(addr, value, size); 117 118 if (!s->enabled && (addr != A_UART_ENABLE)) { 119 return; 120 } 121 122 switch (addr) { 123 case A_UART_TXD: 124 if (!s->pending_tx_byte && s->tx_started) { 125 s->reg[R_UART_TXD] = value; 126 s->pending_tx_byte = true; 127 uart_transmit(NULL, G_IO_OUT, s); 128 } 129 break; 130 case A_UART_INTEN: 131 s->reg[R_UART_INTEN] = value; 132 break; 133 case A_UART_INTENSET: 134 s->reg[R_UART_INTEN] |= value; 135 break; 136 case A_UART_INTENCLR: 137 s->reg[R_UART_INTEN] &= ~value; 138 break; 139 case A_UART_TXDRDY ... A_UART_RXTO: 140 s->reg[addr / 4] = value; 141 break; 142 case A_UART_ERRORSRC: 143 s->reg[addr / 4] &= ~value; 144 break; 145 case A_UART_RXD: 146 break; 147 case A_UART_RXDRDY: 148 if (value == 0) { 149 s->reg[R_UART_RXDRDY] = 0; 150 } 151 break; 152 case A_UART_STARTTX: 153 if (value == 1) { 154 s->tx_started = true; 155 } 156 break; 157 case A_UART_STARTRX: 158 if (value == 1) { 159 s->rx_started = true; 160 } 161 break; 162 case A_UART_ENABLE: 163 if (value) { 164 if (value == 4) { 165 s->enabled = true; 166 } 167 break; 168 } 169 s->enabled = false; 170 value = 1; 171 /* fall through */ 172 case A_UART_SUSPEND: 173 case A_UART_STOPTX: 174 if (value == 1) { 175 s->tx_started = false; 176 } 177 /* fall through */ 178 case A_UART_STOPRX: 179 if (addr != A_UART_STOPTX && value == 1) { 180 s->rx_started = false; 181 s->reg[R_UART_RXTO] = 1; 182 } 183 break; 184 default: 185 s->reg[addr / 4] = value; 186 break; 187 } 188 nrf51_uart_update_irq(s); 189 } 190 191 static const MemoryRegionOps uart_ops = { 192 .read = uart_read, 193 .write = uart_write, 194 .endianness = DEVICE_LITTLE_ENDIAN, 195 }; 196 197 static void nrf51_uart_reset(DeviceState *dev) 198 { 199 NRF51UARTState *s = NRF51_UART(dev); 200 201 s->pending_tx_byte = 0; 202 203 uart_cancel_transmit(s); 204 205 memset(s->reg, 0, sizeof(s->reg)); 206 207 s->reg[R_UART_PSELRTS] = 0xFFFFFFFF; 208 s->reg[R_UART_PSELTXD] = 0xFFFFFFFF; 209 s->reg[R_UART_PSELCTS] = 0xFFFFFFFF; 210 s->reg[R_UART_PSELRXD] = 0xFFFFFFFF; 211 s->reg[R_UART_BAUDRATE] = 0x4000000; 212 213 s->rx_fifo_len = 0; 214 s->rx_fifo_pos = 0; 215 s->rx_started = false; 216 s->tx_started = false; 217 s->enabled = false; 218 } 219 220 static void uart_receive(void *opaque, const uint8_t *buf, int size) 221 { 222 223 NRF51UARTState *s = NRF51_UART(opaque); 224 int i; 225 226 if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) { 227 return; 228 } 229 230 for (i = 0; i < size; i++) { 231 uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH; 232 s->rx_fifo[pos] = buf[i]; 233 s->rx_fifo_len++; 234 } 235 236 s->reg[R_UART_RXDRDY] = 1; 237 nrf51_uart_update_irq(s); 238 } 239 240 static int uart_can_receive(void *opaque) 241 { 242 NRF51UARTState *s = NRF51_UART(opaque); 243 244 return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; 245 } 246 247 static void uart_event(void *opaque, int event) 248 { 249 NRF51UARTState *s = NRF51_UART(opaque); 250 251 if (event == CHR_EVENT_BREAK) { 252 s->reg[R_UART_ERRORSRC] |= 3; 253 s->reg[R_UART_ERROR] = 1; 254 nrf51_uart_update_irq(s); 255 } 256 } 257 258 static void nrf51_uart_realize(DeviceState *dev, Error **errp) 259 { 260 NRF51UARTState *s = NRF51_UART(dev); 261 262 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 263 uart_event, NULL, s, NULL, true); 264 } 265 266 static void nrf51_uart_init(Object *obj) 267 { 268 NRF51UARTState *s = NRF51_UART(obj); 269 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 270 271 memory_region_init_io(&s->iomem, obj, &uart_ops, s, 272 "nrf51_soc.uart", UART_SIZE); 273 sysbus_init_mmio(sbd, &s->iomem); 274 sysbus_init_irq(sbd, &s->irq); 275 } 276 277 static int nrf51_uart_post_load(void *opaque, int version_id) 278 { 279 NRF51UARTState *s = NRF51_UART(opaque); 280 281 if (s->pending_tx_byte) { 282 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 283 uart_transmit, s); 284 } 285 286 return 0; 287 } 288 289 static const VMStateDescription nrf51_uart_vmstate = { 290 .name = "nrf51_soc.uart", 291 .post_load = nrf51_uart_post_load, 292 .fields = (VMStateField[]) { 293 VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C), 294 VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH), 295 VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState), 296 VMSTATE_UINT32(rx_fifo_len, NRF51UARTState), 297 VMSTATE_BOOL(rx_started, NRF51UARTState), 298 VMSTATE_BOOL(tx_started, NRF51UARTState), 299 VMSTATE_BOOL(pending_tx_byte, NRF51UARTState), 300 VMSTATE_BOOL(enabled, NRF51UARTState), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 static Property nrf51_uart_properties[] = { 306 DEFINE_PROP_CHR("chardev", NRF51UARTState, chr), 307 DEFINE_PROP_END_OF_LIST(), 308 }; 309 310 static void nrf51_uart_class_init(ObjectClass *klass, void *data) 311 { 312 DeviceClass *dc = DEVICE_CLASS(klass); 313 314 dc->reset = nrf51_uart_reset; 315 dc->realize = nrf51_uart_realize; 316 dc->props = nrf51_uart_properties; 317 dc->vmsd = &nrf51_uart_vmstate; 318 } 319 320 static const TypeInfo nrf51_uart_info = { 321 .name = TYPE_NRF51_UART, 322 .parent = TYPE_SYS_BUS_DEVICE, 323 .instance_size = sizeof(NRF51UARTState), 324 .instance_init = nrf51_uart_init, 325 .class_init = nrf51_uart_class_init 326 }; 327 328 static void nrf51_uart_register_types(void) 329 { 330 type_register_static(&nrf51_uart_info); 331 } 332 333 type_init(nrf51_uart_register_types) 334