1 /* 2 * TI OMAP processors UART emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * Copyright (C) 2007-2009 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "sysemu/char.h" 21 #include "hw/hw.h" 22 #include "hw/arm/omap.h" 23 #include "hw/char/serial.h" 24 #include "exec/address-spaces.h" 25 26 /* UARTs */ 27 struct omap_uart_s { 28 MemoryRegion iomem; 29 hwaddr base; 30 SerialState *serial; /* TODO */ 31 struct omap_target_agent_s *ta; 32 omap_clk fclk; 33 qemu_irq irq; 34 35 uint8_t eblr; 36 uint8_t syscontrol; 37 uint8_t wkup; 38 uint8_t cfps; 39 uint8_t mdr[2]; 40 uint8_t scr; 41 uint8_t clksel; 42 }; 43 44 void omap_uart_reset(struct omap_uart_s *s) 45 { 46 s->eblr = 0x00; 47 s->syscontrol = 0; 48 s->wkup = 0x3f; 49 s->cfps = 0x69; 50 s->clksel = 0; 51 } 52 53 struct omap_uart_s *omap_uart_init(hwaddr base, 54 qemu_irq irq, omap_clk fclk, omap_clk iclk, 55 qemu_irq txdma, qemu_irq rxdma, 56 const char *label, CharDriverState *chr) 57 { 58 struct omap_uart_s *s = (struct omap_uart_s *) 59 g_malloc0(sizeof(struct omap_uart_s)); 60 61 s->base = base; 62 s->fclk = fclk; 63 s->irq = irq; 64 s->serial = serial_mm_init(get_system_memory(), base, 2, irq, 65 omap_clk_getrate(fclk)/16, 66 chr ?: qemu_chr_new(label, "null", NULL), 67 DEVICE_NATIVE_ENDIAN); 68 return s; 69 } 70 71 static uint64_t omap_uart_read(void *opaque, hwaddr addr, 72 unsigned size) 73 { 74 struct omap_uart_s *s = (struct omap_uart_s *) opaque; 75 76 if (size == 4) { 77 return omap_badwidth_read8(opaque, addr); 78 } 79 80 switch (addr) { 81 case 0x20: /* MDR1 */ 82 return s->mdr[0]; 83 case 0x24: /* MDR2 */ 84 return s->mdr[1]; 85 case 0x40: /* SCR */ 86 return s->scr; 87 case 0x44: /* SSR */ 88 return 0x0; 89 case 0x48: /* EBLR (OMAP2) */ 90 return s->eblr; 91 case 0x4C: /* OSC_12M_SEL (OMAP1) */ 92 return s->clksel; 93 case 0x50: /* MVR */ 94 return 0x30; 95 case 0x54: /* SYSC (OMAP2) */ 96 return s->syscontrol; 97 case 0x58: /* SYSS (OMAP2) */ 98 return 1; 99 case 0x5c: /* WER (OMAP2) */ 100 return s->wkup; 101 case 0x60: /* CFPS (OMAP2) */ 102 return s->cfps; 103 } 104 105 OMAP_BAD_REG(addr); 106 return 0; 107 } 108 109 static void omap_uart_write(void *opaque, hwaddr addr, 110 uint64_t value, unsigned size) 111 { 112 struct omap_uart_s *s = (struct omap_uart_s *) opaque; 113 114 if (size == 4) { 115 return omap_badwidth_write8(opaque, addr, value); 116 } 117 118 switch (addr) { 119 case 0x20: /* MDR1 */ 120 s->mdr[0] = value & 0x7f; 121 break; 122 case 0x24: /* MDR2 */ 123 s->mdr[1] = value & 0xff; 124 break; 125 case 0x40: /* SCR */ 126 s->scr = value & 0xff; 127 break; 128 case 0x48: /* EBLR (OMAP2) */ 129 s->eblr = value & 0xff; 130 break; 131 case 0x4C: /* OSC_12M_SEL (OMAP1) */ 132 s->clksel = value & 1; 133 break; 134 case 0x44: /* SSR */ 135 case 0x50: /* MVR */ 136 case 0x58: /* SYSS (OMAP2) */ 137 OMAP_RO_REG(addr); 138 break; 139 case 0x54: /* SYSC (OMAP2) */ 140 s->syscontrol = value & 0x1d; 141 if (value & 2) 142 omap_uart_reset(s); 143 break; 144 case 0x5c: /* WER (OMAP2) */ 145 s->wkup = value & 0x7f; 146 break; 147 case 0x60: /* CFPS (OMAP2) */ 148 s->cfps = value & 0xff; 149 break; 150 default: 151 OMAP_BAD_REG(addr); 152 } 153 } 154 155 static const MemoryRegionOps omap_uart_ops = { 156 .read = omap_uart_read, 157 .write = omap_uart_write, 158 .endianness = DEVICE_NATIVE_ENDIAN, 159 }; 160 161 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 162 struct omap_target_agent_s *ta, 163 qemu_irq irq, omap_clk fclk, omap_clk iclk, 164 qemu_irq txdma, qemu_irq rxdma, 165 const char *label, CharDriverState *chr) 166 { 167 hwaddr base = omap_l4_attach(ta, 0, NULL); 168 struct omap_uart_s *s = omap_uart_init(base, irq, 169 fclk, iclk, txdma, rxdma, label, chr); 170 171 memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s, "omap.uart", 0x100); 172 173 s->ta = ta; 174 175 memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); 176 177 return s; 178 } 179 180 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) 181 { 182 /* TODO: Should reuse or destroy current s->serial */ 183 s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq, 184 omap_clk_getrate(s->fclk) / 16, 185 chr ?: qemu_chr_new("null", "null", NULL), 186 DEVICE_NATIVE_ENDIAN); 187 } 188