1 /* 2 * QEMU 16550A UART emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2008 Citrix Systems, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/char/serial.h" 28 #include "hw/irq.h" 29 #include "migration/vmstate.h" 30 #include "chardev/char-serial.h" 31 #include "qapi/error.h" 32 #include "qemu/timer.h" 33 #include "sysemu/reset.h" 34 #include "sysemu/runstate.h" 35 #include "qemu/error-report.h" 36 #include "trace.h" 37 #include "hw/qdev-properties.h" 38 39 //#define DEBUG_SERIAL 40 41 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 42 43 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 44 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 45 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 46 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 47 48 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 49 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 50 51 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 52 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 53 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 54 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 55 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ 56 57 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ 58 #define UART_IIR_FE 0xC0 /* Fifo enabled */ 59 60 /* 61 * These are the definitions for the Modem Control Register 62 */ 63 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 64 #define UART_MCR_OUT2 0x08 /* Out2 complement */ 65 #define UART_MCR_OUT1 0x04 /* Out1 complement */ 66 #define UART_MCR_RTS 0x02 /* RTS complement */ 67 #define UART_MCR_DTR 0x01 /* DTR complement */ 68 69 /* 70 * These are the definitions for the Modem Status Register 71 */ 72 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 73 #define UART_MSR_RI 0x40 /* Ring Indicator */ 74 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 75 #define UART_MSR_CTS 0x10 /* Clear to Send */ 76 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 77 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 78 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 79 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 80 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 81 82 #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 83 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 84 #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 85 #define UART_LSR_FE 0x08 /* Frame error indicator */ 86 #define UART_LSR_PE 0x04 /* Parity error indicator */ 87 #define UART_LSR_OE 0x02 /* Overrun error indicator */ 88 #define UART_LSR_DR 0x01 /* Receiver data ready */ 89 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ 90 91 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ 92 93 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ 94 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ 95 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ 96 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ 97 98 #define UART_FCR_DMS 0x08 /* DMA Mode Select */ 99 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ 100 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ 101 #define UART_FCR_FE 0x01 /* FIFO Enable */ 102 103 #define MAX_XMIT_RETRY 4 104 105 #ifdef DEBUG_SERIAL 106 #define DPRINTF(fmt, ...) \ 107 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) 108 #else 109 #define DPRINTF(fmt, ...) \ 110 do {} while (0) 111 #endif 112 113 static void serial_receive1(void *opaque, const uint8_t *buf, int size); 114 static void serial_xmit(SerialState *s); 115 116 static inline void recv_fifo_put(SerialState *s, uint8_t chr) 117 { 118 /* Receive overruns do not overwrite FIFO contents. */ 119 if (!fifo8_is_full(&s->recv_fifo)) { 120 fifo8_push(&s->recv_fifo, chr); 121 } else { 122 s->lsr |= UART_LSR_OE; 123 } 124 } 125 126 static void serial_update_irq(SerialState *s) 127 { 128 uint8_t tmp_iir = UART_IIR_NO_INT; 129 130 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { 131 tmp_iir = UART_IIR_RLSI; 132 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { 133 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, 134 * this is not in the specification but is observed on existing 135 * hardware. */ 136 tmp_iir = UART_IIR_CTI; 137 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && 138 (!(s->fcr & UART_FCR_FE) || 139 s->recv_fifo.num >= s->recv_fifo_itl)) { 140 tmp_iir = UART_IIR_RDI; 141 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { 142 tmp_iir = UART_IIR_THRI; 143 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { 144 tmp_iir = UART_IIR_MSI; 145 } 146 147 s->iir = tmp_iir | (s->iir & 0xF0); 148 149 if (tmp_iir != UART_IIR_NO_INT) { 150 qemu_irq_raise(s->irq); 151 } else { 152 qemu_irq_lower(s->irq); 153 } 154 } 155 156 static void serial_update_parameters(SerialState *s) 157 { 158 float speed; 159 int parity, data_bits, stop_bits, frame_size; 160 QEMUSerialSetParams ssp; 161 162 /* Start bit. */ 163 frame_size = 1; 164 if (s->lcr & 0x08) { 165 /* Parity bit. */ 166 frame_size++; 167 if (s->lcr & 0x10) 168 parity = 'E'; 169 else 170 parity = 'O'; 171 } else { 172 parity = 'N'; 173 } 174 if (s->lcr & 0x04) { 175 stop_bits = 2; 176 } else { 177 stop_bits = 1; 178 } 179 180 data_bits = (s->lcr & 0x03) + 5; 181 frame_size += data_bits + stop_bits; 182 /* Zero divisor should give about 3500 baud */ 183 speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider; 184 ssp.speed = speed; 185 ssp.parity = parity; 186 ssp.data_bits = data_bits; 187 ssp.stop_bits = stop_bits; 188 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; 189 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 190 trace_serial_update_parameters(speed, parity, data_bits, stop_bits); 191 } 192 193 static void serial_update_msl(SerialState *s) 194 { 195 uint8_t omsr; 196 int flags; 197 198 timer_del(s->modem_status_poll); 199 200 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, 201 &flags) == -ENOTSUP) { 202 s->poll_msl = -1; 203 return; 204 } 205 206 omsr = s->msr; 207 208 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; 209 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; 210 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; 211 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; 212 213 if (s->msr != omsr) { 214 /* Set delta bits */ 215 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); 216 /* UART_MSR_TERI only if change was from 1 -> 0 */ 217 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) 218 s->msr &= ~UART_MSR_TERI; 219 serial_update_irq(s); 220 } 221 222 /* The real 16550A apparently has a 250ns response latency to line status changes. 223 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ 224 225 if (s->poll_msl) { 226 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 227 NANOSECONDS_PER_SECOND / 100); 228 } 229 } 230 231 static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond, 232 void *opaque) 233 { 234 SerialState *s = opaque; 235 s->watch_tag = 0; 236 serial_xmit(s); 237 return FALSE; 238 } 239 240 static void serial_xmit(SerialState *s) 241 { 242 do { 243 assert(!(s->lsr & UART_LSR_TEMT)); 244 if (s->tsr_retry == 0) { 245 assert(!(s->lsr & UART_LSR_THRE)); 246 247 if (s->fcr & UART_FCR_FE) { 248 assert(!fifo8_is_empty(&s->xmit_fifo)); 249 s->tsr = fifo8_pop(&s->xmit_fifo); 250 if (!s->xmit_fifo.num) { 251 s->lsr |= UART_LSR_THRE; 252 } 253 } else { 254 s->tsr = s->thr; 255 s->lsr |= UART_LSR_THRE; 256 } 257 if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) { 258 s->thr_ipending = 1; 259 serial_update_irq(s); 260 } 261 } 262 263 if (s->mcr & UART_MCR_LOOP) { 264 /* in loopback mode, say that we just received a char */ 265 serial_receive1(s, &s->tsr, 1); 266 } else { 267 int rc = qemu_chr_fe_write(&s->chr, &s->tsr, 1); 268 269 if ((rc == 0 || 270 (rc == -1 && errno == EAGAIN)) && 271 s->tsr_retry < MAX_XMIT_RETRY) { 272 assert(s->watch_tag == 0); 273 s->watch_tag = 274 qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 275 serial_watch_cb, s); 276 if (s->watch_tag > 0) { 277 s->tsr_retry++; 278 return; 279 } 280 } 281 } 282 s->tsr_retry = 0; 283 284 /* Transmit another byte if it is already available. It is only 285 possible when FIFO is enabled and not empty. */ 286 } while (!(s->lsr & UART_LSR_THRE)); 287 288 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 289 s->lsr |= UART_LSR_TEMT; 290 } 291 292 /* Setter for FCR. 293 is_load flag means, that value is set while loading VM state 294 and interrupt should not be invoked */ 295 static void serial_write_fcr(SerialState *s, uint8_t val) 296 { 297 /* Set fcr - val only has the bits that are supposed to "stick" */ 298 s->fcr = val; 299 300 if (val & UART_FCR_FE) { 301 s->iir |= UART_IIR_FE; 302 /* Set recv_fifo trigger Level */ 303 switch (val & 0xC0) { 304 case UART_FCR_ITL_1: 305 s->recv_fifo_itl = 1; 306 break; 307 case UART_FCR_ITL_2: 308 s->recv_fifo_itl = 4; 309 break; 310 case UART_FCR_ITL_3: 311 s->recv_fifo_itl = 8; 312 break; 313 case UART_FCR_ITL_4: 314 s->recv_fifo_itl = 14; 315 break; 316 } 317 } else { 318 s->iir &= ~UART_IIR_FE; 319 } 320 } 321 322 static void serial_update_tiocm(SerialState *s) 323 { 324 int flags; 325 326 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags); 327 328 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); 329 330 if (s->mcr & UART_MCR_RTS) { 331 flags |= CHR_TIOCM_RTS; 332 } 333 if (s->mcr & UART_MCR_DTR) { 334 flags |= CHR_TIOCM_DTR; 335 } 336 337 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags); 338 } 339 340 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 341 unsigned size) 342 { 343 SerialState *s = opaque; 344 345 assert(size == 1 && addr < 8); 346 trace_serial_ioport_write(addr, val); 347 switch(addr) { 348 default: 349 case 0: 350 if (s->lcr & UART_LCR_DLAB) { 351 if (size == 1) { 352 s->divider = (s->divider & 0xff00) | val; 353 } else { 354 s->divider = val; 355 } 356 serial_update_parameters(s); 357 } else { 358 s->thr = (uint8_t) val; 359 if(s->fcr & UART_FCR_FE) { 360 /* xmit overruns overwrite data, so make space if needed */ 361 if (fifo8_is_full(&s->xmit_fifo)) { 362 fifo8_pop(&s->xmit_fifo); 363 } 364 fifo8_push(&s->xmit_fifo, s->thr); 365 } 366 s->thr_ipending = 0; 367 s->lsr &= ~UART_LSR_THRE; 368 s->lsr &= ~UART_LSR_TEMT; 369 serial_update_irq(s); 370 if (s->tsr_retry == 0) { 371 serial_xmit(s); 372 } 373 } 374 break; 375 case 1: 376 if (s->lcr & UART_LCR_DLAB) { 377 s->divider = (s->divider & 0x00ff) | (val << 8); 378 serial_update_parameters(s); 379 } else { 380 uint8_t changed = (s->ier ^ val) & 0x0f; 381 s->ier = val & 0x0f; 382 /* If the backend device is a real serial port, turn polling of the modem 383 * status lines on physical port on or off depending on UART_IER_MSI state. 384 */ 385 if ((changed & UART_IER_MSI) && s->poll_msl >= 0) { 386 if (s->ier & UART_IER_MSI) { 387 s->poll_msl = 1; 388 serial_update_msl(s); 389 } else { 390 timer_del(s->modem_status_poll); 391 s->poll_msl = 0; 392 } 393 } 394 395 /* Turning on the THRE interrupt on IER can trigger the interrupt 396 * if LSR.THRE=1, even if it had been masked before by reading IIR. 397 * This is not in the datasheet, but Windows relies on it. It is 398 * unclear if THRE has to be resampled every time THRI becomes 399 * 1, or only on the rising edge. Bochs does the latter, and Windows 400 * always toggles IER to all zeroes and back to all ones, so do the 401 * same. 402 * 403 * If IER.THRI is zero, thr_ipending is not used. Set it to zero 404 * so that the thr_ipending subsection is not migrated. 405 */ 406 if (changed & UART_IER_THRI) { 407 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { 408 s->thr_ipending = 1; 409 } else { 410 s->thr_ipending = 0; 411 } 412 } 413 414 if (changed) { 415 serial_update_irq(s); 416 } 417 } 418 break; 419 case 2: 420 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ 421 if ((val ^ s->fcr) & UART_FCR_FE) { 422 val |= UART_FCR_XFR | UART_FCR_RFR; 423 } 424 425 /* FIFO clear */ 426 427 if (val & UART_FCR_RFR) { 428 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 429 timer_del(s->fifo_timeout_timer); 430 s->timeout_ipending = 0; 431 fifo8_reset(&s->recv_fifo); 432 } 433 434 if (val & UART_FCR_XFR) { 435 s->lsr |= UART_LSR_THRE; 436 s->thr_ipending = 1; 437 fifo8_reset(&s->xmit_fifo); 438 } 439 440 serial_write_fcr(s, val & 0xC9); 441 serial_update_irq(s); 442 break; 443 case 3: 444 { 445 int break_enable; 446 s->lcr = val; 447 serial_update_parameters(s); 448 break_enable = (val >> 6) & 1; 449 if (break_enable != s->last_break_enable) { 450 s->last_break_enable = break_enable; 451 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 452 &break_enable); 453 } 454 } 455 break; 456 case 4: 457 { 458 int old_mcr = s->mcr; 459 s->mcr = val & 0x1f; 460 if (val & UART_MCR_LOOP) 461 break; 462 463 if (s->poll_msl >= 0 && old_mcr != s->mcr) { 464 serial_update_tiocm(s); 465 /* Update the modem status after a one-character-send wait-time, since there may be a response 466 from the device/computer at the other end of the serial line */ 467 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); 468 } 469 } 470 break; 471 case 5: 472 break; 473 case 6: 474 break; 475 case 7: 476 s->scr = val; 477 break; 478 } 479 } 480 481 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) 482 { 483 SerialState *s = opaque; 484 uint32_t ret; 485 486 assert(size == 1 && addr < 8); 487 switch(addr) { 488 default: 489 case 0: 490 if (s->lcr & UART_LCR_DLAB) { 491 ret = s->divider & 0xff; 492 } else { 493 if(s->fcr & UART_FCR_FE) { 494 ret = fifo8_is_empty(&s->recv_fifo) ? 495 0 : fifo8_pop(&s->recv_fifo); 496 if (s->recv_fifo.num == 0) { 497 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 498 } else { 499 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); 500 } 501 s->timeout_ipending = 0; 502 } else { 503 ret = s->rbr; 504 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); 505 } 506 serial_update_irq(s); 507 if (!(s->mcr & UART_MCR_LOOP)) { 508 /* in loopback mode, don't receive any data */ 509 qemu_chr_fe_accept_input(&s->chr); 510 } 511 } 512 break; 513 case 1: 514 if (s->lcr & UART_LCR_DLAB) { 515 ret = (s->divider >> 8) & 0xff; 516 } else { 517 ret = s->ier; 518 } 519 break; 520 case 2: 521 ret = s->iir; 522 if ((ret & UART_IIR_ID) == UART_IIR_THRI) { 523 s->thr_ipending = 0; 524 serial_update_irq(s); 525 } 526 break; 527 case 3: 528 ret = s->lcr; 529 break; 530 case 4: 531 ret = s->mcr; 532 break; 533 case 5: 534 ret = s->lsr; 535 /* Clear break and overrun interrupts */ 536 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { 537 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); 538 serial_update_irq(s); 539 } 540 break; 541 case 6: 542 if (s->mcr & UART_MCR_LOOP) { 543 /* in loopback, the modem output pins are connected to the 544 inputs */ 545 ret = (s->mcr & 0x0c) << 4; 546 ret |= (s->mcr & 0x02) << 3; 547 ret |= (s->mcr & 0x01) << 5; 548 } else { 549 if (s->poll_msl >= 0) 550 serial_update_msl(s); 551 ret = s->msr; 552 /* Clear delta bits & msr int after read, if they were set */ 553 if (s->msr & UART_MSR_ANY_DELTA) { 554 s->msr &= 0xF0; 555 serial_update_irq(s); 556 } 557 } 558 break; 559 case 7: 560 ret = s->scr; 561 break; 562 } 563 trace_serial_ioport_read(addr, ret); 564 return ret; 565 } 566 567 static int serial_can_receive(SerialState *s) 568 { 569 if(s->fcr & UART_FCR_FE) { 570 if (s->recv_fifo.num < UART_FIFO_LENGTH) { 571 /* 572 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 573 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the 574 * effect will be to almost always fill the fifo completely before 575 * the guest has a chance to respond, effectively overriding the ITL 576 * that the guest has set. 577 */ 578 return (s->recv_fifo.num <= s->recv_fifo_itl) ? 579 s->recv_fifo_itl - s->recv_fifo.num : 1; 580 } else { 581 return 0; 582 } 583 } else { 584 return !(s->lsr & UART_LSR_DR); 585 } 586 } 587 588 static void serial_receive_break(SerialState *s) 589 { 590 s->rbr = 0; 591 /* When the LSR_DR is set a null byte is pushed into the fifo */ 592 recv_fifo_put(s, '\0'); 593 s->lsr |= UART_LSR_BI | UART_LSR_DR; 594 serial_update_irq(s); 595 } 596 597 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ 598 static void fifo_timeout_int (void *opaque) { 599 SerialState *s = opaque; 600 if (s->recv_fifo.num) { 601 s->timeout_ipending = 1; 602 serial_update_irq(s); 603 } 604 } 605 606 static int serial_can_receive1(void *opaque) 607 { 608 SerialState *s = opaque; 609 return serial_can_receive(s); 610 } 611 612 static void serial_receive1(void *opaque, const uint8_t *buf, int size) 613 { 614 SerialState *s = opaque; 615 616 if (s->wakeup) { 617 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER, NULL); 618 } 619 if(s->fcr & UART_FCR_FE) { 620 int i; 621 for (i = 0; i < size; i++) { 622 recv_fifo_put(s, buf[i]); 623 } 624 s->lsr |= UART_LSR_DR; 625 /* call the timeout receive callback in 4 char transmit time */ 626 timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); 627 } else { 628 if (s->lsr & UART_LSR_DR) 629 s->lsr |= UART_LSR_OE; 630 s->rbr = buf[0]; 631 s->lsr |= UART_LSR_DR; 632 } 633 serial_update_irq(s); 634 } 635 636 static void serial_event(void *opaque, QEMUChrEvent event) 637 { 638 SerialState *s = opaque; 639 DPRINTF("event %x\n", event); 640 if (event == CHR_EVENT_BREAK) 641 serial_receive_break(s); 642 } 643 644 static int serial_pre_save(void *opaque) 645 { 646 SerialState *s = opaque; 647 s->fcr_vmstate = s->fcr; 648 649 return 0; 650 } 651 652 static int serial_pre_load(void *opaque) 653 { 654 SerialState *s = opaque; 655 s->thr_ipending = -1; 656 s->poll_msl = -1; 657 return 0; 658 } 659 660 static int serial_post_load(void *opaque, int version_id) 661 { 662 SerialState *s = opaque; 663 664 if (version_id < 3) { 665 s->fcr_vmstate = 0; 666 } 667 if (s->thr_ipending == -1) { 668 s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); 669 } 670 671 if (s->tsr_retry > 0) { 672 /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */ 673 if (s->lsr & UART_LSR_TEMT) { 674 error_report("inconsistent state in serial device " 675 "(tsr empty, tsr_retry=%d", s->tsr_retry); 676 return -1; 677 } 678 679 if (s->tsr_retry > MAX_XMIT_RETRY) { 680 s->tsr_retry = MAX_XMIT_RETRY; 681 } 682 683 assert(s->watch_tag == 0); 684 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 685 serial_watch_cb, s); 686 } else { 687 /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */ 688 if (!(s->lsr & UART_LSR_TEMT)) { 689 error_report("inconsistent state in serial device " 690 "(tsr not empty, tsr_retry=0"); 691 return -1; 692 } 693 } 694 695 s->last_break_enable = (s->lcr >> 6) & 1; 696 /* Initialize fcr via setter to perform essential side-effects */ 697 serial_write_fcr(s, s->fcr_vmstate); 698 serial_update_parameters(s); 699 return 0; 700 } 701 702 static bool serial_thr_ipending_needed(void *opaque) 703 { 704 SerialState *s = opaque; 705 706 if (s->ier & UART_IER_THRI) { 707 bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); 708 return s->thr_ipending != expected_value; 709 } else { 710 /* LSR.THRE will be sampled again when the interrupt is 711 * enabled. thr_ipending is not used in this case, do 712 * not migrate it. 713 */ 714 return false; 715 } 716 } 717 718 static const VMStateDescription vmstate_serial_thr_ipending = { 719 .name = "serial/thr_ipending", 720 .version_id = 1, 721 .minimum_version_id = 1, 722 .needed = serial_thr_ipending_needed, 723 .fields = (VMStateField[]) { 724 VMSTATE_INT32(thr_ipending, SerialState), 725 VMSTATE_END_OF_LIST() 726 } 727 }; 728 729 static bool serial_tsr_needed(void *opaque) 730 { 731 SerialState *s = (SerialState *)opaque; 732 return s->tsr_retry != 0; 733 } 734 735 static const VMStateDescription vmstate_serial_tsr = { 736 .name = "serial/tsr", 737 .version_id = 1, 738 .minimum_version_id = 1, 739 .needed = serial_tsr_needed, 740 .fields = (VMStateField[]) { 741 VMSTATE_UINT32(tsr_retry, SerialState), 742 VMSTATE_UINT8(thr, SerialState), 743 VMSTATE_UINT8(tsr, SerialState), 744 VMSTATE_END_OF_LIST() 745 } 746 }; 747 748 static bool serial_recv_fifo_needed(void *opaque) 749 { 750 SerialState *s = (SerialState *)opaque; 751 return !fifo8_is_empty(&s->recv_fifo); 752 753 } 754 755 static const VMStateDescription vmstate_serial_recv_fifo = { 756 .name = "serial/recv_fifo", 757 .version_id = 1, 758 .minimum_version_id = 1, 759 .needed = serial_recv_fifo_needed, 760 .fields = (VMStateField[]) { 761 VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8), 762 VMSTATE_END_OF_LIST() 763 } 764 }; 765 766 static bool serial_xmit_fifo_needed(void *opaque) 767 { 768 SerialState *s = (SerialState *)opaque; 769 return !fifo8_is_empty(&s->xmit_fifo); 770 } 771 772 static const VMStateDescription vmstate_serial_xmit_fifo = { 773 .name = "serial/xmit_fifo", 774 .version_id = 1, 775 .minimum_version_id = 1, 776 .needed = serial_xmit_fifo_needed, 777 .fields = (VMStateField[]) { 778 VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8), 779 VMSTATE_END_OF_LIST() 780 } 781 }; 782 783 static bool serial_fifo_timeout_timer_needed(void *opaque) 784 { 785 SerialState *s = (SerialState *)opaque; 786 return timer_pending(s->fifo_timeout_timer); 787 } 788 789 static const VMStateDescription vmstate_serial_fifo_timeout_timer = { 790 .name = "serial/fifo_timeout_timer", 791 .version_id = 1, 792 .minimum_version_id = 1, 793 .needed = serial_fifo_timeout_timer_needed, 794 .fields = (VMStateField[]) { 795 VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState), 796 VMSTATE_END_OF_LIST() 797 } 798 }; 799 800 static bool serial_timeout_ipending_needed(void *opaque) 801 { 802 SerialState *s = (SerialState *)opaque; 803 return s->timeout_ipending != 0; 804 } 805 806 static const VMStateDescription vmstate_serial_timeout_ipending = { 807 .name = "serial/timeout_ipending", 808 .version_id = 1, 809 .minimum_version_id = 1, 810 .needed = serial_timeout_ipending_needed, 811 .fields = (VMStateField[]) { 812 VMSTATE_INT32(timeout_ipending, SerialState), 813 VMSTATE_END_OF_LIST() 814 } 815 }; 816 817 static bool serial_poll_needed(void *opaque) 818 { 819 SerialState *s = (SerialState *)opaque; 820 return s->poll_msl >= 0; 821 } 822 823 static const VMStateDescription vmstate_serial_poll = { 824 .name = "serial/poll", 825 .version_id = 1, 826 .needed = serial_poll_needed, 827 .minimum_version_id = 1, 828 .fields = (VMStateField[]) { 829 VMSTATE_INT32(poll_msl, SerialState), 830 VMSTATE_TIMER_PTR(modem_status_poll, SerialState), 831 VMSTATE_END_OF_LIST() 832 } 833 }; 834 835 const VMStateDescription vmstate_serial = { 836 .name = "serial", 837 .version_id = 3, 838 .minimum_version_id = 2, 839 .pre_save = serial_pre_save, 840 .pre_load = serial_pre_load, 841 .post_load = serial_post_load, 842 .fields = (VMStateField[]) { 843 VMSTATE_UINT16_V(divider, SerialState, 2), 844 VMSTATE_UINT8(rbr, SerialState), 845 VMSTATE_UINT8(ier, SerialState), 846 VMSTATE_UINT8(iir, SerialState), 847 VMSTATE_UINT8(lcr, SerialState), 848 VMSTATE_UINT8(mcr, SerialState), 849 VMSTATE_UINT8(lsr, SerialState), 850 VMSTATE_UINT8(msr, SerialState), 851 VMSTATE_UINT8(scr, SerialState), 852 VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), 853 VMSTATE_END_OF_LIST() 854 }, 855 .subsections = (const VMStateDescription*[]) { 856 &vmstate_serial_thr_ipending, 857 &vmstate_serial_tsr, 858 &vmstate_serial_recv_fifo, 859 &vmstate_serial_xmit_fifo, 860 &vmstate_serial_fifo_timeout_timer, 861 &vmstate_serial_timeout_ipending, 862 &vmstate_serial_poll, 863 NULL 864 } 865 }; 866 867 static void serial_reset(void *opaque) 868 { 869 SerialState *s = opaque; 870 871 if (s->watch_tag > 0) { 872 g_source_remove(s->watch_tag); 873 s->watch_tag = 0; 874 } 875 876 s->rbr = 0; 877 s->ier = 0; 878 s->iir = UART_IIR_NO_INT; 879 s->lcr = 0; 880 s->lsr = UART_LSR_TEMT | UART_LSR_THRE; 881 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; 882 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ 883 s->divider = 0x0C; 884 s->mcr = UART_MCR_OUT2; 885 s->scr = 0; 886 s->tsr_retry = 0; 887 s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10; 888 s->poll_msl = 0; 889 890 s->timeout_ipending = 0; 891 timer_del(s->fifo_timeout_timer); 892 timer_del(s->modem_status_poll); 893 894 fifo8_reset(&s->recv_fifo); 895 fifo8_reset(&s->xmit_fifo); 896 897 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 898 899 s->thr_ipending = 0; 900 s->last_break_enable = 0; 901 qemu_irq_lower(s->irq); 902 903 serial_update_msl(s); 904 s->msr &= ~UART_MSR_ANY_DELTA; 905 } 906 907 static int serial_be_change(void *opaque) 908 { 909 SerialState *s = opaque; 910 911 qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, 912 serial_event, serial_be_change, s, NULL, true); 913 914 serial_update_parameters(s); 915 916 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 917 &s->last_break_enable); 918 919 s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0; 920 serial_update_msl(s); 921 922 if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) { 923 serial_update_tiocm(s); 924 } 925 926 if (s->watch_tag > 0) { 927 g_source_remove(s->watch_tag); 928 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 929 serial_watch_cb, s); 930 } 931 932 return 0; 933 } 934 935 static void serial_realize(DeviceState *dev, Error **errp) 936 { 937 SerialState *s = SERIAL(dev); 938 939 s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); 940 941 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); 942 qemu_register_reset(serial_reset, s); 943 944 qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, 945 serial_event, serial_be_change, s, NULL, true); 946 fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); 947 fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); 948 serial_reset(s); 949 } 950 951 static void serial_unrealize(DeviceState *dev) 952 { 953 SerialState *s = SERIAL(dev); 954 955 qemu_chr_fe_deinit(&s->chr, false); 956 957 timer_del(s->modem_status_poll); 958 timer_free(s->modem_status_poll); 959 960 timer_del(s->fifo_timeout_timer); 961 timer_free(s->fifo_timeout_timer); 962 963 fifo8_destroy(&s->recv_fifo); 964 fifo8_destroy(&s->xmit_fifo); 965 966 qemu_unregister_reset(serial_reset, s); 967 } 968 969 /* Change the main reference oscillator frequency. */ 970 void serial_set_frequency(SerialState *s, uint32_t frequency) 971 { 972 s->baudbase = frequency; 973 serial_update_parameters(s); 974 } 975 976 const MemoryRegionOps serial_io_ops = { 977 .read = serial_ioport_read, 978 .write = serial_ioport_write, 979 .impl = { 980 .min_access_size = 1, 981 .max_access_size = 1, 982 }, 983 .endianness = DEVICE_LITTLE_ENDIAN, 984 }; 985 986 static Property serial_properties[] = { 987 DEFINE_PROP_CHR("chardev", SerialState, chr), 988 DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200), 989 DEFINE_PROP_END_OF_LIST(), 990 }; 991 992 static void serial_class_init(ObjectClass *klass, void* data) 993 { 994 DeviceClass *dc = DEVICE_CLASS(klass); 995 996 /* internal device for serialio/serialmm, not user-creatable */ 997 dc->user_creatable = false; 998 dc->realize = serial_realize; 999 dc->unrealize = serial_unrealize; 1000 device_class_set_props(dc, serial_properties); 1001 } 1002 1003 static const TypeInfo serial_info = { 1004 .name = TYPE_SERIAL, 1005 .parent = TYPE_DEVICE, 1006 .instance_size = sizeof(SerialState), 1007 .class_init = serial_class_init, 1008 }; 1009 1010 /* Memory mapped interface */ 1011 static uint64_t serial_mm_read(void *opaque, hwaddr addr, 1012 unsigned size) 1013 { 1014 SerialMM *s = SERIAL_MM(opaque); 1015 return serial_ioport_read(&s->serial, addr >> s->regshift, 1); 1016 } 1017 1018 static void serial_mm_write(void *opaque, hwaddr addr, 1019 uint64_t value, unsigned size) 1020 { 1021 SerialMM *s = SERIAL_MM(opaque); 1022 value &= 255; 1023 serial_ioport_write(&s->serial, addr >> s->regshift, value, 1); 1024 } 1025 1026 static const MemoryRegionOps serial_mm_ops[3] = { 1027 [DEVICE_NATIVE_ENDIAN] = { 1028 .read = serial_mm_read, 1029 .write = serial_mm_write, 1030 .endianness = DEVICE_NATIVE_ENDIAN, 1031 .valid.max_access_size = 8, 1032 .impl.max_access_size = 8, 1033 }, 1034 [DEVICE_LITTLE_ENDIAN] = { 1035 .read = serial_mm_read, 1036 .write = serial_mm_write, 1037 .endianness = DEVICE_LITTLE_ENDIAN, 1038 .valid.max_access_size = 8, 1039 .impl.max_access_size = 8, 1040 }, 1041 [DEVICE_BIG_ENDIAN] = { 1042 .read = serial_mm_read, 1043 .write = serial_mm_write, 1044 .endianness = DEVICE_BIG_ENDIAN, 1045 .valid.max_access_size = 8, 1046 .impl.max_access_size = 8, 1047 }, 1048 }; 1049 1050 static void serial_mm_realize(DeviceState *dev, Error **errp) 1051 { 1052 SerialMM *smm = SERIAL_MM(dev); 1053 SerialState *s = &smm->serial; 1054 1055 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1056 return; 1057 } 1058 1059 memory_region_init_io(&s->io, OBJECT(dev), 1060 &serial_mm_ops[smm->endianness], smm, "serial", 1061 8 << smm->regshift); 1062 sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io); 1063 sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq); 1064 } 1065 1066 static const VMStateDescription vmstate_serial_mm = { 1067 .name = "serial", 1068 .version_id = 3, 1069 .minimum_version_id = 2, 1070 .fields = (VMStateField[]) { 1071 VMSTATE_STRUCT(serial, SerialMM, 0, vmstate_serial, SerialState), 1072 VMSTATE_END_OF_LIST() 1073 } 1074 }; 1075 1076 SerialMM *serial_mm_init(MemoryRegion *address_space, 1077 hwaddr base, int regshift, 1078 qemu_irq irq, int baudbase, 1079 Chardev *chr, enum device_endian end) 1080 { 1081 SerialMM *smm = SERIAL_MM(qdev_new(TYPE_SERIAL_MM)); 1082 MemoryRegion *mr; 1083 1084 qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift); 1085 qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase); 1086 qdev_prop_set_chr(DEVICE(smm), "chardev", chr); 1087 qdev_set_legacy_instance_id(DEVICE(smm), base, 2); 1088 qdev_prop_set_uint8(DEVICE(smm), "endianness", end); 1089 sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal); 1090 1091 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq); 1092 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0); 1093 memory_region_add_subregion(address_space, base, mr); 1094 1095 return smm; 1096 } 1097 1098 static void serial_mm_instance_init(Object *o) 1099 { 1100 SerialMM *smm = SERIAL_MM(o); 1101 1102 object_initialize_child(o, "serial", &smm->serial, TYPE_SERIAL); 1103 1104 qdev_alias_all_properties(DEVICE(&smm->serial), o); 1105 } 1106 1107 static Property serial_mm_properties[] = { 1108 /* 1109 * Set the spacing between adjacent memory-mapped UART registers. 1110 * Each register will be at (1 << regshift) bytes after the 1111 * previous one. 1112 */ 1113 DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0), 1114 DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN), 1115 DEFINE_PROP_END_OF_LIST(), 1116 }; 1117 1118 static void serial_mm_class_init(ObjectClass *oc, void *data) 1119 { 1120 DeviceClass *dc = DEVICE_CLASS(oc); 1121 1122 device_class_set_props(dc, serial_mm_properties); 1123 dc->realize = serial_mm_realize; 1124 dc->vmsd = &vmstate_serial_mm; 1125 } 1126 1127 static const TypeInfo serial_mm_info = { 1128 .name = TYPE_SERIAL_MM, 1129 .parent = TYPE_SYS_BUS_DEVICE, 1130 .class_init = serial_mm_class_init, 1131 .instance_init = serial_mm_instance_init, 1132 .instance_size = sizeof(SerialMM), 1133 .class_init = serial_mm_class_init, 1134 }; 1135 1136 static void serial_register_types(void) 1137 { 1138 type_register_static(&serial_info); 1139 type_register_static(&serial_mm_info); 1140 } 1141 1142 type_init(serial_register_types) 1143