1 /* 2 * QEMU model of Xilinx uartlite. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/sysbus.h" 28 #include "qemu/module.h" 29 #include "chardev/char-fe.h" 30 31 #define DUART(x) 32 33 #define R_RX 0 34 #define R_TX 1 35 #define R_STATUS 2 36 #define R_CTRL 3 37 #define R_MAX 4 38 39 #define STATUS_RXVALID 0x01 40 #define STATUS_RXFULL 0x02 41 #define STATUS_TXEMPTY 0x04 42 #define STATUS_TXFULL 0x08 43 #define STATUS_IE 0x10 44 #define STATUS_OVERRUN 0x20 45 #define STATUS_FRAME 0x40 46 #define STATUS_PARITY 0x80 47 48 #define CONTROL_RST_TX 0x01 49 #define CONTROL_RST_RX 0x02 50 #define CONTROL_IE 0x10 51 52 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" 53 #define XILINX_UARTLITE(obj) \ 54 OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE) 55 56 typedef struct XilinxUARTLite { 57 SysBusDevice parent_obj; 58 59 MemoryRegion mmio; 60 CharBackend chr; 61 qemu_irq irq; 62 63 uint8_t rx_fifo[8]; 64 unsigned int rx_fifo_pos; 65 unsigned int rx_fifo_len; 66 67 uint32_t regs[R_MAX]; 68 } XilinxUARTLite; 69 70 static void uart_update_irq(XilinxUARTLite *s) 71 { 72 unsigned int irq; 73 74 if (s->rx_fifo_len) 75 s->regs[R_STATUS] |= STATUS_IE; 76 77 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); 78 qemu_set_irq(s->irq, irq); 79 } 80 81 static void uart_update_status(XilinxUARTLite *s) 82 { 83 uint32_t r; 84 85 r = s->regs[R_STATUS]; 86 r &= ~7; 87 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */ 88 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; 89 r |= (!!s->rx_fifo_len); 90 s->regs[R_STATUS] = r; 91 } 92 93 static void xilinx_uartlite_reset(DeviceState *dev) 94 { 95 uart_update_status(XILINX_UARTLITE(dev)); 96 } 97 98 static uint64_t 99 uart_read(void *opaque, hwaddr addr, unsigned int size) 100 { 101 XilinxUARTLite *s = opaque; 102 uint32_t r = 0; 103 addr >>= 2; 104 switch (addr) 105 { 106 case R_RX: 107 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; 108 if (s->rx_fifo_len) 109 s->rx_fifo_len--; 110 uart_update_status(s); 111 uart_update_irq(s); 112 qemu_chr_fe_accept_input(&s->chr); 113 break; 114 115 default: 116 if (addr < ARRAY_SIZE(s->regs)) 117 r = s->regs[addr]; 118 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r)); 119 break; 120 } 121 return r; 122 } 123 124 static void 125 uart_write(void *opaque, hwaddr addr, 126 uint64_t val64, unsigned int size) 127 { 128 XilinxUARTLite *s = opaque; 129 uint32_t value = val64; 130 unsigned char ch = value; 131 132 addr >>= 2; 133 switch (addr) 134 { 135 case R_STATUS: 136 hw_error("write to UART STATUS?\n"); 137 break; 138 139 case R_CTRL: 140 if (value & CONTROL_RST_RX) { 141 s->rx_fifo_pos = 0; 142 s->rx_fifo_len = 0; 143 } 144 s->regs[addr] = value; 145 break; 146 147 case R_TX: 148 /* XXX this blocks entire thread. Rewrite to use 149 * qemu_chr_fe_write and background I/O callbacks */ 150 qemu_chr_fe_write_all(&s->chr, &ch, 1); 151 s->regs[addr] = value; 152 153 /* hax. */ 154 s->regs[R_STATUS] |= STATUS_IE; 155 break; 156 157 default: 158 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value)); 159 if (addr < ARRAY_SIZE(s->regs)) 160 s->regs[addr] = value; 161 break; 162 } 163 uart_update_status(s); 164 uart_update_irq(s); 165 } 166 167 static const MemoryRegionOps uart_ops = { 168 .read = uart_read, 169 .write = uart_write, 170 .endianness = DEVICE_NATIVE_ENDIAN, 171 .valid = { 172 .min_access_size = 1, 173 .max_access_size = 4 174 } 175 }; 176 177 static Property xilinx_uartlite_properties[] = { 178 DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), 179 DEFINE_PROP_END_OF_LIST(), 180 }; 181 182 static void uart_rx(void *opaque, const uint8_t *buf, int size) 183 { 184 XilinxUARTLite *s = opaque; 185 186 /* Got a byte. */ 187 if (s->rx_fifo_len >= 8) { 188 printf("WARNING: UART dropped char.\n"); 189 return; 190 } 191 s->rx_fifo[s->rx_fifo_pos] = *buf; 192 s->rx_fifo_pos++; 193 s->rx_fifo_pos &= 0x7; 194 s->rx_fifo_len++; 195 196 uart_update_status(s); 197 uart_update_irq(s); 198 } 199 200 static int uart_can_rx(void *opaque) 201 { 202 XilinxUARTLite *s = opaque; 203 204 return s->rx_fifo_len < sizeof(s->rx_fifo); 205 } 206 207 static void uart_event(void *opaque, int event) 208 { 209 210 } 211 212 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) 213 { 214 XilinxUARTLite *s = XILINX_UARTLITE(dev); 215 216 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, 217 uart_event, NULL, s, NULL, true); 218 } 219 220 static void xilinx_uartlite_init(Object *obj) 221 { 222 XilinxUARTLite *s = XILINX_UARTLITE(obj); 223 224 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 225 226 memory_region_init_io(&s->mmio, obj, &uart_ops, s, 227 "xlnx.xps-uartlite", R_MAX * 4); 228 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 229 } 230 231 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) 232 { 233 DeviceClass *dc = DEVICE_CLASS(klass); 234 235 dc->reset = xilinx_uartlite_reset; 236 dc->realize = xilinx_uartlite_realize; 237 dc->props = xilinx_uartlite_properties; 238 } 239 240 static const TypeInfo xilinx_uartlite_info = { 241 .name = TYPE_XILINX_UARTLITE, 242 .parent = TYPE_SYS_BUS_DEVICE, 243 .instance_size = sizeof(XilinxUARTLite), 244 .instance_init = xilinx_uartlite_init, 245 .class_init = xilinx_uartlite_class_init, 246 }; 247 248 static void xilinx_uart_register_types(void) 249 { 250 type_register_static(&xilinx_uartlite_info); 251 } 252 253 type_init(xilinx_uart_register_types) 254