xref: /qemu/hw/core/machine.c (revision 0572f558)
1 /*
2  * QEMU Machine
3  *
4  * Copyright (C) 2014 Red Hat Inc
5  *
6  * Authors:
7  *   Marcel Apfelbaum <marcel.a@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qemu/option.h"
15 #include "qapi/qmp/qerror.h"
16 #include "sysemu/replay.h"
17 #include "qemu/units.h"
18 #include "hw/boards.h"
19 #include "hw/loader.h"
20 #include "qapi/error.h"
21 #include "qapi/qapi-visit-common.h"
22 #include "qapi/visitor.h"
23 #include "hw/sysbus.h"
24 #include "sysemu/cpus.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/numa.h"
29 #include "qemu/error-report.h"
30 #include "sysemu/qtest.h"
31 #include "hw/pci/pci.h"
32 #include "hw/mem/nvdimm.h"
33 #include "migration/global_state.h"
34 #include "migration/vmstate.h"
35 
36 GlobalProperty hw_compat_5_2[] = {};
37 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
38 
39 GlobalProperty hw_compat_5_1[] = {
40     { "vhost-scsi", "num_queues", "1"},
41     { "vhost-user-blk", "num-queues", "1"},
42     { "vhost-user-scsi", "num_queues", "1"},
43     { "virtio-blk-device", "num-queues", "1"},
44     { "virtio-scsi-device", "num_queues", "1"},
45     { "nvme", "use-intel-id", "on"},
46     { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
47 };
48 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
49 
50 GlobalProperty hw_compat_5_0[] = {
51     { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
52     { "virtio-balloon-device", "page-poison", "false" },
53     { "vmport", "x-read-set-eax", "off" },
54     { "vmport", "x-signal-unsupported-cmd", "off" },
55     { "vmport", "x-report-vmx-type", "off" },
56     { "vmport", "x-cmds-v2", "off" },
57     { "virtio-device", "x-disable-legacy-check", "true" },
58 };
59 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
60 
61 GlobalProperty hw_compat_4_2[] = {
62     { "virtio-blk-device", "queue-size", "128"},
63     { "virtio-scsi-device", "virtqueue_size", "128"},
64     { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
65     { "virtio-blk-device", "seg-max-adjust", "off"},
66     { "virtio-scsi-device", "seg_max_adjust", "off"},
67     { "vhost-blk-device", "seg_max_adjust", "off"},
68     { "usb-host", "suppress-remote-wake", "off" },
69     { "usb-redir", "suppress-remote-wake", "off" },
70     { "qxl", "revision", "4" },
71     { "qxl-vga", "revision", "4" },
72     { "fw_cfg", "acpi-mr-restore", "false" },
73 };
74 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
75 
76 GlobalProperty hw_compat_4_1[] = {
77     { "virtio-pci", "x-pcie-flr-init", "off" },
78     { "virtio-device", "use-disabled-flag", "false" },
79 };
80 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
81 
82 GlobalProperty hw_compat_4_0[] = {
83     { "VGA",            "edid", "false" },
84     { "secondary-vga",  "edid", "false" },
85     { "bochs-display",  "edid", "false" },
86     { "virtio-vga",     "edid", "false" },
87     { "virtio-gpu-device", "edid", "false" },
88     { "virtio-device", "use-started", "false" },
89     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
90     { "pl031", "migrate-tick-offset", "false" },
91 };
92 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
93 
94 GlobalProperty hw_compat_3_1[] = {
95     { "pcie-root-port", "x-speed", "2_5" },
96     { "pcie-root-port", "x-width", "1" },
97     { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
98     { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
99     { "tpm-crb", "ppi", "false" },
100     { "tpm-tis", "ppi", "false" },
101     { "usb-kbd", "serial", "42" },
102     { "usb-mouse", "serial", "42" },
103     { "usb-tablet", "serial", "42" },
104     { "virtio-blk-device", "discard", "false" },
105     { "virtio-blk-device", "write-zeroes", "false" },
106     { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
107     { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
108 };
109 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
110 
111 GlobalProperty hw_compat_3_0[] = {};
112 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
113 
114 GlobalProperty hw_compat_2_12[] = {
115     { "migration", "decompress-error-check", "off" },
116     { "hda-audio", "use-timer", "false" },
117     { "cirrus-vga", "global-vmstate", "true" },
118     { "VGA", "global-vmstate", "true" },
119     { "vmware-svga", "global-vmstate", "true" },
120     { "qxl-vga", "global-vmstate", "true" },
121 };
122 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
123 
124 GlobalProperty hw_compat_2_11[] = {
125     { "hpet", "hpet-offset-saved", "false" },
126     { "virtio-blk-pci", "vectors", "2" },
127     { "vhost-user-blk-pci", "vectors", "2" },
128     { "e1000", "migrate_tso_props", "off" },
129 };
130 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
131 
132 GlobalProperty hw_compat_2_10[] = {
133     { "virtio-mouse-device", "wheel-axis", "false" },
134     { "virtio-tablet-device", "wheel-axis", "false" },
135 };
136 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
137 
138 GlobalProperty hw_compat_2_9[] = {
139     { "pci-bridge", "shpc", "off" },
140     { "intel-iommu", "pt", "off" },
141     { "virtio-net-device", "x-mtu-bypass-backend", "off" },
142     { "pcie-root-port", "x-migrate-msix", "false" },
143 };
144 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
145 
146 GlobalProperty hw_compat_2_8[] = {
147     { "fw_cfg_mem", "x-file-slots", "0x10" },
148     { "fw_cfg_io", "x-file-slots", "0x10" },
149     { "pflash_cfi01", "old-multiple-chip-handling", "on" },
150     { "pci-bridge", "shpc", "on" },
151     { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
152     { "virtio-pci", "x-pcie-deverr-init", "off" },
153     { "virtio-pci", "x-pcie-lnkctl-init", "off" },
154     { "virtio-pci", "x-pcie-pm-init", "off" },
155     { "cirrus-vga", "vgamem_mb", "8" },
156     { "isa-cirrus-vga", "vgamem_mb", "8" },
157 };
158 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
159 
160 GlobalProperty hw_compat_2_7[] = {
161     { "virtio-pci", "page-per-vq", "on" },
162     { "virtio-serial-device", "emergency-write", "off" },
163     { "ioapic", "version", "0x11" },
164     { "intel-iommu", "x-buggy-eim", "true" },
165     { "virtio-pci", "x-ignore-backend-features", "on" },
166 };
167 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
168 
169 GlobalProperty hw_compat_2_6[] = {
170     { "virtio-mmio", "format_transport_address", "off" },
171     /* Optional because not all virtio-pci devices support legacy mode */
172     { "virtio-pci", "disable-modern", "on",  .optional = true },
173     { "virtio-pci", "disable-legacy", "off", .optional = true },
174 };
175 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
176 
177 GlobalProperty hw_compat_2_5[] = {
178     { "isa-fdc", "fallback", "144" },
179     { "pvscsi", "x-old-pci-configuration", "on" },
180     { "pvscsi", "x-disable-pcie", "on" },
181     { "vmxnet3", "x-old-msi-offsets", "on" },
182     { "vmxnet3", "x-disable-pcie", "on" },
183 };
184 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
185 
186 GlobalProperty hw_compat_2_4[] = {
187     /* Optional because the 'scsi' property is Linux-only */
188     { "virtio-blk-device", "scsi", "true", .optional = true },
189     { "e1000", "extra_mac_registers", "off" },
190     { "virtio-pci", "x-disable-pcie", "on" },
191     { "virtio-pci", "migrate-extra", "off" },
192     { "fw_cfg_mem", "dma_enabled", "off" },
193     { "fw_cfg_io", "dma_enabled", "off" }
194 };
195 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
196 
197 GlobalProperty hw_compat_2_3[] = {
198     { "virtio-blk-pci", "any_layout", "off" },
199     { "virtio-balloon-pci", "any_layout", "off" },
200     { "virtio-serial-pci", "any_layout", "off" },
201     { "virtio-9p-pci", "any_layout", "off" },
202     { "virtio-rng-pci", "any_layout", "off" },
203     { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
204     { "migration", "send-configuration", "off" },
205     { "migration", "send-section-footer", "off" },
206     { "migration", "store-global-state", "off" },
207 };
208 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
209 
210 GlobalProperty hw_compat_2_2[] = {};
211 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
212 
213 GlobalProperty hw_compat_2_1[] = {
214     { "intel-hda", "old_msi_addr", "on" },
215     { "VGA", "qemu-extended-regs", "off" },
216     { "secondary-vga", "qemu-extended-regs", "off" },
217     { "virtio-scsi-pci", "any_layout", "off" },
218     { "usb-mouse", "usb_version", "1" },
219     { "usb-kbd", "usb_version", "1" },
220     { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
221 };
222 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
223 
224 MachineState *current_machine;
225 
226 static char *machine_get_kernel(Object *obj, Error **errp)
227 {
228     MachineState *ms = MACHINE(obj);
229 
230     return g_strdup(ms->kernel_filename);
231 }
232 
233 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
234 {
235     MachineState *ms = MACHINE(obj);
236 
237     g_free(ms->kernel_filename);
238     ms->kernel_filename = g_strdup(value);
239 }
240 
241 static char *machine_get_initrd(Object *obj, Error **errp)
242 {
243     MachineState *ms = MACHINE(obj);
244 
245     return g_strdup(ms->initrd_filename);
246 }
247 
248 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
249 {
250     MachineState *ms = MACHINE(obj);
251 
252     g_free(ms->initrd_filename);
253     ms->initrd_filename = g_strdup(value);
254 }
255 
256 static char *machine_get_append(Object *obj, Error **errp)
257 {
258     MachineState *ms = MACHINE(obj);
259 
260     return g_strdup(ms->kernel_cmdline);
261 }
262 
263 static void machine_set_append(Object *obj, const char *value, Error **errp)
264 {
265     MachineState *ms = MACHINE(obj);
266 
267     g_free(ms->kernel_cmdline);
268     ms->kernel_cmdline = g_strdup(value);
269 }
270 
271 static char *machine_get_dtb(Object *obj, Error **errp)
272 {
273     MachineState *ms = MACHINE(obj);
274 
275     return g_strdup(ms->dtb);
276 }
277 
278 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
279 {
280     MachineState *ms = MACHINE(obj);
281 
282     g_free(ms->dtb);
283     ms->dtb = g_strdup(value);
284 }
285 
286 static char *machine_get_dumpdtb(Object *obj, Error **errp)
287 {
288     MachineState *ms = MACHINE(obj);
289 
290     return g_strdup(ms->dumpdtb);
291 }
292 
293 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
294 {
295     MachineState *ms = MACHINE(obj);
296 
297     g_free(ms->dumpdtb);
298     ms->dumpdtb = g_strdup(value);
299 }
300 
301 static void machine_get_phandle_start(Object *obj, Visitor *v,
302                                       const char *name, void *opaque,
303                                       Error **errp)
304 {
305     MachineState *ms = MACHINE(obj);
306     int64_t value = ms->phandle_start;
307 
308     visit_type_int(v, name, &value, errp);
309 }
310 
311 static void machine_set_phandle_start(Object *obj, Visitor *v,
312                                       const char *name, void *opaque,
313                                       Error **errp)
314 {
315     MachineState *ms = MACHINE(obj);
316     int64_t value;
317 
318     if (!visit_type_int(v, name, &value, errp)) {
319         return;
320     }
321 
322     ms->phandle_start = value;
323 }
324 
325 static char *machine_get_dt_compatible(Object *obj, Error **errp)
326 {
327     MachineState *ms = MACHINE(obj);
328 
329     return g_strdup(ms->dt_compatible);
330 }
331 
332 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
333 {
334     MachineState *ms = MACHINE(obj);
335 
336     g_free(ms->dt_compatible);
337     ms->dt_compatible = g_strdup(value);
338 }
339 
340 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
341 {
342     MachineState *ms = MACHINE(obj);
343 
344     return ms->dump_guest_core;
345 }
346 
347 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
348 {
349     MachineState *ms = MACHINE(obj);
350 
351     ms->dump_guest_core = value;
352 }
353 
354 static bool machine_get_mem_merge(Object *obj, Error **errp)
355 {
356     MachineState *ms = MACHINE(obj);
357 
358     return ms->mem_merge;
359 }
360 
361 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
362 {
363     MachineState *ms = MACHINE(obj);
364 
365     ms->mem_merge = value;
366 }
367 
368 static bool machine_get_usb(Object *obj, Error **errp)
369 {
370     MachineState *ms = MACHINE(obj);
371 
372     return ms->usb;
373 }
374 
375 static void machine_set_usb(Object *obj, bool value, Error **errp)
376 {
377     MachineState *ms = MACHINE(obj);
378 
379     ms->usb = value;
380     ms->usb_disabled = !value;
381 }
382 
383 static bool machine_get_graphics(Object *obj, Error **errp)
384 {
385     MachineState *ms = MACHINE(obj);
386 
387     return ms->enable_graphics;
388 }
389 
390 static void machine_set_graphics(Object *obj, bool value, Error **errp)
391 {
392     MachineState *ms = MACHINE(obj);
393 
394     ms->enable_graphics = value;
395 }
396 
397 static char *machine_get_firmware(Object *obj, Error **errp)
398 {
399     MachineState *ms = MACHINE(obj);
400 
401     return g_strdup(ms->firmware);
402 }
403 
404 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
405 {
406     MachineState *ms = MACHINE(obj);
407 
408     g_free(ms->firmware);
409     ms->firmware = g_strdup(value);
410 }
411 
412 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
413 {
414     MachineState *ms = MACHINE(obj);
415 
416     ms->suppress_vmdesc = value;
417 }
418 
419 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
420 {
421     MachineState *ms = MACHINE(obj);
422 
423     return ms->suppress_vmdesc;
424 }
425 
426 static char *machine_get_memory_encryption(Object *obj, Error **errp)
427 {
428     MachineState *ms = MACHINE(obj);
429 
430     return g_strdup(ms->memory_encryption);
431 }
432 
433 static void machine_set_memory_encryption(Object *obj, const char *value,
434                                         Error **errp)
435 {
436     MachineState *ms = MACHINE(obj);
437 
438     g_free(ms->memory_encryption);
439     ms->memory_encryption = g_strdup(value);
440 
441     /*
442      * With memory encryption, the host can't see the real contents of RAM,
443      * so there's no point in it trying to merge areas.
444      */
445     if (value) {
446         machine_set_mem_merge(obj, false, errp);
447     }
448 }
449 
450 static bool machine_get_nvdimm(Object *obj, Error **errp)
451 {
452     MachineState *ms = MACHINE(obj);
453 
454     return ms->nvdimms_state->is_enabled;
455 }
456 
457 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
458 {
459     MachineState *ms = MACHINE(obj);
460 
461     ms->nvdimms_state->is_enabled = value;
462 }
463 
464 static bool machine_get_hmat(Object *obj, Error **errp)
465 {
466     MachineState *ms = MACHINE(obj);
467 
468     return ms->numa_state->hmat_enabled;
469 }
470 
471 static void machine_set_hmat(Object *obj, bool value, Error **errp)
472 {
473     MachineState *ms = MACHINE(obj);
474 
475     ms->numa_state->hmat_enabled = value;
476 }
477 
478 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
479 {
480     MachineState *ms = MACHINE(obj);
481 
482     return g_strdup(ms->nvdimms_state->persistence_string);
483 }
484 
485 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
486                                            Error **errp)
487 {
488     MachineState *ms = MACHINE(obj);
489     NVDIMMState *nvdimms_state = ms->nvdimms_state;
490 
491     if (strcmp(value, "cpu") == 0) {
492         nvdimms_state->persistence = 3;
493     } else if (strcmp(value, "mem-ctrl") == 0) {
494         nvdimms_state->persistence = 2;
495     } else {
496         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
497                    value);
498         return;
499     }
500 
501     g_free(nvdimms_state->persistence_string);
502     nvdimms_state->persistence_string = g_strdup(value);
503 }
504 
505 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
506 {
507     strList *item = g_new0(strList, 1);
508 
509     item->value = g_strdup(type);
510     item->next = mc->allowed_dynamic_sysbus_devices;
511     mc->allowed_dynamic_sysbus_devices = item;
512 }
513 
514 static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque)
515 {
516     MachineState *machine = opaque;
517     MachineClass *mc = MACHINE_GET_CLASS(machine);
518     bool allowed = false;
519     strList *wl;
520 
521     for (wl = mc->allowed_dynamic_sysbus_devices;
522          !allowed && wl;
523          wl = wl->next) {
524         allowed |= !!object_dynamic_cast(OBJECT(sbdev), wl->value);
525     }
526 
527     if (!allowed) {
528         error_report("Option '-device %s' cannot be handled by this machine",
529                      object_class_get_name(object_get_class(OBJECT(sbdev))));
530         exit(1);
531     }
532 }
533 
534 static char *machine_get_memdev(Object *obj, Error **errp)
535 {
536     MachineState *ms = MACHINE(obj);
537 
538     return g_strdup(ms->ram_memdev_id);
539 }
540 
541 static void machine_set_memdev(Object *obj, const char *value, Error **errp)
542 {
543     MachineState *ms = MACHINE(obj);
544 
545     g_free(ms->ram_memdev_id);
546     ms->ram_memdev_id = g_strdup(value);
547 }
548 
549 
550 static void machine_init_notify(Notifier *notifier, void *data)
551 {
552     MachineState *machine = MACHINE(qdev_get_machine());
553 
554     /*
555      * Loop through all dynamically created sysbus devices and check if they are
556      * all allowed.  If a device is not allowed, error out.
557      */
558     foreach_dynamic_sysbus_device(validate_sysbus_device, machine);
559 }
560 
561 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
562 {
563     int i;
564     HotpluggableCPUList *head = NULL;
565     MachineClass *mc = MACHINE_GET_CLASS(machine);
566 
567     /* force board to initialize possible_cpus if it hasn't been done yet */
568     mc->possible_cpu_arch_ids(machine);
569 
570     for (i = 0; i < machine->possible_cpus->len; i++) {
571         Object *cpu;
572         HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
573         HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
574 
575         cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
576         cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
577         cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
578                                    sizeof(*cpu_item->props));
579 
580         cpu = machine->possible_cpus->cpus[i].cpu;
581         if (cpu) {
582             cpu_item->has_qom_path = true;
583             cpu_item->qom_path = object_get_canonical_path(cpu);
584         }
585         list_item->value = cpu_item;
586         list_item->next = head;
587         head = list_item;
588     }
589     return head;
590 }
591 
592 /**
593  * machine_set_cpu_numa_node:
594  * @machine: machine object to modify
595  * @props: specifies which cpu objects to assign to
596  *         numa node specified by @props.node_id
597  * @errp: if an error occurs, a pointer to an area to store the error
598  *
599  * Associate NUMA node specified by @props.node_id with cpu slots that
600  * match socket/core/thread-ids specified by @props. It's recommended to use
601  * query-hotpluggable-cpus.props values to specify affected cpu slots,
602  * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
603  *
604  * However for CLI convenience it's possible to pass in subset of properties,
605  * which would affect all cpu slots that match it.
606  * Ex for pc machine:
607  *    -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
608  *    -numa cpu,node-id=0,socket_id=0 \
609  *    -numa cpu,node-id=1,socket_id=1
610  * will assign all child cores of socket 0 to node 0 and
611  * of socket 1 to node 1.
612  *
613  * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
614  * return error.
615  * Empty subset is disallowed and function will return with error in this case.
616  */
617 void machine_set_cpu_numa_node(MachineState *machine,
618                                const CpuInstanceProperties *props, Error **errp)
619 {
620     MachineClass *mc = MACHINE_GET_CLASS(machine);
621     NodeInfo *numa_info = machine->numa_state->nodes;
622     bool match = false;
623     int i;
624 
625     if (!mc->possible_cpu_arch_ids) {
626         error_setg(errp, "mapping of CPUs to NUMA node is not supported");
627         return;
628     }
629 
630     /* disabling node mapping is not supported, forbid it */
631     assert(props->has_node_id);
632 
633     /* force board to initialize possible_cpus if it hasn't been done yet */
634     mc->possible_cpu_arch_ids(machine);
635 
636     for (i = 0; i < machine->possible_cpus->len; i++) {
637         CPUArchId *slot = &machine->possible_cpus->cpus[i];
638 
639         /* reject unsupported by board properties */
640         if (props->has_thread_id && !slot->props.has_thread_id) {
641             error_setg(errp, "thread-id is not supported");
642             return;
643         }
644 
645         if (props->has_core_id && !slot->props.has_core_id) {
646             error_setg(errp, "core-id is not supported");
647             return;
648         }
649 
650         if (props->has_socket_id && !slot->props.has_socket_id) {
651             error_setg(errp, "socket-id is not supported");
652             return;
653         }
654 
655         if (props->has_die_id && !slot->props.has_die_id) {
656             error_setg(errp, "die-id is not supported");
657             return;
658         }
659 
660         /* skip slots with explicit mismatch */
661         if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
662                 continue;
663         }
664 
665         if (props->has_core_id && props->core_id != slot->props.core_id) {
666                 continue;
667         }
668 
669         if (props->has_die_id && props->die_id != slot->props.die_id) {
670                 continue;
671         }
672 
673         if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
674                 continue;
675         }
676 
677         /* reject assignment if slot is already assigned, for compatibility
678          * of legacy cpu_index mapping with SPAPR core based mapping do not
679          * error out if cpu thread and matched core have the same node-id */
680         if (slot->props.has_node_id &&
681             slot->props.node_id != props->node_id) {
682             error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
683                        slot->props.node_id);
684             return;
685         }
686 
687         /* assign slot to node as it's matched '-numa cpu' key */
688         match = true;
689         slot->props.node_id = props->node_id;
690         slot->props.has_node_id = props->has_node_id;
691 
692         if (machine->numa_state->hmat_enabled) {
693             if ((numa_info[props->node_id].initiator < MAX_NODES) &&
694                 (props->node_id != numa_info[props->node_id].initiator)) {
695                 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
696                         " should be itself", props->node_id);
697                 return;
698             }
699             numa_info[props->node_id].has_cpu = true;
700             numa_info[props->node_id].initiator = props->node_id;
701         }
702     }
703 
704     if (!match) {
705         error_setg(errp, "no match found");
706     }
707 }
708 
709 static void smp_parse(MachineState *ms, QemuOpts *opts)
710 {
711     if (opts) {
712         unsigned cpus    = qemu_opt_get_number(opts, "cpus", 0);
713         unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
714         unsigned cores   = qemu_opt_get_number(opts, "cores", 0);
715         unsigned threads = qemu_opt_get_number(opts, "threads", 0);
716 
717         /* compute missing values, prefer sockets over cores over threads */
718         if (cpus == 0 || sockets == 0) {
719             cores = cores > 0 ? cores : 1;
720             threads = threads > 0 ? threads : 1;
721             if (cpus == 0) {
722                 sockets = sockets > 0 ? sockets : 1;
723                 cpus = cores * threads * sockets;
724             } else {
725                 ms->smp.max_cpus =
726                         qemu_opt_get_number(opts, "maxcpus", cpus);
727                 sockets = ms->smp.max_cpus / (cores * threads);
728             }
729         } else if (cores == 0) {
730             threads = threads > 0 ? threads : 1;
731             cores = cpus / (sockets * threads);
732             cores = cores > 0 ? cores : 1;
733         } else if (threads == 0) {
734             threads = cpus / (cores * sockets);
735             threads = threads > 0 ? threads : 1;
736         } else if (sockets * cores * threads < cpus) {
737             error_report("cpu topology: "
738                          "sockets (%u) * cores (%u) * threads (%u) < "
739                          "smp_cpus (%u)",
740                          sockets, cores, threads, cpus);
741             exit(1);
742         }
743 
744         ms->smp.max_cpus =
745                 qemu_opt_get_number(opts, "maxcpus", cpus);
746 
747         if (ms->smp.max_cpus < cpus) {
748             error_report("maxcpus must be equal to or greater than smp");
749             exit(1);
750         }
751 
752         if (sockets * cores * threads != ms->smp.max_cpus) {
753             error_report("Invalid CPU topology: "
754                          "sockets (%u) * cores (%u) * threads (%u) "
755                          "!= maxcpus (%u)",
756                          sockets, cores, threads,
757                          ms->smp.max_cpus);
758             exit(1);
759         }
760 
761         ms->smp.cpus = cpus;
762         ms->smp.cores = cores;
763         ms->smp.threads = threads;
764         ms->smp.sockets = sockets;
765     }
766 
767     if (ms->smp.cpus > 1) {
768         Error *blocker = NULL;
769         error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
770         replay_add_blocker(blocker);
771     }
772 }
773 
774 static void machine_class_init(ObjectClass *oc, void *data)
775 {
776     MachineClass *mc = MACHINE_CLASS(oc);
777 
778     /* Default 128 MB as guest ram size */
779     mc->default_ram_size = 128 * MiB;
780     mc->rom_file_has_mr = true;
781     mc->smp_parse = smp_parse;
782 
783     /* numa node memory size aligned on 8MB by default.
784      * On Linux, each node's border has to be 8MB aligned
785      */
786     mc->numa_mem_align_shift = 23;
787 
788     object_class_property_add_str(oc, "kernel",
789         machine_get_kernel, machine_set_kernel);
790     object_class_property_set_description(oc, "kernel",
791         "Linux kernel image file");
792 
793     object_class_property_add_str(oc, "initrd",
794         machine_get_initrd, machine_set_initrd);
795     object_class_property_set_description(oc, "initrd",
796         "Linux initial ramdisk file");
797 
798     object_class_property_add_str(oc, "append",
799         machine_get_append, machine_set_append);
800     object_class_property_set_description(oc, "append",
801         "Linux kernel command line");
802 
803     object_class_property_add_str(oc, "dtb",
804         machine_get_dtb, machine_set_dtb);
805     object_class_property_set_description(oc, "dtb",
806         "Linux kernel device tree file");
807 
808     object_class_property_add_str(oc, "dumpdtb",
809         machine_get_dumpdtb, machine_set_dumpdtb);
810     object_class_property_set_description(oc, "dumpdtb",
811         "Dump current dtb to a file and quit");
812 
813     object_class_property_add(oc, "phandle-start", "int",
814         machine_get_phandle_start, machine_set_phandle_start,
815         NULL, NULL);
816     object_class_property_set_description(oc, "phandle-start",
817         "The first phandle ID we may generate dynamically");
818 
819     object_class_property_add_str(oc, "dt-compatible",
820         machine_get_dt_compatible, machine_set_dt_compatible);
821     object_class_property_set_description(oc, "dt-compatible",
822         "Overrides the \"compatible\" property of the dt root node");
823 
824     object_class_property_add_bool(oc, "dump-guest-core",
825         machine_get_dump_guest_core, machine_set_dump_guest_core);
826     object_class_property_set_description(oc, "dump-guest-core",
827         "Include guest memory in a core dump");
828 
829     object_class_property_add_bool(oc, "mem-merge",
830         machine_get_mem_merge, machine_set_mem_merge);
831     object_class_property_set_description(oc, "mem-merge",
832         "Enable/disable memory merge support");
833 
834     object_class_property_add_bool(oc, "usb",
835         machine_get_usb, machine_set_usb);
836     object_class_property_set_description(oc, "usb",
837         "Set on/off to enable/disable usb");
838 
839     object_class_property_add_bool(oc, "graphics",
840         machine_get_graphics, machine_set_graphics);
841     object_class_property_set_description(oc, "graphics",
842         "Set on/off to enable/disable graphics emulation");
843 
844     object_class_property_add_str(oc, "firmware",
845         machine_get_firmware, machine_set_firmware);
846     object_class_property_set_description(oc, "firmware",
847         "Firmware image");
848 
849     object_class_property_add_bool(oc, "suppress-vmdesc",
850         machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
851     object_class_property_set_description(oc, "suppress-vmdesc",
852         "Set on to disable self-describing migration");
853 
854     object_class_property_add_str(oc, "memory-encryption",
855         machine_get_memory_encryption, machine_set_memory_encryption);
856     object_class_property_set_description(oc, "memory-encryption",
857         "Set memory encryption object to use");
858 
859     object_class_property_add_str(oc, "memory-backend",
860                                   machine_get_memdev, machine_set_memdev);
861     object_class_property_set_description(oc, "memory-backend",
862                                           "Set RAM backend"
863                                           "Valid value is ID of hostmem based backend");
864 }
865 
866 static void machine_class_base_init(ObjectClass *oc, void *data)
867 {
868     MachineClass *mc = MACHINE_CLASS(oc);
869     mc->max_cpus = mc->max_cpus ?: 1;
870     mc->min_cpus = mc->min_cpus ?: 1;
871     mc->default_cpus = mc->default_cpus ?: 1;
872 
873     if (!object_class_is_abstract(oc)) {
874         const char *cname = object_class_get_name(oc);
875         assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
876         mc->name = g_strndup(cname,
877                             strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
878         mc->compat_props = g_ptr_array_new();
879     }
880 }
881 
882 static void machine_initfn(Object *obj)
883 {
884     MachineState *ms = MACHINE(obj);
885     MachineClass *mc = MACHINE_GET_CLASS(obj);
886 
887     container_get(obj, "/peripheral");
888     container_get(obj, "/peripheral-anon");
889 
890     ms->dump_guest_core = true;
891     ms->mem_merge = true;
892     ms->enable_graphics = true;
893     ms->kernel_cmdline = g_strdup("");
894 
895     if (mc->nvdimm_supported) {
896         Object *obj = OBJECT(ms);
897 
898         ms->nvdimms_state = g_new0(NVDIMMState, 1);
899         object_property_add_bool(obj, "nvdimm",
900                                  machine_get_nvdimm, machine_set_nvdimm);
901         object_property_set_description(obj, "nvdimm",
902                                         "Set on/off to enable/disable "
903                                         "NVDIMM instantiation");
904 
905         object_property_add_str(obj, "nvdimm-persistence",
906                                 machine_get_nvdimm_persistence,
907                                 machine_set_nvdimm_persistence);
908         object_property_set_description(obj, "nvdimm-persistence",
909                                         "Set NVDIMM persistence"
910                                         "Valid values are cpu, mem-ctrl");
911     }
912 
913     if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
914         ms->numa_state = g_new0(NumaState, 1);
915         object_property_add_bool(obj, "hmat",
916                                  machine_get_hmat, machine_set_hmat);
917         object_property_set_description(obj, "hmat",
918                                         "Set on/off to enable/disable "
919                                         "ACPI Heterogeneous Memory Attribute "
920                                         "Table (HMAT)");
921     }
922 
923     /* Register notifier when init is done for sysbus sanity checks */
924     ms->sysbus_notifier.notify = machine_init_notify;
925     qemu_add_machine_init_done_notifier(&ms->sysbus_notifier);
926 
927     /* default to mc->default_cpus */
928     ms->smp.cpus = mc->default_cpus;
929     ms->smp.max_cpus = mc->default_cpus;
930     ms->smp.cores = 1;
931     ms->smp.threads = 1;
932     ms->smp.sockets = 1;
933 }
934 
935 static void machine_finalize(Object *obj)
936 {
937     MachineState *ms = MACHINE(obj);
938 
939     g_free(ms->kernel_filename);
940     g_free(ms->initrd_filename);
941     g_free(ms->kernel_cmdline);
942     g_free(ms->dtb);
943     g_free(ms->dumpdtb);
944     g_free(ms->dt_compatible);
945     g_free(ms->firmware);
946     g_free(ms->device_memory);
947     g_free(ms->nvdimms_state);
948     g_free(ms->numa_state);
949 }
950 
951 bool machine_usb(MachineState *machine)
952 {
953     return machine->usb;
954 }
955 
956 int machine_phandle_start(MachineState *machine)
957 {
958     return machine->phandle_start;
959 }
960 
961 bool machine_dump_guest_core(MachineState *machine)
962 {
963     return machine->dump_guest_core;
964 }
965 
966 bool machine_mem_merge(MachineState *machine)
967 {
968     return machine->mem_merge;
969 }
970 
971 static char *cpu_slot_to_string(const CPUArchId *cpu)
972 {
973     GString *s = g_string_new(NULL);
974     if (cpu->props.has_socket_id) {
975         g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
976     }
977     if (cpu->props.has_die_id) {
978         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
979     }
980     if (cpu->props.has_core_id) {
981         if (s->len) {
982             g_string_append_printf(s, ", ");
983         }
984         g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
985     }
986     if (cpu->props.has_thread_id) {
987         if (s->len) {
988             g_string_append_printf(s, ", ");
989         }
990         g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
991     }
992     return g_string_free(s, false);
993 }
994 
995 static void numa_validate_initiator(NumaState *numa_state)
996 {
997     int i;
998     NodeInfo *numa_info = numa_state->nodes;
999 
1000     for (i = 0; i < numa_state->num_nodes; i++) {
1001         if (numa_info[i].initiator == MAX_NODES) {
1002             error_report("The initiator of NUMA node %d is missing, use "
1003                          "'-numa node,initiator' option to declare it", i);
1004             exit(1);
1005         }
1006 
1007         if (!numa_info[numa_info[i].initiator].present) {
1008             error_report("NUMA node %" PRIu16 " is missing, use "
1009                          "'-numa node' option to declare it first",
1010                          numa_info[i].initiator);
1011             exit(1);
1012         }
1013 
1014         if (!numa_info[numa_info[i].initiator].has_cpu) {
1015             error_report("The initiator of NUMA node %d is invalid", i);
1016             exit(1);
1017         }
1018     }
1019 }
1020 
1021 static void machine_numa_finish_cpu_init(MachineState *machine)
1022 {
1023     int i;
1024     bool default_mapping;
1025     GString *s = g_string_new(NULL);
1026     MachineClass *mc = MACHINE_GET_CLASS(machine);
1027     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1028 
1029     assert(machine->numa_state->num_nodes);
1030     for (i = 0; i < possible_cpus->len; i++) {
1031         if (possible_cpus->cpus[i].props.has_node_id) {
1032             break;
1033         }
1034     }
1035     default_mapping = (i == possible_cpus->len);
1036 
1037     for (i = 0; i < possible_cpus->len; i++) {
1038         const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1039 
1040         if (!cpu_slot->props.has_node_id) {
1041             /* fetch default mapping from board and enable it */
1042             CpuInstanceProperties props = cpu_slot->props;
1043 
1044             props.node_id = mc->get_default_cpu_node_id(machine, i);
1045             if (!default_mapping) {
1046                 /* record slots with not set mapping,
1047                  * TODO: make it hard error in future */
1048                 char *cpu_str = cpu_slot_to_string(cpu_slot);
1049                 g_string_append_printf(s, "%sCPU %d [%s]",
1050                                        s->len ? ", " : "", i, cpu_str);
1051                 g_free(cpu_str);
1052 
1053                 /* non mapped cpus used to fallback to node 0 */
1054                 props.node_id = 0;
1055             }
1056 
1057             props.has_node_id = true;
1058             machine_set_cpu_numa_node(machine, &props, &error_fatal);
1059         }
1060     }
1061 
1062     if (machine->numa_state->hmat_enabled) {
1063         numa_validate_initiator(machine->numa_state);
1064     }
1065 
1066     if (s->len && !qtest_enabled()) {
1067         warn_report("CPU(s) not present in any NUMA nodes: %s",
1068                     s->str);
1069         warn_report("All CPU(s) up to maxcpus should be described "
1070                     "in NUMA config, ability to start up with partial NUMA "
1071                     "mappings is obsoleted and will be removed in future");
1072     }
1073     g_string_free(s, true);
1074 }
1075 
1076 MemoryRegion *machine_consume_memdev(MachineState *machine,
1077                                      HostMemoryBackend *backend)
1078 {
1079     MemoryRegion *ret = host_memory_backend_get_memory(backend);
1080 
1081     if (memory_region_is_mapped(ret)) {
1082         error_report("memory backend %s can't be used multiple times.",
1083                      object_get_canonical_path_component(OBJECT(backend)));
1084         exit(EXIT_FAILURE);
1085     }
1086     host_memory_backend_set_mapped(backend, true);
1087     vmstate_register_ram_global(ret);
1088     return ret;
1089 }
1090 
1091 bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp)
1092 {
1093     MachineClass *mc = MACHINE_GET_CLASS(ms);
1094 
1095     mc->smp_parse(ms, opts);
1096 
1097     /* sanity-check smp_cpus and max_cpus against mc */
1098     if (ms->smp.cpus < mc->min_cpus) {
1099         error_setg(errp, "Invalid SMP CPUs %d. The min CPUs "
1100                    "supported by machine '%s' is %d",
1101                    ms->smp.cpus,
1102                    mc->name, mc->min_cpus);
1103         return false;
1104     } else if (ms->smp.max_cpus > mc->max_cpus) {
1105         error_setg(errp, "Invalid SMP CPUs %d. The max CPUs "
1106                    "supported by machine '%s' is %d",
1107                    current_machine->smp.max_cpus,
1108                    mc->name, mc->max_cpus);
1109         return false;
1110     }
1111     return true;
1112 }
1113 
1114 void machine_run_board_init(MachineState *machine)
1115 {
1116     MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1117     ObjectClass *oc = object_class_by_name(machine->cpu_type);
1118     CPUClass *cc;
1119 
1120     /* This checkpoint is required by replay to separate prior clock
1121        reading from the other reads, because timer polling functions query
1122        clock values from the log. */
1123     replay_checkpoint(CHECKPOINT_INIT);
1124 
1125     if (machine->ram_memdev_id) {
1126         Object *o;
1127         o = object_resolve_path_type(machine->ram_memdev_id,
1128                                      TYPE_MEMORY_BACKEND, NULL);
1129         machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o));
1130     }
1131 
1132     if (machine->numa_state) {
1133         numa_complete_configuration(machine);
1134         if (machine->numa_state->num_nodes) {
1135             machine_numa_finish_cpu_init(machine);
1136         }
1137     }
1138 
1139     /* If the machine supports the valid_cpu_types check and the user
1140      * specified a CPU with -cpu check here that the user CPU is supported.
1141      */
1142     if (machine_class->valid_cpu_types && machine->cpu_type) {
1143         int i;
1144 
1145         for (i = 0; machine_class->valid_cpu_types[i]; i++) {
1146             if (object_class_dynamic_cast(oc,
1147                                           machine_class->valid_cpu_types[i])) {
1148                 /* The user specificed CPU is in the valid field, we are
1149                  * good to go.
1150                  */
1151                 break;
1152             }
1153         }
1154 
1155         if (!machine_class->valid_cpu_types[i]) {
1156             /* The user specified CPU is not valid */
1157             error_report("Invalid CPU type: %s", machine->cpu_type);
1158             error_printf("The valid types are: %s",
1159                          machine_class->valid_cpu_types[0]);
1160             for (i = 1; machine_class->valid_cpu_types[i]; i++) {
1161                 error_printf(", %s", machine_class->valid_cpu_types[i]);
1162             }
1163             error_printf("\n");
1164 
1165             exit(1);
1166         }
1167     }
1168 
1169     /* Check if CPU type is deprecated and warn if so */
1170     cc = CPU_CLASS(oc);
1171     if (cc && cc->deprecation_note) {
1172         warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
1173                     cc->deprecation_note);
1174     }
1175 
1176     machine_class->init(machine);
1177     phase_advance(PHASE_MACHINE_INITIALIZED);
1178 }
1179 
1180 static NotifierList machine_init_done_notifiers =
1181     NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1182 
1183 void qemu_add_machine_init_done_notifier(Notifier *notify)
1184 {
1185     notifier_list_add(&machine_init_done_notifiers, notify);
1186     if (phase_check(PHASE_MACHINE_READY)) {
1187         notify->notify(notify, NULL);
1188     }
1189 }
1190 
1191 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1192 {
1193     notifier_remove(notify);
1194 }
1195 
1196 void qdev_machine_creation_done(void)
1197 {
1198     cpu_synchronize_all_post_init();
1199 
1200     if (current_machine->boot_once) {
1201         qemu_boot_set(current_machine->boot_once, &error_fatal);
1202         qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order));
1203     }
1204 
1205     /*
1206      * ok, initial machine setup is done, starting from now we can
1207      * only create hotpluggable devices
1208      */
1209     phase_advance(PHASE_MACHINE_READY);
1210     qdev_assert_realized_properly();
1211 
1212     /* TODO: once all bus devices are qdevified, this should be done
1213      * when bus is created by qdev.c */
1214     /*
1215      * TODO: If we had a main 'reset container' that the whole system
1216      * lived in, we could reset that using the multi-phase reset
1217      * APIs. For the moment, we just reset the sysbus, which will cause
1218      * all devices hanging off it (and all their child buses, recursively)
1219      * to be reset. Note that this will *not* reset any Device objects
1220      * which are not attached to some part of the qbus tree!
1221      */
1222     qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
1223 
1224     notifier_list_notify(&machine_init_done_notifiers, NULL);
1225 
1226     if (rom_check_and_register_reset() != 0) {
1227         error_report("rom check and register reset failed");
1228         exit(1);
1229     }
1230 
1231     replay_start();
1232 
1233     /* This checkpoint is required by replay to separate prior clock
1234        reading from the other reads, because timer polling functions query
1235        clock values from the log. */
1236     replay_checkpoint(CHECKPOINT_RESET);
1237     qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1238     register_global_state();
1239 }
1240 
1241 static const TypeInfo machine_info = {
1242     .name = TYPE_MACHINE,
1243     .parent = TYPE_OBJECT,
1244     .abstract = true,
1245     .class_size = sizeof(MachineClass),
1246     .class_init    = machine_class_init,
1247     .class_base_init = machine_class_base_init,
1248     .instance_size = sizeof(MachineState),
1249     .instance_init = machine_initfn,
1250     .instance_finalize = machine_finalize,
1251 };
1252 
1253 static void machine_register_types(void)
1254 {
1255     type_register_static(&machine_info);
1256 }
1257 
1258 type_init(machine_register_types)
1259