1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/accel.h" 15 #include "sysemu/replay.h" 16 #include "hw/boards.h" 17 #include "hw/loader.h" 18 #include "qapi/error.h" 19 #include "qapi/qapi-visit-machine.h" 20 #include "qom/object_interfaces.h" 21 #include "sysemu/cpus.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/reset.h" 24 #include "sysemu/runstate.h" 25 #include "sysemu/xen.h" 26 #include "sysemu/qtest.h" 27 #include "hw/mem/nvdimm.h" 28 #include "migration/global_state.h" 29 #include "exec/confidential-guest-support.h" 30 #include "hw/virtio/virtio-pci.h" 31 #include "hw/virtio/virtio-net.h" 32 33 GlobalProperty hw_compat_8_1[] = {}; 34 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 35 36 GlobalProperty hw_compat_8_0[] = { 37 { "migration", "multifd-flush-after-each-section", "on"}, 38 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 39 { TYPE_VIRTIO_NET, "host_uso", "off"}, 40 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 41 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 42 }; 43 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 44 45 GlobalProperty hw_compat_7_2[] = { 46 { "e1000e", "migrate-timadj", "off" }, 47 { "virtio-mem", "x-early-migration", "false" }, 48 { "migration", "x-preempt-pre-7-2", "true" }, 49 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 50 }; 51 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 52 53 GlobalProperty hw_compat_7_1[] = { 54 { "virtio-device", "queue_reset", "false" }, 55 { "virtio-rng-pci", "vectors", "0" }, 56 { "virtio-rng-pci-transitional", "vectors", "0" }, 57 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 58 }; 59 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 60 61 GlobalProperty hw_compat_7_0[] = { 62 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 63 { "nvme-ns", "eui64-default", "on"}, 64 }; 65 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 66 67 GlobalProperty hw_compat_6_2[] = { 68 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 69 }; 70 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 71 72 GlobalProperty hw_compat_6_1[] = { 73 { "vhost-user-vsock-device", "seqpacket", "off" }, 74 { "nvme-ns", "shared", "off" }, 75 }; 76 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 77 78 GlobalProperty hw_compat_6_0[] = { 79 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 80 { "i8042", "extended-state", "false"}, 81 { "nvme-ns", "eui64-default", "off"}, 82 { "e1000", "init-vet", "off" }, 83 { "e1000e", "init-vet", "off" }, 84 { "vhost-vsock-device", "seqpacket", "off" }, 85 }; 86 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 87 88 GlobalProperty hw_compat_5_2[] = { 89 { "ICH9-LPC", "smm-compat", "on"}, 90 { "PIIX4_PM", "smm-compat", "on"}, 91 { "virtio-blk-device", "report-discard-granularity", "off" }, 92 { "virtio-net-pci-base", "vectors", "3"}, 93 }; 94 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 95 96 GlobalProperty hw_compat_5_1[] = { 97 { "vhost-scsi", "num_queues", "1"}, 98 { "vhost-user-blk", "num-queues", "1"}, 99 { "vhost-user-scsi", "num_queues", "1"}, 100 { "virtio-blk-device", "num-queues", "1"}, 101 { "virtio-scsi-device", "num_queues", "1"}, 102 { "nvme", "use-intel-id", "on"}, 103 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 104 { "pl011", "migrate-clk", "off" }, 105 { "virtio-pci", "x-ats-page-aligned", "off"}, 106 }; 107 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 108 109 GlobalProperty hw_compat_5_0[] = { 110 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 111 { "virtio-balloon-device", "page-poison", "false" }, 112 { "vmport", "x-read-set-eax", "off" }, 113 { "vmport", "x-signal-unsupported-cmd", "off" }, 114 { "vmport", "x-report-vmx-type", "off" }, 115 { "vmport", "x-cmds-v2", "off" }, 116 { "virtio-device", "x-disable-legacy-check", "true" }, 117 }; 118 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 119 120 GlobalProperty hw_compat_4_2[] = { 121 { "virtio-blk-device", "queue-size", "128"}, 122 { "virtio-scsi-device", "virtqueue_size", "128"}, 123 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 124 { "virtio-blk-device", "seg-max-adjust", "off"}, 125 { "virtio-scsi-device", "seg_max_adjust", "off"}, 126 { "vhost-blk-device", "seg_max_adjust", "off"}, 127 { "usb-host", "suppress-remote-wake", "off" }, 128 { "usb-redir", "suppress-remote-wake", "off" }, 129 { "qxl", "revision", "4" }, 130 { "qxl-vga", "revision", "4" }, 131 { "fw_cfg", "acpi-mr-restore", "false" }, 132 { "virtio-device", "use-disabled-flag", "false" }, 133 }; 134 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 135 136 GlobalProperty hw_compat_4_1[] = { 137 { "virtio-pci", "x-pcie-flr-init", "off" }, 138 }; 139 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 140 141 GlobalProperty hw_compat_4_0[] = { 142 { "VGA", "edid", "false" }, 143 { "secondary-vga", "edid", "false" }, 144 { "bochs-display", "edid", "false" }, 145 { "virtio-vga", "edid", "false" }, 146 { "virtio-gpu-device", "edid", "false" }, 147 { "virtio-device", "use-started", "false" }, 148 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 149 { "pl031", "migrate-tick-offset", "false" }, 150 }; 151 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 152 153 GlobalProperty hw_compat_3_1[] = { 154 { "pcie-root-port", "x-speed", "2_5" }, 155 { "pcie-root-port", "x-width", "1" }, 156 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 157 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 158 { "tpm-crb", "ppi", "false" }, 159 { "tpm-tis", "ppi", "false" }, 160 { "usb-kbd", "serial", "42" }, 161 { "usb-mouse", "serial", "42" }, 162 { "usb-tablet", "serial", "42" }, 163 { "virtio-blk-device", "discard", "false" }, 164 { "virtio-blk-device", "write-zeroes", "false" }, 165 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 166 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 167 }; 168 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 169 170 GlobalProperty hw_compat_3_0[] = {}; 171 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 172 173 GlobalProperty hw_compat_2_12[] = { 174 { "migration", "decompress-error-check", "off" }, 175 { "hda-audio", "use-timer", "false" }, 176 { "cirrus-vga", "global-vmstate", "true" }, 177 { "VGA", "global-vmstate", "true" }, 178 { "vmware-svga", "global-vmstate", "true" }, 179 { "qxl-vga", "global-vmstate", "true" }, 180 }; 181 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 182 183 GlobalProperty hw_compat_2_11[] = { 184 { "hpet", "hpet-offset-saved", "false" }, 185 { "virtio-blk-pci", "vectors", "2" }, 186 { "vhost-user-blk-pci", "vectors", "2" }, 187 { "e1000", "migrate_tso_props", "off" }, 188 }; 189 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 190 191 GlobalProperty hw_compat_2_10[] = { 192 { "virtio-mouse-device", "wheel-axis", "false" }, 193 { "virtio-tablet-device", "wheel-axis", "false" }, 194 }; 195 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 196 197 GlobalProperty hw_compat_2_9[] = { 198 { "pci-bridge", "shpc", "off" }, 199 { "intel-iommu", "pt", "off" }, 200 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 201 { "pcie-root-port", "x-migrate-msix", "false" }, 202 }; 203 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 204 205 GlobalProperty hw_compat_2_8[] = { 206 { "fw_cfg_mem", "x-file-slots", "0x10" }, 207 { "fw_cfg_io", "x-file-slots", "0x10" }, 208 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 209 { "pci-bridge", "shpc", "on" }, 210 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 211 { "virtio-pci", "x-pcie-deverr-init", "off" }, 212 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 213 { "virtio-pci", "x-pcie-pm-init", "off" }, 214 { "cirrus-vga", "vgamem_mb", "8" }, 215 { "isa-cirrus-vga", "vgamem_mb", "8" }, 216 }; 217 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 218 219 GlobalProperty hw_compat_2_7[] = { 220 { "virtio-pci", "page-per-vq", "on" }, 221 { "virtio-serial-device", "emergency-write", "off" }, 222 { "ioapic", "version", "0x11" }, 223 { "intel-iommu", "x-buggy-eim", "true" }, 224 { "virtio-pci", "x-ignore-backend-features", "on" }, 225 }; 226 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 227 228 GlobalProperty hw_compat_2_6[] = { 229 { "virtio-mmio", "format_transport_address", "off" }, 230 /* Optional because not all virtio-pci devices support legacy mode */ 231 { "virtio-pci", "disable-modern", "on", .optional = true }, 232 { "virtio-pci", "disable-legacy", "off", .optional = true }, 233 }; 234 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 235 236 GlobalProperty hw_compat_2_5[] = { 237 { "isa-fdc", "fallback", "144" }, 238 { "pvscsi", "x-old-pci-configuration", "on" }, 239 { "pvscsi", "x-disable-pcie", "on" }, 240 { "vmxnet3", "x-old-msi-offsets", "on" }, 241 { "vmxnet3", "x-disable-pcie", "on" }, 242 }; 243 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 244 245 GlobalProperty hw_compat_2_4[] = { 246 /* Optional because the 'scsi' property is Linux-only */ 247 { "virtio-blk-device", "scsi", "true", .optional = true }, 248 { "e1000", "extra_mac_registers", "off" }, 249 { "virtio-pci", "x-disable-pcie", "on" }, 250 { "virtio-pci", "migrate-extra", "off" }, 251 { "fw_cfg_mem", "dma_enabled", "off" }, 252 { "fw_cfg_io", "dma_enabled", "off" } 253 }; 254 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 255 256 GlobalProperty hw_compat_2_3[] = { 257 { "virtio-blk-pci", "any_layout", "off" }, 258 { "virtio-balloon-pci", "any_layout", "off" }, 259 { "virtio-serial-pci", "any_layout", "off" }, 260 { "virtio-9p-pci", "any_layout", "off" }, 261 { "virtio-rng-pci", "any_layout", "off" }, 262 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 263 { "migration", "send-configuration", "off" }, 264 { "migration", "send-section-footer", "off" }, 265 { "migration", "store-global-state", "off" }, 266 }; 267 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 268 269 GlobalProperty hw_compat_2_2[] = {}; 270 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 271 272 GlobalProperty hw_compat_2_1[] = { 273 { "intel-hda", "old_msi_addr", "on" }, 274 { "VGA", "qemu-extended-regs", "off" }, 275 { "secondary-vga", "qemu-extended-regs", "off" }, 276 { "virtio-scsi-pci", "any_layout", "off" }, 277 { "usb-mouse", "usb_version", "1" }, 278 { "usb-kbd", "usb_version", "1" }, 279 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 280 }; 281 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 282 283 MachineState *current_machine; 284 285 static char *machine_get_kernel(Object *obj, Error **errp) 286 { 287 MachineState *ms = MACHINE(obj); 288 289 return g_strdup(ms->kernel_filename); 290 } 291 292 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 293 { 294 MachineState *ms = MACHINE(obj); 295 296 g_free(ms->kernel_filename); 297 ms->kernel_filename = g_strdup(value); 298 } 299 300 static char *machine_get_initrd(Object *obj, Error **errp) 301 { 302 MachineState *ms = MACHINE(obj); 303 304 return g_strdup(ms->initrd_filename); 305 } 306 307 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 308 { 309 MachineState *ms = MACHINE(obj); 310 311 g_free(ms->initrd_filename); 312 ms->initrd_filename = g_strdup(value); 313 } 314 315 static char *machine_get_append(Object *obj, Error **errp) 316 { 317 MachineState *ms = MACHINE(obj); 318 319 return g_strdup(ms->kernel_cmdline); 320 } 321 322 static void machine_set_append(Object *obj, const char *value, Error **errp) 323 { 324 MachineState *ms = MACHINE(obj); 325 326 g_free(ms->kernel_cmdline); 327 ms->kernel_cmdline = g_strdup(value); 328 } 329 330 static char *machine_get_dtb(Object *obj, Error **errp) 331 { 332 MachineState *ms = MACHINE(obj); 333 334 return g_strdup(ms->dtb); 335 } 336 337 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 338 { 339 MachineState *ms = MACHINE(obj); 340 341 g_free(ms->dtb); 342 ms->dtb = g_strdup(value); 343 } 344 345 static char *machine_get_dumpdtb(Object *obj, Error **errp) 346 { 347 MachineState *ms = MACHINE(obj); 348 349 return g_strdup(ms->dumpdtb); 350 } 351 352 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 353 { 354 MachineState *ms = MACHINE(obj); 355 356 g_free(ms->dumpdtb); 357 ms->dumpdtb = g_strdup(value); 358 } 359 360 static void machine_get_phandle_start(Object *obj, Visitor *v, 361 const char *name, void *opaque, 362 Error **errp) 363 { 364 MachineState *ms = MACHINE(obj); 365 int64_t value = ms->phandle_start; 366 367 visit_type_int(v, name, &value, errp); 368 } 369 370 static void machine_set_phandle_start(Object *obj, Visitor *v, 371 const char *name, void *opaque, 372 Error **errp) 373 { 374 MachineState *ms = MACHINE(obj); 375 int64_t value; 376 377 if (!visit_type_int(v, name, &value, errp)) { 378 return; 379 } 380 381 ms->phandle_start = value; 382 } 383 384 static char *machine_get_dt_compatible(Object *obj, Error **errp) 385 { 386 MachineState *ms = MACHINE(obj); 387 388 return g_strdup(ms->dt_compatible); 389 } 390 391 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 392 { 393 MachineState *ms = MACHINE(obj); 394 395 g_free(ms->dt_compatible); 396 ms->dt_compatible = g_strdup(value); 397 } 398 399 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 400 { 401 MachineState *ms = MACHINE(obj); 402 403 return ms->dump_guest_core; 404 } 405 406 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 407 { 408 MachineState *ms = MACHINE(obj); 409 410 ms->dump_guest_core = value; 411 } 412 413 static bool machine_get_mem_merge(Object *obj, Error **errp) 414 { 415 MachineState *ms = MACHINE(obj); 416 417 return ms->mem_merge; 418 } 419 420 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 421 { 422 MachineState *ms = MACHINE(obj); 423 424 ms->mem_merge = value; 425 } 426 427 static bool machine_get_usb(Object *obj, Error **errp) 428 { 429 MachineState *ms = MACHINE(obj); 430 431 return ms->usb; 432 } 433 434 static void machine_set_usb(Object *obj, bool value, Error **errp) 435 { 436 MachineState *ms = MACHINE(obj); 437 438 ms->usb = value; 439 ms->usb_disabled = !value; 440 } 441 442 static bool machine_get_graphics(Object *obj, Error **errp) 443 { 444 MachineState *ms = MACHINE(obj); 445 446 return ms->enable_graphics; 447 } 448 449 static void machine_set_graphics(Object *obj, bool value, Error **errp) 450 { 451 MachineState *ms = MACHINE(obj); 452 453 ms->enable_graphics = value; 454 } 455 456 static char *machine_get_firmware(Object *obj, Error **errp) 457 { 458 MachineState *ms = MACHINE(obj); 459 460 return g_strdup(ms->firmware); 461 } 462 463 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 464 { 465 MachineState *ms = MACHINE(obj); 466 467 g_free(ms->firmware); 468 ms->firmware = g_strdup(value); 469 } 470 471 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 472 { 473 MachineState *ms = MACHINE(obj); 474 475 ms->suppress_vmdesc = value; 476 } 477 478 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 479 { 480 MachineState *ms = MACHINE(obj); 481 482 return ms->suppress_vmdesc; 483 } 484 485 static char *machine_get_memory_encryption(Object *obj, Error **errp) 486 { 487 MachineState *ms = MACHINE(obj); 488 489 if (ms->cgs) { 490 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 491 } 492 493 return NULL; 494 } 495 496 static void machine_set_memory_encryption(Object *obj, const char *value, 497 Error **errp) 498 { 499 Object *cgs = 500 object_resolve_path_component(object_get_objects_root(), value); 501 502 if (!cgs) { 503 error_setg(errp, "No such memory encryption object '%s'", value); 504 return; 505 } 506 507 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 508 } 509 510 static void machine_check_confidential_guest_support(const Object *obj, 511 const char *name, 512 Object *new_target, 513 Error **errp) 514 { 515 /* 516 * So far the only constraint is that the target has the 517 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 518 * by the QOM core 519 */ 520 } 521 522 static bool machine_get_nvdimm(Object *obj, Error **errp) 523 { 524 MachineState *ms = MACHINE(obj); 525 526 return ms->nvdimms_state->is_enabled; 527 } 528 529 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 530 { 531 MachineState *ms = MACHINE(obj); 532 533 ms->nvdimms_state->is_enabled = value; 534 } 535 536 static bool machine_get_hmat(Object *obj, Error **errp) 537 { 538 MachineState *ms = MACHINE(obj); 539 540 return ms->numa_state->hmat_enabled; 541 } 542 543 static void machine_set_hmat(Object *obj, bool value, Error **errp) 544 { 545 MachineState *ms = MACHINE(obj); 546 547 ms->numa_state->hmat_enabled = value; 548 } 549 550 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 551 void *opaque, Error **errp) 552 { 553 MachineState *ms = MACHINE(obj); 554 MemorySizeConfiguration mem = { 555 .has_size = true, 556 .size = ms->ram_size, 557 .has_max_size = !!ms->ram_slots, 558 .max_size = ms->maxram_size, 559 .has_slots = !!ms->ram_slots, 560 .slots = ms->ram_slots, 561 }; 562 MemorySizeConfiguration *p_mem = &mem; 563 564 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 565 } 566 567 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 568 void *opaque, Error **errp) 569 { 570 ERRP_GUARD(); 571 MachineState *ms = MACHINE(obj); 572 MachineClass *mc = MACHINE_GET_CLASS(obj); 573 MemorySizeConfiguration *mem; 574 575 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 576 return; 577 } 578 579 if (!mem->has_size) { 580 mem->has_size = true; 581 mem->size = mc->default_ram_size; 582 } 583 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 584 if (mc->fixup_ram_size) { 585 mem->size = mc->fixup_ram_size(mem->size); 586 } 587 if ((ram_addr_t)mem->size != mem->size) { 588 error_setg(errp, "ram size too large"); 589 goto out_free; 590 } 591 592 if (mem->has_max_size) { 593 if (mem->max_size < mem->size) { 594 error_setg(errp, "invalid value of maxmem: " 595 "maximum memory size (0x%" PRIx64 ") must be at least " 596 "the initial memory size (0x%" PRIx64 ")", 597 mem->max_size, mem->size); 598 goto out_free; 599 } 600 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 601 error_setg(errp, "invalid value of maxmem: " 602 "memory slots were specified but maximum memory size " 603 "(0x%" PRIx64 ") is equal to the initial memory size " 604 "(0x%" PRIx64 ")", mem->max_size, mem->size); 605 goto out_free; 606 } 607 ms->maxram_size = mem->max_size; 608 } else { 609 if (mem->has_slots) { 610 error_setg(errp, "slots specified but no max-size"); 611 goto out_free; 612 } 613 ms->maxram_size = mem->size; 614 } 615 ms->ram_size = mem->size; 616 ms->ram_slots = mem->has_slots ? mem->slots : 0; 617 out_free: 618 qapi_free_MemorySizeConfiguration(mem); 619 } 620 621 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 622 { 623 MachineState *ms = MACHINE(obj); 624 625 return g_strdup(ms->nvdimms_state->persistence_string); 626 } 627 628 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 629 Error **errp) 630 { 631 MachineState *ms = MACHINE(obj); 632 NVDIMMState *nvdimms_state = ms->nvdimms_state; 633 634 if (strcmp(value, "cpu") == 0) { 635 nvdimms_state->persistence = 3; 636 } else if (strcmp(value, "mem-ctrl") == 0) { 637 nvdimms_state->persistence = 2; 638 } else { 639 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 640 value); 641 return; 642 } 643 644 g_free(nvdimms_state->persistence_string); 645 nvdimms_state->persistence_string = g_strdup(value); 646 } 647 648 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 649 { 650 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 651 } 652 653 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 654 { 655 Object *obj = OBJECT(dev); 656 657 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 658 return false; 659 } 660 661 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 662 } 663 664 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 665 { 666 bool allowed = false; 667 strList *wl; 668 ObjectClass *klass = object_class_by_name(type); 669 670 for (wl = mc->allowed_dynamic_sysbus_devices; 671 !allowed && wl; 672 wl = wl->next) { 673 allowed |= !!object_class_dynamic_cast(klass, wl->value); 674 } 675 676 return allowed; 677 } 678 679 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 680 { 681 int i; 682 HotpluggableCPUList *head = NULL; 683 MachineClass *mc = MACHINE_GET_CLASS(machine); 684 685 /* force board to initialize possible_cpus if it hasn't been done yet */ 686 mc->possible_cpu_arch_ids(machine); 687 688 for (i = 0; i < machine->possible_cpus->len; i++) { 689 Object *cpu; 690 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 691 692 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 693 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 694 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 695 sizeof(*cpu_item->props)); 696 697 cpu = machine->possible_cpus->cpus[i].cpu; 698 if (cpu) { 699 cpu_item->qom_path = object_get_canonical_path(cpu); 700 } 701 QAPI_LIST_PREPEND(head, cpu_item); 702 } 703 return head; 704 } 705 706 /** 707 * machine_set_cpu_numa_node: 708 * @machine: machine object to modify 709 * @props: specifies which cpu objects to assign to 710 * numa node specified by @props.node_id 711 * @errp: if an error occurs, a pointer to an area to store the error 712 * 713 * Associate NUMA node specified by @props.node_id with cpu slots that 714 * match socket/core/thread-ids specified by @props. It's recommended to use 715 * query-hotpluggable-cpus.props values to specify affected cpu slots, 716 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 717 * 718 * However for CLI convenience it's possible to pass in subset of properties, 719 * which would affect all cpu slots that match it. 720 * Ex for pc machine: 721 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 722 * -numa cpu,node-id=0,socket_id=0 \ 723 * -numa cpu,node-id=1,socket_id=1 724 * will assign all child cores of socket 0 to node 0 and 725 * of socket 1 to node 1. 726 * 727 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 728 * return error. 729 * Empty subset is disallowed and function will return with error in this case. 730 */ 731 void machine_set_cpu_numa_node(MachineState *machine, 732 const CpuInstanceProperties *props, Error **errp) 733 { 734 MachineClass *mc = MACHINE_GET_CLASS(machine); 735 NodeInfo *numa_info = machine->numa_state->nodes; 736 bool match = false; 737 int i; 738 739 if (!mc->possible_cpu_arch_ids) { 740 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 741 return; 742 } 743 744 /* disabling node mapping is not supported, forbid it */ 745 assert(props->has_node_id); 746 747 /* force board to initialize possible_cpus if it hasn't been done yet */ 748 mc->possible_cpu_arch_ids(machine); 749 750 for (i = 0; i < machine->possible_cpus->len; i++) { 751 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 752 753 /* reject unsupported by board properties */ 754 if (props->has_thread_id && !slot->props.has_thread_id) { 755 error_setg(errp, "thread-id is not supported"); 756 return; 757 } 758 759 if (props->has_core_id && !slot->props.has_core_id) { 760 error_setg(errp, "core-id is not supported"); 761 return; 762 } 763 764 if (props->has_cluster_id && !slot->props.has_cluster_id) { 765 error_setg(errp, "cluster-id is not supported"); 766 return; 767 } 768 769 if (props->has_socket_id && !slot->props.has_socket_id) { 770 error_setg(errp, "socket-id is not supported"); 771 return; 772 } 773 774 if (props->has_die_id && !slot->props.has_die_id) { 775 error_setg(errp, "die-id is not supported"); 776 return; 777 } 778 779 /* skip slots with explicit mismatch */ 780 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 781 continue; 782 } 783 784 if (props->has_core_id && props->core_id != slot->props.core_id) { 785 continue; 786 } 787 788 if (props->has_cluster_id && 789 props->cluster_id != slot->props.cluster_id) { 790 continue; 791 } 792 793 if (props->has_die_id && props->die_id != slot->props.die_id) { 794 continue; 795 } 796 797 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 798 continue; 799 } 800 801 /* reject assignment if slot is already assigned, for compatibility 802 * of legacy cpu_index mapping with SPAPR core based mapping do not 803 * error out if cpu thread and matched core have the same node-id */ 804 if (slot->props.has_node_id && 805 slot->props.node_id != props->node_id) { 806 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 807 slot->props.node_id); 808 return; 809 } 810 811 /* assign slot to node as it's matched '-numa cpu' key */ 812 match = true; 813 slot->props.node_id = props->node_id; 814 slot->props.has_node_id = props->has_node_id; 815 816 if (machine->numa_state->hmat_enabled) { 817 if ((numa_info[props->node_id].initiator < MAX_NODES) && 818 (props->node_id != numa_info[props->node_id].initiator)) { 819 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 820 " should be itself (got %" PRIu16 ")", 821 props->node_id, numa_info[props->node_id].initiator); 822 return; 823 } 824 numa_info[props->node_id].has_cpu = true; 825 numa_info[props->node_id].initiator = props->node_id; 826 } 827 } 828 829 if (!match) { 830 error_setg(errp, "no match found"); 831 } 832 } 833 834 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 835 void *opaque, Error **errp) 836 { 837 MachineState *ms = MACHINE(obj); 838 SMPConfiguration *config = &(SMPConfiguration){ 839 .has_cpus = true, .cpus = ms->smp.cpus, 840 .has_sockets = true, .sockets = ms->smp.sockets, 841 .has_dies = true, .dies = ms->smp.dies, 842 .has_clusters = true, .clusters = ms->smp.clusters, 843 .has_cores = true, .cores = ms->smp.cores, 844 .has_threads = true, .threads = ms->smp.threads, 845 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 846 }; 847 848 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 849 return; 850 } 851 } 852 853 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 854 void *opaque, Error **errp) 855 { 856 MachineState *ms = MACHINE(obj); 857 g_autoptr(SMPConfiguration) config = NULL; 858 859 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 860 return; 861 } 862 863 machine_parse_smp_config(ms, config, errp); 864 } 865 866 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 867 void *opaque, Error **errp) 868 { 869 MachineState *ms = MACHINE(obj); 870 BootConfiguration *config = &ms->boot_config; 871 visit_type_BootConfiguration(v, name, &config, &error_abort); 872 } 873 874 static void machine_free_boot_config(MachineState *ms) 875 { 876 g_free(ms->boot_config.order); 877 g_free(ms->boot_config.once); 878 g_free(ms->boot_config.splash); 879 } 880 881 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 882 { 883 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 884 885 machine_free_boot_config(ms); 886 ms->boot_config = *config; 887 if (!config->order) { 888 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 889 } 890 } 891 892 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 893 void *opaque, Error **errp) 894 { 895 ERRP_GUARD(); 896 MachineState *ms = MACHINE(obj); 897 BootConfiguration *config = NULL; 898 899 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 900 return; 901 } 902 if (config->order) { 903 validate_bootdevices(config->order, errp); 904 if (*errp) { 905 goto out_free; 906 } 907 } 908 if (config->once) { 909 validate_bootdevices(config->once, errp); 910 if (*errp) { 911 goto out_free; 912 } 913 } 914 915 machine_copy_boot_config(ms, config); 916 /* Strings live in ms->boot_config. */ 917 free(config); 918 return; 919 920 out_free: 921 qapi_free_BootConfiguration(config); 922 } 923 924 static void machine_class_init(ObjectClass *oc, void *data) 925 { 926 MachineClass *mc = MACHINE_CLASS(oc); 927 928 /* Default 128 MB as guest ram size */ 929 mc->default_ram_size = 128 * MiB; 930 mc->rom_file_has_mr = true; 931 932 /* numa node memory size aligned on 8MB by default. 933 * On Linux, each node's border has to be 8MB aligned 934 */ 935 mc->numa_mem_align_shift = 23; 936 937 object_class_property_add_str(oc, "kernel", 938 machine_get_kernel, machine_set_kernel); 939 object_class_property_set_description(oc, "kernel", 940 "Linux kernel image file"); 941 942 object_class_property_add_str(oc, "initrd", 943 machine_get_initrd, machine_set_initrd); 944 object_class_property_set_description(oc, "initrd", 945 "Linux initial ramdisk file"); 946 947 object_class_property_add_str(oc, "append", 948 machine_get_append, machine_set_append); 949 object_class_property_set_description(oc, "append", 950 "Linux kernel command line"); 951 952 object_class_property_add_str(oc, "dtb", 953 machine_get_dtb, machine_set_dtb); 954 object_class_property_set_description(oc, "dtb", 955 "Linux kernel device tree file"); 956 957 object_class_property_add_str(oc, "dumpdtb", 958 machine_get_dumpdtb, machine_set_dumpdtb); 959 object_class_property_set_description(oc, "dumpdtb", 960 "Dump current dtb to a file and quit"); 961 962 object_class_property_add(oc, "boot", "BootConfiguration", 963 machine_get_boot, machine_set_boot, 964 NULL, NULL); 965 object_class_property_set_description(oc, "boot", 966 "Boot configuration"); 967 968 object_class_property_add(oc, "smp", "SMPConfiguration", 969 machine_get_smp, machine_set_smp, 970 NULL, NULL); 971 object_class_property_set_description(oc, "smp", 972 "CPU topology"); 973 974 object_class_property_add(oc, "phandle-start", "int", 975 machine_get_phandle_start, machine_set_phandle_start, 976 NULL, NULL); 977 object_class_property_set_description(oc, "phandle-start", 978 "The first phandle ID we may generate dynamically"); 979 980 object_class_property_add_str(oc, "dt-compatible", 981 machine_get_dt_compatible, machine_set_dt_compatible); 982 object_class_property_set_description(oc, "dt-compatible", 983 "Overrides the \"compatible\" property of the dt root node"); 984 985 object_class_property_add_bool(oc, "dump-guest-core", 986 machine_get_dump_guest_core, machine_set_dump_guest_core); 987 object_class_property_set_description(oc, "dump-guest-core", 988 "Include guest memory in a core dump"); 989 990 object_class_property_add_bool(oc, "mem-merge", 991 machine_get_mem_merge, machine_set_mem_merge); 992 object_class_property_set_description(oc, "mem-merge", 993 "Enable/disable memory merge support"); 994 995 object_class_property_add_bool(oc, "usb", 996 machine_get_usb, machine_set_usb); 997 object_class_property_set_description(oc, "usb", 998 "Set on/off to enable/disable usb"); 999 1000 object_class_property_add_bool(oc, "graphics", 1001 machine_get_graphics, machine_set_graphics); 1002 object_class_property_set_description(oc, "graphics", 1003 "Set on/off to enable/disable graphics emulation"); 1004 1005 object_class_property_add_str(oc, "firmware", 1006 machine_get_firmware, machine_set_firmware); 1007 object_class_property_set_description(oc, "firmware", 1008 "Firmware image"); 1009 1010 object_class_property_add_bool(oc, "suppress-vmdesc", 1011 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1012 object_class_property_set_description(oc, "suppress-vmdesc", 1013 "Set on to disable self-describing migration"); 1014 1015 object_class_property_add_link(oc, "confidential-guest-support", 1016 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1017 offsetof(MachineState, cgs), 1018 machine_check_confidential_guest_support, 1019 OBJ_PROP_LINK_STRONG); 1020 object_class_property_set_description(oc, "confidential-guest-support", 1021 "Set confidential guest scheme to support"); 1022 1023 /* For compatibility */ 1024 object_class_property_add_str(oc, "memory-encryption", 1025 machine_get_memory_encryption, machine_set_memory_encryption); 1026 object_class_property_set_description(oc, "memory-encryption", 1027 "Set memory encryption object to use"); 1028 1029 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1030 offsetof(MachineState, memdev), object_property_allow_set_link, 1031 OBJ_PROP_LINK_STRONG); 1032 object_class_property_set_description(oc, "memory-backend", 1033 "Set RAM backend" 1034 "Valid value is ID of hostmem based backend"); 1035 1036 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1037 machine_get_mem, machine_set_mem, 1038 NULL, NULL); 1039 object_class_property_set_description(oc, "memory", 1040 "Memory size configuration"); 1041 } 1042 1043 static void machine_class_base_init(ObjectClass *oc, void *data) 1044 { 1045 MachineClass *mc = MACHINE_CLASS(oc); 1046 mc->max_cpus = mc->max_cpus ?: 1; 1047 mc->min_cpus = mc->min_cpus ?: 1; 1048 mc->default_cpus = mc->default_cpus ?: 1; 1049 1050 if (!object_class_is_abstract(oc)) { 1051 const char *cname = object_class_get_name(oc); 1052 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1053 mc->name = g_strndup(cname, 1054 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1055 mc->compat_props = g_ptr_array_new(); 1056 } 1057 } 1058 1059 static void machine_initfn(Object *obj) 1060 { 1061 MachineState *ms = MACHINE(obj); 1062 MachineClass *mc = MACHINE_GET_CLASS(obj); 1063 1064 container_get(obj, "/peripheral"); 1065 container_get(obj, "/peripheral-anon"); 1066 1067 ms->dump_guest_core = true; 1068 ms->mem_merge = true; 1069 ms->enable_graphics = true; 1070 ms->kernel_cmdline = g_strdup(""); 1071 ms->ram_size = mc->default_ram_size; 1072 ms->maxram_size = mc->default_ram_size; 1073 1074 if (mc->nvdimm_supported) { 1075 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1076 object_property_add_bool(obj, "nvdimm", 1077 machine_get_nvdimm, machine_set_nvdimm); 1078 object_property_set_description(obj, "nvdimm", 1079 "Set on/off to enable/disable " 1080 "NVDIMM instantiation"); 1081 1082 object_property_add_str(obj, "nvdimm-persistence", 1083 machine_get_nvdimm_persistence, 1084 machine_set_nvdimm_persistence); 1085 object_property_set_description(obj, "nvdimm-persistence", 1086 "Set NVDIMM persistence" 1087 "Valid values are cpu, mem-ctrl"); 1088 } 1089 1090 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1091 ms->numa_state = g_new0(NumaState, 1); 1092 object_property_add_bool(obj, "hmat", 1093 machine_get_hmat, machine_set_hmat); 1094 object_property_set_description(obj, "hmat", 1095 "Set on/off to enable/disable " 1096 "ACPI Heterogeneous Memory Attribute " 1097 "Table (HMAT)"); 1098 } 1099 1100 /* default to mc->default_cpus */ 1101 ms->smp.cpus = mc->default_cpus; 1102 ms->smp.max_cpus = mc->default_cpus; 1103 ms->smp.sockets = 1; 1104 ms->smp.dies = 1; 1105 ms->smp.clusters = 1; 1106 ms->smp.cores = 1; 1107 ms->smp.threads = 1; 1108 1109 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1110 } 1111 1112 static void machine_finalize(Object *obj) 1113 { 1114 MachineState *ms = MACHINE(obj); 1115 1116 machine_free_boot_config(ms); 1117 g_free(ms->kernel_filename); 1118 g_free(ms->initrd_filename); 1119 g_free(ms->kernel_cmdline); 1120 g_free(ms->dtb); 1121 g_free(ms->dumpdtb); 1122 g_free(ms->dt_compatible); 1123 g_free(ms->firmware); 1124 g_free(ms->device_memory); 1125 g_free(ms->nvdimms_state); 1126 g_free(ms->numa_state); 1127 } 1128 1129 bool machine_usb(MachineState *machine) 1130 { 1131 return machine->usb; 1132 } 1133 1134 int machine_phandle_start(MachineState *machine) 1135 { 1136 return machine->phandle_start; 1137 } 1138 1139 bool machine_dump_guest_core(MachineState *machine) 1140 { 1141 return machine->dump_guest_core; 1142 } 1143 1144 bool machine_mem_merge(MachineState *machine) 1145 { 1146 return machine->mem_merge; 1147 } 1148 1149 static char *cpu_slot_to_string(const CPUArchId *cpu) 1150 { 1151 GString *s = g_string_new(NULL); 1152 if (cpu->props.has_socket_id) { 1153 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1154 } 1155 if (cpu->props.has_die_id) { 1156 if (s->len) { 1157 g_string_append_printf(s, ", "); 1158 } 1159 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1160 } 1161 if (cpu->props.has_cluster_id) { 1162 if (s->len) { 1163 g_string_append_printf(s, ", "); 1164 } 1165 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1166 } 1167 if (cpu->props.has_core_id) { 1168 if (s->len) { 1169 g_string_append_printf(s, ", "); 1170 } 1171 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1172 } 1173 if (cpu->props.has_thread_id) { 1174 if (s->len) { 1175 g_string_append_printf(s, ", "); 1176 } 1177 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1178 } 1179 return g_string_free(s, false); 1180 } 1181 1182 static void numa_validate_initiator(NumaState *numa_state) 1183 { 1184 int i; 1185 NodeInfo *numa_info = numa_state->nodes; 1186 1187 for (i = 0; i < numa_state->num_nodes; i++) { 1188 if (numa_info[i].initiator == MAX_NODES) { 1189 continue; 1190 } 1191 1192 if (!numa_info[numa_info[i].initiator].present) { 1193 error_report("NUMA node %" PRIu16 " is missing, use " 1194 "'-numa node' option to declare it first", 1195 numa_info[i].initiator); 1196 exit(1); 1197 } 1198 1199 if (!numa_info[numa_info[i].initiator].has_cpu) { 1200 error_report("The initiator of NUMA node %d is invalid", i); 1201 exit(1); 1202 } 1203 } 1204 } 1205 1206 static void machine_numa_finish_cpu_init(MachineState *machine) 1207 { 1208 int i; 1209 bool default_mapping; 1210 GString *s = g_string_new(NULL); 1211 MachineClass *mc = MACHINE_GET_CLASS(machine); 1212 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1213 1214 assert(machine->numa_state->num_nodes); 1215 for (i = 0; i < possible_cpus->len; i++) { 1216 if (possible_cpus->cpus[i].props.has_node_id) { 1217 break; 1218 } 1219 } 1220 default_mapping = (i == possible_cpus->len); 1221 1222 for (i = 0; i < possible_cpus->len; i++) { 1223 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1224 1225 if (!cpu_slot->props.has_node_id) { 1226 /* fetch default mapping from board and enable it */ 1227 CpuInstanceProperties props = cpu_slot->props; 1228 1229 props.node_id = mc->get_default_cpu_node_id(machine, i); 1230 if (!default_mapping) { 1231 /* record slots with not set mapping, 1232 * TODO: make it hard error in future */ 1233 char *cpu_str = cpu_slot_to_string(cpu_slot); 1234 g_string_append_printf(s, "%sCPU %d [%s]", 1235 s->len ? ", " : "", i, cpu_str); 1236 g_free(cpu_str); 1237 1238 /* non mapped cpus used to fallback to node 0 */ 1239 props.node_id = 0; 1240 } 1241 1242 props.has_node_id = true; 1243 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1244 } 1245 } 1246 1247 if (machine->numa_state->hmat_enabled) { 1248 numa_validate_initiator(machine->numa_state); 1249 } 1250 1251 if (s->len && !qtest_enabled()) { 1252 warn_report("CPU(s) not present in any NUMA nodes: %s", 1253 s->str); 1254 warn_report("All CPU(s) up to maxcpus should be described " 1255 "in NUMA config, ability to start up with partial NUMA " 1256 "mappings is obsoleted and will be removed in future"); 1257 } 1258 g_string_free(s, true); 1259 } 1260 1261 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1262 { 1263 MachineClass *mc = MACHINE_GET_CLASS(ms); 1264 NumaState *state = ms->numa_state; 1265 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1266 const CPUArchId *cpus = possible_cpus->cpus; 1267 int i, j; 1268 1269 if (state->num_nodes <= 1 || possible_cpus->len <= 1) { 1270 return; 1271 } 1272 1273 /* 1274 * The Linux scheduling domain can't be parsed when the multiple CPUs 1275 * in one cluster have been associated with different NUMA nodes. However, 1276 * it's fine to associate one NUMA node with CPUs in different clusters. 1277 */ 1278 for (i = 0; i < possible_cpus->len; i++) { 1279 for (j = i + 1; j < possible_cpus->len; j++) { 1280 if (cpus[i].props.has_socket_id && 1281 cpus[i].props.has_cluster_id && 1282 cpus[i].props.has_node_id && 1283 cpus[j].props.has_socket_id && 1284 cpus[j].props.has_cluster_id && 1285 cpus[j].props.has_node_id && 1286 cpus[i].props.socket_id == cpus[j].props.socket_id && 1287 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1288 cpus[i].props.node_id != cpus[j].props.node_id) { 1289 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1290 " have been associated with node-%" PRId64 " and node-%" PRId64 1291 " respectively. It can cause OSes like Linux to" 1292 " misbehave", i, j, cpus[i].props.socket_id, 1293 cpus[i].props.cluster_id, cpus[i].props.node_id, 1294 cpus[j].props.node_id); 1295 } 1296 } 1297 } 1298 } 1299 1300 MemoryRegion *machine_consume_memdev(MachineState *machine, 1301 HostMemoryBackend *backend) 1302 { 1303 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1304 1305 if (host_memory_backend_is_mapped(backend)) { 1306 error_report("memory backend %s can't be used multiple times.", 1307 object_get_canonical_path_component(OBJECT(backend))); 1308 exit(EXIT_FAILURE); 1309 } 1310 host_memory_backend_set_mapped(backend, true); 1311 vmstate_register_ram_global(ret); 1312 return ret; 1313 } 1314 1315 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) 1316 { 1317 Object *obj; 1318 MachineClass *mc = MACHINE_GET_CLASS(ms); 1319 bool r = false; 1320 1321 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1322 if (path) { 1323 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1324 goto out; 1325 } 1326 } 1327 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1328 goto out; 1329 } 1330 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1331 obj); 1332 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1333 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1334 false, errp)) { 1335 goto out; 1336 } 1337 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1338 goto out; 1339 } 1340 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1341 1342 out: 1343 object_unref(obj); 1344 return r; 1345 } 1346 1347 1348 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1349 { 1350 ERRP_GUARD(); 1351 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1352 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1353 CPUClass *cc; 1354 1355 /* This checkpoint is required by replay to separate prior clock 1356 reading from the other reads, because timer polling functions query 1357 clock values from the log. */ 1358 replay_checkpoint(CHECKPOINT_INIT); 1359 1360 if (!xen_enabled()) { 1361 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1362 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1363 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1364 return; 1365 } 1366 } 1367 1368 if (machine->memdev) { 1369 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1370 "size", &error_abort); 1371 if (backend_size != machine->ram_size) { 1372 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1373 return; 1374 } 1375 } else if (machine_class->default_ram_id && machine->ram_size && 1376 numa_uses_legacy_mem()) { 1377 if (object_property_find(object_get_objects_root(), 1378 machine_class->default_ram_id)) { 1379 error_setg(errp, "object's id '%s' is reserved for the default" 1380 " RAM backend, it can't be used for any other purposes", 1381 machine_class->default_ram_id); 1382 error_append_hint(errp, 1383 "Change the object's 'id' to something else or disable" 1384 " automatic creation of the default RAM backend by setting" 1385 " 'memory-backend=%s' with '-machine'.\n", 1386 machine_class->default_ram_id); 1387 return; 1388 } 1389 if (!create_default_memdev(current_machine, mem_path, errp)) { 1390 return; 1391 } 1392 } 1393 1394 if (machine->numa_state) { 1395 numa_complete_configuration(machine); 1396 if (machine->numa_state->num_nodes) { 1397 machine_numa_finish_cpu_init(machine); 1398 if (machine_class->cpu_cluster_has_numa_boundary) { 1399 validate_cpu_cluster_to_numa_boundary(machine); 1400 } 1401 } 1402 } 1403 1404 if (!machine->ram && machine->memdev) { 1405 machine->ram = machine_consume_memdev(machine, machine->memdev); 1406 } 1407 1408 /* If the machine supports the valid_cpu_types check and the user 1409 * specified a CPU with -cpu check here that the user CPU is supported. 1410 */ 1411 if (machine_class->valid_cpu_types && machine->cpu_type) { 1412 int i; 1413 1414 for (i = 0; machine_class->valid_cpu_types[i]; i++) { 1415 if (object_class_dynamic_cast(oc, 1416 machine_class->valid_cpu_types[i])) { 1417 /* The user specified CPU is in the valid field, we are 1418 * good to go. 1419 */ 1420 break; 1421 } 1422 } 1423 1424 if (!machine_class->valid_cpu_types[i]) { 1425 /* The user specified CPU is not valid */ 1426 error_report("Invalid CPU type: %s", machine->cpu_type); 1427 error_printf("The valid types are: %s", 1428 machine_class->valid_cpu_types[0]); 1429 for (i = 1; machine_class->valid_cpu_types[i]; i++) { 1430 error_printf(", %s", machine_class->valid_cpu_types[i]); 1431 } 1432 error_printf("\n"); 1433 1434 exit(1); 1435 } 1436 } 1437 1438 /* Check if CPU type is deprecated and warn if so */ 1439 cc = CPU_CLASS(oc); 1440 if (cc && cc->deprecation_note) { 1441 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, 1442 cc->deprecation_note); 1443 } 1444 1445 if (machine->cgs) { 1446 /* 1447 * With confidential guests, the host can't see the real 1448 * contents of RAM, so there's no point in it trying to merge 1449 * areas. 1450 */ 1451 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1452 1453 /* 1454 * Virtio devices can't count on directly accessing guest 1455 * memory, so they need iommu_platform=on to use normal DMA 1456 * mechanisms. That requires also disabling legacy virtio 1457 * support for those virtio pci devices which allow it. 1458 */ 1459 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1460 "on", true); 1461 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1462 "on", false); 1463 } 1464 1465 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1466 machine_class->init(machine); 1467 phase_advance(PHASE_MACHINE_INITIALIZED); 1468 } 1469 1470 static NotifierList machine_init_done_notifiers = 1471 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1472 1473 void qemu_add_machine_init_done_notifier(Notifier *notify) 1474 { 1475 notifier_list_add(&machine_init_done_notifiers, notify); 1476 if (phase_check(PHASE_MACHINE_READY)) { 1477 notify->notify(notify, NULL); 1478 } 1479 } 1480 1481 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1482 { 1483 notifier_remove(notify); 1484 } 1485 1486 void qdev_machine_creation_done(void) 1487 { 1488 cpu_synchronize_all_post_init(); 1489 1490 if (current_machine->boot_config.once) { 1491 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1492 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1493 } 1494 1495 /* 1496 * ok, initial machine setup is done, starting from now we can 1497 * only create hotpluggable devices 1498 */ 1499 phase_advance(PHASE_MACHINE_READY); 1500 qdev_assert_realized_properly(); 1501 1502 /* TODO: once all bus devices are qdevified, this should be done 1503 * when bus is created by qdev.c */ 1504 /* 1505 * TODO: If we had a main 'reset container' that the whole system 1506 * lived in, we could reset that using the multi-phase reset 1507 * APIs. For the moment, we just reset the sysbus, which will cause 1508 * all devices hanging off it (and all their child buses, recursively) 1509 * to be reset. Note that this will *not* reset any Device objects 1510 * which are not attached to some part of the qbus tree! 1511 */ 1512 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); 1513 1514 notifier_list_notify(&machine_init_done_notifiers, NULL); 1515 1516 if (rom_check_and_register_reset() != 0) { 1517 exit(1); 1518 } 1519 1520 replay_start(); 1521 1522 /* This checkpoint is required by replay to separate prior clock 1523 reading from the other reads, because timer polling functions query 1524 clock values from the log. */ 1525 replay_checkpoint(CHECKPOINT_RESET); 1526 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1527 register_global_state(); 1528 } 1529 1530 static const TypeInfo machine_info = { 1531 .name = TYPE_MACHINE, 1532 .parent = TYPE_OBJECT, 1533 .abstract = true, 1534 .class_size = sizeof(MachineClass), 1535 .class_init = machine_class_init, 1536 .class_base_init = machine_class_base_init, 1537 .instance_size = sizeof(MachineState), 1538 .instance_init = machine_initfn, 1539 .instance_finalize = machine_finalize, 1540 }; 1541 1542 static void machine_register_types(void) 1543 { 1544 type_register_static(&machine_info); 1545 } 1546 1547 type_init(machine_register_types) 1548