1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/option.h" 15 #include "qemu/accel.h" 16 #include "sysemu/replay.h" 17 #include "qemu/units.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-common.h" 22 #include "qapi/qapi-visit-machine.h" 23 #include "qapi/visitor.h" 24 #include "qom/object_interfaces.h" 25 #include "hw/sysbus.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/numa.h" 31 #include "sysemu/xen.h" 32 #include "qemu/error-report.h" 33 #include "sysemu/qtest.h" 34 #include "hw/pci/pci.h" 35 #include "hw/pci/pci_bridge.h" 36 #include "hw/mem/nvdimm.h" 37 #include "migration/global_state.h" 38 #include "migration/vmstate.h" 39 #include "exec/confidential-guest-support.h" 40 #include "hw/virtio/virtio.h" 41 #include "hw/virtio/virtio-pci.h" 42 #include "hw/virtio/virtio-net.h" 43 44 GlobalProperty hw_compat_8_1[] = { 45 { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, 46 }; 47 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 48 49 GlobalProperty hw_compat_8_0[] = { 50 { "migration", "multifd-flush-after-each-section", "on"}, 51 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 52 { TYPE_VIRTIO_NET, "host_uso", "off"}, 53 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 54 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 55 }; 56 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 57 58 GlobalProperty hw_compat_7_2[] = { 59 { "e1000e", "migrate-timadj", "off" }, 60 { "virtio-mem", "x-early-migration", "false" }, 61 { "migration", "x-preempt-pre-7-2", "true" }, 62 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 63 }; 64 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 65 66 GlobalProperty hw_compat_7_1[] = { 67 { "virtio-device", "queue_reset", "false" }, 68 { "virtio-rng-pci", "vectors", "0" }, 69 { "virtio-rng-pci-transitional", "vectors", "0" }, 70 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 71 }; 72 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 73 74 GlobalProperty hw_compat_7_0[] = { 75 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 76 { "nvme-ns", "eui64-default", "on"}, 77 }; 78 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 79 80 GlobalProperty hw_compat_6_2[] = { 81 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 82 }; 83 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 84 85 GlobalProperty hw_compat_6_1[] = { 86 { "vhost-user-vsock-device", "seqpacket", "off" }, 87 { "nvme-ns", "shared", "off" }, 88 }; 89 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 90 91 GlobalProperty hw_compat_6_0[] = { 92 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 93 { "i8042", "extended-state", "false"}, 94 { "nvme-ns", "eui64-default", "off"}, 95 { "e1000", "init-vet", "off" }, 96 { "e1000e", "init-vet", "off" }, 97 { "vhost-vsock-device", "seqpacket", "off" }, 98 }; 99 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 100 101 GlobalProperty hw_compat_5_2[] = { 102 { "ICH9-LPC", "smm-compat", "on"}, 103 { "PIIX4_PM", "smm-compat", "on"}, 104 { "virtio-blk-device", "report-discard-granularity", "off" }, 105 { "virtio-net-pci-base", "vectors", "3"}, 106 }; 107 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 108 109 GlobalProperty hw_compat_5_1[] = { 110 { "vhost-scsi", "num_queues", "1"}, 111 { "vhost-user-blk", "num-queues", "1"}, 112 { "vhost-user-scsi", "num_queues", "1"}, 113 { "virtio-blk-device", "num-queues", "1"}, 114 { "virtio-scsi-device", "num_queues", "1"}, 115 { "nvme", "use-intel-id", "on"}, 116 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 117 { "pl011", "migrate-clk", "off" }, 118 { "virtio-pci", "x-ats-page-aligned", "off"}, 119 }; 120 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 121 122 GlobalProperty hw_compat_5_0[] = { 123 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 124 { "virtio-balloon-device", "page-poison", "false" }, 125 { "vmport", "x-read-set-eax", "off" }, 126 { "vmport", "x-signal-unsupported-cmd", "off" }, 127 { "vmport", "x-report-vmx-type", "off" }, 128 { "vmport", "x-cmds-v2", "off" }, 129 { "virtio-device", "x-disable-legacy-check", "true" }, 130 }; 131 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 132 133 GlobalProperty hw_compat_4_2[] = { 134 { "virtio-blk-device", "queue-size", "128"}, 135 { "virtio-scsi-device", "virtqueue_size", "128"}, 136 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 137 { "virtio-blk-device", "seg-max-adjust", "off"}, 138 { "virtio-scsi-device", "seg_max_adjust", "off"}, 139 { "vhost-blk-device", "seg_max_adjust", "off"}, 140 { "usb-host", "suppress-remote-wake", "off" }, 141 { "usb-redir", "suppress-remote-wake", "off" }, 142 { "qxl", "revision", "4" }, 143 { "qxl-vga", "revision", "4" }, 144 { "fw_cfg", "acpi-mr-restore", "false" }, 145 { "virtio-device", "use-disabled-flag", "false" }, 146 }; 147 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 148 149 GlobalProperty hw_compat_4_1[] = { 150 { "virtio-pci", "x-pcie-flr-init", "off" }, 151 }; 152 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 153 154 GlobalProperty hw_compat_4_0[] = { 155 { "VGA", "edid", "false" }, 156 { "secondary-vga", "edid", "false" }, 157 { "bochs-display", "edid", "false" }, 158 { "virtio-vga", "edid", "false" }, 159 { "virtio-gpu-device", "edid", "false" }, 160 { "virtio-device", "use-started", "false" }, 161 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 162 { "pl031", "migrate-tick-offset", "false" }, 163 }; 164 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 165 166 GlobalProperty hw_compat_3_1[] = { 167 { "pcie-root-port", "x-speed", "2_5" }, 168 { "pcie-root-port", "x-width", "1" }, 169 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 170 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 171 { "tpm-crb", "ppi", "false" }, 172 { "tpm-tis", "ppi", "false" }, 173 { "usb-kbd", "serial", "42" }, 174 { "usb-mouse", "serial", "42" }, 175 { "usb-tablet", "serial", "42" }, 176 { "virtio-blk-device", "discard", "false" }, 177 { "virtio-blk-device", "write-zeroes", "false" }, 178 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 179 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 180 }; 181 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 182 183 GlobalProperty hw_compat_3_0[] = {}; 184 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 185 186 GlobalProperty hw_compat_2_12[] = { 187 { "migration", "decompress-error-check", "off" }, 188 { "hda-audio", "use-timer", "false" }, 189 { "cirrus-vga", "global-vmstate", "true" }, 190 { "VGA", "global-vmstate", "true" }, 191 { "vmware-svga", "global-vmstate", "true" }, 192 { "qxl-vga", "global-vmstate", "true" }, 193 }; 194 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 195 196 GlobalProperty hw_compat_2_11[] = { 197 { "hpet", "hpet-offset-saved", "false" }, 198 { "virtio-blk-pci", "vectors", "2" }, 199 { "vhost-user-blk-pci", "vectors", "2" }, 200 { "e1000", "migrate_tso_props", "off" }, 201 }; 202 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 203 204 GlobalProperty hw_compat_2_10[] = { 205 { "virtio-mouse-device", "wheel-axis", "false" }, 206 { "virtio-tablet-device", "wheel-axis", "false" }, 207 }; 208 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 209 210 GlobalProperty hw_compat_2_9[] = { 211 { "pci-bridge", "shpc", "off" }, 212 { "intel-iommu", "pt", "off" }, 213 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 214 { "pcie-root-port", "x-migrate-msix", "false" }, 215 }; 216 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 217 218 GlobalProperty hw_compat_2_8[] = { 219 { "fw_cfg_mem", "x-file-slots", "0x10" }, 220 { "fw_cfg_io", "x-file-slots", "0x10" }, 221 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 222 { "pci-bridge", "shpc", "on" }, 223 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 224 { "virtio-pci", "x-pcie-deverr-init", "off" }, 225 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 226 { "virtio-pci", "x-pcie-pm-init", "off" }, 227 { "cirrus-vga", "vgamem_mb", "8" }, 228 { "isa-cirrus-vga", "vgamem_mb", "8" }, 229 }; 230 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 231 232 GlobalProperty hw_compat_2_7[] = { 233 { "virtio-pci", "page-per-vq", "on" }, 234 { "virtio-serial-device", "emergency-write", "off" }, 235 { "ioapic", "version", "0x11" }, 236 { "intel-iommu", "x-buggy-eim", "true" }, 237 { "virtio-pci", "x-ignore-backend-features", "on" }, 238 }; 239 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 240 241 GlobalProperty hw_compat_2_6[] = { 242 { "virtio-mmio", "format_transport_address", "off" }, 243 /* Optional because not all virtio-pci devices support legacy mode */ 244 { "virtio-pci", "disable-modern", "on", .optional = true }, 245 { "virtio-pci", "disable-legacy", "off", .optional = true }, 246 }; 247 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 248 249 GlobalProperty hw_compat_2_5[] = { 250 { "isa-fdc", "fallback", "144" }, 251 { "pvscsi", "x-old-pci-configuration", "on" }, 252 { "pvscsi", "x-disable-pcie", "on" }, 253 { "vmxnet3", "x-old-msi-offsets", "on" }, 254 { "vmxnet3", "x-disable-pcie", "on" }, 255 }; 256 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 257 258 GlobalProperty hw_compat_2_4[] = { 259 /* Optional because the 'scsi' property is Linux-only */ 260 { "virtio-blk-device", "scsi", "true", .optional = true }, 261 { "e1000", "extra_mac_registers", "off" }, 262 { "virtio-pci", "x-disable-pcie", "on" }, 263 { "virtio-pci", "migrate-extra", "off" }, 264 { "fw_cfg_mem", "dma_enabled", "off" }, 265 { "fw_cfg_io", "dma_enabled", "off" } 266 }; 267 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 268 269 GlobalProperty hw_compat_2_3[] = { 270 { "virtio-blk-pci", "any_layout", "off" }, 271 { "virtio-balloon-pci", "any_layout", "off" }, 272 { "virtio-serial-pci", "any_layout", "off" }, 273 { "virtio-9p-pci", "any_layout", "off" }, 274 { "virtio-rng-pci", "any_layout", "off" }, 275 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, 276 { "migration", "send-configuration", "off" }, 277 { "migration", "send-section-footer", "off" }, 278 { "migration", "store-global-state", "off" }, 279 }; 280 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); 281 282 GlobalProperty hw_compat_2_2[] = {}; 283 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); 284 285 GlobalProperty hw_compat_2_1[] = { 286 { "intel-hda", "old_msi_addr", "on" }, 287 { "VGA", "qemu-extended-regs", "off" }, 288 { "secondary-vga", "qemu-extended-regs", "off" }, 289 { "virtio-scsi-pci", "any_layout", "off" }, 290 { "usb-mouse", "usb_version", "1" }, 291 { "usb-kbd", "usb_version", "1" }, 292 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, 293 }; 294 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); 295 296 MachineState *current_machine; 297 298 static char *machine_get_kernel(Object *obj, Error **errp) 299 { 300 MachineState *ms = MACHINE(obj); 301 302 return g_strdup(ms->kernel_filename); 303 } 304 305 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 306 { 307 MachineState *ms = MACHINE(obj); 308 309 g_free(ms->kernel_filename); 310 ms->kernel_filename = g_strdup(value); 311 } 312 313 static char *machine_get_initrd(Object *obj, Error **errp) 314 { 315 MachineState *ms = MACHINE(obj); 316 317 return g_strdup(ms->initrd_filename); 318 } 319 320 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 321 { 322 MachineState *ms = MACHINE(obj); 323 324 g_free(ms->initrd_filename); 325 ms->initrd_filename = g_strdup(value); 326 } 327 328 static char *machine_get_append(Object *obj, Error **errp) 329 { 330 MachineState *ms = MACHINE(obj); 331 332 return g_strdup(ms->kernel_cmdline); 333 } 334 335 static void machine_set_append(Object *obj, const char *value, Error **errp) 336 { 337 MachineState *ms = MACHINE(obj); 338 339 g_free(ms->kernel_cmdline); 340 ms->kernel_cmdline = g_strdup(value); 341 } 342 343 static char *machine_get_dtb(Object *obj, Error **errp) 344 { 345 MachineState *ms = MACHINE(obj); 346 347 return g_strdup(ms->dtb); 348 } 349 350 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 351 { 352 MachineState *ms = MACHINE(obj); 353 354 g_free(ms->dtb); 355 ms->dtb = g_strdup(value); 356 } 357 358 static char *machine_get_dumpdtb(Object *obj, Error **errp) 359 { 360 MachineState *ms = MACHINE(obj); 361 362 return g_strdup(ms->dumpdtb); 363 } 364 365 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 366 { 367 MachineState *ms = MACHINE(obj); 368 369 g_free(ms->dumpdtb); 370 ms->dumpdtb = g_strdup(value); 371 } 372 373 static void machine_get_phandle_start(Object *obj, Visitor *v, 374 const char *name, void *opaque, 375 Error **errp) 376 { 377 MachineState *ms = MACHINE(obj); 378 int64_t value = ms->phandle_start; 379 380 visit_type_int(v, name, &value, errp); 381 } 382 383 static void machine_set_phandle_start(Object *obj, Visitor *v, 384 const char *name, void *opaque, 385 Error **errp) 386 { 387 MachineState *ms = MACHINE(obj); 388 int64_t value; 389 390 if (!visit_type_int(v, name, &value, errp)) { 391 return; 392 } 393 394 ms->phandle_start = value; 395 } 396 397 static char *machine_get_dt_compatible(Object *obj, Error **errp) 398 { 399 MachineState *ms = MACHINE(obj); 400 401 return g_strdup(ms->dt_compatible); 402 } 403 404 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 405 { 406 MachineState *ms = MACHINE(obj); 407 408 g_free(ms->dt_compatible); 409 ms->dt_compatible = g_strdup(value); 410 } 411 412 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 413 { 414 MachineState *ms = MACHINE(obj); 415 416 return ms->dump_guest_core; 417 } 418 419 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 420 { 421 MachineState *ms = MACHINE(obj); 422 423 ms->dump_guest_core = value; 424 } 425 426 static bool machine_get_mem_merge(Object *obj, Error **errp) 427 { 428 MachineState *ms = MACHINE(obj); 429 430 return ms->mem_merge; 431 } 432 433 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 434 { 435 MachineState *ms = MACHINE(obj); 436 437 ms->mem_merge = value; 438 } 439 440 static bool machine_get_usb(Object *obj, Error **errp) 441 { 442 MachineState *ms = MACHINE(obj); 443 444 return ms->usb; 445 } 446 447 static void machine_set_usb(Object *obj, bool value, Error **errp) 448 { 449 MachineState *ms = MACHINE(obj); 450 451 ms->usb = value; 452 ms->usb_disabled = !value; 453 } 454 455 static bool machine_get_graphics(Object *obj, Error **errp) 456 { 457 MachineState *ms = MACHINE(obj); 458 459 return ms->enable_graphics; 460 } 461 462 static void machine_set_graphics(Object *obj, bool value, Error **errp) 463 { 464 MachineState *ms = MACHINE(obj); 465 466 ms->enable_graphics = value; 467 } 468 469 static char *machine_get_firmware(Object *obj, Error **errp) 470 { 471 MachineState *ms = MACHINE(obj); 472 473 return g_strdup(ms->firmware); 474 } 475 476 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 477 { 478 MachineState *ms = MACHINE(obj); 479 480 g_free(ms->firmware); 481 ms->firmware = g_strdup(value); 482 } 483 484 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 485 { 486 MachineState *ms = MACHINE(obj); 487 488 ms->suppress_vmdesc = value; 489 } 490 491 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 492 { 493 MachineState *ms = MACHINE(obj); 494 495 return ms->suppress_vmdesc; 496 } 497 498 static char *machine_get_memory_encryption(Object *obj, Error **errp) 499 { 500 MachineState *ms = MACHINE(obj); 501 502 if (ms->cgs) { 503 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 504 } 505 506 return NULL; 507 } 508 509 static void machine_set_memory_encryption(Object *obj, const char *value, 510 Error **errp) 511 { 512 Object *cgs = 513 object_resolve_path_component(object_get_objects_root(), value); 514 515 if (!cgs) { 516 error_setg(errp, "No such memory encryption object '%s'", value); 517 return; 518 } 519 520 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 521 } 522 523 static void machine_check_confidential_guest_support(const Object *obj, 524 const char *name, 525 Object *new_target, 526 Error **errp) 527 { 528 /* 529 * So far the only constraint is that the target has the 530 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 531 * by the QOM core 532 */ 533 } 534 535 static bool machine_get_nvdimm(Object *obj, Error **errp) 536 { 537 MachineState *ms = MACHINE(obj); 538 539 return ms->nvdimms_state->is_enabled; 540 } 541 542 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 543 { 544 MachineState *ms = MACHINE(obj); 545 546 ms->nvdimms_state->is_enabled = value; 547 } 548 549 static bool machine_get_hmat(Object *obj, Error **errp) 550 { 551 MachineState *ms = MACHINE(obj); 552 553 return ms->numa_state->hmat_enabled; 554 } 555 556 static void machine_set_hmat(Object *obj, bool value, Error **errp) 557 { 558 MachineState *ms = MACHINE(obj); 559 560 ms->numa_state->hmat_enabled = value; 561 } 562 563 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 564 void *opaque, Error **errp) 565 { 566 MachineState *ms = MACHINE(obj); 567 MemorySizeConfiguration mem = { 568 .has_size = true, 569 .size = ms->ram_size, 570 .has_max_size = !!ms->ram_slots, 571 .max_size = ms->maxram_size, 572 .has_slots = !!ms->ram_slots, 573 .slots = ms->ram_slots, 574 }; 575 MemorySizeConfiguration *p_mem = &mem; 576 577 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 578 } 579 580 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 581 void *opaque, Error **errp) 582 { 583 ERRP_GUARD(); 584 MachineState *ms = MACHINE(obj); 585 MachineClass *mc = MACHINE_GET_CLASS(obj); 586 MemorySizeConfiguration *mem; 587 588 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 589 return; 590 } 591 592 if (!mem->has_size) { 593 mem->has_size = true; 594 mem->size = mc->default_ram_size; 595 } 596 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 597 if (mc->fixup_ram_size) { 598 mem->size = mc->fixup_ram_size(mem->size); 599 } 600 if ((ram_addr_t)mem->size != mem->size) { 601 error_setg(errp, "ram size too large"); 602 goto out_free; 603 } 604 605 if (mem->has_max_size) { 606 if (mem->max_size < mem->size) { 607 error_setg(errp, "invalid value of maxmem: " 608 "maximum memory size (0x%" PRIx64 ") must be at least " 609 "the initial memory size (0x%" PRIx64 ")", 610 mem->max_size, mem->size); 611 goto out_free; 612 } 613 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 614 error_setg(errp, "invalid value of maxmem: " 615 "memory slots were specified but maximum memory size " 616 "(0x%" PRIx64 ") is equal to the initial memory size " 617 "(0x%" PRIx64 ")", mem->max_size, mem->size); 618 goto out_free; 619 } 620 ms->maxram_size = mem->max_size; 621 } else { 622 if (mem->has_slots) { 623 error_setg(errp, "slots specified but no max-size"); 624 goto out_free; 625 } 626 ms->maxram_size = mem->size; 627 } 628 ms->ram_size = mem->size; 629 ms->ram_slots = mem->has_slots ? mem->slots : 0; 630 out_free: 631 qapi_free_MemorySizeConfiguration(mem); 632 } 633 634 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 635 { 636 MachineState *ms = MACHINE(obj); 637 638 return g_strdup(ms->nvdimms_state->persistence_string); 639 } 640 641 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 642 Error **errp) 643 { 644 MachineState *ms = MACHINE(obj); 645 NVDIMMState *nvdimms_state = ms->nvdimms_state; 646 647 if (strcmp(value, "cpu") == 0) { 648 nvdimms_state->persistence = 3; 649 } else if (strcmp(value, "mem-ctrl") == 0) { 650 nvdimms_state->persistence = 2; 651 } else { 652 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 653 value); 654 return; 655 } 656 657 g_free(nvdimms_state->persistence_string); 658 nvdimms_state->persistence_string = g_strdup(value); 659 } 660 661 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 662 { 663 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 664 } 665 666 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 667 { 668 Object *obj = OBJECT(dev); 669 670 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 671 return false; 672 } 673 674 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 675 } 676 677 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 678 { 679 bool allowed = false; 680 strList *wl; 681 ObjectClass *klass = object_class_by_name(type); 682 683 for (wl = mc->allowed_dynamic_sysbus_devices; 684 !allowed && wl; 685 wl = wl->next) { 686 allowed |= !!object_class_dynamic_cast(klass, wl->value); 687 } 688 689 return allowed; 690 } 691 692 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 693 { 694 int i; 695 HotpluggableCPUList *head = NULL; 696 MachineClass *mc = MACHINE_GET_CLASS(machine); 697 698 /* force board to initialize possible_cpus if it hasn't been done yet */ 699 mc->possible_cpu_arch_ids(machine); 700 701 for (i = 0; i < machine->possible_cpus->len; i++) { 702 Object *cpu; 703 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 704 705 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 706 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 707 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 708 sizeof(*cpu_item->props)); 709 710 cpu = machine->possible_cpus->cpus[i].cpu; 711 if (cpu) { 712 cpu_item->qom_path = object_get_canonical_path(cpu); 713 } 714 QAPI_LIST_PREPEND(head, cpu_item); 715 } 716 return head; 717 } 718 719 /** 720 * machine_set_cpu_numa_node: 721 * @machine: machine object to modify 722 * @props: specifies which cpu objects to assign to 723 * numa node specified by @props.node_id 724 * @errp: if an error occurs, a pointer to an area to store the error 725 * 726 * Associate NUMA node specified by @props.node_id with cpu slots that 727 * match socket/core/thread-ids specified by @props. It's recommended to use 728 * query-hotpluggable-cpus.props values to specify affected cpu slots, 729 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 730 * 731 * However for CLI convenience it's possible to pass in subset of properties, 732 * which would affect all cpu slots that match it. 733 * Ex for pc machine: 734 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 735 * -numa cpu,node-id=0,socket_id=0 \ 736 * -numa cpu,node-id=1,socket_id=1 737 * will assign all child cores of socket 0 to node 0 and 738 * of socket 1 to node 1. 739 * 740 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 741 * return error. 742 * Empty subset is disallowed and function will return with error in this case. 743 */ 744 void machine_set_cpu_numa_node(MachineState *machine, 745 const CpuInstanceProperties *props, Error **errp) 746 { 747 MachineClass *mc = MACHINE_GET_CLASS(machine); 748 NodeInfo *numa_info = machine->numa_state->nodes; 749 bool match = false; 750 int i; 751 752 if (!mc->possible_cpu_arch_ids) { 753 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 754 return; 755 } 756 757 /* disabling node mapping is not supported, forbid it */ 758 assert(props->has_node_id); 759 760 /* force board to initialize possible_cpus if it hasn't been done yet */ 761 mc->possible_cpu_arch_ids(machine); 762 763 for (i = 0; i < machine->possible_cpus->len; i++) { 764 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 765 766 /* reject unsupported by board properties */ 767 if (props->has_thread_id && !slot->props.has_thread_id) { 768 error_setg(errp, "thread-id is not supported"); 769 return; 770 } 771 772 if (props->has_core_id && !slot->props.has_core_id) { 773 error_setg(errp, "core-id is not supported"); 774 return; 775 } 776 777 if (props->has_cluster_id && !slot->props.has_cluster_id) { 778 error_setg(errp, "cluster-id is not supported"); 779 return; 780 } 781 782 if (props->has_socket_id && !slot->props.has_socket_id) { 783 error_setg(errp, "socket-id is not supported"); 784 return; 785 } 786 787 if (props->has_die_id && !slot->props.has_die_id) { 788 error_setg(errp, "die-id is not supported"); 789 return; 790 } 791 792 /* skip slots with explicit mismatch */ 793 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 794 continue; 795 } 796 797 if (props->has_core_id && props->core_id != slot->props.core_id) { 798 continue; 799 } 800 801 if (props->has_cluster_id && 802 props->cluster_id != slot->props.cluster_id) { 803 continue; 804 } 805 806 if (props->has_die_id && props->die_id != slot->props.die_id) { 807 continue; 808 } 809 810 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 811 continue; 812 } 813 814 /* reject assignment if slot is already assigned, for compatibility 815 * of legacy cpu_index mapping with SPAPR core based mapping do not 816 * error out if cpu thread and matched core have the same node-id */ 817 if (slot->props.has_node_id && 818 slot->props.node_id != props->node_id) { 819 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 820 slot->props.node_id); 821 return; 822 } 823 824 /* assign slot to node as it's matched '-numa cpu' key */ 825 match = true; 826 slot->props.node_id = props->node_id; 827 slot->props.has_node_id = props->has_node_id; 828 829 if (machine->numa_state->hmat_enabled) { 830 if ((numa_info[props->node_id].initiator < MAX_NODES) && 831 (props->node_id != numa_info[props->node_id].initiator)) { 832 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 833 " should be itself (got %" PRIu16 ")", 834 props->node_id, numa_info[props->node_id].initiator); 835 return; 836 } 837 numa_info[props->node_id].has_cpu = true; 838 numa_info[props->node_id].initiator = props->node_id; 839 } 840 } 841 842 if (!match) { 843 error_setg(errp, "no match found"); 844 } 845 } 846 847 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 848 void *opaque, Error **errp) 849 { 850 MachineState *ms = MACHINE(obj); 851 SMPConfiguration *config = &(SMPConfiguration){ 852 .has_cpus = true, .cpus = ms->smp.cpus, 853 .has_sockets = true, .sockets = ms->smp.sockets, 854 .has_dies = true, .dies = ms->smp.dies, 855 .has_clusters = true, .clusters = ms->smp.clusters, 856 .has_cores = true, .cores = ms->smp.cores, 857 .has_threads = true, .threads = ms->smp.threads, 858 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 859 }; 860 861 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 862 return; 863 } 864 } 865 866 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 867 void *opaque, Error **errp) 868 { 869 MachineState *ms = MACHINE(obj); 870 g_autoptr(SMPConfiguration) config = NULL; 871 872 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 873 return; 874 } 875 876 machine_parse_smp_config(ms, config, errp); 877 } 878 879 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 880 void *opaque, Error **errp) 881 { 882 MachineState *ms = MACHINE(obj); 883 BootConfiguration *config = &ms->boot_config; 884 visit_type_BootConfiguration(v, name, &config, &error_abort); 885 } 886 887 static void machine_free_boot_config(MachineState *ms) 888 { 889 g_free(ms->boot_config.order); 890 g_free(ms->boot_config.once); 891 g_free(ms->boot_config.splash); 892 } 893 894 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 895 { 896 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 897 898 machine_free_boot_config(ms); 899 ms->boot_config = *config; 900 if (!config->order) { 901 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 902 } 903 } 904 905 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 906 void *opaque, Error **errp) 907 { 908 ERRP_GUARD(); 909 MachineState *ms = MACHINE(obj); 910 BootConfiguration *config = NULL; 911 912 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 913 return; 914 } 915 if (config->order) { 916 validate_bootdevices(config->order, errp); 917 if (*errp) { 918 goto out_free; 919 } 920 } 921 if (config->once) { 922 validate_bootdevices(config->once, errp); 923 if (*errp) { 924 goto out_free; 925 } 926 } 927 928 machine_copy_boot_config(ms, config); 929 /* Strings live in ms->boot_config. */ 930 free(config); 931 return; 932 933 out_free: 934 qapi_free_BootConfiguration(config); 935 } 936 937 static void machine_class_init(ObjectClass *oc, void *data) 938 { 939 MachineClass *mc = MACHINE_CLASS(oc); 940 941 /* Default 128 MB as guest ram size */ 942 mc->default_ram_size = 128 * MiB; 943 mc->rom_file_has_mr = true; 944 945 /* numa node memory size aligned on 8MB by default. 946 * On Linux, each node's border has to be 8MB aligned 947 */ 948 mc->numa_mem_align_shift = 23; 949 950 object_class_property_add_str(oc, "kernel", 951 machine_get_kernel, machine_set_kernel); 952 object_class_property_set_description(oc, "kernel", 953 "Linux kernel image file"); 954 955 object_class_property_add_str(oc, "initrd", 956 machine_get_initrd, machine_set_initrd); 957 object_class_property_set_description(oc, "initrd", 958 "Linux initial ramdisk file"); 959 960 object_class_property_add_str(oc, "append", 961 machine_get_append, machine_set_append); 962 object_class_property_set_description(oc, "append", 963 "Linux kernel command line"); 964 965 object_class_property_add_str(oc, "dtb", 966 machine_get_dtb, machine_set_dtb); 967 object_class_property_set_description(oc, "dtb", 968 "Linux kernel device tree file"); 969 970 object_class_property_add_str(oc, "dumpdtb", 971 machine_get_dumpdtb, machine_set_dumpdtb); 972 object_class_property_set_description(oc, "dumpdtb", 973 "Dump current dtb to a file and quit"); 974 975 object_class_property_add(oc, "boot", "BootConfiguration", 976 machine_get_boot, machine_set_boot, 977 NULL, NULL); 978 object_class_property_set_description(oc, "boot", 979 "Boot configuration"); 980 981 object_class_property_add(oc, "smp", "SMPConfiguration", 982 machine_get_smp, machine_set_smp, 983 NULL, NULL); 984 object_class_property_set_description(oc, "smp", 985 "CPU topology"); 986 987 object_class_property_add(oc, "phandle-start", "int", 988 machine_get_phandle_start, machine_set_phandle_start, 989 NULL, NULL); 990 object_class_property_set_description(oc, "phandle-start", 991 "The first phandle ID we may generate dynamically"); 992 993 object_class_property_add_str(oc, "dt-compatible", 994 machine_get_dt_compatible, machine_set_dt_compatible); 995 object_class_property_set_description(oc, "dt-compatible", 996 "Overrides the \"compatible\" property of the dt root node"); 997 998 object_class_property_add_bool(oc, "dump-guest-core", 999 machine_get_dump_guest_core, machine_set_dump_guest_core); 1000 object_class_property_set_description(oc, "dump-guest-core", 1001 "Include guest memory in a core dump"); 1002 1003 object_class_property_add_bool(oc, "mem-merge", 1004 machine_get_mem_merge, machine_set_mem_merge); 1005 object_class_property_set_description(oc, "mem-merge", 1006 "Enable/disable memory merge support"); 1007 1008 object_class_property_add_bool(oc, "usb", 1009 machine_get_usb, machine_set_usb); 1010 object_class_property_set_description(oc, "usb", 1011 "Set on/off to enable/disable usb"); 1012 1013 object_class_property_add_bool(oc, "graphics", 1014 machine_get_graphics, machine_set_graphics); 1015 object_class_property_set_description(oc, "graphics", 1016 "Set on/off to enable/disable graphics emulation"); 1017 1018 object_class_property_add_str(oc, "firmware", 1019 machine_get_firmware, machine_set_firmware); 1020 object_class_property_set_description(oc, "firmware", 1021 "Firmware image"); 1022 1023 object_class_property_add_bool(oc, "suppress-vmdesc", 1024 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1025 object_class_property_set_description(oc, "suppress-vmdesc", 1026 "Set on to disable self-describing migration"); 1027 1028 object_class_property_add_link(oc, "confidential-guest-support", 1029 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1030 offsetof(MachineState, cgs), 1031 machine_check_confidential_guest_support, 1032 OBJ_PROP_LINK_STRONG); 1033 object_class_property_set_description(oc, "confidential-guest-support", 1034 "Set confidential guest scheme to support"); 1035 1036 /* For compatibility */ 1037 object_class_property_add_str(oc, "memory-encryption", 1038 machine_get_memory_encryption, machine_set_memory_encryption); 1039 object_class_property_set_description(oc, "memory-encryption", 1040 "Set memory encryption object to use"); 1041 1042 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1043 offsetof(MachineState, memdev), object_property_allow_set_link, 1044 OBJ_PROP_LINK_STRONG); 1045 object_class_property_set_description(oc, "memory-backend", 1046 "Set RAM backend" 1047 "Valid value is ID of hostmem based backend"); 1048 1049 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1050 machine_get_mem, machine_set_mem, 1051 NULL, NULL); 1052 object_class_property_set_description(oc, "memory", 1053 "Memory size configuration"); 1054 } 1055 1056 static void machine_class_base_init(ObjectClass *oc, void *data) 1057 { 1058 MachineClass *mc = MACHINE_CLASS(oc); 1059 mc->max_cpus = mc->max_cpus ?: 1; 1060 mc->min_cpus = mc->min_cpus ?: 1; 1061 mc->default_cpus = mc->default_cpus ?: 1; 1062 1063 if (!object_class_is_abstract(oc)) { 1064 const char *cname = object_class_get_name(oc); 1065 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1066 mc->name = g_strndup(cname, 1067 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1068 mc->compat_props = g_ptr_array_new(); 1069 } 1070 } 1071 1072 static void machine_initfn(Object *obj) 1073 { 1074 MachineState *ms = MACHINE(obj); 1075 MachineClass *mc = MACHINE_GET_CLASS(obj); 1076 1077 container_get(obj, "/peripheral"); 1078 container_get(obj, "/peripheral-anon"); 1079 1080 ms->dump_guest_core = true; 1081 ms->mem_merge = true; 1082 ms->enable_graphics = true; 1083 ms->kernel_cmdline = g_strdup(""); 1084 ms->ram_size = mc->default_ram_size; 1085 ms->maxram_size = mc->default_ram_size; 1086 1087 if (mc->nvdimm_supported) { 1088 Object *obj = OBJECT(ms); 1089 1090 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1091 object_property_add_bool(obj, "nvdimm", 1092 machine_get_nvdimm, machine_set_nvdimm); 1093 object_property_set_description(obj, "nvdimm", 1094 "Set on/off to enable/disable " 1095 "NVDIMM instantiation"); 1096 1097 object_property_add_str(obj, "nvdimm-persistence", 1098 machine_get_nvdimm_persistence, 1099 machine_set_nvdimm_persistence); 1100 object_property_set_description(obj, "nvdimm-persistence", 1101 "Set NVDIMM persistence" 1102 "Valid values are cpu, mem-ctrl"); 1103 } 1104 1105 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1106 ms->numa_state = g_new0(NumaState, 1); 1107 object_property_add_bool(obj, "hmat", 1108 machine_get_hmat, machine_set_hmat); 1109 object_property_set_description(obj, "hmat", 1110 "Set on/off to enable/disable " 1111 "ACPI Heterogeneous Memory Attribute " 1112 "Table (HMAT)"); 1113 } 1114 1115 /* default to mc->default_cpus */ 1116 ms->smp.cpus = mc->default_cpus; 1117 ms->smp.max_cpus = mc->default_cpus; 1118 ms->smp.sockets = 1; 1119 ms->smp.dies = 1; 1120 ms->smp.clusters = 1; 1121 ms->smp.cores = 1; 1122 ms->smp.threads = 1; 1123 1124 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1125 } 1126 1127 static void machine_finalize(Object *obj) 1128 { 1129 MachineState *ms = MACHINE(obj); 1130 1131 machine_free_boot_config(ms); 1132 g_free(ms->kernel_filename); 1133 g_free(ms->initrd_filename); 1134 g_free(ms->kernel_cmdline); 1135 g_free(ms->dtb); 1136 g_free(ms->dumpdtb); 1137 g_free(ms->dt_compatible); 1138 g_free(ms->firmware); 1139 g_free(ms->device_memory); 1140 g_free(ms->nvdimms_state); 1141 g_free(ms->numa_state); 1142 } 1143 1144 bool machine_usb(MachineState *machine) 1145 { 1146 return machine->usb; 1147 } 1148 1149 int machine_phandle_start(MachineState *machine) 1150 { 1151 return machine->phandle_start; 1152 } 1153 1154 bool machine_dump_guest_core(MachineState *machine) 1155 { 1156 return machine->dump_guest_core; 1157 } 1158 1159 bool machine_mem_merge(MachineState *machine) 1160 { 1161 return machine->mem_merge; 1162 } 1163 1164 static char *cpu_slot_to_string(const CPUArchId *cpu) 1165 { 1166 GString *s = g_string_new(NULL); 1167 if (cpu->props.has_socket_id) { 1168 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1169 } 1170 if (cpu->props.has_die_id) { 1171 if (s->len) { 1172 g_string_append_printf(s, ", "); 1173 } 1174 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1175 } 1176 if (cpu->props.has_cluster_id) { 1177 if (s->len) { 1178 g_string_append_printf(s, ", "); 1179 } 1180 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1181 } 1182 if (cpu->props.has_core_id) { 1183 if (s->len) { 1184 g_string_append_printf(s, ", "); 1185 } 1186 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1187 } 1188 if (cpu->props.has_thread_id) { 1189 if (s->len) { 1190 g_string_append_printf(s, ", "); 1191 } 1192 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1193 } 1194 return g_string_free(s, false); 1195 } 1196 1197 static void numa_validate_initiator(NumaState *numa_state) 1198 { 1199 int i; 1200 NodeInfo *numa_info = numa_state->nodes; 1201 1202 for (i = 0; i < numa_state->num_nodes; i++) { 1203 if (numa_info[i].initiator == MAX_NODES) { 1204 continue; 1205 } 1206 1207 if (!numa_info[numa_info[i].initiator].present) { 1208 error_report("NUMA node %" PRIu16 " is missing, use " 1209 "'-numa node' option to declare it first", 1210 numa_info[i].initiator); 1211 exit(1); 1212 } 1213 1214 if (!numa_info[numa_info[i].initiator].has_cpu) { 1215 error_report("The initiator of NUMA node %d is invalid", i); 1216 exit(1); 1217 } 1218 } 1219 } 1220 1221 static void machine_numa_finish_cpu_init(MachineState *machine) 1222 { 1223 int i; 1224 bool default_mapping; 1225 GString *s = g_string_new(NULL); 1226 MachineClass *mc = MACHINE_GET_CLASS(machine); 1227 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1228 1229 assert(machine->numa_state->num_nodes); 1230 for (i = 0; i < possible_cpus->len; i++) { 1231 if (possible_cpus->cpus[i].props.has_node_id) { 1232 break; 1233 } 1234 } 1235 default_mapping = (i == possible_cpus->len); 1236 1237 for (i = 0; i < possible_cpus->len; i++) { 1238 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1239 1240 if (!cpu_slot->props.has_node_id) { 1241 /* fetch default mapping from board and enable it */ 1242 CpuInstanceProperties props = cpu_slot->props; 1243 1244 props.node_id = mc->get_default_cpu_node_id(machine, i); 1245 if (!default_mapping) { 1246 /* record slots with not set mapping, 1247 * TODO: make it hard error in future */ 1248 char *cpu_str = cpu_slot_to_string(cpu_slot); 1249 g_string_append_printf(s, "%sCPU %d [%s]", 1250 s->len ? ", " : "", i, cpu_str); 1251 g_free(cpu_str); 1252 1253 /* non mapped cpus used to fallback to node 0 */ 1254 props.node_id = 0; 1255 } 1256 1257 props.has_node_id = true; 1258 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1259 } 1260 } 1261 1262 if (machine->numa_state->hmat_enabled) { 1263 numa_validate_initiator(machine->numa_state); 1264 } 1265 1266 if (s->len && !qtest_enabled()) { 1267 warn_report("CPU(s) not present in any NUMA nodes: %s", 1268 s->str); 1269 warn_report("All CPU(s) up to maxcpus should be described " 1270 "in NUMA config, ability to start up with partial NUMA " 1271 "mappings is obsoleted and will be removed in future"); 1272 } 1273 g_string_free(s, true); 1274 } 1275 1276 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1277 { 1278 MachineClass *mc = MACHINE_GET_CLASS(ms); 1279 NumaState *state = ms->numa_state; 1280 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1281 const CPUArchId *cpus = possible_cpus->cpus; 1282 int i, j; 1283 1284 if (state->num_nodes <= 1 || possible_cpus->len <= 1) { 1285 return; 1286 } 1287 1288 /* 1289 * The Linux scheduling domain can't be parsed when the multiple CPUs 1290 * in one cluster have been associated with different NUMA nodes. However, 1291 * it's fine to associate one NUMA node with CPUs in different clusters. 1292 */ 1293 for (i = 0; i < possible_cpus->len; i++) { 1294 for (j = i + 1; j < possible_cpus->len; j++) { 1295 if (cpus[i].props.has_socket_id && 1296 cpus[i].props.has_cluster_id && 1297 cpus[i].props.has_node_id && 1298 cpus[j].props.has_socket_id && 1299 cpus[j].props.has_cluster_id && 1300 cpus[j].props.has_node_id && 1301 cpus[i].props.socket_id == cpus[j].props.socket_id && 1302 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1303 cpus[i].props.node_id != cpus[j].props.node_id) { 1304 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1305 " have been associated with node-%" PRId64 " and node-%" PRId64 1306 " respectively. It can cause OSes like Linux to" 1307 " misbehave", i, j, cpus[i].props.socket_id, 1308 cpus[i].props.cluster_id, cpus[i].props.node_id, 1309 cpus[j].props.node_id); 1310 } 1311 } 1312 } 1313 } 1314 1315 MemoryRegion *machine_consume_memdev(MachineState *machine, 1316 HostMemoryBackend *backend) 1317 { 1318 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1319 1320 if (host_memory_backend_is_mapped(backend)) { 1321 error_report("memory backend %s can't be used multiple times.", 1322 object_get_canonical_path_component(OBJECT(backend))); 1323 exit(EXIT_FAILURE); 1324 } 1325 host_memory_backend_set_mapped(backend, true); 1326 vmstate_register_ram_global(ret); 1327 return ret; 1328 } 1329 1330 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) 1331 { 1332 Object *obj; 1333 MachineClass *mc = MACHINE_GET_CLASS(ms); 1334 bool r = false; 1335 1336 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1337 if (path) { 1338 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1339 goto out; 1340 } 1341 } 1342 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1343 goto out; 1344 } 1345 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1346 obj); 1347 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1348 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1349 false, errp)) { 1350 goto out; 1351 } 1352 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1353 goto out; 1354 } 1355 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1356 1357 out: 1358 object_unref(obj); 1359 return r; 1360 } 1361 1362 1363 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1364 { 1365 ERRP_GUARD(); 1366 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1367 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1368 CPUClass *cc; 1369 1370 /* This checkpoint is required by replay to separate prior clock 1371 reading from the other reads, because timer polling functions query 1372 clock values from the log. */ 1373 replay_checkpoint(CHECKPOINT_INIT); 1374 1375 if (!xen_enabled()) { 1376 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1377 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1378 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1379 return; 1380 } 1381 } 1382 1383 if (machine->memdev) { 1384 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1385 "size", &error_abort); 1386 if (backend_size != machine->ram_size) { 1387 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1388 return; 1389 } 1390 } else if (machine_class->default_ram_id && machine->ram_size && 1391 numa_uses_legacy_mem()) { 1392 if (object_property_find(object_get_objects_root(), 1393 machine_class->default_ram_id)) { 1394 error_setg(errp, "object's id '%s' is reserved for the default" 1395 " RAM backend, it can't be used for any other purposes", 1396 machine_class->default_ram_id); 1397 error_append_hint(errp, 1398 "Change the object's 'id' to something else or disable" 1399 " automatic creation of the default RAM backend by setting" 1400 " 'memory-backend=%s' with '-machine'.\n", 1401 machine_class->default_ram_id); 1402 return; 1403 } 1404 if (!create_default_memdev(current_machine, mem_path, errp)) { 1405 return; 1406 } 1407 } 1408 1409 if (machine->numa_state) { 1410 numa_complete_configuration(machine); 1411 if (machine->numa_state->num_nodes) { 1412 machine_numa_finish_cpu_init(machine); 1413 if (machine_class->cpu_cluster_has_numa_boundary) { 1414 validate_cpu_cluster_to_numa_boundary(machine); 1415 } 1416 } 1417 } 1418 1419 if (!machine->ram && machine->memdev) { 1420 machine->ram = machine_consume_memdev(machine, machine->memdev); 1421 } 1422 1423 /* If the machine supports the valid_cpu_types check and the user 1424 * specified a CPU with -cpu check here that the user CPU is supported. 1425 */ 1426 if (machine_class->valid_cpu_types && machine->cpu_type) { 1427 int i; 1428 1429 for (i = 0; machine_class->valid_cpu_types[i]; i++) { 1430 if (object_class_dynamic_cast(oc, 1431 machine_class->valid_cpu_types[i])) { 1432 /* The user specified CPU is in the valid field, we are 1433 * good to go. 1434 */ 1435 break; 1436 } 1437 } 1438 1439 if (!machine_class->valid_cpu_types[i]) { 1440 /* The user specified CPU is not valid */ 1441 error_report("Invalid CPU type: %s", machine->cpu_type); 1442 error_printf("The valid types are: %s", 1443 machine_class->valid_cpu_types[0]); 1444 for (i = 1; machine_class->valid_cpu_types[i]; i++) { 1445 error_printf(", %s", machine_class->valid_cpu_types[i]); 1446 } 1447 error_printf("\n"); 1448 1449 exit(1); 1450 } 1451 } 1452 1453 /* Check if CPU type is deprecated and warn if so */ 1454 cc = CPU_CLASS(oc); 1455 if (cc && cc->deprecation_note) { 1456 warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, 1457 cc->deprecation_note); 1458 } 1459 1460 if (machine->cgs) { 1461 /* 1462 * With confidential guests, the host can't see the real 1463 * contents of RAM, so there's no point in it trying to merge 1464 * areas. 1465 */ 1466 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1467 1468 /* 1469 * Virtio devices can't count on directly accessing guest 1470 * memory, so they need iommu_platform=on to use normal DMA 1471 * mechanisms. That requires also disabling legacy virtio 1472 * support for those virtio pci devices which allow it. 1473 */ 1474 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1475 "on", true); 1476 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1477 "on", false); 1478 } 1479 1480 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1481 machine_class->init(machine); 1482 phase_advance(PHASE_MACHINE_INITIALIZED); 1483 } 1484 1485 static NotifierList machine_init_done_notifiers = 1486 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1487 1488 void qemu_add_machine_init_done_notifier(Notifier *notify) 1489 { 1490 notifier_list_add(&machine_init_done_notifiers, notify); 1491 if (phase_check(PHASE_MACHINE_READY)) { 1492 notify->notify(notify, NULL); 1493 } 1494 } 1495 1496 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1497 { 1498 notifier_remove(notify); 1499 } 1500 1501 void qdev_machine_creation_done(void) 1502 { 1503 cpu_synchronize_all_post_init(); 1504 1505 if (current_machine->boot_config.once) { 1506 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1507 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1508 } 1509 1510 /* 1511 * ok, initial machine setup is done, starting from now we can 1512 * only create hotpluggable devices 1513 */ 1514 phase_advance(PHASE_MACHINE_READY); 1515 qdev_assert_realized_properly(); 1516 1517 /* TODO: once all bus devices are qdevified, this should be done 1518 * when bus is created by qdev.c */ 1519 /* 1520 * TODO: If we had a main 'reset container' that the whole system 1521 * lived in, we could reset that using the multi-phase reset 1522 * APIs. For the moment, we just reset the sysbus, which will cause 1523 * all devices hanging off it (and all their child buses, recursively) 1524 * to be reset. Note that this will *not* reset any Device objects 1525 * which are not attached to some part of the qbus tree! 1526 */ 1527 qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); 1528 1529 notifier_list_notify(&machine_init_done_notifiers, NULL); 1530 1531 if (rom_check_and_register_reset() != 0) { 1532 exit(1); 1533 } 1534 1535 replay_start(); 1536 1537 /* This checkpoint is required by replay to separate prior clock 1538 reading from the other reads, because timer polling functions query 1539 clock values from the log. */ 1540 replay_checkpoint(CHECKPOINT_RESET); 1541 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1542 register_global_state(); 1543 } 1544 1545 static const TypeInfo machine_info = { 1546 .name = TYPE_MACHINE, 1547 .parent = TYPE_OBJECT, 1548 .abstract = true, 1549 .class_size = sizeof(MachineClass), 1550 .class_init = machine_class_init, 1551 .class_base_init = machine_class_base_init, 1552 .instance_size = sizeof(MachineState), 1553 .instance_init = machine_initfn, 1554 .instance_finalize = machine_finalize, 1555 }; 1556 1557 static void machine_register_types(void) 1558 { 1559 type_register_static(&machine_info); 1560 } 1561 1562 type_init(machine_register_types) 1563