1 /* 2 * ARM11MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "qemu/timer.h" 12 13 /* MPCore private memory region. */ 14 15 #define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv" 16 #define ARM11MPCORE_PRIV(obj) \ 17 OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV) 18 19 typedef struct ARM11MPCorePriveState { 20 SysBusDevice parent_obj; 21 22 uint32_t scu_control; 23 uint32_t num_cpu; 24 MemoryRegion iomem; 25 MemoryRegion container; 26 DeviceState *mptimer; 27 DeviceState *wdtimer; 28 DeviceState *gic; 29 uint32_t num_irq; 30 } ARM11MPCorePriveState; 31 32 /* Per-CPU private memory mapped IO. */ 33 34 static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, 35 unsigned size) 36 { 37 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 38 int id; 39 /* SCU */ 40 switch (offset) { 41 case 0x00: /* Control. */ 42 return s->scu_control; 43 case 0x04: /* Configuration. */ 44 id = ((1 << s->num_cpu) - 1) << 4; 45 return id | (s->num_cpu - 1); 46 case 0x08: /* CPU status. */ 47 return 0; 48 case 0x0c: /* Invalidate all. */ 49 return 0; 50 default: 51 qemu_log_mask(LOG_GUEST_ERROR, 52 "mpcore_priv_read: Bad offset %x\n", (int)offset); 53 return 0; 54 } 55 } 56 57 static void mpcore_scu_write(void *opaque, hwaddr offset, 58 uint64_t value, unsigned size) 59 { 60 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 61 /* SCU */ 62 switch (offset) { 63 case 0: /* Control register. */ 64 s->scu_control = value & 1; 65 break; 66 case 0x0c: /* Invalidate all. */ 67 /* This is a no-op as cache is not emulated. */ 68 break; 69 default: 70 qemu_log_mask(LOG_GUEST_ERROR, 71 "mpcore_priv_read: Bad offset %x\n", (int)offset); 72 } 73 } 74 75 static const MemoryRegionOps mpcore_scu_ops = { 76 .read = mpcore_scu_read, 77 .write = mpcore_scu_write, 78 .endianness = DEVICE_NATIVE_ENDIAN, 79 }; 80 81 static void mpcore_priv_set_irq(void *opaque, int irq, int level) 82 { 83 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 84 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); 85 } 86 87 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) 88 { 89 int i; 90 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); 91 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer); 92 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer); 93 memory_region_init_io(&s->iomem, OBJECT(s), 94 &mpcore_scu_ops, s, "mpcore-scu", 0x100); 95 memory_region_add_subregion(&s->container, 0, &s->iomem); 96 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs 97 * at 0x200, 0x300... 98 */ 99 for (i = 0; i < (s->num_cpu + 1); i++) { 100 hwaddr offset = 0x100 + (i * 0x100); 101 memory_region_add_subregion(&s->container, offset, 102 sysbus_mmio_get_region(gicbusdev, i + 1)); 103 } 104 /* Add the regions for timer and watchdog for "current CPU" and 105 * for each specific CPU. 106 */ 107 for (i = 0; i < (s->num_cpu + 1); i++) { 108 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ 109 hwaddr offset = 0x600 + i * 0x100; 110 memory_region_add_subregion(&s->container, offset, 111 sysbus_mmio_get_region(timerbusdev, i)); 112 memory_region_add_subregion(&s->container, offset + 0x20, 113 sysbus_mmio_get_region(wdtbusdev, i)); 114 } 115 memory_region_add_subregion(&s->container, 0x1000, 116 sysbus_mmio_get_region(gicbusdev, 0)); 117 /* Wire up the interrupt from each watchdog and timer. 118 * For each core the timer is PPI 29 and the watchdog PPI 30. 119 */ 120 for (i = 0; i < s->num_cpu; i++) { 121 int ppibase = (s->num_irq - 32) + i * 32; 122 sysbus_connect_irq(timerbusdev, i, 123 qdev_get_gpio_in(s->gic, ppibase + 29)); 124 sysbus_connect_irq(wdtbusdev, i, 125 qdev_get_gpio_in(s->gic, ppibase + 30)); 126 } 127 } 128 129 static int mpcore_priv_init(SysBusDevice *sbd) 130 { 131 DeviceState *dev = DEVICE(sbd); 132 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); 133 134 s->gic = qdev_create(NULL, "arm_gic"); 135 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 136 qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); 137 /* Request the legacy 11MPCore GIC behaviour: */ 138 qdev_prop_set_uint32(s->gic, "revision", 0); 139 qdev_init_nofail(s->gic); 140 141 /* Pass through outbound IRQ lines from the GIC */ 142 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic)); 143 144 /* Pass through inbound GPIO lines to the GIC */ 145 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); 146 147 s->mptimer = qdev_create(NULL, "arm_mptimer"); 148 qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); 149 qdev_init_nofail(s->mptimer); 150 151 s->wdtimer = qdev_create(NULL, "arm_mptimer"); 152 qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); 153 qdev_init_nofail(s->wdtimer); 154 155 mpcore_priv_map_setup(s); 156 return 0; 157 } 158 159 static void mpcore_priv_initfn(Object *obj) 160 { 161 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 162 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); 163 164 memory_region_init(&s->container, OBJECT(s), 165 "mpcore-priv-container", 0x2000); 166 sysbus_init_mmio(sbd, &s->container); 167 } 168 169 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" 170 #define REALVIEW_MPCORE_RIRQ(obj) \ 171 OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) 172 173 /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ 174 controllers. The output of these, plus some of the raw input lines 175 are fed into a single SMP-aware interrupt controller on the CPU. */ 176 typedef struct { 177 SysBusDevice parent_obj; 178 179 SysBusDevice *priv; 180 qemu_irq cpuic[32]; 181 qemu_irq rvic[4][64]; 182 uint32_t num_cpu; 183 } mpcore_rirq_state; 184 185 /* Map baseboard IRQs onto CPU IRQ lines. */ 186 static const int mpcore_irq_map[32] = { 187 -1, -1, -1, -1, 1, 2, -1, -1, 188 -1, -1, 6, -1, 4, 5, -1, -1, 189 -1, 14, 15, 0, 7, 8, -1, -1, 190 -1, -1, -1, -1, 9, 3, -1, -1, 191 }; 192 193 static void mpcore_rirq_set_irq(void *opaque, int irq, int level) 194 { 195 mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; 196 int i; 197 198 for (i = 0; i < 4; i++) { 199 qemu_set_irq(s->rvic[i][irq], level); 200 } 201 if (irq < 32) { 202 irq = mpcore_irq_map[irq]; 203 if (irq >= 0) { 204 qemu_set_irq(s->cpuic[irq], level); 205 } 206 } 207 } 208 209 static int realview_mpcore_init(SysBusDevice *sbd) 210 { 211 DeviceState *dev = DEVICE(sbd); 212 mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); 213 DeviceState *gic; 214 DeviceState *priv; 215 int n; 216 int i; 217 218 priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV); 219 qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); 220 qdev_init_nofail(priv); 221 s->priv = SYS_BUS_DEVICE(priv); 222 sysbus_pass_irq(sbd, s->priv); 223 for (i = 0; i < 32; i++) { 224 s->cpuic[i] = qdev_get_gpio_in(priv, i); 225 } 226 /* ??? IRQ routing is hardcoded to "normal" mode. */ 227 for (n = 0; n < 4; n++) { 228 gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, 229 s->cpuic[10 + n]); 230 for (i = 0; i < 64; i++) { 231 s->rvic[n][i] = qdev_get_gpio_in(gic, i); 232 } 233 } 234 qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); 235 sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0)); 236 return 0; 237 } 238 239 static Property mpcore_rirq_properties[] = { 240 DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), 241 DEFINE_PROP_END_OF_LIST(), 242 }; 243 244 static void mpcore_rirq_class_init(ObjectClass *klass, void *data) 245 { 246 DeviceClass *dc = DEVICE_CLASS(klass); 247 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 248 249 k->init = realview_mpcore_init; 250 dc->props = mpcore_rirq_properties; 251 } 252 253 static const TypeInfo mpcore_rirq_info = { 254 .name = TYPE_REALVIEW_MPCORE_RIRQ, 255 .parent = TYPE_SYS_BUS_DEVICE, 256 .instance_size = sizeof(mpcore_rirq_state), 257 .class_init = mpcore_rirq_class_init, 258 }; 259 260 static Property mpcore_priv_properties[] = { 261 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), 262 /* The ARM11 MPCORE TRM says the on-chip controller may have 263 * anything from 0 to 224 external interrupt IRQ lines (with another 264 * 32 internal). We default to 32+32, which is the number provided by 265 * the ARM11 MPCore test chip in the Realview Versatile Express 266 * coretile. Other boards may differ and should set this property 267 * appropriately. Some Linux kernels may not boot if the hardware 268 * has more IRQ lines than the kernel expects. 269 */ 270 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), 271 DEFINE_PROP_END_OF_LIST(), 272 }; 273 274 static void mpcore_priv_class_init(ObjectClass *klass, void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(klass); 277 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 278 279 k->init = mpcore_priv_init; 280 dc->props = mpcore_priv_properties; 281 } 282 283 static const TypeInfo mpcore_priv_info = { 284 .name = TYPE_ARM11MPCORE_PRIV, 285 .parent = TYPE_SYS_BUS_DEVICE, 286 .instance_size = sizeof(ARM11MPCorePriveState), 287 .instance_init = mpcore_priv_initfn, 288 .class_init = mpcore_priv_class_init, 289 }; 290 291 static void arm11mpcore_register_types(void) 292 { 293 type_register_static(&mpcore_rirq_info); 294 type_register_static(&mpcore_priv_info); 295 } 296 297 type_init(arm11mpcore_register_types) 298