1 /* 2 * QEMU model for the AXIS devboard 88. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "net/net.h" 28 #include "hw/block/flash.h" 29 #include "hw/boards.h" 30 #include "hw/cris/etraxfs.h" 31 #include "hw/loader.h" 32 #include "elf.h" 33 #include "boot.h" 34 #include "sysemu/block-backend.h" 35 #include "exec/address-spaces.h" 36 #include "sysemu/qtest.h" 37 38 #define D(x) 39 #define DNAND(x) 40 41 struct nand_state_t 42 { 43 DeviceState *nand; 44 MemoryRegion iomem; 45 unsigned int rdy:1; 46 unsigned int ale:1; 47 unsigned int cle:1; 48 unsigned int ce:1; 49 }; 50 51 static struct nand_state_t nand_state; 52 static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size) 53 { 54 struct nand_state_t *s = opaque; 55 uint32_t r; 56 int rdy; 57 58 r = nand_getio(s->nand); 59 nand_getpins(s->nand, &rdy); 60 s->rdy = rdy; 61 62 DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r)); 63 return r; 64 } 65 66 static void 67 nand_write(void *opaque, hwaddr addr, uint64_t value, 68 unsigned size) 69 { 70 struct nand_state_t *s = opaque; 71 int rdy; 72 73 DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value)); 74 nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0); 75 nand_setio(s->nand, value); 76 nand_getpins(s->nand, &rdy); 77 s->rdy = rdy; 78 } 79 80 static const MemoryRegionOps nand_ops = { 81 .read = nand_read, 82 .write = nand_write, 83 .endianness = DEVICE_NATIVE_ENDIAN, 84 }; 85 86 struct tempsensor_t 87 { 88 unsigned int shiftreg; 89 unsigned int count; 90 enum { 91 ST_OUT, ST_IN, ST_Z 92 } state; 93 94 uint16_t regs[3]; 95 }; 96 97 static void tempsensor_clkedge(struct tempsensor_t *s, 98 unsigned int clk, unsigned int data_in) 99 { 100 D(printf("%s clk=%d state=%d sr=%x\n", __func__, 101 clk, s->state, s->shiftreg)); 102 if (s->count == 0) { 103 s->count = 16; 104 s->state = ST_OUT; 105 } 106 switch (s->state) { 107 case ST_OUT: 108 /* Output reg is clocked at negedge. */ 109 if (!clk) { 110 s->count--; 111 s->shiftreg <<= 1; 112 if (s->count == 0) { 113 s->shiftreg = 0; 114 s->state = ST_IN; 115 s->count = 16; 116 } 117 } 118 break; 119 case ST_Z: 120 if (clk) { 121 s->count--; 122 if (s->count == 0) { 123 s->shiftreg = 0; 124 s->state = ST_OUT; 125 s->count = 16; 126 } 127 } 128 break; 129 case ST_IN: 130 /* Indata is sampled at posedge. */ 131 if (clk) { 132 s->count--; 133 s->shiftreg <<= 1; 134 s->shiftreg |= data_in & 1; 135 if (s->count == 0) { 136 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg)); 137 s->regs[0] = s->shiftreg; 138 s->state = ST_OUT; 139 s->count = 16; 140 141 if ((s->regs[0] & 0xff) == 0) { 142 /* 25 degrees celsius. */ 143 s->shiftreg = 0x0b9f; 144 } else if ((s->regs[0] & 0xff) == 0xff) { 145 /* Sensor ID, 0x8100 LM70. */ 146 s->shiftreg = 0x8100; 147 } else 148 printf("Invalid tempsens state %x\n", s->regs[0]); 149 } 150 } 151 break; 152 } 153 } 154 155 156 #define RW_PA_DOUT 0x00 157 #define R_PA_DIN 0x01 158 #define RW_PA_OE 0x02 159 #define RW_PD_DOUT 0x10 160 #define R_PD_DIN 0x11 161 #define RW_PD_OE 0x12 162 163 static struct gpio_state_t 164 { 165 MemoryRegion iomem; 166 struct nand_state_t *nand; 167 struct tempsensor_t tempsensor; 168 uint32_t regs[0x5c / 4]; 169 } gpio_state; 170 171 static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size) 172 { 173 struct gpio_state_t *s = opaque; 174 uint32_t r = 0; 175 176 addr >>= 2; 177 switch (addr) 178 { 179 case R_PA_DIN: 180 r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE]; 181 182 /* Encode pins from the nand. */ 183 r |= s->nand->rdy << 7; 184 break; 185 case R_PD_DIN: 186 r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE]; 187 188 /* Encode temp sensor pins. */ 189 r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4; 190 break; 191 192 default: 193 r = s->regs[addr]; 194 break; 195 } 196 return r; 197 D(printf("%s %x=%x\n", __func__, addr, r)); 198 } 199 200 static void gpio_write(void *opaque, hwaddr addr, uint64_t value, 201 unsigned size) 202 { 203 struct gpio_state_t *s = opaque; 204 D(printf("%s %x=%x\n", __func__, addr, (unsigned)value)); 205 206 addr >>= 2; 207 switch (addr) 208 { 209 case RW_PA_DOUT: 210 /* Decode nand pins. */ 211 s->nand->ale = !!(value & (1 << 6)); 212 s->nand->cle = !!(value & (1 << 5)); 213 s->nand->ce = !!(value & (1 << 4)); 214 215 s->regs[addr] = value; 216 break; 217 218 case RW_PD_DOUT: 219 /* Temp sensor clk. */ 220 if ((s->regs[addr] ^ value) & 2) 221 tempsensor_clkedge(&s->tempsensor, !!(value & 2), 222 !!(value & 16)); 223 s->regs[addr] = value; 224 break; 225 226 default: 227 s->regs[addr] = value; 228 break; 229 } 230 } 231 232 static const MemoryRegionOps gpio_ops = { 233 .read = gpio_read, 234 .write = gpio_write, 235 .endianness = DEVICE_NATIVE_ENDIAN, 236 .valid = { 237 .min_access_size = 4, 238 .max_access_size = 4, 239 }, 240 }; 241 242 #define INTMEM_SIZE (128 * 1024) 243 244 static struct cris_load_info li; 245 246 static 247 void axisdev88_init(MachineState *machine) 248 { 249 ram_addr_t ram_size = machine->ram_size; 250 const char *cpu_model = machine->cpu_model; 251 const char *kernel_filename = machine->kernel_filename; 252 const char *kernel_cmdline = machine->kernel_cmdline; 253 CRISCPU *cpu; 254 CPUCRISState *env; 255 DeviceState *dev; 256 SysBusDevice *s; 257 DriveInfo *nand; 258 qemu_irq irq[30], nmi[2]; 259 void *etraxfs_dmac; 260 struct etraxfs_dma_client *dma_eth; 261 int i; 262 MemoryRegion *address_space_mem = get_system_memory(); 263 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 264 MemoryRegion *phys_intmem = g_new(MemoryRegion, 1); 265 266 /* init CPUs */ 267 if (cpu_model == NULL) { 268 cpu_model = "crisv32"; 269 } 270 cpu = cpu_cris_init(cpu_model); 271 env = &cpu->env; 272 273 /* allocate RAM */ 274 memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram", 275 ram_size); 276 memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram); 277 278 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 279 internal memory. */ 280 memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE, 281 &error_fatal); 282 vmstate_register_ram_global(phys_intmem); 283 memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem); 284 285 /* Attach a NAND flash to CS1. */ 286 nand = drive_get(IF_MTD, 0, 0); 287 nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL, 288 NAND_MFR_STMICRO, 0x39); 289 memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state, 290 "nand", 0x05000000); 291 memory_region_add_subregion(address_space_mem, 0x10000000, 292 &nand_state.iomem); 293 294 gpio_state.nand = &nand_state; 295 memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state, 296 "gpio", 0x5c); 297 memory_region_add_subregion(address_space_mem, 0x3001a000, 298 &gpio_state.iomem); 299 300 301 dev = qdev_create(NULL, "etraxfs,pic"); 302 /* FIXME: Is there a proper way to signal vectors to the CPU core? */ 303 qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector); 304 qdev_init_nofail(dev); 305 s = SYS_BUS_DEVICE(dev); 306 sysbus_mmio_map(s, 0, 0x3001c000); 307 sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ)); 308 sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI)); 309 for (i = 0; i < 30; i++) { 310 irq[i] = qdev_get_gpio_in(dev, i); 311 } 312 nmi[0] = qdev_get_gpio_in(dev, 30); 313 nmi[1] = qdev_get_gpio_in(dev, 31); 314 315 etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10); 316 for (i = 0; i < 10; i++) { 317 /* On ETRAX, odd numbered channels are inputs. */ 318 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1); 319 } 320 321 /* Add the two ethernet blocks. */ 322 dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */ 323 etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]); 324 if (nb_nics > 1) { 325 etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]); 326 } 327 328 /* The DMA Connector block is missing, hardwire things for now. */ 329 etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]); 330 etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]); 331 if (nb_nics > 1) { 332 etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]); 333 etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]); 334 } 335 336 /* 2 timers. */ 337 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL); 338 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL); 339 340 for (i = 0; i < 4; i++) { 341 sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000, 342 irq[0x14 + i]); 343 } 344 345 if (kernel_filename) { 346 li.image_filename = kernel_filename; 347 li.cmdline = kernel_cmdline; 348 cris_load_image(cpu, &li); 349 } else if (!qtest_enabled()) { 350 fprintf(stderr, "Kernel image must be specified\n"); 351 exit(1); 352 } 353 } 354 355 static void axisdev88_machine_init(MachineClass *mc) 356 { 357 mc->desc = "AXIS devboard 88"; 358 mc->init = axisdev88_init; 359 mc->is_default = 1; 360 } 361 362 DEFINE_MACHINE("axis-dev88", axisdev88_machine_init) 363