xref: /qemu/hw/cxl/cxl-host.c (revision 118d4ed0) 
1 /*
2  * CXL host parameter parsing routines
3  *
4  * Copyright (c) 2022 Huawei
5  * Modeled loosely on the NUMA options handling in hw/core/numa.c
6  */
7 
8 #include "qemu/osdep.h"
9 #include "qemu/units.h"
10 #include "qemu/bitmap.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "sysemu/qtest.h"
14 #include "hw/boards.h"
15 
16 #include "qapi/qapi-visit-machine.h"
17 #include "hw/cxl/cxl.h"
18 #include "hw/cxl/cxl_host.h"
19 #include "hw/pci/pci_bus.h"
20 #include "hw/pci/pci_bridge.h"
21 #include "hw/pci/pci_host.h"
22 #include "hw/pci/pcie_port.h"
23 #include "hw/pci-bridge/pci_expander_bridge.h"
24 
25 static void cxl_fixed_memory_window_config(CXLState *cxl_state,
26                                            CXLFixedMemoryWindowOptions *object,
27                                            Error **errp)
28 {
29     CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
30     strList *target;
31     int i;
32 
33     for (target = object->targets; target; target = target->next) {
34         fw->num_targets++;
35     }
36 
37     fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
38     if (*errp) {
39         return;
40     }
41 
42     fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
43     for (i = 0, target = object->targets; target; i++, target = target->next) {
44         /* This link cannot be resolved yet, so stash the name for now */
45         fw->targets[i] = g_strdup(target->value);
46     }
47 
48     if (object->size % (256 * MiB)) {
49         error_setg(errp,
50                    "Size of a CXL fixed memory window must my a multiple of 256MiB");
51         return;
52     }
53     fw->size = object->size;
54 
55     if (object->has_interleave_granularity) {
56         fw->enc_int_gran =
57             cxl_interleave_granularity_enc(object->interleave_granularity,
58                                            errp);
59         if (*errp) {
60             return;
61         }
62     } else {
63         /* Default to 256 byte interleave */
64         fw->enc_int_gran = 0;
65     }
66 
67     cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, fw);
68 
69     return;
70 }
71 
72 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
73 {
74     if (cxl_state && cxl_state->fixed_windows) {
75         GList *it;
76 
77         for (it = cxl_state->fixed_windows; it; it = it->next) {
78             CXLFixedWindow *fw = it->data;
79             int i;
80 
81             for (i = 0; i < fw->num_targets; i++) {
82                 Object *o;
83                 bool ambig;
84 
85                 o = object_resolve_path_type(fw->targets[i],
86                                              TYPE_PXB_CXL_DEVICE,
87                                              &ambig);
88                 if (!o) {
89                     error_setg(errp, "Could not resolve CXLFM target %s",
90                                fw->targets[i]);
91                     return;
92                 }
93                 fw->target_hbs[i] = PXB_CXL_DEV(o);
94             }
95         }
96     }
97 }
98 
99 /* TODO: support, multiple hdm decoders */
100 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
101                                 uint8_t *target)
102 {
103     uint32_t ctrl;
104     uint32_t ig_enc;
105     uint32_t iw_enc;
106     uint32_t target_reg;
107     uint32_t target_idx;
108 
109     ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
110     if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
111         return false;
112     }
113 
114     ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
115     iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
116     target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
117 
118     if (target_idx > 4) {
119         target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
120         target_reg >>= target_idx * 8;
121     } else {
122         target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
123         target_reg >>= (target_idx - 4) * 8;
124     }
125     *target = target_reg & 0xff;
126 
127     return true;
128 }
129 
130 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
131 {
132     CXLComponentState *hb_cstate, *usp_cstate;
133     PCIHostState *hb;
134     CXLUpstreamPort *usp;
135     int rb_index;
136     uint32_t *cache_mem;
137     uint8_t target;
138     bool target_found;
139     PCIDevice *rp, *d;
140 
141     /* Address is relative to memory region. Convert to HPA */
142     addr += fw->base;
143 
144     rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
145     hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
146     if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
147         return NULL;
148     }
149 
150     hb_cstate = cxl_get_hb_cstate(hb);
151     if (!hb_cstate) {
152         return NULL;
153     }
154 
155     cache_mem = hb_cstate->crb.cache_mem_registers;
156 
157     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
158     if (!target_found) {
159         return NULL;
160     }
161 
162     rp = pcie_find_port_by_pn(hb->bus, target);
163     if (!rp) {
164         return NULL;
165     }
166 
167     d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
168     if (!d) {
169         return NULL;
170     }
171 
172     if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
173         return d;
174     }
175 
176     /*
177      * Could also be a switch.  Note only one level of switching currently
178      * supported.
179      */
180     if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) {
181         return NULL;
182     }
183     usp = CXL_USP(d);
184 
185     usp_cstate = cxl_usp_to_cstate(usp);
186     if (!usp_cstate) {
187         return NULL;
188     }
189 
190     cache_mem = usp_cstate->crb.cache_mem_registers;
191 
192     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
193     if (!target_found) {
194         return NULL;
195     }
196 
197     d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);
198     if (!d) {
199         return NULL;
200     }
201 
202     d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0];
203     if (!d) {
204         return NULL;
205     }
206 
207     if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
208         return NULL;
209     }
210 
211     return d;
212 }
213 
214 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
215                                   unsigned size, MemTxAttrs attrs)
216 {
217     CXLFixedWindow *fw = opaque;
218     PCIDevice *d;
219 
220     d = cxl_cfmws_find_device(fw, addr);
221     if (d == NULL) {
222         *data = 0;
223         /* Reads to invalid address return poison */
224         return MEMTX_ERROR;
225     }
226 
227     return cxl_type3_read(d, addr + fw->base, data, size, attrs);
228 }
229 
230 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
231                                    uint64_t data, unsigned size,
232                                    MemTxAttrs attrs)
233 {
234     CXLFixedWindow *fw = opaque;
235     PCIDevice *d;
236 
237     d = cxl_cfmws_find_device(fw, addr);
238     if (d == NULL) {
239         /* Writes to invalid address are silent */
240         return MEMTX_OK;
241     }
242 
243     return cxl_type3_write(d, addr + fw->base, data, size, attrs);
244 }
245 
246 const MemoryRegionOps cfmws_ops = {
247     .read_with_attrs = cxl_read_cfmws,
248     .write_with_attrs = cxl_write_cfmws,
249     .endianness = DEVICE_LITTLE_ENDIAN,
250     .valid = {
251         .min_access_size = 1,
252         .max_access_size = 8,
253         .unaligned = true,
254     },
255     .impl = {
256         .min_access_size = 1,
257         .max_access_size = 8,
258         .unaligned = true,
259     },
260 };
261 
262 static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
263                             void *opaque, Error **errp)
264 {
265     CXLState *cxl_state = opaque;
266     bool value = cxl_state->is_enabled;
267 
268     visit_type_bool(v, name, &value, errp);
269 }
270 
271 static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
272                             void *opaque, Error **errp)
273 {
274     CXLState *cxl_state = opaque;
275     bool value;
276 
277     if (!visit_type_bool(v, name, &value, errp)) {
278         return;
279     }
280     cxl_state->is_enabled = value;
281 }
282 
283 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
284                              void *opaque, Error **errp)
285 {
286     CXLFixedMemoryWindowOptionsList **list = opaque;
287 
288     visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
289 }
290 
291 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
292                              void *opaque, Error **errp)
293 {
294     CXLState *state = opaque;
295     CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
296     CXLFixedMemoryWindowOptionsList *it;
297 
298     visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
299     if (!cfmw_list) {
300         return;
301     }
302 
303     for (it = cfmw_list; it; it = it->next) {
304         cxl_fixed_memory_window_config(state, it->value, errp);
305     }
306     state->cfmw_list = cfmw_list;
307 }
308 
309 void cxl_machine_init(Object *obj, CXLState *state)
310 {
311     object_property_add(obj, "cxl", "bool", machine_get_cxl,
312                         machine_set_cxl, NULL, state);
313     object_property_set_description(obj, "cxl",
314                                     "Set on/off to enable/disable "
315                                     "CXL instantiation");
316 
317     object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
318                         machine_get_cfmw, machine_set_cfmw,
319                         NULL, state);
320     object_property_set_description(obj, "cxl-fmw",
321                                     "CXL Fixed Memory Windows (array)");
322 }
323 
324 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
325 {
326     /* Walk the pci busses looking for pxb busses to hook up */
327     if (bus) {
328         QLIST_FOREACH(bus, &bus->child, sibling) {
329             if (!pci_bus_is_root(bus)) {
330                 continue;
331             }
332             if (pci_bus_is_cxl(bus)) {
333                 if (!state->is_enabled) {
334                     error_setg(errp, "CXL host bridges present, but cxl=off");
335                     return;
336                 }
337                 pxb_cxl_hook_up_registers(state, bus, errp);
338             }
339         }
340     }
341 }
342