1 /* 2 * QEMU CG3 Frame buffer 3 * 4 * Copyright (c) 2012 Bob Breuer 5 * Copyright (c) 2013 Mark Cave-Ayland 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "qemu/error-report.h" 30 #include "ui/console.h" 31 #include "hw/sysbus.h" 32 #include "hw/loader.h" 33 #include "qemu/log.h" 34 35 /* Change to 1 to enable debugging */ 36 #define DEBUG_CG3 0 37 38 #define CG3_ROM_FILE "QEMU,cgthree.bin" 39 #define FCODE_MAX_ROM_SIZE 0x10000 40 41 #define CG3_REG_SIZE 0x20 42 43 #define CG3_REG_BT458_ADDR 0x0 44 #define CG3_REG_BT458_COLMAP 0x4 45 #define CG3_REG_FBC_CTRL 0x10 46 #define CG3_REG_FBC_STATUS 0x11 47 #define CG3_REG_FBC_CURSTART 0x12 48 #define CG3_REG_FBC_CUREND 0x13 49 #define CG3_REG_FBC_VCTRL 0x14 50 51 /* Control register flags */ 52 #define CG3_CR_ENABLE_INTS 0x80 53 54 /* Status register flags */ 55 #define CG3_SR_PENDING_INT 0x80 56 #define CG3_SR_1152_900_76_B 0x60 57 #define CG3_SR_ID_COLOR 0x01 58 59 #define CG3_VRAM_SIZE 0x100000 60 #define CG3_VRAM_OFFSET 0x800000 61 62 #define DPRINTF(fmt, ...) do { \ 63 if (DEBUG_CG3) { \ 64 printf("CG3: " fmt , ## __VA_ARGS__); \ 65 } \ 66 } while (0); 67 68 #define TYPE_CG3 "cgthree" 69 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3) 70 71 typedef struct CG3State { 72 SysBusDevice parent_obj; 73 74 QemuConsole *con; 75 qemu_irq irq; 76 hwaddr prom_addr; 77 MemoryRegion vram_mem; 78 MemoryRegion rom; 79 MemoryRegion reg; 80 uint32_t vram_size; 81 int full_update; 82 uint8_t regs[16]; 83 uint8_t r[256], g[256], b[256]; 84 uint16_t width, height, depth; 85 uint8_t dac_index, dac_state; 86 } CG3State; 87 88 static void cg3_update_display(void *opaque) 89 { 90 CG3State *s = opaque; 91 DisplaySurface *surface = qemu_console_surface(s->con); 92 const uint8_t *pix; 93 uint32_t *data; 94 uint32_t dval; 95 int x, y, y_start; 96 unsigned int width, height; 97 ram_addr_t page, page_min, page_max; 98 99 if (surface_bits_per_pixel(surface) != 32) { 100 return; 101 } 102 width = s->width; 103 height = s->height; 104 105 y_start = -1; 106 page_min = -1; 107 page_max = 0; 108 page = 0; 109 pix = memory_region_get_ram_ptr(&s->vram_mem); 110 data = (uint32_t *)surface_data(surface); 111 112 memory_region_sync_dirty_bitmap(&s->vram_mem); 113 for (y = 0; y < height; y++) { 114 int update = s->full_update; 115 116 page = y * width; 117 update |= memory_region_get_dirty(&s->vram_mem, page, width, 118 DIRTY_MEMORY_VGA); 119 if (update) { 120 if (y_start < 0) { 121 y_start = y; 122 } 123 if (page < page_min) { 124 page_min = page; 125 } 126 if (page > page_max) { 127 page_max = page; 128 } 129 130 for (x = 0; x < width; x++) { 131 dval = *pix++; 132 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval]; 133 *data++ = dval; 134 } 135 } else { 136 if (y_start >= 0) { 137 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start); 138 y_start = -1; 139 } 140 pix += width; 141 data += width; 142 } 143 } 144 s->full_update = 0; 145 if (y_start >= 0) { 146 dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start); 147 } 148 if (page_max >= page_min) { 149 memory_region_reset_dirty(&s->vram_mem, 150 page_min, page_max - page_min, DIRTY_MEMORY_VGA); 151 } 152 /* vsync interrupt? */ 153 if (s->regs[0] & CG3_CR_ENABLE_INTS) { 154 s->regs[1] |= CG3_SR_PENDING_INT; 155 qemu_irq_raise(s->irq); 156 } 157 } 158 159 static void cg3_invalidate_display(void *opaque) 160 { 161 CG3State *s = opaque; 162 163 memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE); 164 } 165 166 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size) 167 { 168 CG3State *s = opaque; 169 int val; 170 171 switch (addr) { 172 case CG3_REG_BT458_ADDR: 173 case CG3_REG_BT458_COLMAP: 174 val = 0; 175 break; 176 case CG3_REG_FBC_CTRL: 177 val = s->regs[0]; 178 break; 179 case CG3_REG_FBC_STATUS: 180 /* monitor ID 6, board type = 1 (color) */ 181 val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR; 182 break; 183 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 184 val = s->regs[addr - 0x10]; 185 break; 186 default: 187 qemu_log_mask(LOG_UNIMP, 188 "cg3: Unimplemented register read " 189 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 190 addr, size); 191 val = 0; 192 break; 193 } 194 DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr); 195 return val; 196 } 197 198 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val, 199 unsigned size) 200 { 201 CG3State *s = opaque; 202 uint8_t regval; 203 int i; 204 205 DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n", 206 val, addr, size); 207 208 switch (addr) { 209 case CG3_REG_BT458_ADDR: 210 s->dac_index = val; 211 s->dac_state = 0; 212 break; 213 case CG3_REG_BT458_COLMAP: 214 /* This register can be written to as either a long word or a byte */ 215 if (size == 1) { 216 val <<= 24; 217 } 218 219 for (i = 0; i < size; i++) { 220 regval = val >> 24; 221 222 switch (s->dac_state) { 223 case 0: 224 s->r[s->dac_index] = regval; 225 s->dac_state++; 226 break; 227 case 1: 228 s->g[s->dac_index] = regval; 229 s->dac_state++; 230 break; 231 case 2: 232 s->b[s->dac_index] = regval; 233 /* Index autoincrement */ 234 s->dac_index = (s->dac_index + 1) & 0xff; 235 default: 236 s->dac_state = 0; 237 break; 238 } 239 val <<= 8; 240 } 241 s->full_update = 1; 242 break; 243 case CG3_REG_FBC_CTRL: 244 s->regs[0] = val; 245 break; 246 case CG3_REG_FBC_STATUS: 247 if (s->regs[1] & CG3_SR_PENDING_INT) { 248 /* clear interrupt */ 249 s->regs[1] &= ~CG3_SR_PENDING_INT; 250 qemu_irq_lower(s->irq); 251 } 252 break; 253 case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1: 254 s->regs[addr - 0x10] = val; 255 break; 256 default: 257 qemu_log_mask(LOG_UNIMP, 258 "cg3: Unimplemented register write " 259 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 260 addr, size, val); 261 break; 262 } 263 } 264 265 static const MemoryRegionOps cg3_reg_ops = { 266 .read = cg3_reg_read, 267 .write = cg3_reg_write, 268 .endianness = DEVICE_NATIVE_ENDIAN, 269 .valid = { 270 .min_access_size = 1, 271 .max_access_size = 4, 272 }, 273 }; 274 275 static const GraphicHwOps cg3_ops = { 276 .invalidate = cg3_invalidate_display, 277 .gfx_update = cg3_update_display, 278 }; 279 280 static void cg3_initfn(Object *obj) 281 { 282 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 283 CG3State *s = CG3(obj); 284 285 memory_region_init_ram(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE, 286 &error_fatal); 287 memory_region_set_readonly(&s->rom, true); 288 sysbus_init_mmio(sbd, &s->rom); 289 290 memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg", 291 CG3_REG_SIZE); 292 sysbus_init_mmio(sbd, &s->reg); 293 } 294 295 static void cg3_realizefn(DeviceState *dev, Error **errp) 296 { 297 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 298 CG3State *s = CG3(dev); 299 int ret; 300 char *fcode_filename; 301 302 /* FCode ROM */ 303 vmstate_register_ram_global(&s->rom); 304 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE); 305 if (fcode_filename) { 306 ret = load_image_mr(fcode_filename, &s->rom); 307 g_free(fcode_filename); 308 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 309 error_report("cg3: could not load prom '%s'", CG3_ROM_FILE); 310 } 311 } 312 313 memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, 314 &error_fatal); 315 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 316 vmstate_register_ram_global(&s->vram_mem); 317 sysbus_init_mmio(sbd, &s->vram_mem); 318 319 sysbus_init_irq(sbd, &s->irq); 320 321 s->con = graphic_console_init(DEVICE(dev), 0, &cg3_ops, s); 322 qemu_console_resize(s->con, s->width, s->height); 323 } 324 325 static int vmstate_cg3_post_load(void *opaque, int version_id) 326 { 327 CG3State *s = opaque; 328 329 cg3_invalidate_display(s); 330 331 return 0; 332 } 333 334 static const VMStateDescription vmstate_cg3 = { 335 .name = "cg3", 336 .version_id = 1, 337 .minimum_version_id = 1, 338 .post_load = vmstate_cg3_post_load, 339 .fields = (VMStateField[]) { 340 VMSTATE_UINT16(height, CG3State), 341 VMSTATE_UINT16(width, CG3State), 342 VMSTATE_UINT16(depth, CG3State), 343 VMSTATE_BUFFER(r, CG3State), 344 VMSTATE_BUFFER(g, CG3State), 345 VMSTATE_BUFFER(b, CG3State), 346 VMSTATE_UINT8(dac_index, CG3State), 347 VMSTATE_UINT8(dac_state, CG3State), 348 VMSTATE_END_OF_LIST() 349 } 350 }; 351 352 static void cg3_reset(DeviceState *d) 353 { 354 CG3State *s = CG3(d); 355 356 /* Initialize palette */ 357 memset(s->r, 0, 256); 358 memset(s->g, 0, 256); 359 memset(s->b, 0, 256); 360 361 s->dac_state = 0; 362 s->full_update = 1; 363 qemu_irq_lower(s->irq); 364 } 365 366 static Property cg3_properties[] = { 367 DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1), 368 DEFINE_PROP_UINT16("width", CG3State, width, -1), 369 DEFINE_PROP_UINT16("height", CG3State, height, -1), 370 DEFINE_PROP_UINT16("depth", CG3State, depth, -1), 371 DEFINE_PROP_END_OF_LIST(), 372 }; 373 374 static void cg3_class_init(ObjectClass *klass, void *data) 375 { 376 DeviceClass *dc = DEVICE_CLASS(klass); 377 378 dc->realize = cg3_realizefn; 379 dc->reset = cg3_reset; 380 dc->vmsd = &vmstate_cg3; 381 dc->props = cg3_properties; 382 } 383 384 static const TypeInfo cg3_info = { 385 .name = TYPE_CG3, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(CG3State), 388 .instance_init = cg3_initfn, 389 .class_init = cg3_class_init, 390 }; 391 392 static void cg3_register_types(void) 393 { 394 type_register_static(&cg3_info); 395 } 396 397 type_init(cg3_register_types) 398