1 /* 2 * QEMU Cirrus CLGD 54xx VGA Emulator. 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * Copyright (c) 2004 Makoto Suzuki (suzu) 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * Reference: Finn Thogersons' VGADOC4b 27 * available at http://home.worldonline.dk/~finth/ 28 */ 29 #include "hw/hw.h" 30 #include "hw/pci/pci.h" 31 #include "ui/console.h" 32 #include "ui/pixel_ops.h" 33 #include "vga_int.h" 34 #include "hw/loader.h" 35 36 /* 37 * TODO: 38 * - destination write mask support not complete (bits 5..7) 39 * - optimize linear mappings 40 * - optimize bitblt functions 41 */ 42 43 //#define DEBUG_CIRRUS 44 //#define DEBUG_BITBLT 45 46 /*************************************** 47 * 48 * definitions 49 * 50 ***************************************/ 51 52 // ID 53 #define CIRRUS_ID_CLGD5422 (0x23<<2) 54 #define CIRRUS_ID_CLGD5426 (0x24<<2) 55 #define CIRRUS_ID_CLGD5424 (0x25<<2) 56 #define CIRRUS_ID_CLGD5428 (0x26<<2) 57 #define CIRRUS_ID_CLGD5430 (0x28<<2) 58 #define CIRRUS_ID_CLGD5434 (0x2A<<2) 59 #define CIRRUS_ID_CLGD5436 (0x2B<<2) 60 #define CIRRUS_ID_CLGD5446 (0x2E<<2) 61 62 // sequencer 0x07 63 #define CIRRUS_SR7_BPP_VGA 0x00 64 #define CIRRUS_SR7_BPP_SVGA 0x01 65 #define CIRRUS_SR7_BPP_MASK 0x0e 66 #define CIRRUS_SR7_BPP_8 0x00 67 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 68 #define CIRRUS_SR7_BPP_24 0x04 69 #define CIRRUS_SR7_BPP_16 0x06 70 #define CIRRUS_SR7_BPP_32 0x08 71 #define CIRRUS_SR7_ISAADDR_MASK 0xe0 72 73 // sequencer 0x0f 74 #define CIRRUS_MEMSIZE_512k 0x08 75 #define CIRRUS_MEMSIZE_1M 0x10 76 #define CIRRUS_MEMSIZE_2M 0x18 77 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. 78 79 // sequencer 0x12 80 #define CIRRUS_CURSOR_SHOW 0x01 81 #define CIRRUS_CURSOR_HIDDENPEL 0x02 82 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear 83 84 // sequencer 0x17 85 #define CIRRUS_BUSTYPE_VLBFAST 0x10 86 #define CIRRUS_BUSTYPE_PCI 0x20 87 #define CIRRUS_BUSTYPE_VLBSLOW 0x30 88 #define CIRRUS_BUSTYPE_ISA 0x38 89 #define CIRRUS_MMIO_ENABLE 0x04 90 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. 91 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 92 93 // control 0x0b 94 #define CIRRUS_BANKING_DUAL 0x01 95 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k 96 97 // control 0x30 98 #define CIRRUS_BLTMODE_BACKWARDS 0x01 99 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 100 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 101 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 102 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 103 #define CIRRUS_BLTMODE_COLOREXPAND 0x80 104 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 105 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 106 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 107 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 108 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 109 110 // control 0x31 111 #define CIRRUS_BLT_BUSY 0x01 112 #define CIRRUS_BLT_START 0x02 113 #define CIRRUS_BLT_RESET 0x04 114 #define CIRRUS_BLT_FIFOUSED 0x10 115 #define CIRRUS_BLT_AUTOSTART 0x80 116 117 // control 0x32 118 #define CIRRUS_ROP_0 0x00 119 #define CIRRUS_ROP_SRC_AND_DST 0x05 120 #define CIRRUS_ROP_NOP 0x06 121 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 122 #define CIRRUS_ROP_NOTDST 0x0b 123 #define CIRRUS_ROP_SRC 0x0d 124 #define CIRRUS_ROP_1 0x0e 125 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 126 #define CIRRUS_ROP_SRC_XOR_DST 0x59 127 #define CIRRUS_ROP_SRC_OR_DST 0x6d 128 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 129 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 130 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad 131 #define CIRRUS_ROP_NOTSRC 0xd0 132 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 133 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda 134 135 #define CIRRUS_ROP_NOP_INDEX 2 136 #define CIRRUS_ROP_SRC_INDEX 5 137 138 // control 0x33 139 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 140 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 141 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 142 143 // memory-mapped IO 144 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword 145 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword 146 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word 147 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word 148 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word 149 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word 150 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword 151 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword 152 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte 153 #define CIRRUS_MMIO_BLTMODE 0x18 // byte 154 #define CIRRUS_MMIO_BLTROP 0x1a // byte 155 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte 156 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? 157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? 158 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word 159 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word 160 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word 161 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word 162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte 163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte 164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte 165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte 166 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word 167 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word 168 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word 169 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word 170 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte 171 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte 172 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte 173 174 #define CIRRUS_PNPMMIO_SIZE 0x1000 175 176 struct CirrusVGAState; 177 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, 178 uint8_t * dst, const uint8_t * src, 179 int dstpitch, int srcpitch, 180 int bltwidth, int bltheight); 181 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, 182 uint8_t *dst, int dst_pitch, int width, int height); 183 184 typedef struct CirrusVGAState { 185 VGACommonState vga; 186 187 MemoryRegion cirrus_vga_io; 188 MemoryRegion cirrus_linear_io; 189 MemoryRegion cirrus_linear_bitblt_io; 190 MemoryRegion cirrus_mmio_io; 191 MemoryRegion pci_bar; 192 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */ 193 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */ 194 MemoryRegion low_mem; /* always mapped, overridden by: */ 195 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */ 196 uint32_t cirrus_addr_mask; 197 uint32_t linear_mmio_mask; 198 uint8_t cirrus_shadow_gr0; 199 uint8_t cirrus_shadow_gr1; 200 uint8_t cirrus_hidden_dac_lockindex; 201 uint8_t cirrus_hidden_dac_data; 202 uint32_t cirrus_bank_base[2]; 203 uint32_t cirrus_bank_limit[2]; 204 uint8_t cirrus_hidden_palette[48]; 205 int cirrus_blt_pixelwidth; 206 int cirrus_blt_width; 207 int cirrus_blt_height; 208 int cirrus_blt_dstpitch; 209 int cirrus_blt_srcpitch; 210 uint32_t cirrus_blt_fgcol; 211 uint32_t cirrus_blt_bgcol; 212 uint32_t cirrus_blt_dstaddr; 213 uint32_t cirrus_blt_srcaddr; 214 uint8_t cirrus_blt_mode; 215 uint8_t cirrus_blt_modeext; 216 cirrus_bitblt_rop_t cirrus_rop; 217 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ 218 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; 219 uint8_t *cirrus_srcptr; 220 uint8_t *cirrus_srcptr_end; 221 uint32_t cirrus_srccounter; 222 /* hwcursor display state */ 223 int last_hw_cursor_size; 224 int last_hw_cursor_x; 225 int last_hw_cursor_y; 226 int last_hw_cursor_y_start; 227 int last_hw_cursor_y_end; 228 int real_vram_size; /* XXX: suppress that */ 229 int device_id; 230 int bustype; 231 } CirrusVGAState; 232 233 typedef struct PCICirrusVGAState { 234 PCIDevice dev; 235 CirrusVGAState cirrus_vga; 236 } PCICirrusVGAState; 237 238 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga" 239 #define PCI_CIRRUS_VGA(obj) \ 240 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA) 241 242 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga" 243 #define ISA_CIRRUS_VGA(obj) \ 244 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA) 245 246 typedef struct ISACirrusVGAState { 247 ISADevice parent_obj; 248 249 CirrusVGAState cirrus_vga; 250 } ISACirrusVGAState; 251 252 static uint8_t rop_to_index[256]; 253 254 /*************************************** 255 * 256 * prototypes. 257 * 258 ***************************************/ 259 260 261 static void cirrus_bitblt_reset(CirrusVGAState *s); 262 static void cirrus_update_memory_access(CirrusVGAState *s); 263 264 /*************************************** 265 * 266 * raster operations 267 * 268 ***************************************/ 269 270 static bool blit_region_is_unsafe(struct CirrusVGAState *s, 271 int32_t pitch, int32_t addr) 272 { 273 if (pitch < 0) { 274 int64_t min = addr 275 + ((int64_t)s->cirrus_blt_height-1) * pitch; 276 int32_t max = addr 277 + s->cirrus_blt_width; 278 if (min < 0 || max >= s->vga.vram_size) { 279 return true; 280 } 281 } else { 282 int64_t max = addr 283 + ((int64_t)s->cirrus_blt_height-1) * pitch 284 + s->cirrus_blt_width; 285 if (max >= s->vga.vram_size) { 286 return true; 287 } 288 } 289 return false; 290 } 291 292 static bool blit_is_unsafe(struct CirrusVGAState *s) 293 { 294 /* should be the case, see cirrus_bitblt_start */ 295 assert(s->cirrus_blt_width > 0); 296 assert(s->cirrus_blt_height > 0); 297 298 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) { 299 return true; 300 } 301 302 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch, 303 s->cirrus_blt_dstaddr & s->cirrus_addr_mask)) { 304 return true; 305 } 306 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch, 307 s->cirrus_blt_srcaddr & s->cirrus_addr_mask)) { 308 return true; 309 } 310 311 return false; 312 } 313 314 static void cirrus_bitblt_rop_nop(CirrusVGAState *s, 315 uint8_t *dst,const uint8_t *src, 316 int dstpitch,int srcpitch, 317 int bltwidth,int bltheight) 318 { 319 } 320 321 static void cirrus_bitblt_fill_nop(CirrusVGAState *s, 322 uint8_t *dst, 323 int dstpitch, int bltwidth,int bltheight) 324 { 325 } 326 327 #define ROP_NAME 0 328 #define ROP_FN(d, s) 0 329 #include "cirrus_vga_rop.h" 330 331 #define ROP_NAME src_and_dst 332 #define ROP_FN(d, s) (s) & (d) 333 #include "cirrus_vga_rop.h" 334 335 #define ROP_NAME src_and_notdst 336 #define ROP_FN(d, s) (s) & (~(d)) 337 #include "cirrus_vga_rop.h" 338 339 #define ROP_NAME notdst 340 #define ROP_FN(d, s) ~(d) 341 #include "cirrus_vga_rop.h" 342 343 #define ROP_NAME src 344 #define ROP_FN(d, s) s 345 #include "cirrus_vga_rop.h" 346 347 #define ROP_NAME 1 348 #define ROP_FN(d, s) ~0 349 #include "cirrus_vga_rop.h" 350 351 #define ROP_NAME notsrc_and_dst 352 #define ROP_FN(d, s) (~(s)) & (d) 353 #include "cirrus_vga_rop.h" 354 355 #define ROP_NAME src_xor_dst 356 #define ROP_FN(d, s) (s) ^ (d) 357 #include "cirrus_vga_rop.h" 358 359 #define ROP_NAME src_or_dst 360 #define ROP_FN(d, s) (s) | (d) 361 #include "cirrus_vga_rop.h" 362 363 #define ROP_NAME notsrc_or_notdst 364 #define ROP_FN(d, s) (~(s)) | (~(d)) 365 #include "cirrus_vga_rop.h" 366 367 #define ROP_NAME src_notxor_dst 368 #define ROP_FN(d, s) ~((s) ^ (d)) 369 #include "cirrus_vga_rop.h" 370 371 #define ROP_NAME src_or_notdst 372 #define ROP_FN(d, s) (s) | (~(d)) 373 #include "cirrus_vga_rop.h" 374 375 #define ROP_NAME notsrc 376 #define ROP_FN(d, s) (~(s)) 377 #include "cirrus_vga_rop.h" 378 379 #define ROP_NAME notsrc_or_dst 380 #define ROP_FN(d, s) (~(s)) | (d) 381 #include "cirrus_vga_rop.h" 382 383 #define ROP_NAME notsrc_and_notdst 384 #define ROP_FN(d, s) (~(s)) & (~(d)) 385 #include "cirrus_vga_rop.h" 386 387 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { 388 cirrus_bitblt_rop_fwd_0, 389 cirrus_bitblt_rop_fwd_src_and_dst, 390 cirrus_bitblt_rop_nop, 391 cirrus_bitblt_rop_fwd_src_and_notdst, 392 cirrus_bitblt_rop_fwd_notdst, 393 cirrus_bitblt_rop_fwd_src, 394 cirrus_bitblt_rop_fwd_1, 395 cirrus_bitblt_rop_fwd_notsrc_and_dst, 396 cirrus_bitblt_rop_fwd_src_xor_dst, 397 cirrus_bitblt_rop_fwd_src_or_dst, 398 cirrus_bitblt_rop_fwd_notsrc_or_notdst, 399 cirrus_bitblt_rop_fwd_src_notxor_dst, 400 cirrus_bitblt_rop_fwd_src_or_notdst, 401 cirrus_bitblt_rop_fwd_notsrc, 402 cirrus_bitblt_rop_fwd_notsrc_or_dst, 403 cirrus_bitblt_rop_fwd_notsrc_and_notdst, 404 }; 405 406 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { 407 cirrus_bitblt_rop_bkwd_0, 408 cirrus_bitblt_rop_bkwd_src_and_dst, 409 cirrus_bitblt_rop_nop, 410 cirrus_bitblt_rop_bkwd_src_and_notdst, 411 cirrus_bitblt_rop_bkwd_notdst, 412 cirrus_bitblt_rop_bkwd_src, 413 cirrus_bitblt_rop_bkwd_1, 414 cirrus_bitblt_rop_bkwd_notsrc_and_dst, 415 cirrus_bitblt_rop_bkwd_src_xor_dst, 416 cirrus_bitblt_rop_bkwd_src_or_dst, 417 cirrus_bitblt_rop_bkwd_notsrc_or_notdst, 418 cirrus_bitblt_rop_bkwd_src_notxor_dst, 419 cirrus_bitblt_rop_bkwd_src_or_notdst, 420 cirrus_bitblt_rop_bkwd_notsrc, 421 cirrus_bitblt_rop_bkwd_notsrc_or_dst, 422 cirrus_bitblt_rop_bkwd_notsrc_and_notdst, 423 }; 424 425 #define TRANSP_ROP(name) {\ 426 name ## _8,\ 427 name ## _16,\ 428 } 429 #define TRANSP_NOP(func) {\ 430 func,\ 431 func,\ 432 } 433 434 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { 435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), 436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), 437 TRANSP_NOP(cirrus_bitblt_rop_nop), 438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), 439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), 440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), 441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), 442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), 443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), 444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), 445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), 446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), 447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), 448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), 449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), 450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), 451 }; 452 453 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { 454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), 455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), 456 TRANSP_NOP(cirrus_bitblt_rop_nop), 457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), 458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), 459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), 460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), 461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), 462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), 463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), 464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), 465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), 466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), 467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), 468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), 469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), 470 }; 471 472 #define ROP2(name) {\ 473 name ## _8,\ 474 name ## _16,\ 475 name ## _24,\ 476 name ## _32,\ 477 } 478 479 #define ROP_NOP2(func) {\ 480 func,\ 481 func,\ 482 func,\ 483 func,\ 484 } 485 486 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { 487 ROP2(cirrus_patternfill_0), 488 ROP2(cirrus_patternfill_src_and_dst), 489 ROP_NOP2(cirrus_bitblt_rop_nop), 490 ROP2(cirrus_patternfill_src_and_notdst), 491 ROP2(cirrus_patternfill_notdst), 492 ROP2(cirrus_patternfill_src), 493 ROP2(cirrus_patternfill_1), 494 ROP2(cirrus_patternfill_notsrc_and_dst), 495 ROP2(cirrus_patternfill_src_xor_dst), 496 ROP2(cirrus_patternfill_src_or_dst), 497 ROP2(cirrus_patternfill_notsrc_or_notdst), 498 ROP2(cirrus_patternfill_src_notxor_dst), 499 ROP2(cirrus_patternfill_src_or_notdst), 500 ROP2(cirrus_patternfill_notsrc), 501 ROP2(cirrus_patternfill_notsrc_or_dst), 502 ROP2(cirrus_patternfill_notsrc_and_notdst), 503 }; 504 505 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { 506 ROP2(cirrus_colorexpand_transp_0), 507 ROP2(cirrus_colorexpand_transp_src_and_dst), 508 ROP_NOP2(cirrus_bitblt_rop_nop), 509 ROP2(cirrus_colorexpand_transp_src_and_notdst), 510 ROP2(cirrus_colorexpand_transp_notdst), 511 ROP2(cirrus_colorexpand_transp_src), 512 ROP2(cirrus_colorexpand_transp_1), 513 ROP2(cirrus_colorexpand_transp_notsrc_and_dst), 514 ROP2(cirrus_colorexpand_transp_src_xor_dst), 515 ROP2(cirrus_colorexpand_transp_src_or_dst), 516 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), 517 ROP2(cirrus_colorexpand_transp_src_notxor_dst), 518 ROP2(cirrus_colorexpand_transp_src_or_notdst), 519 ROP2(cirrus_colorexpand_transp_notsrc), 520 ROP2(cirrus_colorexpand_transp_notsrc_or_dst), 521 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), 522 }; 523 524 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { 525 ROP2(cirrus_colorexpand_0), 526 ROP2(cirrus_colorexpand_src_and_dst), 527 ROP_NOP2(cirrus_bitblt_rop_nop), 528 ROP2(cirrus_colorexpand_src_and_notdst), 529 ROP2(cirrus_colorexpand_notdst), 530 ROP2(cirrus_colorexpand_src), 531 ROP2(cirrus_colorexpand_1), 532 ROP2(cirrus_colorexpand_notsrc_and_dst), 533 ROP2(cirrus_colorexpand_src_xor_dst), 534 ROP2(cirrus_colorexpand_src_or_dst), 535 ROP2(cirrus_colorexpand_notsrc_or_notdst), 536 ROP2(cirrus_colorexpand_src_notxor_dst), 537 ROP2(cirrus_colorexpand_src_or_notdst), 538 ROP2(cirrus_colorexpand_notsrc), 539 ROP2(cirrus_colorexpand_notsrc_or_dst), 540 ROP2(cirrus_colorexpand_notsrc_and_notdst), 541 }; 542 543 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { 544 ROP2(cirrus_colorexpand_pattern_transp_0), 545 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), 546 ROP_NOP2(cirrus_bitblt_rop_nop), 547 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), 548 ROP2(cirrus_colorexpand_pattern_transp_notdst), 549 ROP2(cirrus_colorexpand_pattern_transp_src), 550 ROP2(cirrus_colorexpand_pattern_transp_1), 551 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), 552 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), 553 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), 554 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), 555 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), 556 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), 557 ROP2(cirrus_colorexpand_pattern_transp_notsrc), 558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), 559 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), 560 }; 561 562 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { 563 ROP2(cirrus_colorexpand_pattern_0), 564 ROP2(cirrus_colorexpand_pattern_src_and_dst), 565 ROP_NOP2(cirrus_bitblt_rop_nop), 566 ROP2(cirrus_colorexpand_pattern_src_and_notdst), 567 ROP2(cirrus_colorexpand_pattern_notdst), 568 ROP2(cirrus_colorexpand_pattern_src), 569 ROP2(cirrus_colorexpand_pattern_1), 570 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), 571 ROP2(cirrus_colorexpand_pattern_src_xor_dst), 572 ROP2(cirrus_colorexpand_pattern_src_or_dst), 573 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), 574 ROP2(cirrus_colorexpand_pattern_src_notxor_dst), 575 ROP2(cirrus_colorexpand_pattern_src_or_notdst), 576 ROP2(cirrus_colorexpand_pattern_notsrc), 577 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), 578 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), 579 }; 580 581 static const cirrus_fill_t cirrus_fill[16][4] = { 582 ROP2(cirrus_fill_0), 583 ROP2(cirrus_fill_src_and_dst), 584 ROP_NOP2(cirrus_bitblt_fill_nop), 585 ROP2(cirrus_fill_src_and_notdst), 586 ROP2(cirrus_fill_notdst), 587 ROP2(cirrus_fill_src), 588 ROP2(cirrus_fill_1), 589 ROP2(cirrus_fill_notsrc_and_dst), 590 ROP2(cirrus_fill_src_xor_dst), 591 ROP2(cirrus_fill_src_or_dst), 592 ROP2(cirrus_fill_notsrc_or_notdst), 593 ROP2(cirrus_fill_src_notxor_dst), 594 ROP2(cirrus_fill_src_or_notdst), 595 ROP2(cirrus_fill_notsrc), 596 ROP2(cirrus_fill_notsrc_or_dst), 597 ROP2(cirrus_fill_notsrc_and_notdst), 598 }; 599 600 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) 601 { 602 unsigned int color; 603 switch (s->cirrus_blt_pixelwidth) { 604 case 1: 605 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; 606 break; 607 case 2: 608 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); 609 s->cirrus_blt_fgcol = le16_to_cpu(color); 610 break; 611 case 3: 612 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | 613 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); 614 break; 615 default: 616 case 4: 617 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | 618 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); 619 s->cirrus_blt_fgcol = le32_to_cpu(color); 620 break; 621 } 622 } 623 624 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) 625 { 626 unsigned int color; 627 switch (s->cirrus_blt_pixelwidth) { 628 case 1: 629 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; 630 break; 631 case 2: 632 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); 633 s->cirrus_blt_bgcol = le16_to_cpu(color); 634 break; 635 case 3: 636 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | 637 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); 638 break; 639 default: 640 case 4: 641 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | 642 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); 643 s->cirrus_blt_bgcol = le32_to_cpu(color); 644 break; 645 } 646 } 647 648 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, 649 int off_pitch, int bytesperline, 650 int lines) 651 { 652 int y; 653 int off_cur; 654 int off_cur_end; 655 656 for (y = 0; y < lines; y++) { 657 off_cur = off_begin; 658 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; 659 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur); 660 off_begin += off_pitch; 661 } 662 } 663 664 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, 665 const uint8_t * src) 666 { 667 uint8_t *dst; 668 669 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); 670 671 if (blit_is_unsafe(s)) 672 return 0; 673 674 (*s->cirrus_rop) (s, dst, src, 675 s->cirrus_blt_dstpitch, 0, 676 s->cirrus_blt_width, s->cirrus_blt_height); 677 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 678 s->cirrus_blt_dstpitch, s->cirrus_blt_width, 679 s->cirrus_blt_height); 680 return 1; 681 } 682 683 /* fill */ 684 685 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) 686 { 687 cirrus_fill_t rop_func; 688 689 if (blit_is_unsafe(s)) { 690 return 0; 691 } 692 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 693 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), 694 s->cirrus_blt_dstpitch, 695 s->cirrus_blt_width, s->cirrus_blt_height); 696 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 697 s->cirrus_blt_dstpitch, s->cirrus_blt_width, 698 s->cirrus_blt_height); 699 cirrus_bitblt_reset(s); 700 return 1; 701 } 702 703 /*************************************** 704 * 705 * bitblt (video-to-video) 706 * 707 ***************************************/ 708 709 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) 710 { 711 return cirrus_bitblt_common_patterncopy(s, 712 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) & 713 s->cirrus_addr_mask)); 714 } 715 716 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) 717 { 718 int sx = 0, sy = 0; 719 int dx = 0, dy = 0; 720 int depth = 0; 721 int notify = 0; 722 723 /* make sure to only copy if it's a plain copy ROP */ 724 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src || 725 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) { 726 727 int width, height; 728 729 depth = s->vga.get_bpp(&s->vga) / 8; 730 s->vga.get_resolution(&s->vga, &width, &height); 731 732 /* extra x, y */ 733 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; 734 sy = (src / ABS(s->cirrus_blt_srcpitch)); 735 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; 736 dy = (dst / ABS(s->cirrus_blt_dstpitch)); 737 738 /* normalize width */ 739 w /= depth; 740 741 /* if we're doing a backward copy, we have to adjust 742 our x/y to be the upper left corner (instead of the lower 743 right corner) */ 744 if (s->cirrus_blt_dstpitch < 0) { 745 sx -= (s->cirrus_blt_width / depth) - 1; 746 dx -= (s->cirrus_blt_width / depth) - 1; 747 sy -= s->cirrus_blt_height - 1; 748 dy -= s->cirrus_blt_height - 1; 749 } 750 751 /* are we in the visible portion of memory? */ 752 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && 753 (sx + w) <= width && (sy + h) <= height && 754 (dx + w) <= width && (dy + h) <= height) { 755 notify = 1; 756 } 757 } 758 759 /* we have to flush all pending changes so that the copy 760 is generated at the appropriate moment in time */ 761 if (notify) 762 graphic_hw_update(s->vga.con); 763 764 (*s->cirrus_rop) (s, s->vga.vram_ptr + 765 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), 766 s->vga.vram_ptr + 767 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask), 768 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, 769 s->cirrus_blt_width, s->cirrus_blt_height); 770 771 if (notify) { 772 qemu_console_copy(s->vga.con, 773 sx, sy, dx, dy, 774 s->cirrus_blt_width / depth, 775 s->cirrus_blt_height); 776 } 777 778 /* we don't have to notify the display that this portion has 779 changed since qemu_console_copy implies this */ 780 781 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 782 s->cirrus_blt_dstpitch, s->cirrus_blt_width, 783 s->cirrus_blt_height); 784 } 785 786 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) 787 { 788 if (blit_is_unsafe(s)) 789 return 0; 790 791 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, 792 s->cirrus_blt_srcaddr - s->vga.start_addr, 793 s->cirrus_blt_width, s->cirrus_blt_height); 794 795 return 1; 796 } 797 798 /*************************************** 799 * 800 * bitblt (cpu-to-video) 801 * 802 ***************************************/ 803 804 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) 805 { 806 int copy_count; 807 uint8_t *end_ptr; 808 809 if (s->cirrus_srccounter > 0) { 810 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 811 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); 812 the_end: 813 s->cirrus_srccounter = 0; 814 cirrus_bitblt_reset(s); 815 } else { 816 /* at least one scan line */ 817 do { 818 (*s->cirrus_rop)(s, s->vga.vram_ptr + 819 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), 820 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); 821 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0, 822 s->cirrus_blt_width, 1); 823 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; 824 s->cirrus_srccounter -= s->cirrus_blt_srcpitch; 825 if (s->cirrus_srccounter <= 0) 826 goto the_end; 827 /* more bytes than needed can be transferred because of 828 word alignment, so we keep them for the next line */ 829 /* XXX: keep alignment to speed up transfer */ 830 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; 831 copy_count = s->cirrus_srcptr_end - end_ptr; 832 memmove(s->cirrus_bltbuf, end_ptr, copy_count); 833 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; 834 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; 835 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end); 836 } 837 } 838 } 839 840 /*************************************** 841 * 842 * bitblt wrapper 843 * 844 ***************************************/ 845 846 static void cirrus_bitblt_reset(CirrusVGAState * s) 847 { 848 int need_update; 849 850 s->vga.gr[0x31] &= 851 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); 852 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0] 853 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0]; 854 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; 855 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; 856 s->cirrus_srccounter = 0; 857 if (!need_update) 858 return; 859 cirrus_update_memory_access(s); 860 } 861 862 static int cirrus_bitblt_cputovideo(CirrusVGAState * s) 863 { 864 int w; 865 866 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; 867 s->cirrus_srcptr = &s->cirrus_bltbuf[0]; 868 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; 869 870 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 871 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { 872 s->cirrus_blt_srcpitch = 8; 873 } else { 874 /* XXX: check for 24 bpp */ 875 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; 876 } 877 s->cirrus_srccounter = s->cirrus_blt_srcpitch; 878 } else { 879 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { 880 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; 881 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY) 882 s->cirrus_blt_srcpitch = ((w + 31) >> 5); 883 else 884 s->cirrus_blt_srcpitch = ((w + 7) >> 3); 885 } else { 886 /* always align input size to 32 bits */ 887 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; 888 } 889 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; 890 } 891 s->cirrus_srcptr = s->cirrus_bltbuf; 892 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; 893 cirrus_update_memory_access(s); 894 return 1; 895 } 896 897 static int cirrus_bitblt_videotocpu(CirrusVGAState * s) 898 { 899 /* XXX */ 900 #ifdef DEBUG_BITBLT 901 printf("cirrus: bitblt (video to cpu) is not implemented yet\n"); 902 #endif 903 return 0; 904 } 905 906 static int cirrus_bitblt_videotovideo(CirrusVGAState * s) 907 { 908 int ret; 909 910 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 911 ret = cirrus_bitblt_videotovideo_patterncopy(s); 912 } else { 913 ret = cirrus_bitblt_videotovideo_copy(s); 914 } 915 if (ret) 916 cirrus_bitblt_reset(s); 917 return ret; 918 } 919 920 static void cirrus_bitblt_start(CirrusVGAState * s) 921 { 922 uint8_t blt_rop; 923 924 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY; 925 926 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; 927 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; 928 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); 929 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); 930 s->cirrus_blt_dstaddr = 931 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); 932 s->cirrus_blt_srcaddr = 933 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); 934 s->cirrus_blt_mode = s->vga.gr[0x30]; 935 s->cirrus_blt_modeext = s->vga.gr[0x33]; 936 blt_rop = s->vga.gr[0x32]; 937 938 #ifdef DEBUG_BITBLT 939 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", 940 blt_rop, 941 s->cirrus_blt_mode, 942 s->cirrus_blt_modeext, 943 s->cirrus_blt_width, 944 s->cirrus_blt_height, 945 s->cirrus_blt_dstpitch, 946 s->cirrus_blt_srcpitch, 947 s->cirrus_blt_dstaddr, 948 s->cirrus_blt_srcaddr, 949 s->vga.gr[0x2f]); 950 #endif 951 952 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { 953 case CIRRUS_BLTMODE_PIXELWIDTH8: 954 s->cirrus_blt_pixelwidth = 1; 955 break; 956 case CIRRUS_BLTMODE_PIXELWIDTH16: 957 s->cirrus_blt_pixelwidth = 2; 958 break; 959 case CIRRUS_BLTMODE_PIXELWIDTH24: 960 s->cirrus_blt_pixelwidth = 3; 961 break; 962 case CIRRUS_BLTMODE_PIXELWIDTH32: 963 s->cirrus_blt_pixelwidth = 4; 964 break; 965 default: 966 #ifdef DEBUG_BITBLT 967 printf("cirrus: bitblt - pixel width is unknown\n"); 968 #endif 969 goto bitblt_ignore; 970 } 971 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; 972 973 if ((s-> 974 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | 975 CIRRUS_BLTMODE_MEMSYSDEST)) 976 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { 977 #ifdef DEBUG_BITBLT 978 printf("cirrus: bitblt - memory-to-memory copy is requested\n"); 979 #endif 980 goto bitblt_ignore; 981 } 982 983 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) && 984 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | 985 CIRRUS_BLTMODE_TRANSPARENTCOMP | 986 CIRRUS_BLTMODE_PATTERNCOPY | 987 CIRRUS_BLTMODE_COLOREXPAND)) == 988 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { 989 cirrus_bitblt_fgcol(s); 990 cirrus_bitblt_solidfill(s, blt_rop); 991 } else { 992 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND | 993 CIRRUS_BLTMODE_PATTERNCOPY)) == 994 CIRRUS_BLTMODE_COLOREXPAND) { 995 996 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { 997 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) 998 cirrus_bitblt_bgcol(s); 999 else 1000 cirrus_bitblt_fgcol(s); 1001 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1002 } else { 1003 cirrus_bitblt_fgcol(s); 1004 cirrus_bitblt_bgcol(s); 1005 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1006 } 1007 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { 1008 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { 1009 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { 1010 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) 1011 cirrus_bitblt_bgcol(s); 1012 else 1013 cirrus_bitblt_fgcol(s); 1014 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1015 } else { 1016 cirrus_bitblt_fgcol(s); 1017 cirrus_bitblt_bgcol(s); 1018 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1019 } 1020 } else { 1021 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1022 } 1023 } else { 1024 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { 1025 if (s->cirrus_blt_pixelwidth > 2) { 1026 printf("src transparent without colorexpand must be 8bpp or 16bpp\n"); 1027 goto bitblt_ignore; 1028 } 1029 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { 1030 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; 1031 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; 1032 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1033 } else { 1034 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 1035 } 1036 } else { 1037 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { 1038 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; 1039 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; 1040 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; 1041 } else { 1042 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; 1043 } 1044 } 1045 } 1046 // setup bitblt engine. 1047 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) { 1048 if (!cirrus_bitblt_cputovideo(s)) 1049 goto bitblt_ignore; 1050 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { 1051 if (!cirrus_bitblt_videotocpu(s)) 1052 goto bitblt_ignore; 1053 } else { 1054 if (!cirrus_bitblt_videotovideo(s)) 1055 goto bitblt_ignore; 1056 } 1057 } 1058 return; 1059 bitblt_ignore:; 1060 cirrus_bitblt_reset(s); 1061 } 1062 1063 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) 1064 { 1065 unsigned old_value; 1066 1067 old_value = s->vga.gr[0x31]; 1068 s->vga.gr[0x31] = reg_value; 1069 1070 if (((old_value & CIRRUS_BLT_RESET) != 0) && 1071 ((reg_value & CIRRUS_BLT_RESET) == 0)) { 1072 cirrus_bitblt_reset(s); 1073 } else if (((old_value & CIRRUS_BLT_START) == 0) && 1074 ((reg_value & CIRRUS_BLT_START) != 0)) { 1075 cirrus_bitblt_start(s); 1076 } 1077 } 1078 1079 1080 /*************************************** 1081 * 1082 * basic parameters 1083 * 1084 ***************************************/ 1085 1086 static void cirrus_get_offsets(VGACommonState *s1, 1087 uint32_t *pline_offset, 1088 uint32_t *pstart_addr, 1089 uint32_t *pline_compare) 1090 { 1091 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); 1092 uint32_t start_addr, line_offset, line_compare; 1093 1094 line_offset = s->vga.cr[0x13] 1095 | ((s->vga.cr[0x1b] & 0x10) << 4); 1096 line_offset <<= 3; 1097 *pline_offset = line_offset; 1098 1099 start_addr = (s->vga.cr[0x0c] << 8) 1100 | s->vga.cr[0x0d] 1101 | ((s->vga.cr[0x1b] & 0x01) << 16) 1102 | ((s->vga.cr[0x1b] & 0x0c) << 15) 1103 | ((s->vga.cr[0x1d] & 0x80) << 12); 1104 *pstart_addr = start_addr; 1105 1106 line_compare = s->vga.cr[0x18] | 1107 ((s->vga.cr[0x07] & 0x10) << 4) | 1108 ((s->vga.cr[0x09] & 0x40) << 3); 1109 *pline_compare = line_compare; 1110 } 1111 1112 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s) 1113 { 1114 uint32_t ret = 16; 1115 1116 switch (s->cirrus_hidden_dac_data & 0xf) { 1117 case 0: 1118 ret = 15; 1119 break; /* Sierra HiColor */ 1120 case 1: 1121 ret = 16; 1122 break; /* XGA HiColor */ 1123 default: 1124 #ifdef DEBUG_CIRRUS 1125 printf("cirrus: invalid DAC value %x in 16bpp\n", 1126 (s->cirrus_hidden_dac_data & 0xf)); 1127 #endif 1128 ret = 15; /* XXX */ 1129 break; 1130 } 1131 return ret; 1132 } 1133 1134 static int cirrus_get_bpp(VGACommonState *s1) 1135 { 1136 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); 1137 uint32_t ret = 8; 1138 1139 if ((s->vga.sr[0x07] & 0x01) != 0) { 1140 /* Cirrus SVGA */ 1141 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { 1142 case CIRRUS_SR7_BPP_8: 1143 ret = 8; 1144 break; 1145 case CIRRUS_SR7_BPP_16_DOUBLEVCLK: 1146 ret = cirrus_get_bpp16_depth(s); 1147 break; 1148 case CIRRUS_SR7_BPP_24: 1149 ret = 24; 1150 break; 1151 case CIRRUS_SR7_BPP_16: 1152 ret = cirrus_get_bpp16_depth(s); 1153 break; 1154 case CIRRUS_SR7_BPP_32: 1155 ret = 32; 1156 break; 1157 default: 1158 #ifdef DEBUG_CIRRUS 1159 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); 1160 #endif 1161 ret = 8; 1162 break; 1163 } 1164 } else { 1165 /* VGA */ 1166 ret = 0; 1167 } 1168 1169 return ret; 1170 } 1171 1172 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) 1173 { 1174 int width, height; 1175 1176 width = (s->cr[0x01] + 1) * 8; 1177 height = s->cr[0x12] | 1178 ((s->cr[0x07] & 0x02) << 7) | 1179 ((s->cr[0x07] & 0x40) << 3); 1180 height = (height + 1); 1181 /* interlace support */ 1182 if (s->cr[0x1a] & 0x01) 1183 height = height * 2; 1184 *pwidth = width; 1185 *pheight = height; 1186 } 1187 1188 /*************************************** 1189 * 1190 * bank memory 1191 * 1192 ***************************************/ 1193 1194 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) 1195 { 1196 unsigned offset; 1197 unsigned limit; 1198 1199 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ 1200 offset = s->vga.gr[0x09 + bank_index]; 1201 else /* single bank */ 1202 offset = s->vga.gr[0x09]; 1203 1204 if ((s->vga.gr[0x0b] & 0x20) != 0) 1205 offset <<= 14; 1206 else 1207 offset <<= 12; 1208 1209 if (s->real_vram_size <= offset) 1210 limit = 0; 1211 else 1212 limit = s->real_vram_size - offset; 1213 1214 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { 1215 if (limit > 0x8000) { 1216 offset += 0x8000; 1217 limit -= 0x8000; 1218 } else { 1219 limit = 0; 1220 } 1221 } 1222 1223 if (limit > 0) { 1224 s->cirrus_bank_base[bank_index] = offset; 1225 s->cirrus_bank_limit[bank_index] = limit; 1226 } else { 1227 s->cirrus_bank_base[bank_index] = 0; 1228 s->cirrus_bank_limit[bank_index] = 0; 1229 } 1230 } 1231 1232 /*************************************** 1233 * 1234 * I/O access between 0x3c4-0x3c5 1235 * 1236 ***************************************/ 1237 1238 static int cirrus_vga_read_sr(CirrusVGAState * s) 1239 { 1240 switch (s->vga.sr_index) { 1241 case 0x00: // Standard VGA 1242 case 0x01: // Standard VGA 1243 case 0x02: // Standard VGA 1244 case 0x03: // Standard VGA 1245 case 0x04: // Standard VGA 1246 return s->vga.sr[s->vga.sr_index]; 1247 case 0x06: // Unlock Cirrus extensions 1248 return s->vga.sr[s->vga.sr_index]; 1249 case 0x10: 1250 case 0x30: 1251 case 0x50: 1252 case 0x70: // Graphics Cursor X 1253 case 0x90: 1254 case 0xb0: 1255 case 0xd0: 1256 case 0xf0: // Graphics Cursor X 1257 return s->vga.sr[0x10]; 1258 case 0x11: 1259 case 0x31: 1260 case 0x51: 1261 case 0x71: // Graphics Cursor Y 1262 case 0x91: 1263 case 0xb1: 1264 case 0xd1: 1265 case 0xf1: // Graphics Cursor Y 1266 return s->vga.sr[0x11]; 1267 case 0x05: // ??? 1268 case 0x07: // Extended Sequencer Mode 1269 case 0x08: // EEPROM Control 1270 case 0x09: // Scratch Register 0 1271 case 0x0a: // Scratch Register 1 1272 case 0x0b: // VCLK 0 1273 case 0x0c: // VCLK 1 1274 case 0x0d: // VCLK 2 1275 case 0x0e: // VCLK 3 1276 case 0x0f: // DRAM Control 1277 case 0x12: // Graphics Cursor Attribute 1278 case 0x13: // Graphics Cursor Pattern Address 1279 case 0x14: // Scratch Register 2 1280 case 0x15: // Scratch Register 3 1281 case 0x16: // Performance Tuning Register 1282 case 0x17: // Configuration Readback and Extended Control 1283 case 0x18: // Signature Generator Control 1284 case 0x19: // Signal Generator Result 1285 case 0x1a: // Signal Generator Result 1286 case 0x1b: // VCLK 0 Denominator & Post 1287 case 0x1c: // VCLK 1 Denominator & Post 1288 case 0x1d: // VCLK 2 Denominator & Post 1289 case 0x1e: // VCLK 3 Denominator & Post 1290 case 0x1f: // BIOS Write Enable and MCLK select 1291 #ifdef DEBUG_CIRRUS 1292 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index); 1293 #endif 1294 return s->vga.sr[s->vga.sr_index]; 1295 default: 1296 #ifdef DEBUG_CIRRUS 1297 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index); 1298 #endif 1299 return 0xff; 1300 break; 1301 } 1302 } 1303 1304 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) 1305 { 1306 switch (s->vga.sr_index) { 1307 case 0x00: // Standard VGA 1308 case 0x01: // Standard VGA 1309 case 0x02: // Standard VGA 1310 case 0x03: // Standard VGA 1311 case 0x04: // Standard VGA 1312 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; 1313 if (s->vga.sr_index == 1) 1314 s->vga.update_retrace_info(&s->vga); 1315 break; 1316 case 0x06: // Unlock Cirrus extensions 1317 val &= 0x17; 1318 if (val == 0x12) { 1319 s->vga.sr[s->vga.sr_index] = 0x12; 1320 } else { 1321 s->vga.sr[s->vga.sr_index] = 0x0f; 1322 } 1323 break; 1324 case 0x10: 1325 case 0x30: 1326 case 0x50: 1327 case 0x70: // Graphics Cursor X 1328 case 0x90: 1329 case 0xb0: 1330 case 0xd0: 1331 case 0xf0: // Graphics Cursor X 1332 s->vga.sr[0x10] = val; 1333 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); 1334 break; 1335 case 0x11: 1336 case 0x31: 1337 case 0x51: 1338 case 0x71: // Graphics Cursor Y 1339 case 0x91: 1340 case 0xb1: 1341 case 0xd1: 1342 case 0xf1: // Graphics Cursor Y 1343 s->vga.sr[0x11] = val; 1344 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); 1345 break; 1346 case 0x07: // Extended Sequencer Mode 1347 cirrus_update_memory_access(s); 1348 case 0x08: // EEPROM Control 1349 case 0x09: // Scratch Register 0 1350 case 0x0a: // Scratch Register 1 1351 case 0x0b: // VCLK 0 1352 case 0x0c: // VCLK 1 1353 case 0x0d: // VCLK 2 1354 case 0x0e: // VCLK 3 1355 case 0x0f: // DRAM Control 1356 case 0x13: // Graphics Cursor Pattern Address 1357 case 0x14: // Scratch Register 2 1358 case 0x15: // Scratch Register 3 1359 case 0x16: // Performance Tuning Register 1360 case 0x18: // Signature Generator Control 1361 case 0x19: // Signature Generator Result 1362 case 0x1a: // Signature Generator Result 1363 case 0x1b: // VCLK 0 Denominator & Post 1364 case 0x1c: // VCLK 1 Denominator & Post 1365 case 0x1d: // VCLK 2 Denominator & Post 1366 case 0x1e: // VCLK 3 Denominator & Post 1367 case 0x1f: // BIOS Write Enable and MCLK select 1368 s->vga.sr[s->vga.sr_index] = val; 1369 #ifdef DEBUG_CIRRUS 1370 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n", 1371 s->vga.sr_index, val); 1372 #endif 1373 break; 1374 case 0x12: // Graphics Cursor Attribute 1375 s->vga.sr[0x12] = val; 1376 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW); 1377 #ifdef DEBUG_CIRRUS 1378 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n", 1379 val, s->vga.force_shadow); 1380 #endif 1381 break; 1382 case 0x17: // Configuration Readback and Extended Control 1383 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) 1384 | (val & 0xc7); 1385 cirrus_update_memory_access(s); 1386 break; 1387 default: 1388 #ifdef DEBUG_CIRRUS 1389 printf("cirrus: outport sr_index %02x, sr_value %02x\n", 1390 s->vga.sr_index, val); 1391 #endif 1392 break; 1393 } 1394 } 1395 1396 /*************************************** 1397 * 1398 * I/O access at 0x3c6 1399 * 1400 ***************************************/ 1401 1402 static int cirrus_read_hidden_dac(CirrusVGAState * s) 1403 { 1404 if (++s->cirrus_hidden_dac_lockindex == 5) { 1405 s->cirrus_hidden_dac_lockindex = 0; 1406 return s->cirrus_hidden_dac_data; 1407 } 1408 return 0xff; 1409 } 1410 1411 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) 1412 { 1413 if (s->cirrus_hidden_dac_lockindex == 4) { 1414 s->cirrus_hidden_dac_data = reg_value; 1415 #if defined(DEBUG_CIRRUS) 1416 printf("cirrus: outport hidden DAC, value %02x\n", reg_value); 1417 #endif 1418 } 1419 s->cirrus_hidden_dac_lockindex = 0; 1420 } 1421 1422 /*************************************** 1423 * 1424 * I/O access at 0x3c9 1425 * 1426 ***************************************/ 1427 1428 static int cirrus_vga_read_palette(CirrusVGAState * s) 1429 { 1430 int val; 1431 1432 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { 1433 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + 1434 s->vga.dac_sub_index]; 1435 } else { 1436 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index]; 1437 } 1438 if (++s->vga.dac_sub_index == 3) { 1439 s->vga.dac_sub_index = 0; 1440 s->vga.dac_read_index++; 1441 } 1442 return val; 1443 } 1444 1445 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) 1446 { 1447 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; 1448 if (++s->vga.dac_sub_index == 3) { 1449 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { 1450 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], 1451 s->vga.dac_cache, 3); 1452 } else { 1453 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); 1454 } 1455 /* XXX update cursor */ 1456 s->vga.dac_sub_index = 0; 1457 s->vga.dac_write_index++; 1458 } 1459 } 1460 1461 /*************************************** 1462 * 1463 * I/O access between 0x3ce-0x3cf 1464 * 1465 ***************************************/ 1466 1467 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index) 1468 { 1469 switch (reg_index) { 1470 case 0x00: // Standard VGA, BGCOLOR 0x000000ff 1471 return s->cirrus_shadow_gr0; 1472 case 0x01: // Standard VGA, FGCOLOR 0x000000ff 1473 return s->cirrus_shadow_gr1; 1474 case 0x02: // Standard VGA 1475 case 0x03: // Standard VGA 1476 case 0x04: // Standard VGA 1477 case 0x06: // Standard VGA 1478 case 0x07: // Standard VGA 1479 case 0x08: // Standard VGA 1480 return s->vga.gr[s->vga.gr_index]; 1481 case 0x05: // Standard VGA, Cirrus extended mode 1482 default: 1483 break; 1484 } 1485 1486 if (reg_index < 0x3a) { 1487 return s->vga.gr[reg_index]; 1488 } else { 1489 #ifdef DEBUG_CIRRUS 1490 printf("cirrus: inport gr_index %02x\n", reg_index); 1491 #endif 1492 return 0xff; 1493 } 1494 } 1495 1496 static void 1497 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) 1498 { 1499 #if defined(DEBUG_BITBLT) && 0 1500 printf("gr%02x: %02x\n", reg_index, reg_value); 1501 #endif 1502 switch (reg_index) { 1503 case 0x00: // Standard VGA, BGCOLOR 0x000000ff 1504 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; 1505 s->cirrus_shadow_gr0 = reg_value; 1506 break; 1507 case 0x01: // Standard VGA, FGCOLOR 0x000000ff 1508 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; 1509 s->cirrus_shadow_gr1 = reg_value; 1510 break; 1511 case 0x02: // Standard VGA 1512 case 0x03: // Standard VGA 1513 case 0x04: // Standard VGA 1514 case 0x06: // Standard VGA 1515 case 0x07: // Standard VGA 1516 case 0x08: // Standard VGA 1517 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; 1518 break; 1519 case 0x05: // Standard VGA, Cirrus extended mode 1520 s->vga.gr[reg_index] = reg_value & 0x7f; 1521 cirrus_update_memory_access(s); 1522 break; 1523 case 0x09: // bank offset #0 1524 case 0x0A: // bank offset #1 1525 s->vga.gr[reg_index] = reg_value; 1526 cirrus_update_bank_ptr(s, 0); 1527 cirrus_update_bank_ptr(s, 1); 1528 cirrus_update_memory_access(s); 1529 break; 1530 case 0x0B: 1531 s->vga.gr[reg_index] = reg_value; 1532 cirrus_update_bank_ptr(s, 0); 1533 cirrus_update_bank_ptr(s, 1); 1534 cirrus_update_memory_access(s); 1535 break; 1536 case 0x10: // BGCOLOR 0x0000ff00 1537 case 0x11: // FGCOLOR 0x0000ff00 1538 case 0x12: // BGCOLOR 0x00ff0000 1539 case 0x13: // FGCOLOR 0x00ff0000 1540 case 0x14: // BGCOLOR 0xff000000 1541 case 0x15: // FGCOLOR 0xff000000 1542 case 0x20: // BLT WIDTH 0x0000ff 1543 case 0x22: // BLT HEIGHT 0x0000ff 1544 case 0x24: // BLT DEST PITCH 0x0000ff 1545 case 0x26: // BLT SRC PITCH 0x0000ff 1546 case 0x28: // BLT DEST ADDR 0x0000ff 1547 case 0x29: // BLT DEST ADDR 0x00ff00 1548 case 0x2c: // BLT SRC ADDR 0x0000ff 1549 case 0x2d: // BLT SRC ADDR 0x00ff00 1550 case 0x2f: // BLT WRITEMASK 1551 case 0x30: // BLT MODE 1552 case 0x32: // RASTER OP 1553 case 0x33: // BLT MODEEXT 1554 case 0x34: // BLT TRANSPARENT COLOR 0x00ff 1555 case 0x35: // BLT TRANSPARENT COLOR 0xff00 1556 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff 1557 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 1558 s->vga.gr[reg_index] = reg_value; 1559 break; 1560 case 0x21: // BLT WIDTH 0x001f00 1561 case 0x23: // BLT HEIGHT 0x001f00 1562 case 0x25: // BLT DEST PITCH 0x001f00 1563 case 0x27: // BLT SRC PITCH 0x001f00 1564 s->vga.gr[reg_index] = reg_value & 0x1f; 1565 break; 1566 case 0x2a: // BLT DEST ADDR 0x3f0000 1567 s->vga.gr[reg_index] = reg_value & 0x3f; 1568 /* if auto start mode, starts bit blt now */ 1569 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { 1570 cirrus_bitblt_start(s); 1571 } 1572 break; 1573 case 0x2e: // BLT SRC ADDR 0x3f0000 1574 s->vga.gr[reg_index] = reg_value & 0x3f; 1575 break; 1576 case 0x31: // BLT STATUS/START 1577 cirrus_write_bitblt(s, reg_value); 1578 break; 1579 default: 1580 #ifdef DEBUG_CIRRUS 1581 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index, 1582 reg_value); 1583 #endif 1584 break; 1585 } 1586 } 1587 1588 /*************************************** 1589 * 1590 * I/O access between 0x3d4-0x3d5 1591 * 1592 ***************************************/ 1593 1594 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index) 1595 { 1596 switch (reg_index) { 1597 case 0x00: // Standard VGA 1598 case 0x01: // Standard VGA 1599 case 0x02: // Standard VGA 1600 case 0x03: // Standard VGA 1601 case 0x04: // Standard VGA 1602 case 0x05: // Standard VGA 1603 case 0x06: // Standard VGA 1604 case 0x07: // Standard VGA 1605 case 0x08: // Standard VGA 1606 case 0x09: // Standard VGA 1607 case 0x0a: // Standard VGA 1608 case 0x0b: // Standard VGA 1609 case 0x0c: // Standard VGA 1610 case 0x0d: // Standard VGA 1611 case 0x0e: // Standard VGA 1612 case 0x0f: // Standard VGA 1613 case 0x10: // Standard VGA 1614 case 0x11: // Standard VGA 1615 case 0x12: // Standard VGA 1616 case 0x13: // Standard VGA 1617 case 0x14: // Standard VGA 1618 case 0x15: // Standard VGA 1619 case 0x16: // Standard VGA 1620 case 0x17: // Standard VGA 1621 case 0x18: // Standard VGA 1622 return s->vga.cr[s->vga.cr_index]; 1623 case 0x24: // Attribute Controller Toggle Readback (R) 1624 return (s->vga.ar_flip_flop << 7); 1625 case 0x19: // Interlace End 1626 case 0x1a: // Miscellaneous Control 1627 case 0x1b: // Extended Display Control 1628 case 0x1c: // Sync Adjust and Genlock 1629 case 0x1d: // Overlay Extended Control 1630 case 0x22: // Graphics Data Latches Readback (R) 1631 case 0x25: // Part Status 1632 case 0x27: // Part ID (R) 1633 return s->vga.cr[s->vga.cr_index]; 1634 case 0x26: // Attribute Controller Index Readback (R) 1635 return s->vga.ar_index & 0x3f; 1636 break; 1637 default: 1638 #ifdef DEBUG_CIRRUS 1639 printf("cirrus: inport cr_index %02x\n", reg_index); 1640 #endif 1641 return 0xff; 1642 } 1643 } 1644 1645 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) 1646 { 1647 switch (s->vga.cr_index) { 1648 case 0x00: // Standard VGA 1649 case 0x01: // Standard VGA 1650 case 0x02: // Standard VGA 1651 case 0x03: // Standard VGA 1652 case 0x04: // Standard VGA 1653 case 0x05: // Standard VGA 1654 case 0x06: // Standard VGA 1655 case 0x07: // Standard VGA 1656 case 0x08: // Standard VGA 1657 case 0x09: // Standard VGA 1658 case 0x0a: // Standard VGA 1659 case 0x0b: // Standard VGA 1660 case 0x0c: // Standard VGA 1661 case 0x0d: // Standard VGA 1662 case 0x0e: // Standard VGA 1663 case 0x0f: // Standard VGA 1664 case 0x10: // Standard VGA 1665 case 0x11: // Standard VGA 1666 case 0x12: // Standard VGA 1667 case 0x13: // Standard VGA 1668 case 0x14: // Standard VGA 1669 case 0x15: // Standard VGA 1670 case 0x16: // Standard VGA 1671 case 0x17: // Standard VGA 1672 case 0x18: // Standard VGA 1673 /* handle CR0-7 protection */ 1674 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { 1675 /* can always write bit 4 of CR7 */ 1676 if (s->vga.cr_index == 7) 1677 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); 1678 return; 1679 } 1680 s->vga.cr[s->vga.cr_index] = reg_value; 1681 switch(s->vga.cr_index) { 1682 case 0x00: 1683 case 0x04: 1684 case 0x05: 1685 case 0x06: 1686 case 0x07: 1687 case 0x11: 1688 case 0x17: 1689 s->vga.update_retrace_info(&s->vga); 1690 break; 1691 } 1692 break; 1693 case 0x19: // Interlace End 1694 case 0x1a: // Miscellaneous Control 1695 case 0x1b: // Extended Display Control 1696 case 0x1c: // Sync Adjust and Genlock 1697 case 0x1d: // Overlay Extended Control 1698 s->vga.cr[s->vga.cr_index] = reg_value; 1699 #ifdef DEBUG_CIRRUS 1700 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n", 1701 s->vga.cr_index, reg_value); 1702 #endif 1703 break; 1704 case 0x22: // Graphics Data Latches Readback (R) 1705 case 0x24: // Attribute Controller Toggle Readback (R) 1706 case 0x26: // Attribute Controller Index Readback (R) 1707 case 0x27: // Part ID (R) 1708 break; 1709 case 0x25: // Part Status 1710 default: 1711 #ifdef DEBUG_CIRRUS 1712 printf("cirrus: outport cr_index %02x, cr_value %02x\n", 1713 s->vga.cr_index, reg_value); 1714 #endif 1715 break; 1716 } 1717 } 1718 1719 /*************************************** 1720 * 1721 * memory-mapped I/O (bitblt) 1722 * 1723 ***************************************/ 1724 1725 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) 1726 { 1727 int value = 0xff; 1728 1729 switch (address) { 1730 case (CIRRUS_MMIO_BLTBGCOLOR + 0): 1731 value = cirrus_vga_read_gr(s, 0x00); 1732 break; 1733 case (CIRRUS_MMIO_BLTBGCOLOR + 1): 1734 value = cirrus_vga_read_gr(s, 0x10); 1735 break; 1736 case (CIRRUS_MMIO_BLTBGCOLOR + 2): 1737 value = cirrus_vga_read_gr(s, 0x12); 1738 break; 1739 case (CIRRUS_MMIO_BLTBGCOLOR + 3): 1740 value = cirrus_vga_read_gr(s, 0x14); 1741 break; 1742 case (CIRRUS_MMIO_BLTFGCOLOR + 0): 1743 value = cirrus_vga_read_gr(s, 0x01); 1744 break; 1745 case (CIRRUS_MMIO_BLTFGCOLOR + 1): 1746 value = cirrus_vga_read_gr(s, 0x11); 1747 break; 1748 case (CIRRUS_MMIO_BLTFGCOLOR + 2): 1749 value = cirrus_vga_read_gr(s, 0x13); 1750 break; 1751 case (CIRRUS_MMIO_BLTFGCOLOR + 3): 1752 value = cirrus_vga_read_gr(s, 0x15); 1753 break; 1754 case (CIRRUS_MMIO_BLTWIDTH + 0): 1755 value = cirrus_vga_read_gr(s, 0x20); 1756 break; 1757 case (CIRRUS_MMIO_BLTWIDTH + 1): 1758 value = cirrus_vga_read_gr(s, 0x21); 1759 break; 1760 case (CIRRUS_MMIO_BLTHEIGHT + 0): 1761 value = cirrus_vga_read_gr(s, 0x22); 1762 break; 1763 case (CIRRUS_MMIO_BLTHEIGHT + 1): 1764 value = cirrus_vga_read_gr(s, 0x23); 1765 break; 1766 case (CIRRUS_MMIO_BLTDESTPITCH + 0): 1767 value = cirrus_vga_read_gr(s, 0x24); 1768 break; 1769 case (CIRRUS_MMIO_BLTDESTPITCH + 1): 1770 value = cirrus_vga_read_gr(s, 0x25); 1771 break; 1772 case (CIRRUS_MMIO_BLTSRCPITCH + 0): 1773 value = cirrus_vga_read_gr(s, 0x26); 1774 break; 1775 case (CIRRUS_MMIO_BLTSRCPITCH + 1): 1776 value = cirrus_vga_read_gr(s, 0x27); 1777 break; 1778 case (CIRRUS_MMIO_BLTDESTADDR + 0): 1779 value = cirrus_vga_read_gr(s, 0x28); 1780 break; 1781 case (CIRRUS_MMIO_BLTDESTADDR + 1): 1782 value = cirrus_vga_read_gr(s, 0x29); 1783 break; 1784 case (CIRRUS_MMIO_BLTDESTADDR + 2): 1785 value = cirrus_vga_read_gr(s, 0x2a); 1786 break; 1787 case (CIRRUS_MMIO_BLTSRCADDR + 0): 1788 value = cirrus_vga_read_gr(s, 0x2c); 1789 break; 1790 case (CIRRUS_MMIO_BLTSRCADDR + 1): 1791 value = cirrus_vga_read_gr(s, 0x2d); 1792 break; 1793 case (CIRRUS_MMIO_BLTSRCADDR + 2): 1794 value = cirrus_vga_read_gr(s, 0x2e); 1795 break; 1796 case CIRRUS_MMIO_BLTWRITEMASK: 1797 value = cirrus_vga_read_gr(s, 0x2f); 1798 break; 1799 case CIRRUS_MMIO_BLTMODE: 1800 value = cirrus_vga_read_gr(s, 0x30); 1801 break; 1802 case CIRRUS_MMIO_BLTROP: 1803 value = cirrus_vga_read_gr(s, 0x32); 1804 break; 1805 case CIRRUS_MMIO_BLTMODEEXT: 1806 value = cirrus_vga_read_gr(s, 0x33); 1807 break; 1808 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): 1809 value = cirrus_vga_read_gr(s, 0x34); 1810 break; 1811 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): 1812 value = cirrus_vga_read_gr(s, 0x35); 1813 break; 1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): 1815 value = cirrus_vga_read_gr(s, 0x38); 1816 break; 1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): 1818 value = cirrus_vga_read_gr(s, 0x39); 1819 break; 1820 case CIRRUS_MMIO_BLTSTATUS: 1821 value = cirrus_vga_read_gr(s, 0x31); 1822 break; 1823 default: 1824 #ifdef DEBUG_CIRRUS 1825 printf("cirrus: mmio read - address 0x%04x\n", address); 1826 #endif 1827 break; 1828 } 1829 1830 return (uint8_t) value; 1831 } 1832 1833 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, 1834 uint8_t value) 1835 { 1836 switch (address) { 1837 case (CIRRUS_MMIO_BLTBGCOLOR + 0): 1838 cirrus_vga_write_gr(s, 0x00, value); 1839 break; 1840 case (CIRRUS_MMIO_BLTBGCOLOR + 1): 1841 cirrus_vga_write_gr(s, 0x10, value); 1842 break; 1843 case (CIRRUS_MMIO_BLTBGCOLOR + 2): 1844 cirrus_vga_write_gr(s, 0x12, value); 1845 break; 1846 case (CIRRUS_MMIO_BLTBGCOLOR + 3): 1847 cirrus_vga_write_gr(s, 0x14, value); 1848 break; 1849 case (CIRRUS_MMIO_BLTFGCOLOR + 0): 1850 cirrus_vga_write_gr(s, 0x01, value); 1851 break; 1852 case (CIRRUS_MMIO_BLTFGCOLOR + 1): 1853 cirrus_vga_write_gr(s, 0x11, value); 1854 break; 1855 case (CIRRUS_MMIO_BLTFGCOLOR + 2): 1856 cirrus_vga_write_gr(s, 0x13, value); 1857 break; 1858 case (CIRRUS_MMIO_BLTFGCOLOR + 3): 1859 cirrus_vga_write_gr(s, 0x15, value); 1860 break; 1861 case (CIRRUS_MMIO_BLTWIDTH + 0): 1862 cirrus_vga_write_gr(s, 0x20, value); 1863 break; 1864 case (CIRRUS_MMIO_BLTWIDTH + 1): 1865 cirrus_vga_write_gr(s, 0x21, value); 1866 break; 1867 case (CIRRUS_MMIO_BLTHEIGHT + 0): 1868 cirrus_vga_write_gr(s, 0x22, value); 1869 break; 1870 case (CIRRUS_MMIO_BLTHEIGHT + 1): 1871 cirrus_vga_write_gr(s, 0x23, value); 1872 break; 1873 case (CIRRUS_MMIO_BLTDESTPITCH + 0): 1874 cirrus_vga_write_gr(s, 0x24, value); 1875 break; 1876 case (CIRRUS_MMIO_BLTDESTPITCH + 1): 1877 cirrus_vga_write_gr(s, 0x25, value); 1878 break; 1879 case (CIRRUS_MMIO_BLTSRCPITCH + 0): 1880 cirrus_vga_write_gr(s, 0x26, value); 1881 break; 1882 case (CIRRUS_MMIO_BLTSRCPITCH + 1): 1883 cirrus_vga_write_gr(s, 0x27, value); 1884 break; 1885 case (CIRRUS_MMIO_BLTDESTADDR + 0): 1886 cirrus_vga_write_gr(s, 0x28, value); 1887 break; 1888 case (CIRRUS_MMIO_BLTDESTADDR + 1): 1889 cirrus_vga_write_gr(s, 0x29, value); 1890 break; 1891 case (CIRRUS_MMIO_BLTDESTADDR + 2): 1892 cirrus_vga_write_gr(s, 0x2a, value); 1893 break; 1894 case (CIRRUS_MMIO_BLTDESTADDR + 3): 1895 /* ignored */ 1896 break; 1897 case (CIRRUS_MMIO_BLTSRCADDR + 0): 1898 cirrus_vga_write_gr(s, 0x2c, value); 1899 break; 1900 case (CIRRUS_MMIO_BLTSRCADDR + 1): 1901 cirrus_vga_write_gr(s, 0x2d, value); 1902 break; 1903 case (CIRRUS_MMIO_BLTSRCADDR + 2): 1904 cirrus_vga_write_gr(s, 0x2e, value); 1905 break; 1906 case CIRRUS_MMIO_BLTWRITEMASK: 1907 cirrus_vga_write_gr(s, 0x2f, value); 1908 break; 1909 case CIRRUS_MMIO_BLTMODE: 1910 cirrus_vga_write_gr(s, 0x30, value); 1911 break; 1912 case CIRRUS_MMIO_BLTROP: 1913 cirrus_vga_write_gr(s, 0x32, value); 1914 break; 1915 case CIRRUS_MMIO_BLTMODEEXT: 1916 cirrus_vga_write_gr(s, 0x33, value); 1917 break; 1918 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): 1919 cirrus_vga_write_gr(s, 0x34, value); 1920 break; 1921 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): 1922 cirrus_vga_write_gr(s, 0x35, value); 1923 break; 1924 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): 1925 cirrus_vga_write_gr(s, 0x38, value); 1926 break; 1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): 1928 cirrus_vga_write_gr(s, 0x39, value); 1929 break; 1930 case CIRRUS_MMIO_BLTSTATUS: 1931 cirrus_vga_write_gr(s, 0x31, value); 1932 break; 1933 default: 1934 #ifdef DEBUG_CIRRUS 1935 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n", 1936 address, value); 1937 #endif 1938 break; 1939 } 1940 } 1941 1942 /*************************************** 1943 * 1944 * write mode 4/5 1945 * 1946 ***************************************/ 1947 1948 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, 1949 unsigned mode, 1950 unsigned offset, 1951 uint32_t mem_value) 1952 { 1953 int x; 1954 unsigned val = mem_value; 1955 uint8_t *dst; 1956 1957 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); 1958 for (x = 0; x < 8; x++) { 1959 if (val & 0x80) { 1960 *dst = s->cirrus_shadow_gr1; 1961 } else if (mode == 5) { 1962 *dst = s->cirrus_shadow_gr0; 1963 } 1964 val <<= 1; 1965 dst++; 1966 } 1967 memory_region_set_dirty(&s->vga.vram, offset, 8); 1968 } 1969 1970 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, 1971 unsigned mode, 1972 unsigned offset, 1973 uint32_t mem_value) 1974 { 1975 int x; 1976 unsigned val = mem_value; 1977 uint8_t *dst; 1978 1979 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); 1980 for (x = 0; x < 8; x++) { 1981 if (val & 0x80) { 1982 *dst = s->cirrus_shadow_gr1; 1983 *(dst + 1) = s->vga.gr[0x11]; 1984 } else if (mode == 5) { 1985 *dst = s->cirrus_shadow_gr0; 1986 *(dst + 1) = s->vga.gr[0x10]; 1987 } 1988 val <<= 1; 1989 dst += 2; 1990 } 1991 memory_region_set_dirty(&s->vga.vram, offset, 16); 1992 } 1993 1994 /*************************************** 1995 * 1996 * memory access between 0xa0000-0xbffff 1997 * 1998 ***************************************/ 1999 2000 static uint64_t cirrus_vga_mem_read(void *opaque, 2001 hwaddr addr, 2002 uint32_t size) 2003 { 2004 CirrusVGAState *s = opaque; 2005 unsigned bank_index; 2006 unsigned bank_offset; 2007 uint32_t val; 2008 2009 if ((s->vga.sr[0x07] & 0x01) == 0) { 2010 return vga_mem_readb(&s->vga, addr); 2011 } 2012 2013 if (addr < 0x10000) { 2014 /* XXX handle bitblt */ 2015 /* video memory */ 2016 bank_index = addr >> 15; 2017 bank_offset = addr & 0x7fff; 2018 if (bank_offset < s->cirrus_bank_limit[bank_index]) { 2019 bank_offset += s->cirrus_bank_base[bank_index]; 2020 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2021 bank_offset <<= 4; 2022 } else if (s->vga.gr[0x0B] & 0x02) { 2023 bank_offset <<= 3; 2024 } 2025 bank_offset &= s->cirrus_addr_mask; 2026 val = *(s->vga.vram_ptr + bank_offset); 2027 } else 2028 val = 0xff; 2029 } else if (addr >= 0x18000 && addr < 0x18100) { 2030 /* memory-mapped I/O */ 2031 val = 0xff; 2032 if ((s->vga.sr[0x17] & 0x44) == 0x04) { 2033 val = cirrus_mmio_blt_read(s, addr & 0xff); 2034 } 2035 } else { 2036 val = 0xff; 2037 #ifdef DEBUG_CIRRUS 2038 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); 2039 #endif 2040 } 2041 return val; 2042 } 2043 2044 static void cirrus_vga_mem_write(void *opaque, 2045 hwaddr addr, 2046 uint64_t mem_value, 2047 uint32_t size) 2048 { 2049 CirrusVGAState *s = opaque; 2050 unsigned bank_index; 2051 unsigned bank_offset; 2052 unsigned mode; 2053 2054 if ((s->vga.sr[0x07] & 0x01) == 0) { 2055 vga_mem_writeb(&s->vga, addr, mem_value); 2056 return; 2057 } 2058 2059 if (addr < 0x10000) { 2060 if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2061 /* bitblt */ 2062 *s->cirrus_srcptr++ = (uint8_t) mem_value; 2063 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { 2064 cirrus_bitblt_cputovideo_next(s); 2065 } 2066 } else { 2067 /* video memory */ 2068 bank_index = addr >> 15; 2069 bank_offset = addr & 0x7fff; 2070 if (bank_offset < s->cirrus_bank_limit[bank_index]) { 2071 bank_offset += s->cirrus_bank_base[bank_index]; 2072 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2073 bank_offset <<= 4; 2074 } else if (s->vga.gr[0x0B] & 0x02) { 2075 bank_offset <<= 3; 2076 } 2077 bank_offset &= s->cirrus_addr_mask; 2078 mode = s->vga.gr[0x05] & 0x7; 2079 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { 2080 *(s->vga.vram_ptr + bank_offset) = mem_value; 2081 memory_region_set_dirty(&s->vga.vram, bank_offset, 2082 sizeof(mem_value)); 2083 } else { 2084 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { 2085 cirrus_mem_writeb_mode4and5_8bpp(s, mode, 2086 bank_offset, 2087 mem_value); 2088 } else { 2089 cirrus_mem_writeb_mode4and5_16bpp(s, mode, 2090 bank_offset, 2091 mem_value); 2092 } 2093 } 2094 } 2095 } 2096 } else if (addr >= 0x18000 && addr < 0x18100) { 2097 /* memory-mapped I/O */ 2098 if ((s->vga.sr[0x17] & 0x44) == 0x04) { 2099 cirrus_mmio_blt_write(s, addr & 0xff, mem_value); 2100 } 2101 } else { 2102 #ifdef DEBUG_CIRRUS 2103 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr, 2104 mem_value); 2105 #endif 2106 } 2107 } 2108 2109 static const MemoryRegionOps cirrus_vga_mem_ops = { 2110 .read = cirrus_vga_mem_read, 2111 .write = cirrus_vga_mem_write, 2112 .endianness = DEVICE_LITTLE_ENDIAN, 2113 .impl = { 2114 .min_access_size = 1, 2115 .max_access_size = 1, 2116 }, 2117 }; 2118 2119 /*************************************** 2120 * 2121 * hardware cursor 2122 * 2123 ***************************************/ 2124 2125 static inline void invalidate_cursor1(CirrusVGAState *s) 2126 { 2127 if (s->last_hw_cursor_size) { 2128 vga_invalidate_scanlines(&s->vga, 2129 s->last_hw_cursor_y + s->last_hw_cursor_y_start, 2130 s->last_hw_cursor_y + s->last_hw_cursor_y_end); 2131 } 2132 } 2133 2134 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) 2135 { 2136 const uint8_t *src; 2137 uint32_t content; 2138 int y, y_min, y_max; 2139 2140 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; 2141 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { 2142 src += (s->vga.sr[0x13] & 0x3c) * 256; 2143 y_min = 64; 2144 y_max = -1; 2145 for(y = 0; y < 64; y++) { 2146 content = ((uint32_t *)src)[0] | 2147 ((uint32_t *)src)[1] | 2148 ((uint32_t *)src)[2] | 2149 ((uint32_t *)src)[3]; 2150 if (content) { 2151 if (y < y_min) 2152 y_min = y; 2153 if (y > y_max) 2154 y_max = y; 2155 } 2156 src += 16; 2157 } 2158 } else { 2159 src += (s->vga.sr[0x13] & 0x3f) * 256; 2160 y_min = 32; 2161 y_max = -1; 2162 for(y = 0; y < 32; y++) { 2163 content = ((uint32_t *)src)[0] | 2164 ((uint32_t *)(src + 128))[0]; 2165 if (content) { 2166 if (y < y_min) 2167 y_min = y; 2168 if (y > y_max) 2169 y_max = y; 2170 } 2171 src += 4; 2172 } 2173 } 2174 if (y_min > y_max) { 2175 s->last_hw_cursor_y_start = 0; 2176 s->last_hw_cursor_y_end = 0; 2177 } else { 2178 s->last_hw_cursor_y_start = y_min; 2179 s->last_hw_cursor_y_end = y_max + 1; 2180 } 2181 } 2182 2183 /* NOTE: we do not currently handle the cursor bitmap change, so we 2184 update the cursor only if it moves. */ 2185 static void cirrus_cursor_invalidate(VGACommonState *s1) 2186 { 2187 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); 2188 int size; 2189 2190 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { 2191 size = 0; 2192 } else { 2193 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) 2194 size = 64; 2195 else 2196 size = 32; 2197 } 2198 /* invalidate last cursor and new cursor if any change */ 2199 if (s->last_hw_cursor_size != size || 2200 s->last_hw_cursor_x != s->vga.hw_cursor_x || 2201 s->last_hw_cursor_y != s->vga.hw_cursor_y) { 2202 2203 invalidate_cursor1(s); 2204 2205 s->last_hw_cursor_size = size; 2206 s->last_hw_cursor_x = s->vga.hw_cursor_x; 2207 s->last_hw_cursor_y = s->vga.hw_cursor_y; 2208 /* compute the real cursor min and max y */ 2209 cirrus_cursor_compute_yrange(s); 2210 invalidate_cursor1(s); 2211 } 2212 } 2213 2214 static void vga_draw_cursor_line(uint8_t *d1, 2215 const uint8_t *src1, 2216 int poffset, int w, 2217 unsigned int color0, 2218 unsigned int color1, 2219 unsigned int color_xor) 2220 { 2221 const uint8_t *plane0, *plane1; 2222 int x, b0, b1; 2223 uint8_t *d; 2224 2225 d = d1; 2226 plane0 = src1; 2227 plane1 = src1 + poffset; 2228 for (x = 0; x < w; x++) { 2229 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1; 2230 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1; 2231 switch (b0 | (b1 << 1)) { 2232 case 0: 2233 break; 2234 case 1: 2235 ((uint32_t *)d)[0] ^= color_xor; 2236 break; 2237 case 2: 2238 ((uint32_t *)d)[0] = color0; 2239 break; 2240 case 3: 2241 ((uint32_t *)d)[0] = color1; 2242 break; 2243 } 2244 d += 4; 2245 } 2246 } 2247 2248 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) 2249 { 2250 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); 2251 int w, h, x1, x2, poffset; 2252 unsigned int color0, color1; 2253 const uint8_t *palette, *src; 2254 uint32_t content; 2255 2256 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) 2257 return; 2258 /* fast test to see if the cursor intersects with the scan line */ 2259 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { 2260 h = 64; 2261 } else { 2262 h = 32; 2263 } 2264 if (scr_y < s->vga.hw_cursor_y || 2265 scr_y >= (s->vga.hw_cursor_y + h)) { 2266 return; 2267 } 2268 2269 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; 2270 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { 2271 src += (s->vga.sr[0x13] & 0x3c) * 256; 2272 src += (scr_y - s->vga.hw_cursor_y) * 16; 2273 poffset = 8; 2274 content = ((uint32_t *)src)[0] | 2275 ((uint32_t *)src)[1] | 2276 ((uint32_t *)src)[2] | 2277 ((uint32_t *)src)[3]; 2278 } else { 2279 src += (s->vga.sr[0x13] & 0x3f) * 256; 2280 src += (scr_y - s->vga.hw_cursor_y) * 4; 2281 2282 2283 poffset = 128; 2284 content = ((uint32_t *)src)[0] | 2285 ((uint32_t *)(src + 128))[0]; 2286 } 2287 /* if nothing to draw, no need to continue */ 2288 if (!content) 2289 return; 2290 w = h; 2291 2292 x1 = s->vga.hw_cursor_x; 2293 if (x1 >= s->vga.last_scr_width) 2294 return; 2295 x2 = s->vga.hw_cursor_x + w; 2296 if (x2 > s->vga.last_scr_width) 2297 x2 = s->vga.last_scr_width; 2298 w = x2 - x1; 2299 palette = s->cirrus_hidden_palette; 2300 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]), 2301 c6_to_8(palette[0x0 * 3 + 1]), 2302 c6_to_8(palette[0x0 * 3 + 2])); 2303 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]), 2304 c6_to_8(palette[0xf * 3 + 1]), 2305 c6_to_8(palette[0xf * 3 + 2])); 2306 d1 += x1 * 4; 2307 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff); 2308 } 2309 2310 /*************************************** 2311 * 2312 * LFB memory access 2313 * 2314 ***************************************/ 2315 2316 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr, 2317 unsigned size) 2318 { 2319 CirrusVGAState *s = opaque; 2320 uint32_t ret; 2321 2322 addr &= s->cirrus_addr_mask; 2323 2324 if (((s->vga.sr[0x17] & 0x44) == 0x44) && 2325 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { 2326 /* memory-mapped I/O */ 2327 ret = cirrus_mmio_blt_read(s, addr & 0xff); 2328 } else if (0) { 2329 /* XXX handle bitblt */ 2330 ret = 0xff; 2331 } else { 2332 /* video memory */ 2333 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2334 addr <<= 4; 2335 } else if (s->vga.gr[0x0B] & 0x02) { 2336 addr <<= 3; 2337 } 2338 addr &= s->cirrus_addr_mask; 2339 ret = *(s->vga.vram_ptr + addr); 2340 } 2341 2342 return ret; 2343 } 2344 2345 static void cirrus_linear_write(void *opaque, hwaddr addr, 2346 uint64_t val, unsigned size) 2347 { 2348 CirrusVGAState *s = opaque; 2349 unsigned mode; 2350 2351 addr &= s->cirrus_addr_mask; 2352 2353 if (((s->vga.sr[0x17] & 0x44) == 0x44) && 2354 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { 2355 /* memory-mapped I/O */ 2356 cirrus_mmio_blt_write(s, addr & 0xff, val); 2357 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2358 /* bitblt */ 2359 *s->cirrus_srcptr++ = (uint8_t) val; 2360 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { 2361 cirrus_bitblt_cputovideo_next(s); 2362 } 2363 } else { 2364 /* video memory */ 2365 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2366 addr <<= 4; 2367 } else if (s->vga.gr[0x0B] & 0x02) { 2368 addr <<= 3; 2369 } 2370 addr &= s->cirrus_addr_mask; 2371 2372 mode = s->vga.gr[0x05] & 0x7; 2373 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { 2374 *(s->vga.vram_ptr + addr) = (uint8_t) val; 2375 memory_region_set_dirty(&s->vga.vram, addr, 1); 2376 } else { 2377 if ((s->vga.gr[0x0B] & 0x14) != 0x14) { 2378 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); 2379 } else { 2380 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); 2381 } 2382 } 2383 } 2384 } 2385 2386 /*************************************** 2387 * 2388 * system to screen memory access 2389 * 2390 ***************************************/ 2391 2392 2393 static uint64_t cirrus_linear_bitblt_read(void *opaque, 2394 hwaddr addr, 2395 unsigned size) 2396 { 2397 CirrusVGAState *s = opaque; 2398 uint32_t ret; 2399 2400 /* XXX handle bitblt */ 2401 (void)s; 2402 ret = 0xff; 2403 return ret; 2404 } 2405 2406 static void cirrus_linear_bitblt_write(void *opaque, 2407 hwaddr addr, 2408 uint64_t val, 2409 unsigned size) 2410 { 2411 CirrusVGAState *s = opaque; 2412 2413 if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2414 /* bitblt */ 2415 *s->cirrus_srcptr++ = (uint8_t) val; 2416 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { 2417 cirrus_bitblt_cputovideo_next(s); 2418 } 2419 } 2420 } 2421 2422 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { 2423 .read = cirrus_linear_bitblt_read, 2424 .write = cirrus_linear_bitblt_write, 2425 .endianness = DEVICE_LITTLE_ENDIAN, 2426 .impl = { 2427 .min_access_size = 1, 2428 .max_access_size = 1, 2429 }, 2430 }; 2431 2432 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank) 2433 { 2434 MemoryRegion *mr = &s->cirrus_bank[bank]; 2435 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end) 2436 && !((s->vga.sr[0x07] & 0x01) == 0) 2437 && !((s->vga.gr[0x0B] & 0x14) == 0x14) 2438 && !(s->vga.gr[0x0B] & 0x02); 2439 2440 memory_region_set_enabled(mr, enabled); 2441 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); 2442 } 2443 2444 static void map_linear_vram(CirrusVGAState *s) 2445 { 2446 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) { 2447 s->linear_vram = true; 2448 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); 2449 } 2450 map_linear_vram_bank(s, 0); 2451 map_linear_vram_bank(s, 1); 2452 } 2453 2454 static void unmap_linear_vram(CirrusVGAState *s) 2455 { 2456 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) { 2457 s->linear_vram = false; 2458 memory_region_del_subregion(&s->pci_bar, &s->vga.vram); 2459 } 2460 memory_region_set_enabled(&s->cirrus_bank[0], false); 2461 memory_region_set_enabled(&s->cirrus_bank[1], false); 2462 } 2463 2464 /* Compute the memory access functions */ 2465 static void cirrus_update_memory_access(CirrusVGAState *s) 2466 { 2467 unsigned mode; 2468 2469 memory_region_transaction_begin(); 2470 if ((s->vga.sr[0x17] & 0x44) == 0x44) { 2471 goto generic_io; 2472 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2473 goto generic_io; 2474 } else { 2475 if ((s->vga.gr[0x0B] & 0x14) == 0x14) { 2476 goto generic_io; 2477 } else if (s->vga.gr[0x0B] & 0x02) { 2478 goto generic_io; 2479 } 2480 2481 mode = s->vga.gr[0x05] & 0x7; 2482 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { 2483 map_linear_vram(s); 2484 } else { 2485 generic_io: 2486 unmap_linear_vram(s); 2487 } 2488 } 2489 memory_region_transaction_commit(); 2490 } 2491 2492 2493 /* I/O ports */ 2494 2495 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr, 2496 unsigned size) 2497 { 2498 CirrusVGAState *c = opaque; 2499 VGACommonState *s = &c->vga; 2500 int val, index; 2501 2502 addr += 0x3b0; 2503 2504 if (vga_ioport_invalid(s, addr)) { 2505 val = 0xff; 2506 } else { 2507 switch (addr) { 2508 case 0x3c0: 2509 if (s->ar_flip_flop == 0) { 2510 val = s->ar_index; 2511 } else { 2512 val = 0; 2513 } 2514 break; 2515 case 0x3c1: 2516 index = s->ar_index & 0x1f; 2517 if (index < 21) 2518 val = s->ar[index]; 2519 else 2520 val = 0; 2521 break; 2522 case 0x3c2: 2523 val = s->st00; 2524 break; 2525 case 0x3c4: 2526 val = s->sr_index; 2527 break; 2528 case 0x3c5: 2529 val = cirrus_vga_read_sr(c); 2530 break; 2531 #ifdef DEBUG_VGA_REG 2532 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); 2533 #endif 2534 break; 2535 case 0x3c6: 2536 val = cirrus_read_hidden_dac(c); 2537 break; 2538 case 0x3c7: 2539 val = s->dac_state; 2540 break; 2541 case 0x3c8: 2542 val = s->dac_write_index; 2543 c->cirrus_hidden_dac_lockindex = 0; 2544 break; 2545 case 0x3c9: 2546 val = cirrus_vga_read_palette(c); 2547 break; 2548 case 0x3ca: 2549 val = s->fcr; 2550 break; 2551 case 0x3cc: 2552 val = s->msr; 2553 break; 2554 case 0x3ce: 2555 val = s->gr_index; 2556 break; 2557 case 0x3cf: 2558 val = cirrus_vga_read_gr(c, s->gr_index); 2559 #ifdef DEBUG_VGA_REG 2560 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); 2561 #endif 2562 break; 2563 case 0x3b4: 2564 case 0x3d4: 2565 val = s->cr_index; 2566 break; 2567 case 0x3b5: 2568 case 0x3d5: 2569 val = cirrus_vga_read_cr(c, s->cr_index); 2570 #ifdef DEBUG_VGA_REG 2571 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); 2572 #endif 2573 break; 2574 case 0x3ba: 2575 case 0x3da: 2576 /* just toggle to fool polling */ 2577 val = s->st01 = s->retrace(s); 2578 s->ar_flip_flop = 0; 2579 break; 2580 default: 2581 val = 0x00; 2582 break; 2583 } 2584 } 2585 #if defined(DEBUG_VGA) 2586 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val); 2587 #endif 2588 return val; 2589 } 2590 2591 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val, 2592 unsigned size) 2593 { 2594 CirrusVGAState *c = opaque; 2595 VGACommonState *s = &c->vga; 2596 int index; 2597 2598 addr += 0x3b0; 2599 2600 /* check port range access depending on color/monochrome mode */ 2601 if (vga_ioport_invalid(s, addr)) { 2602 return; 2603 } 2604 #ifdef DEBUG_VGA 2605 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val); 2606 #endif 2607 2608 switch (addr) { 2609 case 0x3c0: 2610 if (s->ar_flip_flop == 0) { 2611 val &= 0x3f; 2612 s->ar_index = val; 2613 } else { 2614 index = s->ar_index & 0x1f; 2615 switch (index) { 2616 case 0x00 ... 0x0f: 2617 s->ar[index] = val & 0x3f; 2618 break; 2619 case 0x10: 2620 s->ar[index] = val & ~0x10; 2621 break; 2622 case 0x11: 2623 s->ar[index] = val; 2624 break; 2625 case 0x12: 2626 s->ar[index] = val & ~0xc0; 2627 break; 2628 case 0x13: 2629 s->ar[index] = val & ~0xf0; 2630 break; 2631 case 0x14: 2632 s->ar[index] = val & ~0xf0; 2633 break; 2634 default: 2635 break; 2636 } 2637 } 2638 s->ar_flip_flop ^= 1; 2639 break; 2640 case 0x3c2: 2641 s->msr = val & ~0x10; 2642 s->update_retrace_info(s); 2643 break; 2644 case 0x3c4: 2645 s->sr_index = val; 2646 break; 2647 case 0x3c5: 2648 #ifdef DEBUG_VGA_REG 2649 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val); 2650 #endif 2651 cirrus_vga_write_sr(c, val); 2652 break; 2653 case 0x3c6: 2654 cirrus_write_hidden_dac(c, val); 2655 break; 2656 case 0x3c7: 2657 s->dac_read_index = val; 2658 s->dac_sub_index = 0; 2659 s->dac_state = 3; 2660 break; 2661 case 0x3c8: 2662 s->dac_write_index = val; 2663 s->dac_sub_index = 0; 2664 s->dac_state = 0; 2665 break; 2666 case 0x3c9: 2667 cirrus_vga_write_palette(c, val); 2668 break; 2669 case 0x3ce: 2670 s->gr_index = val; 2671 break; 2672 case 0x3cf: 2673 #ifdef DEBUG_VGA_REG 2674 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val); 2675 #endif 2676 cirrus_vga_write_gr(c, s->gr_index, val); 2677 break; 2678 case 0x3b4: 2679 case 0x3d4: 2680 s->cr_index = val; 2681 break; 2682 case 0x3b5: 2683 case 0x3d5: 2684 #ifdef DEBUG_VGA_REG 2685 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val); 2686 #endif 2687 cirrus_vga_write_cr(c, val); 2688 break; 2689 case 0x3ba: 2690 case 0x3da: 2691 s->fcr = val & 0x10; 2692 break; 2693 } 2694 } 2695 2696 /*************************************** 2697 * 2698 * memory-mapped I/O access 2699 * 2700 ***************************************/ 2701 2702 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr, 2703 unsigned size) 2704 { 2705 CirrusVGAState *s = opaque; 2706 2707 if (addr >= 0x100) { 2708 return cirrus_mmio_blt_read(s, addr - 0x100); 2709 } else { 2710 return cirrus_vga_ioport_read(s, addr + 0x10, size); 2711 } 2712 } 2713 2714 static void cirrus_mmio_write(void *opaque, hwaddr addr, 2715 uint64_t val, unsigned size) 2716 { 2717 CirrusVGAState *s = opaque; 2718 2719 if (addr >= 0x100) { 2720 cirrus_mmio_blt_write(s, addr - 0x100, val); 2721 } else { 2722 cirrus_vga_ioport_write(s, addr + 0x10, val, size); 2723 } 2724 } 2725 2726 static const MemoryRegionOps cirrus_mmio_io_ops = { 2727 .read = cirrus_mmio_read, 2728 .write = cirrus_mmio_write, 2729 .endianness = DEVICE_LITTLE_ENDIAN, 2730 .impl = { 2731 .min_access_size = 1, 2732 .max_access_size = 1, 2733 }, 2734 }; 2735 2736 /* load/save state */ 2737 2738 static int cirrus_post_load(void *opaque, int version_id) 2739 { 2740 CirrusVGAState *s = opaque; 2741 2742 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; 2743 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; 2744 2745 cirrus_update_memory_access(s); 2746 /* force refresh */ 2747 s->vga.graphic_mode = -1; 2748 cirrus_update_bank_ptr(s, 0); 2749 cirrus_update_bank_ptr(s, 1); 2750 return 0; 2751 } 2752 2753 static const VMStateDescription vmstate_cirrus_vga = { 2754 .name = "cirrus_vga", 2755 .version_id = 2, 2756 .minimum_version_id = 1, 2757 .post_load = cirrus_post_load, 2758 .fields = (VMStateField[]) { 2759 VMSTATE_UINT32(vga.latch, CirrusVGAState), 2760 VMSTATE_UINT8(vga.sr_index, CirrusVGAState), 2761 VMSTATE_BUFFER(vga.sr, CirrusVGAState), 2762 VMSTATE_UINT8(vga.gr_index, CirrusVGAState), 2763 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState), 2764 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState), 2765 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2), 2766 VMSTATE_UINT8(vga.ar_index, CirrusVGAState), 2767 VMSTATE_BUFFER(vga.ar, CirrusVGAState), 2768 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState), 2769 VMSTATE_UINT8(vga.cr_index, CirrusVGAState), 2770 VMSTATE_BUFFER(vga.cr, CirrusVGAState), 2771 VMSTATE_UINT8(vga.msr, CirrusVGAState), 2772 VMSTATE_UINT8(vga.fcr, CirrusVGAState), 2773 VMSTATE_UINT8(vga.st00, CirrusVGAState), 2774 VMSTATE_UINT8(vga.st01, CirrusVGAState), 2775 VMSTATE_UINT8(vga.dac_state, CirrusVGAState), 2776 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState), 2777 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState), 2778 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState), 2779 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState), 2780 VMSTATE_BUFFER(vga.palette, CirrusVGAState), 2781 VMSTATE_INT32(vga.bank_offset, CirrusVGAState), 2782 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState), 2783 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState), 2784 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState), 2785 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState), 2786 /* XXX: we do not save the bitblt state - we assume we do not save 2787 the state when the blitter is active */ 2788 VMSTATE_END_OF_LIST() 2789 } 2790 }; 2791 2792 static const VMStateDescription vmstate_pci_cirrus_vga = { 2793 .name = "cirrus_vga", 2794 .version_id = 2, 2795 .minimum_version_id = 2, 2796 .fields = (VMStateField[]) { 2797 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState), 2798 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0, 2799 vmstate_cirrus_vga, CirrusVGAState), 2800 VMSTATE_END_OF_LIST() 2801 } 2802 }; 2803 2804 /*************************************** 2805 * 2806 * initialize 2807 * 2808 ***************************************/ 2809 2810 static void cirrus_reset(void *opaque) 2811 { 2812 CirrusVGAState *s = opaque; 2813 2814 vga_common_reset(&s->vga); 2815 unmap_linear_vram(s); 2816 s->vga.sr[0x06] = 0x0f; 2817 if (s->device_id == CIRRUS_ID_CLGD5446) { 2818 /* 4MB 64 bit memory config, always PCI */ 2819 s->vga.sr[0x1F] = 0x2d; // MemClock 2820 s->vga.gr[0x18] = 0x0f; // fastest memory configuration 2821 s->vga.sr[0x0f] = 0x98; 2822 s->vga.sr[0x17] = 0x20; 2823 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ 2824 } else { 2825 s->vga.sr[0x1F] = 0x22; // MemClock 2826 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M; 2827 s->vga.sr[0x17] = s->bustype; 2828 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ 2829 } 2830 s->vga.cr[0x27] = s->device_id; 2831 2832 s->cirrus_hidden_dac_lockindex = 5; 2833 s->cirrus_hidden_dac_data = 0; 2834 } 2835 2836 static const MemoryRegionOps cirrus_linear_io_ops = { 2837 .read = cirrus_linear_read, 2838 .write = cirrus_linear_write, 2839 .endianness = DEVICE_LITTLE_ENDIAN, 2840 .impl = { 2841 .min_access_size = 1, 2842 .max_access_size = 1, 2843 }, 2844 }; 2845 2846 static const MemoryRegionOps cirrus_vga_io_ops = { 2847 .read = cirrus_vga_ioport_read, 2848 .write = cirrus_vga_ioport_write, 2849 .endianness = DEVICE_LITTLE_ENDIAN, 2850 .impl = { 2851 .min_access_size = 1, 2852 .max_access_size = 1, 2853 }, 2854 }; 2855 2856 static void cirrus_init_common(CirrusVGAState *s, Object *owner, 2857 int device_id, int is_pci, 2858 MemoryRegion *system_memory, 2859 MemoryRegion *system_io) 2860 { 2861 int i; 2862 static int inited; 2863 2864 if (!inited) { 2865 inited = 1; 2866 for(i = 0;i < 256; i++) 2867 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */ 2868 rop_to_index[CIRRUS_ROP_0] = 0; 2869 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1; 2870 rop_to_index[CIRRUS_ROP_NOP] = 2; 2871 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3; 2872 rop_to_index[CIRRUS_ROP_NOTDST] = 4; 2873 rop_to_index[CIRRUS_ROP_SRC] = 5; 2874 rop_to_index[CIRRUS_ROP_1] = 6; 2875 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7; 2876 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8; 2877 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9; 2878 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10; 2879 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11; 2880 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12; 2881 rop_to_index[CIRRUS_ROP_NOTSRC] = 13; 2882 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14; 2883 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15; 2884 s->device_id = device_id; 2885 if (is_pci) 2886 s->bustype = CIRRUS_BUSTYPE_PCI; 2887 else 2888 s->bustype = CIRRUS_BUSTYPE_ISA; 2889 } 2890 2891 /* Register ioport 0x3b0 - 0x3df */ 2892 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s, 2893 "cirrus-io", 0x30); 2894 memory_region_set_flush_coalesced(&s->cirrus_vga_io); 2895 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io); 2896 2897 memory_region_init(&s->low_mem_container, owner, 2898 "cirrus-lowmem-container", 2899 0x20000); 2900 2901 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s, 2902 "cirrus-low-memory", 0x20000); 2903 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem); 2904 for (i = 0; i < 2; ++i) { 2905 static const char *names[] = { "vga.bank0", "vga.bank1" }; 2906 MemoryRegion *bank = &s->cirrus_bank[i]; 2907 memory_region_init_alias(bank, owner, names[i], &s->vga.vram, 2908 0, 0x8000); 2909 memory_region_set_enabled(bank, false); 2910 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000, 2911 bank, 1); 2912 } 2913 memory_region_add_subregion_overlap(system_memory, 2914 0x000a0000, 2915 &s->low_mem_container, 2916 1); 2917 memory_region_set_coalescing(&s->low_mem); 2918 2919 /* I/O handler for LFB */ 2920 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s, 2921 "cirrus-linear-io", s->vga.vram_size_mb 2922 * 1024 * 1024); 2923 memory_region_set_flush_coalesced(&s->cirrus_linear_io); 2924 2925 /* I/O handler for LFB */ 2926 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner, 2927 &cirrus_linear_bitblt_io_ops, 2928 s, 2929 "cirrus-bitblt-mmio", 2930 0x400000); 2931 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io); 2932 2933 /* I/O handler for memory-mapped I/O */ 2934 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s, 2935 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE); 2936 memory_region_set_flush_coalesced(&s->cirrus_mmio_io); 2937 2938 s->real_vram_size = 2939 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; 2940 2941 /* XXX: s->vga.vram_size must be a power of two */ 2942 s->cirrus_addr_mask = s->real_vram_size - 1; 2943 s->linear_mmio_mask = s->real_vram_size - 256; 2944 2945 s->vga.get_bpp = cirrus_get_bpp; 2946 s->vga.get_offsets = cirrus_get_offsets; 2947 s->vga.get_resolution = cirrus_get_resolution; 2948 s->vga.cursor_invalidate = cirrus_cursor_invalidate; 2949 s->vga.cursor_draw_line = cirrus_cursor_draw_line; 2950 2951 qemu_register_reset(cirrus_reset, s); 2952 } 2953 2954 /*************************************** 2955 * 2956 * ISA bus support 2957 * 2958 ***************************************/ 2959 2960 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp) 2961 { 2962 ISADevice *isadev = ISA_DEVICE(dev); 2963 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev); 2964 VGACommonState *s = &d->cirrus_vga.vga; 2965 2966 /* follow real hardware, cirrus card emulated has 4 MB video memory. 2967 Also accept 8 MB/16 MB for backward compatibility. */ 2968 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 && 2969 s->vram_size_mb != 16) { 2970 error_setg(errp, "Invalid cirrus_vga ram size '%u'", 2971 s->vram_size_mb); 2972 return; 2973 } 2974 vga_common_init(s, OBJECT(dev), true); 2975 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0, 2976 isa_address_space(isadev), 2977 isa_address_space_io(isadev)); 2978 s->con = graphic_console_init(dev, 0, s->hw_ops, s); 2979 rom_add_vga(VGABIOS_CIRRUS_FILENAME); 2980 /* XXX ISA-LFB support */ 2981 /* FIXME not qdev yet */ 2982 } 2983 2984 static Property isa_cirrus_vga_properties[] = { 2985 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState, 2986 cirrus_vga.vga.vram_size_mb, 8), 2987 DEFINE_PROP_END_OF_LIST(), 2988 }; 2989 2990 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) 2991 { 2992 DeviceClass *dc = DEVICE_CLASS(klass); 2993 2994 dc->vmsd = &vmstate_cirrus_vga; 2995 dc->realize = isa_cirrus_vga_realizefn; 2996 dc->props = isa_cirrus_vga_properties; 2997 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2998 } 2999 3000 static const TypeInfo isa_cirrus_vga_info = { 3001 .name = TYPE_ISA_CIRRUS_VGA, 3002 .parent = TYPE_ISA_DEVICE, 3003 .instance_size = sizeof(ISACirrusVGAState), 3004 .class_init = isa_cirrus_vga_class_init, 3005 }; 3006 3007 /*************************************** 3008 * 3009 * PCI bus support 3010 * 3011 ***************************************/ 3012 3013 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp) 3014 { 3015 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev); 3016 CirrusVGAState *s = &d->cirrus_vga; 3017 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 3018 int16_t device_id = pc->device_id; 3019 3020 /* follow real hardware, cirrus card emulated has 4 MB video memory. 3021 Also accept 8 MB/16 MB for backward compatibility. */ 3022 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 && 3023 s->vga.vram_size_mb != 16) { 3024 error_setg(errp, "Invalid cirrus_vga ram size '%u'", 3025 s->vga.vram_size_mb); 3026 return; 3027 } 3028 /* setup VGA */ 3029 vga_common_init(&s->vga, OBJECT(dev), true); 3030 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev), 3031 pci_address_space_io(dev)); 3032 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga); 3033 3034 /* setup PCI */ 3035 3036 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000); 3037 3038 /* XXX: add byte swapping apertures */ 3039 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io); 3040 memory_region_add_subregion(&s->pci_bar, 0x1000000, 3041 &s->cirrus_linear_bitblt_io); 3042 3043 /* setup memory space */ 3044 /* memory #0 LFB */ 3045 /* memory #1 memory-mapped I/O */ 3046 /* XXX: s->vga.vram_size must be a power of two */ 3047 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar); 3048 if (device_id == CIRRUS_ID_CLGD5446) { 3049 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); 3050 } 3051 } 3052 3053 static Property pci_vga_cirrus_properties[] = { 3054 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState, 3055 cirrus_vga.vga.vram_size_mb, 8), 3056 DEFINE_PROP_END_OF_LIST(), 3057 }; 3058 3059 static void cirrus_vga_class_init(ObjectClass *klass, void *data) 3060 { 3061 DeviceClass *dc = DEVICE_CLASS(klass); 3062 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3063 3064 k->realize = pci_cirrus_vga_realize; 3065 k->romfile = VGABIOS_CIRRUS_FILENAME; 3066 k->vendor_id = PCI_VENDOR_ID_CIRRUS; 3067 k->device_id = CIRRUS_ID_CLGD5446; 3068 k->class_id = PCI_CLASS_DISPLAY_VGA; 3069 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 3070 dc->desc = "Cirrus CLGD 54xx VGA"; 3071 dc->vmsd = &vmstate_pci_cirrus_vga; 3072 dc->props = pci_vga_cirrus_properties; 3073 dc->hotpluggable = false; 3074 } 3075 3076 static const TypeInfo cirrus_vga_info = { 3077 .name = TYPE_PCI_CIRRUS_VGA, 3078 .parent = TYPE_PCI_DEVICE, 3079 .instance_size = sizeof(PCICirrusVGAState), 3080 .class_init = cirrus_vga_class_init, 3081 }; 3082 3083 static void cirrus_vga_register_types(void) 3084 { 3085 type_register_static(&isa_cirrus_vga_info); 3086 type_register_static(&cirrus_vga_info); 3087 } 3088 3089 type_init(cirrus_vga_register_types) 3090