1 /* 2 * Samsung exynos4210 Display Controller (FIMD) 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * Based on LCD controller for Samsung S5PC1xx-based board emulation 7 * by Kirill Batuzov <batuzovk@ispras.ru> 8 * 9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sysbus.h" 29 #include "migration/vmstate.h" 30 #include "ui/console.h" 31 #include "ui/pixel_ops.h" 32 #include "qemu/bswap.h" 33 #include "qemu/module.h" 34 35 /* Debug messages configuration */ 36 #define EXYNOS4210_FIMD_DEBUG 0 37 #define EXYNOS4210_FIMD_MODE_TRACE 0 38 39 #if EXYNOS4210_FIMD_DEBUG == 0 40 #define DPRINT_L1(fmt, args...) do { } while (0) 41 #define DPRINT_L2(fmt, args...) do { } while (0) 42 #define DPRINT_ERROR(fmt, args...) do { } while (0) 43 #elif EXYNOS4210_FIMD_DEBUG == 1 44 #define DPRINT_L1(fmt, args...) \ 45 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 46 #define DPRINT_L2(fmt, args...) do { } while (0) 47 #define DPRINT_ERROR(fmt, args...) \ 48 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0) 49 #else 50 #define DPRINT_L1(fmt, args...) \ 51 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 52 #define DPRINT_L2(fmt, args...) \ 53 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 54 #define DPRINT_ERROR(fmt, args...) \ 55 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0) 56 #endif 57 58 #if EXYNOS4210_FIMD_MODE_TRACE == 0 59 #define DPRINT_TRACE(fmt, args...) do { } while (0) 60 #else 61 #define DPRINT_TRACE(fmt, args...) \ 62 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) 63 #endif 64 65 #define NUM_OF_WINDOWS 5 66 #define FIMD_REGS_SIZE 0x4114 67 68 /* Video main control registers */ 69 #define FIMD_VIDCON0 0x0000 70 #define FIMD_VIDCON1 0x0004 71 #define FIMD_VIDCON2 0x0008 72 #define FIMD_VIDCON3 0x000C 73 #define FIMD_VIDCON0_ENVID_F (1 << 0) 74 #define FIMD_VIDCON0_ENVID (1 << 1) 75 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1)) 76 #define FIMD_VIDCON1_ROMASK 0x07FFE000 77 78 /* Video time control registers */ 79 #define FIMD_VIDTCON_START 0x10 80 #define FIMD_VIDTCON_END 0x1C 81 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF 82 #define FIMD_VIDTCON2_HOR_SHIFT 0 83 #define FIMD_VIDTCON2_VER_SHIFT 11 84 85 /* Window control registers */ 86 #define FIMD_WINCON_START 0x0020 87 #define FIMD_WINCON_END 0x0030 88 #define FIMD_WINCON_ROMASK 0x82200000 89 #define FIMD_WINCON_ENWIN (1 << 0) 90 #define FIMD_WINCON_BLD_PIX (1 << 6) 91 #define FIMD_WINCON_ALPHA_MUL (1 << 7) 92 #define FIMD_WINCON_ALPHA_SEL (1 << 1) 93 #define FIMD_WINCON_SWAP 0x078000 94 #define FIMD_WINCON_SWAP_SHIFT 15 95 #define FIMD_WINCON_SWAP_WORD 0x1 96 #define FIMD_WINCON_SWAP_HWORD 0x2 97 #define FIMD_WINCON_SWAP_BYTE 0x4 98 #define FIMD_WINCON_SWAP_BITS 0x8 99 #define FIMD_WINCON_BUFSTAT_L (1 << 21) 100 #define FIMD_WINCON_BUFSTAT_H (1 << 31) 101 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31)) 102 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31)) 103 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31)) 104 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31)) 105 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30)) 106 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30)) 107 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30)) 108 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30)) 109 #define FIMD_WINCON_BUFMODE (1 << 14) 110 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC) 111 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7) 112 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF) 113 #define WIN_BPP_MODE_WITH_ALPHA(w) \ 114 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE) 115 116 /* Shadow control register */ 117 #define FIMD_SHADOWCON 0x0034 118 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w)))) 119 /* Channel mapping control register */ 120 #define FIMD_WINCHMAP 0x003C 121 122 /* Window position control registers */ 123 #define FIMD_VIDOSD_START 0x0040 124 #define FIMD_VIDOSD_END 0x0088 125 #define FIMD_VIDOSD_COORD_MASK 0x07FF 126 #define FIMD_VIDOSD_HOR_SHIFT 11 127 #define FIMD_VIDOSD_VER_SHIFT 0 128 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000 129 #define FIMD_VIDOSD_AEN0_SHIFT 12 130 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF 131 132 /* Frame buffer address registers */ 133 #define FIMD_VIDWADD0_START 0x00A0 134 #define FIMD_VIDWADD0_END 0x00C4 135 #define FIMD_VIDWADD0_END 0x00C4 136 #define FIMD_VIDWADD1_START 0x00D0 137 #define FIMD_VIDWADD1_END 0x00F4 138 #define FIMD_VIDWADD2_START 0x0100 139 #define FIMD_VIDWADD2_END 0x0110 140 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF 141 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF 142 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13 143 #define FIMD_VIDW0ADD0_B2 0x20A0 144 #define FIMD_VIDW4ADD0_B2 0x20C0 145 146 /* Video interrupt control registers */ 147 #define FIMD_VIDINTCON0 0x130 148 #define FIMD_VIDINTCON1 0x134 149 150 /* Window color key registers */ 151 #define FIMD_WKEYCON_START 0x140 152 #define FIMD_WKEYCON_END 0x15C 153 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF 154 #define FIMD_WKEYCON0_CTL_SHIFT 24 155 #define FIMD_WKEYCON0_DIRCON (1 << 24) 156 #define FIMD_WKEYCON0_KEYEN (1 << 25) 157 #define FIMD_WKEYCON0_KEYBLEN (1 << 26) 158 /* Window color key alpha control register */ 159 #define FIMD_WKEYALPHA_START 0x160 160 #define FIMD_WKEYALPHA_END 0x16C 161 162 /* Dithering control register */ 163 #define FIMD_DITHMODE 0x170 164 165 /* Window alpha control registers */ 166 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F 167 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0 168 #define FIMD_VIDWALPHA_START 0x21C 169 #define FIMD_VIDWALPHA_END 0x240 170 171 /* Window color map registers */ 172 #define FIMD_WINMAP_START 0x180 173 #define FIMD_WINMAP_END 0x190 174 #define FIMD_WINMAP_EN (1 << 24) 175 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF 176 177 /* Window palette control registers */ 178 #define FIMD_WPALCON_HIGH 0x019C 179 #define FIMD_WPALCON_LOW 0x01A0 180 #define FIMD_WPALCON_UPDATEEN (1 << 9) 181 #define FIMD_WPAL_W0PAL_L 0x07 182 #define FIMD_WPAL_W0PAL_L_SHT 0 183 #define FIMD_WPAL_W1PAL_L 0x07 184 #define FIMD_WPAL_W1PAL_L_SHT 3 185 #define FIMD_WPAL_W2PAL_L 0x01 186 #define FIMD_WPAL_W2PAL_L_SHT 6 187 #define FIMD_WPAL_W2PAL_H 0x06 188 #define FIMD_WPAL_W2PAL_H_SHT 8 189 #define FIMD_WPAL_W3PAL_L 0x01 190 #define FIMD_WPAL_W3PAL_L_SHT 7 191 #define FIMD_WPAL_W3PAL_H 0x06 192 #define FIMD_WPAL_W3PAL_H_SHT 12 193 #define FIMD_WPAL_W4PAL_L 0x01 194 #define FIMD_WPAL_W4PAL_L_SHT 8 195 #define FIMD_WPAL_W4PAL_H 0x06 196 #define FIMD_WPAL_W4PAL_H_SHT 16 197 198 /* Trigger control registers */ 199 #define FIMD_TRIGCON 0x01A4 200 #define FIMD_TRIGCON_ROMASK 0x00000004 201 202 /* LCD I80 Interface Control */ 203 #define FIMD_I80IFCON_START 0x01B0 204 #define FIMD_I80IFCON_END 0x01BC 205 /* Color gain control register */ 206 #define FIMD_COLORGAINCON 0x01C0 207 /* LCD i80 Interface Command Control */ 208 #define FIMD_LDI_CMDCON0 0x01D0 209 #define FIMD_LDI_CMDCON1 0x01D4 210 /* I80 System Interface Manual Command Control */ 211 #define FIMD_SIFCCON0 0x01E0 212 #define FIMD_SIFCCON2 0x01E8 213 214 /* Hue Control Registers */ 215 #define FIMD_HUECOEFCR_START 0x01EC 216 #define FIMD_HUECOEFCR_END 0x01F4 217 #define FIMD_HUECOEFCB_START 0x01FC 218 #define FIMD_HUECOEFCB_END 0x0208 219 #define FIMD_HUEOFFSET 0x020C 220 221 /* Video interrupt control registers */ 222 #define FIMD_VIDINT_INTFIFOPEND (1 << 0) 223 #define FIMD_VIDINT_INTFRMPEND (1 << 1) 224 #define FIMD_VIDINT_INTI80PEND (1 << 2) 225 #define FIMD_VIDINT_INTEN (1 << 0) 226 #define FIMD_VIDINT_INTFIFOEN (1 << 1) 227 #define FIMD_VIDINT_INTFRMEN (1 << 12) 228 #define FIMD_VIDINT_I80IFDONE (1 << 17) 229 230 /* Window blend equation control registers */ 231 #define FIMD_BLENDEQ_START 0x0244 232 #define FIMD_BLENDEQ_END 0x0250 233 #define FIMD_BLENDCON 0x0260 234 #define FIMD_ALPHA_8BIT (1 << 0) 235 #define FIMD_BLENDEQ_COEF_MASK 0xF 236 237 /* Window RTQOS Control Registers */ 238 #define FIMD_WRTQOSCON_START 0x0264 239 #define FIMD_WRTQOSCON_END 0x0274 240 241 /* LCD I80 Interface Command */ 242 #define FIMD_I80IFCMD_START 0x0280 243 #define FIMD_I80IFCMD_END 0x02AC 244 245 /* Shadow windows control registers */ 246 #define FIMD_SHD_ADD0_START 0x40A0 247 #define FIMD_SHD_ADD0_END 0x40C0 248 #define FIMD_SHD_ADD1_START 0x40D0 249 #define FIMD_SHD_ADD1_END 0x40F0 250 #define FIMD_SHD_ADD2_START 0x4100 251 #define FIMD_SHD_ADD2_END 0x4110 252 253 /* Palette memory */ 254 #define FIMD_PAL_MEM_START 0x2400 255 #define FIMD_PAL_MEM_END 0x37FC 256 /* Palette memory aliases for windows 0 and 1 */ 257 #define FIMD_PALMEM_AL_START 0x0400 258 #define FIMD_PALMEM_AL_END 0x0BFC 259 260 typedef struct { 261 uint8_t r, g, b; 262 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */ 263 uint32_t a; 264 } rgba; 265 #define RGBA_SIZE 7 266 267 typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p); 268 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow; 269 270 struct Exynos4210fimdWindow { 271 uint32_t wincon; /* Window control register */ 272 uint32_t buf_start[3]; /* Start address for video frame buffer */ 273 uint32_t buf_end[3]; /* End address for video frame buffer */ 274 uint32_t keycon[2]; /* Window color key registers */ 275 uint32_t keyalpha; /* Color key alpha control register */ 276 uint32_t winmap; /* Window color map register */ 277 uint32_t blendeq; /* Window blending equation control register */ 278 uint32_t rtqoscon; /* Window RTQOS Control Registers */ 279 uint32_t palette[256]; /* Palette RAM */ 280 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */ 281 uint32_t shadow_buf_end; /* End address of shadow frame buffer */ 282 uint32_t shadow_buf_size; /* Virtual shadow screen width */ 283 284 pixel_to_rgb_func *pixel_to_rgb; 285 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst, 286 bool blend); 287 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a); 288 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */ 289 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */ 290 uint32_t osdsize; /* VIDOSD2&3 register */ 291 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */ 292 uint16_t virtpage_width; /* VIDWADD2 register */ 293 uint16_t virtpage_offsize; /* VIDWADD2 register */ 294 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */ 295 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */ 296 hwaddr fb_len; /* Framebuffer length */ 297 }; 298 299 #define TYPE_EXYNOS4210_FIMD "exynos4210.fimd" 300 #define EXYNOS4210_FIMD(obj) \ 301 OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD) 302 303 typedef struct { 304 SysBusDevice parent_obj; 305 306 MemoryRegion iomem; 307 QemuConsole *console; 308 qemu_irq irq[3]; 309 310 uint32_t vidcon[4]; /* Video main control registers 0-3 */ 311 uint32_t vidtcon[4]; /* Video time control registers 0-3 */ 312 uint32_t shadowcon; /* Window shadow control register */ 313 uint32_t winchmap; /* Channel mapping control register */ 314 uint32_t vidintcon[2]; /* Video interrupt control registers */ 315 uint32_t dithmode; /* Dithering control register */ 316 uint32_t wpalcon[2]; /* Window palette control registers */ 317 uint32_t trigcon; /* Trigger control register */ 318 uint32_t i80ifcon[4]; /* I80 interface control registers */ 319 uint32_t colorgaincon; /* Color gain control register */ 320 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */ 321 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */ 322 uint32_t huecoef_cr[4]; /* Hue control registers */ 323 uint32_t huecoef_cb[4]; /* Hue control registers */ 324 uint32_t hueoffset; /* Hue offset control register */ 325 uint32_t blendcon; /* Blending control register */ 326 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */ 327 328 Exynos4210fimdWindow window[5]; /* Window-specific registers */ 329 uint8_t *ifb; /* Internal frame buffer */ 330 bool invalidate; /* Image needs to be redrawn */ 331 bool enabled; /* Display controller is enabled */ 332 } Exynos4210fimdState; 333 334 /* Perform byte/halfword/word swap of data according to WINCON */ 335 static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data) 336 { 337 int i; 338 uint64_t res; 339 uint64_t x = *data; 340 341 if (swap_ctl & FIMD_WINCON_SWAP_BITS) { 342 res = 0; 343 for (i = 0; i < 64; i++) { 344 if (x & (1ULL << (63 - i))) { 345 res |= (1ULL << i); 346 } 347 } 348 x = res; 349 } 350 351 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) { 352 x = bswap64(x); 353 } 354 355 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) { 356 x = ((x & 0x000000000000FFFFULL) << 48) | 357 ((x & 0x00000000FFFF0000ULL) << 16) | 358 ((x & 0x0000FFFF00000000ULL) >> 16) | 359 ((x & 0xFFFF000000000000ULL) >> 48); 360 } 361 362 if (swap_ctl & FIMD_WINCON_SWAP_WORD) { 363 x = ((x & 0x00000000FFFFFFFFULL) << 32) | 364 ((x & 0xFFFFFFFF00000000ULL) >> 32); 365 } 366 367 *data = x; 368 } 369 370 /* Conversion routines of Pixel data from frame buffer area to internal RGBA 371 * pixel representation. 372 * Every color component internally represented as 8-bit value. If original 373 * data has less than 8 bit for component, data is extended to 8 bit. For 374 * example, if blue component has only two possible values 0 and 1 it will be 375 * extended to 0 and 0xFF */ 376 377 /* One bit for alpha representation */ 378 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \ 379 static void N(uint32_t pixel, rgba *p) \ 380 { \ 381 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 382 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 383 pixel >>= (B); \ 384 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 385 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 386 pixel >>= (G); \ 387 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 388 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 389 pixel >>= (R); \ 390 p->a = (pixel & 0x1); \ 391 } 392 393 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4) 394 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5) 395 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6) 396 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5) 397 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8) 398 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7) 399 400 /* Alpha component is always zero */ 401 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \ 402 static void N(uint32_t pixel, rgba *p) \ 403 { \ 404 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 405 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 406 pixel >>= (B); \ 407 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 408 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 409 pixel >>= (G); \ 410 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 411 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 412 p->a = 0x0; \ 413 } 414 415 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5) 416 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5) 417 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6) 418 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8) 419 420 /* Alpha component has some meaningful value */ 421 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \ 422 static void N(uint32_t pixel, rgba *p) \ 423 { \ 424 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \ 425 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \ 426 pixel >>= (B); \ 427 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \ 428 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \ 429 pixel >>= (G); \ 430 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \ 431 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \ 432 pixel >>= (R); \ 433 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \ 434 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \ 435 p->a = p->a | (p->a << 8) | (p->a << 16); \ 436 } 437 438 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4) 439 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8) 440 441 /* Lookup table to extent 2-bit color component to 8 bit */ 442 static const uint8_t pixel_lutable_2b[4] = { 443 0x0, 0x55, 0xAA, 0xFF 444 }; 445 /* Lookup table to extent 3-bit color component to 8 bit */ 446 static const uint8_t pixel_lutable_3b[8] = { 447 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF 448 }; 449 /* Special case for a232 bpp mode */ 450 static void pixel_a232_to_rgb(uint32_t pixel, rgba *p) 451 { 452 p->b = pixel_lutable_2b[(pixel & 0x3)]; 453 pixel >>= 2; 454 p->g = pixel_lutable_3b[(pixel & 0x7)]; 455 pixel >>= 3; 456 p->r = pixel_lutable_2b[(pixel & 0x3)]; 457 pixel >>= 2; 458 p->a = (pixel & 0x1); 459 } 460 461 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB 462 * for all three color components */ 463 static void pixel_1555_to_rgb(uint32_t pixel, rgba *p) 464 { 465 uint8_t comm = (pixel >> 15) & 1; 466 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 467 pixel >>= 5; 468 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 469 pixel >>= 5; 470 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); 471 p->a = 0x0; 472 } 473 474 /* Put/get pixel to/from internal LCD Controller framebuffer */ 475 476 static int put_pixel_ifb(const rgba p, uint8_t *d) 477 { 478 *(uint8_t *)d++ = p.r; 479 *(uint8_t *)d++ = p.g; 480 *(uint8_t *)d++ = p.b; 481 *(uint32_t *)d = p.a; 482 return RGBA_SIZE; 483 } 484 485 static int get_pixel_ifb(const uint8_t *s, rgba *p) 486 { 487 p->r = *(uint8_t *)s++; 488 p->g = *(uint8_t *)s++; 489 p->b = *(uint8_t *)s++; 490 p->a = (*(uint32_t *)s) & 0x00FFFFFF; 491 return RGBA_SIZE; 492 } 493 494 static pixel_to_rgb_func *palette_data_format[8] = { 495 [0] = pixel_565_to_rgb, 496 [1] = pixel_a555_to_rgb, 497 [2] = pixel_666_to_rgb, 498 [3] = pixel_a665_to_rgb, 499 [4] = pixel_a666_to_rgb, 500 [5] = pixel_888_to_rgb, 501 [6] = pixel_a888_to_rgb, 502 [7] = pixel_8888_to_rgb 503 }; 504 505 /* Returns Index in palette data formats table for given window number WINDOW */ 506 static uint32_t 507 exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window) 508 { 509 uint32_t ret; 510 511 switch (window) { 512 case 0: 513 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L; 514 if (ret != 7) { 515 ret = 6 - ret; 516 } 517 break; 518 case 1: 519 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L; 520 if (ret != 7) { 521 ret = 6 - ret; 522 } 523 break; 524 case 2: 525 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) | 526 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L); 527 break; 528 case 3: 529 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) | 530 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L); 531 break; 532 case 4: 533 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) | 534 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L); 535 break; 536 default: 537 hw_error("exynos4210.fimd: incorrect window number %d\n", window); 538 ret = 0; 539 break; 540 } 541 return ret; 542 } 543 544 #define FIMD_1_MINUS_COLOR(x) \ 545 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \ 546 (0xFF0000 - ((x) & 0xFF0000))) 547 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0)) 548 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F)) 549 550 /* Multiply three lower bytes of two 32-bit words with each other. 551 * Each byte with values 0-255 is considered as a number with possible values 552 * in a range [0 - 1] */ 553 static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b) 554 { 555 uint32_t tmp; 556 uint32_t ret; 557 558 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp; 559 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 560 0xFF00 : tmp << 8; 561 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? 562 0xFF0000 : tmp << 16; 563 return ret; 564 } 565 566 /* For each corresponding bytes of two 32-bit words: (a*b + c*d) 567 * Byte values 0-255 are mapped to a range [0 .. 1] */ 568 static inline uint32_t 569 fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d) 570 { 571 uint32_t tmp; 572 uint32_t ret; 573 574 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF)) 575 > 0xFF) ? 0xFF : tmp; 576 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) * 577 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8; 578 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) + 579 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? 580 0xFF0000 : tmp << 16; 581 return ret; 582 } 583 584 /* These routines cover all possible sources of window's transparent factor 585 * used in blending equation. Choice of routine is affected by WPALCON 586 * registers, BLENDCON register and window's WINCON register */ 587 588 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a) 589 { 590 return pix_a; 591 } 592 593 static uint32_t 594 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a) 595 { 596 return EXTEND_LOWER_HALFBYTE(pix_a); 597 } 598 599 static uint32_t 600 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a) 601 { 602 return EXTEND_UPPER_HALFBYTE(pix_a); 603 } 604 605 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a) 606 { 607 return fimd_mult_each_byte(pix_a, w->alpha_val[0]); 608 } 609 610 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 611 { 612 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a), 613 EXTEND_UPPER_HALFBYTE(w->alpha_val[0])); 614 } 615 616 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a) 617 { 618 return w->alpha_val[pix_a]; 619 } 620 621 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 622 { 623 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]); 624 } 625 626 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a) 627 { 628 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0]; 629 } 630 631 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a) 632 { 633 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon & 634 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]); 635 } 636 637 /* Updates currently active alpha value get function for specified window */ 638 static void fimd_update_get_alpha(Exynos4210fimdState *s, int win) 639 { 640 Exynos4210fimdWindow *w = &s->window[win]; 641 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT; 642 643 if (w->wincon & FIMD_WINCON_BLD_PIX) { 644 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) { 645 /* In this case, alpha component contains meaningful value */ 646 if (w->wincon & FIMD_WINCON_ALPHA_MUL) { 647 w->get_alpha = alpha_is_8bit ? 648 fimd_get_alpha_mult : fimd_get_alpha_mult_ext; 649 } else { 650 w->get_alpha = alpha_is_8bit ? 651 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow; 652 } 653 } else { 654 if (IS_PALETTIZED_MODE(w) && 655 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) { 656 /* Alpha component has 8-bit numeric value */ 657 w->get_alpha = alpha_is_8bit ? 658 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh; 659 } else { 660 /* Alpha has only two possible values (AEN) */ 661 w->get_alpha = alpha_is_8bit ? 662 fimd_get_alpha_aen : fimd_get_alpha_aen_ext; 663 } 664 } 665 } else { 666 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel : 667 fimd_get_alpha_sel_ext; 668 } 669 } 670 671 /* Blends current window's (w) pixel (foreground pixel *ret) with background 672 * window (w_blend) pixel p_bg according to formula: 673 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR 674 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA 675 */ 676 static void 677 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret) 678 { 679 rgba p_fg = *ret; 680 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) | 681 (p_bg.b & 0xFF); 682 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) | 683 (p_fg.b & 0xFF); 684 uint32_t alpha_fg = p_fg.a; 685 int i; 686 /* It is possible that blending equation parameters a and b do not 687 * depend on window BLENEQ register. Account for this with first_coef */ 688 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4}; 689 uint32_t first_coef = A_COEF; 690 uint32_t blend_param[COEF_NUM]; 691 692 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) { 693 uint32_t colorkey = (w->keycon[1] & 694 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY; 695 696 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) && 697 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { 698 /* Foreground pixel is displayed */ 699 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { 700 alpha_fg = w->keyalpha; 701 blend_param[A_COEF] = alpha_fg; 702 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg); 703 } else { 704 alpha_fg = 0; 705 blend_param[A_COEF] = 0xFFFFFF; 706 blend_param[B_COEF] = 0x0; 707 } 708 first_coef = P_COEF; 709 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 && 710 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { 711 /* Background pixel is displayed */ 712 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { 713 alpha_fg = w->keyalpha; 714 blend_param[A_COEF] = alpha_fg; 715 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg); 716 } else { 717 alpha_fg = 0; 718 blend_param[A_COEF] = 0x0; 719 blend_param[B_COEF] = 0xFFFFFF; 720 } 721 first_coef = P_COEF; 722 } 723 } 724 725 for (i = first_coef; i < COEF_NUM; i++) { 726 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) { 727 case 0: 728 blend_param[i] = 0; 729 break; 730 case 1: 731 blend_param[i] = 0xFFFFFF; 732 break; 733 case 2: 734 blend_param[i] = alpha_fg; 735 break; 736 case 3: 737 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg); 738 break; 739 case 4: 740 blend_param[i] = p_bg.a; 741 break; 742 case 5: 743 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a); 744 break; 745 case 6: 746 blend_param[i] = w->alpha_val[0]; 747 break; 748 case 10: 749 blend_param[i] = fg_color; 750 break; 751 case 11: 752 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color); 753 break; 754 case 12: 755 blend_param[i] = bg_color; 756 break; 757 case 13: 758 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color); 759 break; 760 default: 761 hw_error("exynos4210.fimd: blend equation coef illegal value\n"); 762 break; 763 } 764 } 765 766 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF], 767 fg_color, blend_param[A_COEF]); 768 ret->b = fg_color & 0xFF; 769 fg_color >>= 8; 770 ret->g = fg_color & 0xFF; 771 fg_color >>= 8; 772 ret->r = fg_color & 0xFF; 773 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF], 774 p_bg.a, blend_param[Q_COEF]); 775 } 776 777 /* These routines read data from video frame buffer in system RAM, convert 778 * this data to display controller internal representation, if necessary, 779 * perform pixel blending with data, currently presented in internal buffer. 780 * Result is stored in display controller internal frame buffer. */ 781 782 /* Draw line with index in palette table in RAM frame buffer data */ 783 #define DEF_DRAW_LINE_PALETTE(N) \ 784 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \ 785 uint8_t *dst, bool blend) \ 786 { \ 787 int width = w->rightbot_x - w->lefttop_x + 1; \ 788 uint8_t *ifb = dst; \ 789 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \ 790 uint64_t data; \ 791 rgba p, p_old; \ 792 int i; \ 793 do { \ 794 memcpy(&data, src, sizeof(data)); \ 795 src += 8; \ 796 fimd_swap_data(swap, &data); \ 797 for (i = (64 / (N) - 1); i >= 0; i--) { \ 798 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \ 799 ((1ULL << (N)) - 1)], &p); \ 800 p.a = w->get_alpha(w, p.a); \ 801 if (blend) { \ 802 ifb += get_pixel_ifb(ifb, &p_old); \ 803 exynos4210_fimd_blend_pixel(w, p_old, &p); \ 804 } \ 805 dst += put_pixel_ifb(p, dst); \ 806 } \ 807 width -= (64 / (N)); \ 808 } while (width > 0); \ 809 } 810 811 /* Draw line with direct color value in RAM frame buffer data */ 812 #define DEF_DRAW_LINE_NOPALETTE(N) \ 813 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \ 814 uint8_t *dst, bool blend) \ 815 { \ 816 int width = w->rightbot_x - w->lefttop_x + 1; \ 817 uint8_t *ifb = dst; \ 818 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \ 819 uint64_t data; \ 820 rgba p, p_old; \ 821 int i; \ 822 do { \ 823 memcpy(&data, src, sizeof(data)); \ 824 src += 8; \ 825 fimd_swap_data(swap, &data); \ 826 for (i = (64 / (N) - 1); i >= 0; i--) { \ 827 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \ 828 p.a = w->get_alpha(w, p.a); \ 829 if (blend) { \ 830 ifb += get_pixel_ifb(ifb, &p_old); \ 831 exynos4210_fimd_blend_pixel(w, p_old, &p); \ 832 } \ 833 dst += put_pixel_ifb(p, dst); \ 834 } \ 835 width -= (64 / (N)); \ 836 } while (width > 0); \ 837 } 838 839 DEF_DRAW_LINE_PALETTE(1) 840 DEF_DRAW_LINE_PALETTE(2) 841 DEF_DRAW_LINE_PALETTE(4) 842 DEF_DRAW_LINE_PALETTE(8) 843 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */ 844 DEF_DRAW_LINE_NOPALETTE(16) 845 DEF_DRAW_LINE_NOPALETTE(32) 846 847 /* Special draw line routine for window color map case */ 848 static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src, 849 uint8_t *dst, bool blend) 850 { 851 rgba p, p_old; 852 uint8_t *ifb = dst; 853 int width = w->rightbot_x - w->lefttop_x + 1; 854 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK; 855 856 do { 857 pixel_888_to_rgb(map_color, &p); 858 p.a = w->get_alpha(w, p.a); 859 if (blend) { 860 ifb += get_pixel_ifb(ifb, &p_old); 861 exynos4210_fimd_blend_pixel(w, p_old, &p); 862 } 863 dst += put_pixel_ifb(p, dst); 864 } while (--width); 865 } 866 867 /* Write RGB to QEMU's GraphicConsole framebuffer */ 868 869 static int put_to_qemufb_pixel8(const rgba p, uint8_t *d) 870 { 871 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b); 872 *(uint8_t *)d = pixel; 873 return 1; 874 } 875 876 static int put_to_qemufb_pixel15(const rgba p, uint8_t *d) 877 { 878 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b); 879 *(uint16_t *)d = pixel; 880 return 2; 881 } 882 883 static int put_to_qemufb_pixel16(const rgba p, uint8_t *d) 884 { 885 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b); 886 *(uint16_t *)d = pixel; 887 return 2; 888 } 889 890 static int put_to_qemufb_pixel24(const rgba p, uint8_t *d) 891 { 892 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b); 893 *(uint8_t *)d++ = (pixel >> 0) & 0xFF; 894 *(uint8_t *)d++ = (pixel >> 8) & 0xFF; 895 *(uint8_t *)d++ = (pixel >> 16) & 0xFF; 896 return 3; 897 } 898 899 static int put_to_qemufb_pixel32(const rgba p, uint8_t *d) 900 { 901 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b); 902 *(uint32_t *)d = pixel; 903 return 4; 904 } 905 906 /* Routine to copy pixel from internal buffer to QEMU buffer */ 907 static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel); 908 static inline void fimd_update_putpix_qemu(int bpp) 909 { 910 switch (bpp) { 911 case 8: 912 put_pixel_toqemu = put_to_qemufb_pixel8; 913 break; 914 case 15: 915 put_pixel_toqemu = put_to_qemufb_pixel15; 916 break; 917 case 16: 918 put_pixel_toqemu = put_to_qemufb_pixel16; 919 break; 920 case 24: 921 put_pixel_toqemu = put_to_qemufb_pixel24; 922 break; 923 case 32: 924 put_pixel_toqemu = put_to_qemufb_pixel32; 925 break; 926 default: 927 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp); 928 break; 929 } 930 } 931 932 /* Routine to copy a line from internal frame buffer to QEMU display */ 933 static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst) 934 { 935 rgba p; 936 937 do { 938 src += get_pixel_ifb(src, &p); 939 dst += put_pixel_toqemu(p, dst); 940 } while (--width); 941 } 942 943 /* Parse BPPMODE_F = WINCON1[5:2] bits */ 944 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win) 945 { 946 Exynos4210fimdWindow *w = &s->window[win]; 947 948 if (w->winmap & FIMD_WINMAP_EN) { 949 w->draw_line = draw_line_mapcolor; 950 return; 951 } 952 953 switch (WIN_BPP_MODE(w)) { 954 case 0: 955 w->draw_line = draw_line_palette_1; 956 w->pixel_to_rgb = 957 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 958 break; 959 case 1: 960 w->draw_line = draw_line_palette_2; 961 w->pixel_to_rgb = 962 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 963 break; 964 case 2: 965 w->draw_line = draw_line_palette_4; 966 w->pixel_to_rgb = 967 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 968 break; 969 case 3: 970 w->draw_line = draw_line_palette_8; 971 w->pixel_to_rgb = 972 palette_data_format[exynos4210_fimd_palette_format(s, win)]; 973 break; 974 case 4: 975 w->draw_line = draw_line_8; 976 w->pixel_to_rgb = pixel_a232_to_rgb; 977 break; 978 case 5: 979 w->draw_line = draw_line_16; 980 w->pixel_to_rgb = pixel_565_to_rgb; 981 break; 982 case 6: 983 w->draw_line = draw_line_16; 984 w->pixel_to_rgb = pixel_a555_to_rgb; 985 break; 986 case 7: 987 w->draw_line = draw_line_16; 988 w->pixel_to_rgb = pixel_1555_to_rgb; 989 break; 990 case 8: 991 w->draw_line = draw_line_32; 992 w->pixel_to_rgb = pixel_666_to_rgb; 993 break; 994 case 9: 995 w->draw_line = draw_line_32; 996 w->pixel_to_rgb = pixel_a665_to_rgb; 997 break; 998 case 10: 999 w->draw_line = draw_line_32; 1000 w->pixel_to_rgb = pixel_a666_to_rgb; 1001 break; 1002 case 11: 1003 w->draw_line = draw_line_32; 1004 w->pixel_to_rgb = pixel_888_to_rgb; 1005 break; 1006 case 12: 1007 w->draw_line = draw_line_32; 1008 w->pixel_to_rgb = pixel_a887_to_rgb; 1009 break; 1010 case 13: 1011 w->draw_line = draw_line_32; 1012 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon & 1013 FIMD_WINCON_ALPHA_SEL)) { 1014 w->pixel_to_rgb = pixel_8888_to_rgb; 1015 } else { 1016 w->pixel_to_rgb = pixel_a888_to_rgb; 1017 } 1018 break; 1019 case 14: 1020 w->draw_line = draw_line_16; 1021 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon & 1022 FIMD_WINCON_ALPHA_SEL)) { 1023 w->pixel_to_rgb = pixel_4444_to_rgb; 1024 } else { 1025 w->pixel_to_rgb = pixel_a444_to_rgb; 1026 } 1027 break; 1028 case 15: 1029 w->draw_line = draw_line_16; 1030 w->pixel_to_rgb = pixel_555_to_rgb; 1031 break; 1032 } 1033 } 1034 1035 #if EXYNOS4210_FIMD_MODE_TRACE > 0 1036 static const char *exynos4210_fimd_get_bppmode(int mode_code) 1037 { 1038 switch (mode_code) { 1039 case 0: 1040 return "1 bpp"; 1041 case 1: 1042 return "2 bpp"; 1043 case 2: 1044 return "4 bpp"; 1045 case 3: 1046 return "8 bpp (palettized)"; 1047 case 4: 1048 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)"; 1049 case 5: 1050 return "16 bpp (non-palettized, R:5-G:6-B:5)"; 1051 case 6: 1052 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)"; 1053 case 7: 1054 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)"; 1055 case 8: 1056 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)"; 1057 case 9: 1058 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)"; 1059 case 10: 1060 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)"; 1061 case 11: 1062 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)"; 1063 case 12: 1064 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)"; 1065 case 13: 1066 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)"; 1067 case 14: 1068 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)"; 1069 case 15: 1070 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)"; 1071 default: 1072 return "Non-existing bpp mode"; 1073 } 1074 } 1075 1076 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s, 1077 int win_num, uint32_t val) 1078 { 1079 Exynos4210fimdWindow *w = &s->window[win_num]; 1080 1081 if (w->winmap & FIMD_WINMAP_EN) { 1082 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n", 1083 win_num, w->winmap & 0xFFFFFF); 1084 return; 1085 } 1086 1087 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) { 1088 return; 1089 } 1090 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num, 1091 exynos4210_fimd_get_bppmode((val >> 2) & 0xF)); 1092 } 1093 #else 1094 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s, 1095 int win_num, uint32_t val) 1096 { 1097 1098 } 1099 #endif 1100 1101 static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w) 1102 { 1103 switch (w->wincon & FIMD_WINCON_BUFSTATUS) { 1104 case FIMD_WINCON_BUF0_STAT: 1105 return 0; 1106 case FIMD_WINCON_BUF1_STAT: 1107 return 1; 1108 case FIMD_WINCON_BUF2_STAT: 1109 return 2; 1110 default: 1111 DPRINT_ERROR("Non-existent buffer index\n"); 1112 return 0; 1113 } 1114 } 1115 1116 static void exynos4210_fimd_invalidate(void *opaque) 1117 { 1118 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1119 s->invalidate = true; 1120 } 1121 1122 /* Updates specified window's MemorySection based on values of WINCON, 1123 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */ 1124 static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win) 1125 { 1126 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1127 Exynos4210fimdWindow *w = &s->window[win]; 1128 hwaddr fb_start_addr, fb_mapped_len; 1129 1130 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) || 1131 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) { 1132 return; 1133 } 1134 1135 if (w->host_fb_addr) { 1136 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0); 1137 w->host_fb_addr = NULL; 1138 w->fb_len = 0; 1139 } 1140 1141 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)]; 1142 /* Total number of bytes of virtual screen used by current window */ 1143 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) * 1144 (w->rightbot_y - w->lefttop_y + 1); 1145 1146 /* TODO: add .exit and unref the region there. Not needed yet since sysbus 1147 * does not support hot-unplug. 1148 */ 1149 if (w->mem_section.mr) { 1150 memory_region_set_log(w->mem_section.mr, false, DIRTY_MEMORY_VGA); 1151 memory_region_unref(w->mem_section.mr); 1152 } 1153 1154 w->mem_section = memory_region_find(sysbus_address_space(sbd), 1155 fb_start_addr, w->fb_len); 1156 assert(w->mem_section.mr); 1157 assert(w->mem_section.offset_within_address_space == fb_start_addr); 1158 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n", 1159 win, fb_start_addr, w->fb_len); 1160 1161 if (int128_get64(w->mem_section.size) != w->fb_len || 1162 !memory_region_is_ram(w->mem_section.mr)) { 1163 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win); 1164 goto error_return; 1165 } 1166 1167 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0); 1168 if (!w->host_fb_addr) { 1169 DPRINT_ERROR("Failed to map window %u framebuffer\n", win); 1170 goto error_return; 1171 } 1172 1173 if (fb_mapped_len != w->fb_len) { 1174 DPRINT_ERROR("Window %u mapped framebuffer length is less then " 1175 "expected\n", win); 1176 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0); 1177 goto error_return; 1178 } 1179 memory_region_set_log(w->mem_section.mr, true, DIRTY_MEMORY_VGA); 1180 exynos4210_fimd_invalidate(s); 1181 return; 1182 1183 error_return: 1184 memory_region_unref(w->mem_section.mr); 1185 w->mem_section.mr = NULL; 1186 w->mem_section.size = int128_zero(); 1187 w->host_fb_addr = NULL; 1188 w->fb_len = 0; 1189 } 1190 1191 static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled) 1192 { 1193 if (enabled && !s->enabled) { 1194 unsigned w; 1195 s->enabled = true; 1196 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1197 fimd_update_memory_section(s, w); 1198 } 1199 } 1200 s->enabled = enabled; 1201 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled"); 1202 } 1203 1204 static inline uint32_t unpack_upper_4(uint32_t x) 1205 { 1206 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4); 1207 } 1208 1209 static inline uint32_t pack_upper_4(uint32_t x) 1210 { 1211 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) | 1212 ((x & 0xF0) >> 4)) & 0xFFF; 1213 } 1214 1215 static void exynos4210_fimd_update_irq(Exynos4210fimdState *s) 1216 { 1217 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) { 1218 qemu_irq_lower(s->irq[0]); 1219 qemu_irq_lower(s->irq[1]); 1220 qemu_irq_lower(s->irq[2]); 1221 return; 1222 } 1223 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) && 1224 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) { 1225 qemu_irq_raise(s->irq[0]); 1226 } else { 1227 qemu_irq_lower(s->irq[0]); 1228 } 1229 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) && 1230 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) { 1231 qemu_irq_raise(s->irq[1]); 1232 } else { 1233 qemu_irq_lower(s->irq[1]); 1234 } 1235 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) && 1236 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) { 1237 qemu_irq_raise(s->irq[2]); 1238 } else { 1239 qemu_irq_lower(s->irq[2]); 1240 } 1241 } 1242 1243 static void exynos4210_update_resolution(Exynos4210fimdState *s) 1244 { 1245 DisplaySurface *surface = qemu_console_surface(s->console); 1246 1247 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */ 1248 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) & 1249 FIMD_VIDTCON2_SIZE_MASK) + 1; 1250 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) & 1251 FIMD_VIDTCON2_SIZE_MASK) + 1; 1252 1253 if (s->ifb == NULL || surface_width(surface) != width || 1254 surface_height(surface) != height) { 1255 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n", 1256 surface_width(surface), surface_height(surface), width, height); 1257 qemu_console_resize(s->console, width, height); 1258 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1); 1259 memset(s->ifb, 0, width * height * RGBA_SIZE + 1); 1260 exynos4210_fimd_invalidate(s); 1261 } 1262 } 1263 1264 static void exynos4210_fimd_update(void *opaque) 1265 { 1266 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1267 DisplaySurface *surface; 1268 Exynos4210fimdWindow *w; 1269 DirtyBitmapSnapshot *snap; 1270 int i, line; 1271 hwaddr fb_line_addr, inc_size; 1272 int scrn_height; 1273 int first_line = -1, last_line = -1, scrn_width; 1274 bool blend = false; 1275 uint8_t *host_fb_addr; 1276 bool is_dirty = false; 1277 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; 1278 1279 if (!s || !s->console || !s->enabled || 1280 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { 1281 return; 1282 } 1283 exynos4210_update_resolution(s); 1284 surface = qemu_console_surface(s->console); 1285 1286 for (i = 0; i < NUM_OF_WINDOWS; i++) { 1287 w = &s->window[i]; 1288 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) { 1289 scrn_height = w->rightbot_y - w->lefttop_y + 1; 1290 scrn_width = w->virtpage_width; 1291 /* Total width of virtual screen page in bytes */ 1292 inc_size = scrn_width + w->virtpage_offsize; 1293 host_fb_addr = w->host_fb_addr; 1294 fb_line_addr = w->mem_section.offset_within_region; 1295 snap = memory_region_snapshot_and_clear_dirty(w->mem_section.mr, 1296 fb_line_addr, inc_size * scrn_height, DIRTY_MEMORY_VGA); 1297 1298 for (line = 0; line < scrn_height; line++) { 1299 is_dirty = memory_region_snapshot_get_dirty(w->mem_section.mr, 1300 snap, fb_line_addr, scrn_width); 1301 1302 if (s->invalidate || is_dirty) { 1303 if (first_line == -1) { 1304 first_line = line; 1305 } 1306 last_line = line; 1307 w->draw_line(w, host_fb_addr, s->ifb + 1308 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) * 1309 global_width * RGBA_SIZE, blend); 1310 } 1311 host_fb_addr += inc_size; 1312 fb_line_addr += inc_size; 1313 is_dirty = false; 1314 } 1315 g_free(snap); 1316 blend = true; 1317 } 1318 } 1319 1320 /* Copy resulting image to QEMU_CONSOLE. */ 1321 if (first_line >= 0) { 1322 uint8_t *d; 1323 int bpp; 1324 1325 bpp = surface_bits_per_pixel(surface); 1326 fimd_update_putpix_qemu(bpp); 1327 bpp = (bpp + 1) >> 3; 1328 d = surface_data(surface); 1329 for (line = first_line; line <= last_line; line++) { 1330 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line * 1331 RGBA_SIZE, d + global_width * line * bpp); 1332 } 1333 dpy_gfx_update_full(s->console); 1334 } 1335 s->invalidate = false; 1336 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND; 1337 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) { 1338 exynos4210_fimd_enable(s, false); 1339 } 1340 exynos4210_fimd_update_irq(s); 1341 } 1342 1343 static void exynos4210_fimd_reset(DeviceState *d) 1344 { 1345 Exynos4210fimdState *s = EXYNOS4210_FIMD(d); 1346 unsigned w; 1347 1348 DPRINT_TRACE("Display controller reset\n"); 1349 /* Set all display controller registers to 0 */ 1350 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon); 1351 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1352 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow)); 1353 s->window[w].blendeq = 0xC2; 1354 exynos4210_fimd_update_win_bppmode(s, w); 1355 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); 1356 fimd_update_get_alpha(s, w); 1357 } 1358 1359 g_free(s->ifb); 1360 s->ifb = NULL; 1361 1362 exynos4210_fimd_invalidate(s); 1363 exynos4210_fimd_enable(s, false); 1364 /* Some registers have non-zero initial values */ 1365 s->winchmap = 0x7D517D51; 1366 s->colorgaincon = 0x10040100; 1367 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100; 1368 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100; 1369 s->hueoffset = 0x01800080; 1370 } 1371 1372 static void exynos4210_fimd_write(void *opaque, hwaddr offset, 1373 uint64_t val, unsigned size) 1374 { 1375 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1376 unsigned w, i; 1377 uint32_t old_value; 1378 1379 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset, 1380 (long long unsigned int)val, (long long unsigned int)val); 1381 1382 switch (offset) { 1383 case FIMD_VIDCON0: 1384 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) { 1385 exynos4210_fimd_enable(s, true); 1386 } else { 1387 if ((val & FIMD_VIDCON0_ENVID) == 0) { 1388 exynos4210_fimd_enable(s, false); 1389 } 1390 } 1391 s->vidcon[0] = val; 1392 break; 1393 case FIMD_VIDCON1: 1394 /* Leave read-only bits as is */ 1395 val = (val & (~FIMD_VIDCON1_ROMASK)) | 1396 (s->vidcon[1] & FIMD_VIDCON1_ROMASK); 1397 s->vidcon[1] = val; 1398 break; 1399 case FIMD_VIDCON2 ... FIMD_VIDCON3: 1400 s->vidcon[(offset) >> 2] = val; 1401 break; 1402 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END: 1403 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val; 1404 break; 1405 case FIMD_WINCON_START ... FIMD_WINCON_END: 1406 w = (offset - FIMD_WINCON_START) >> 2; 1407 /* Window's current buffer ID */ 1408 i = fimd_get_buffer_id(&s->window[w]); 1409 old_value = s->window[w].wincon; 1410 val = (val & ~FIMD_WINCON_ROMASK) | 1411 (s->window[w].wincon & FIMD_WINCON_ROMASK); 1412 if (w == 0) { 1413 /* Window 0 wincon ALPHA_MUL bit must always be 0 */ 1414 val &= ~FIMD_WINCON_ALPHA_MUL; 1415 } 1416 exynos4210_fimd_trace_bppmode(s, w, val); 1417 switch (val & FIMD_WINCON_BUFSELECT) { 1418 case FIMD_WINCON_BUF0_SEL: 1419 val &= ~FIMD_WINCON_BUFSTATUS; 1420 break; 1421 case FIMD_WINCON_BUF1_SEL: 1422 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L; 1423 break; 1424 case FIMD_WINCON_BUF2_SEL: 1425 if (val & FIMD_WINCON_BUFMODE) { 1426 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H; 1427 } 1428 break; 1429 default: 1430 break; 1431 } 1432 s->window[w].wincon = val; 1433 exynos4210_fimd_update_win_bppmode(s, w); 1434 fimd_update_get_alpha(s, w); 1435 if ((i != fimd_get_buffer_id(&s->window[w])) || 1436 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon & 1437 FIMD_WINCON_ENWIN))) { 1438 fimd_update_memory_section(s, w); 1439 } 1440 break; 1441 case FIMD_SHADOWCON: 1442 old_value = s->shadowcon; 1443 s->shadowcon = val; 1444 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1445 if (FIMD_WINDOW_PROTECTED(old_value, w) && 1446 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) { 1447 fimd_update_memory_section(s, w); 1448 } 1449 } 1450 break; 1451 case FIMD_WINCHMAP: 1452 s->winchmap = val; 1453 break; 1454 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END: 1455 w = (offset - FIMD_VIDOSD_START) >> 4; 1456 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; 1457 switch (i) { 1458 case 0: 1459 old_value = s->window[w].lefttop_y; 1460 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) & 1461 FIMD_VIDOSD_COORD_MASK; 1462 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) & 1463 FIMD_VIDOSD_COORD_MASK; 1464 if (s->window[w].lefttop_y != old_value) { 1465 fimd_update_memory_section(s, w); 1466 } 1467 break; 1468 case 1: 1469 old_value = s->window[w].rightbot_y; 1470 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) & 1471 FIMD_VIDOSD_COORD_MASK; 1472 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) & 1473 FIMD_VIDOSD_COORD_MASK; 1474 if (s->window[w].rightbot_y != old_value) { 1475 fimd_update_memory_section(s, w); 1476 } 1477 break; 1478 case 2: 1479 if (w == 0) { 1480 s->window[w].osdsize = val; 1481 } else { 1482 s->window[w].alpha_val[0] = 1483 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >> 1484 FIMD_VIDOSD_AEN0_SHIFT) | 1485 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER); 1486 s->window[w].alpha_val[1] = 1487 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) | 1488 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER); 1489 } 1490 break; 1491 case 3: 1492 if (w != 1 && w != 2) { 1493 DPRINT_ERROR("Bad write offset 0x%08x\n", offset); 1494 return; 1495 } 1496 s->window[w].osdsize = val; 1497 break; 1498 } 1499 break; 1500 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END: 1501 w = (offset - FIMD_VIDWADD0_START) >> 3; 1502 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1; 1503 if (i == fimd_get_buffer_id(&s->window[w]) && 1504 s->window[w].buf_start[i] != val) { 1505 s->window[w].buf_start[i] = val; 1506 fimd_update_memory_section(s, w); 1507 break; 1508 } 1509 s->window[w].buf_start[i] = val; 1510 break; 1511 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END: 1512 w = (offset - FIMD_VIDWADD1_START) >> 3; 1513 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1; 1514 s->window[w].buf_end[i] = val; 1515 break; 1516 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END: 1517 w = (offset - FIMD_VIDWADD2_START) >> 2; 1518 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) || 1519 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) != 1520 s->window[w].virtpage_offsize)) { 1521 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH; 1522 s->window[w].virtpage_offsize = 1523 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE; 1524 fimd_update_memory_section(s, w); 1525 } 1526 break; 1527 case FIMD_VIDINTCON0: 1528 s->vidintcon[0] = val; 1529 break; 1530 case FIMD_VIDINTCON1: 1531 s->vidintcon[1] &= ~(val & 7); 1532 exynos4210_fimd_update_irq(s); 1533 break; 1534 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END: 1535 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1; 1536 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1; 1537 s->window[w].keycon[i] = val; 1538 break; 1539 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END: 1540 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1; 1541 s->window[w].keyalpha = val; 1542 break; 1543 case FIMD_DITHMODE: 1544 s->dithmode = val; 1545 break; 1546 case FIMD_WINMAP_START ... FIMD_WINMAP_END: 1547 w = (offset - FIMD_WINMAP_START) >> 2; 1548 old_value = s->window[w].winmap; 1549 s->window[w].winmap = val; 1550 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) { 1551 exynos4210_fimd_invalidate(s); 1552 exynos4210_fimd_update_win_bppmode(s, w); 1553 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); 1554 exynos4210_fimd_update(s); 1555 } 1556 break; 1557 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW: 1558 i = (offset - FIMD_WPALCON_HIGH) >> 2; 1559 s->wpalcon[i] = val; 1560 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) { 1561 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1562 exynos4210_fimd_update_win_bppmode(s, w); 1563 fimd_update_get_alpha(s, w); 1564 } 1565 } 1566 break; 1567 case FIMD_TRIGCON: 1568 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK); 1569 s->trigcon = val; 1570 break; 1571 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END: 1572 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val; 1573 break; 1574 case FIMD_COLORGAINCON: 1575 s->colorgaincon = val; 1576 break; 1577 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1: 1578 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val; 1579 break; 1580 case FIMD_SIFCCON0 ... FIMD_SIFCCON2: 1581 i = (offset - FIMD_SIFCCON0) >> 2; 1582 if (i != 2) { 1583 s->sifccon[i] = val; 1584 } 1585 break; 1586 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END: 1587 i = (offset - FIMD_HUECOEFCR_START) >> 2; 1588 s->huecoef_cr[i] = val; 1589 break; 1590 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END: 1591 i = (offset - FIMD_HUECOEFCB_START) >> 2; 1592 s->huecoef_cb[i] = val; 1593 break; 1594 case FIMD_HUEOFFSET: 1595 s->hueoffset = val; 1596 break; 1597 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END: 1598 w = ((offset - FIMD_VIDWALPHA_START) >> 3); 1599 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1; 1600 if (w == 0) { 1601 s->window[w].alpha_val[i] = val; 1602 } else { 1603 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) | 1604 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER); 1605 } 1606 break; 1607 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END: 1608 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val; 1609 break; 1610 case FIMD_BLENDCON: 1611 old_value = s->blendcon; 1612 s->blendcon = val; 1613 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) { 1614 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1615 fimd_update_get_alpha(s, w); 1616 } 1617 } 1618 break; 1619 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END: 1620 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val; 1621 break; 1622 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END: 1623 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val; 1624 break; 1625 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: 1626 if (offset & 0x0004) { 1627 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1628 break; 1629 } 1630 w = (offset - FIMD_VIDW0ADD0_B2) >> 3; 1631 if (fimd_get_buffer_id(&s->window[w]) == 2 && 1632 s->window[w].buf_start[2] != val) { 1633 s->window[w].buf_start[2] = val; 1634 fimd_update_memory_section(s, w); 1635 break; 1636 } 1637 s->window[w].buf_start[2] = val; 1638 break; 1639 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: 1640 if (offset & 0x0004) { 1641 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1642 break; 1643 } 1644 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val; 1645 break; 1646 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: 1647 if (offset & 0x0004) { 1648 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1649 break; 1650 } 1651 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val; 1652 break; 1653 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END: 1654 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val; 1655 break; 1656 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END: 1657 w = (offset - FIMD_PAL_MEM_START) >> 10; 1658 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; 1659 s->window[w].palette[i] = val; 1660 break; 1661 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END: 1662 /* Palette memory aliases for windows 0 and 1 */ 1663 w = (offset - FIMD_PALMEM_AL_START) >> 10; 1664 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; 1665 s->window[w].palette[i] = val; 1666 break; 1667 default: 1668 DPRINT_ERROR("bad write offset 0x%08x\n", offset); 1669 break; 1670 } 1671 } 1672 1673 static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset, 1674 unsigned size) 1675 { 1676 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1677 int w, i; 1678 uint32_t ret = 0; 1679 1680 DPRINT_L2("read offset 0x%08x\n", offset); 1681 1682 switch (offset) { 1683 case FIMD_VIDCON0 ... FIMD_VIDCON3: 1684 return s->vidcon[(offset - FIMD_VIDCON0) >> 2]; 1685 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END: 1686 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2]; 1687 case FIMD_WINCON_START ... FIMD_WINCON_END: 1688 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon; 1689 case FIMD_SHADOWCON: 1690 return s->shadowcon; 1691 case FIMD_WINCHMAP: 1692 return s->winchmap; 1693 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END: 1694 w = (offset - FIMD_VIDOSD_START) >> 4; 1695 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; 1696 switch (i) { 1697 case 0: 1698 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) << 1699 FIMD_VIDOSD_HOR_SHIFT) | 1700 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK); 1701 break; 1702 case 1: 1703 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) << 1704 FIMD_VIDOSD_HOR_SHIFT) | 1705 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK); 1706 break; 1707 case 2: 1708 if (w == 0) { 1709 ret = s->window[w].osdsize; 1710 } else { 1711 ret = (pack_upper_4(s->window[w].alpha_val[0]) << 1712 FIMD_VIDOSD_AEN0_SHIFT) | 1713 pack_upper_4(s->window[w].alpha_val[1]); 1714 } 1715 break; 1716 case 3: 1717 if (w != 1 && w != 2) { 1718 DPRINT_ERROR("bad read offset 0x%08x\n", offset); 1719 return 0xBAADBAAD; 1720 } 1721 ret = s->window[w].osdsize; 1722 break; 1723 } 1724 return ret; 1725 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END: 1726 w = (offset - FIMD_VIDWADD0_START) >> 3; 1727 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1; 1728 return s->window[w].buf_start[i]; 1729 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END: 1730 w = (offset - FIMD_VIDWADD1_START) >> 3; 1731 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1; 1732 return s->window[w].buf_end[i]; 1733 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END: 1734 w = (offset - FIMD_VIDWADD2_START) >> 2; 1735 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize << 1736 FIMD_VIDWADD2_OFFSIZE_SHIFT); 1737 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1: 1738 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2]; 1739 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END: 1740 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1; 1741 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1; 1742 return s->window[w].keycon[i]; 1743 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END: 1744 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1; 1745 return s->window[w].keyalpha; 1746 case FIMD_DITHMODE: 1747 return s->dithmode; 1748 case FIMD_WINMAP_START ... FIMD_WINMAP_END: 1749 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap; 1750 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW: 1751 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2]; 1752 case FIMD_TRIGCON: 1753 return s->trigcon; 1754 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END: 1755 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2]; 1756 case FIMD_COLORGAINCON: 1757 return s->colorgaincon; 1758 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1: 1759 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2]; 1760 case FIMD_SIFCCON0 ... FIMD_SIFCCON2: 1761 i = (offset - FIMD_SIFCCON0) >> 2; 1762 return s->sifccon[i]; 1763 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END: 1764 i = (offset - FIMD_HUECOEFCR_START) >> 2; 1765 return s->huecoef_cr[i]; 1766 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END: 1767 i = (offset - FIMD_HUECOEFCB_START) >> 2; 1768 return s->huecoef_cb[i]; 1769 case FIMD_HUEOFFSET: 1770 return s->hueoffset; 1771 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END: 1772 w = ((offset - FIMD_VIDWALPHA_START) >> 3); 1773 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1; 1774 return s->window[w].alpha_val[i] & 1775 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER); 1776 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END: 1777 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq; 1778 case FIMD_BLENDCON: 1779 return s->blendcon; 1780 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END: 1781 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon; 1782 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END: 1783 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2]; 1784 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: 1785 if (offset & 0x0004) { 1786 break; 1787 } 1788 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2]; 1789 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: 1790 if (offset & 0x0004) { 1791 break; 1792 } 1793 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start; 1794 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: 1795 if (offset & 0x0004) { 1796 break; 1797 } 1798 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end; 1799 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END: 1800 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size; 1801 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END: 1802 w = (offset - FIMD_PAL_MEM_START) >> 10; 1803 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; 1804 return s->window[w].palette[i]; 1805 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END: 1806 /* Palette aliases for win 0,1 */ 1807 w = (offset - FIMD_PALMEM_AL_START) >> 10; 1808 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; 1809 return s->window[w].palette[i]; 1810 } 1811 1812 DPRINT_ERROR("bad read offset 0x%08x\n", offset); 1813 return 0xBAADBAAD; 1814 } 1815 1816 static const MemoryRegionOps exynos4210_fimd_mmio_ops = { 1817 .read = exynos4210_fimd_read, 1818 .write = exynos4210_fimd_write, 1819 .valid = { 1820 .min_access_size = 4, 1821 .max_access_size = 4, 1822 .unaligned = false 1823 }, 1824 .endianness = DEVICE_NATIVE_ENDIAN, 1825 }; 1826 1827 static int exynos4210_fimd_load(void *opaque, int version_id) 1828 { 1829 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; 1830 int w; 1831 1832 if (version_id != 1) { 1833 return -EINVAL; 1834 } 1835 1836 for (w = 0; w < NUM_OF_WINDOWS; w++) { 1837 exynos4210_fimd_update_win_bppmode(s, w); 1838 fimd_update_get_alpha(s, w); 1839 fimd_update_memory_section(s, w); 1840 } 1841 1842 /* Redraw the whole screen */ 1843 exynos4210_update_resolution(s); 1844 exynos4210_fimd_invalidate(s); 1845 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) == 1846 FIMD_VIDCON0_ENVID_MASK); 1847 return 0; 1848 } 1849 1850 static const VMStateDescription exynos4210_fimd_window_vmstate = { 1851 .name = "exynos4210.fimd_window", 1852 .version_id = 1, 1853 .minimum_version_id = 1, 1854 .fields = (VMStateField[]) { 1855 VMSTATE_UINT32(wincon, Exynos4210fimdWindow), 1856 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3), 1857 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3), 1858 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2), 1859 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow), 1860 VMSTATE_UINT32(winmap, Exynos4210fimdWindow), 1861 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow), 1862 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow), 1863 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256), 1864 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow), 1865 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow), 1866 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow), 1867 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow), 1868 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow), 1869 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow), 1870 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow), 1871 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow), 1872 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2), 1873 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow), 1874 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow), 1875 VMSTATE_END_OF_LIST() 1876 } 1877 }; 1878 1879 static const VMStateDescription exynos4210_fimd_vmstate = { 1880 .name = "exynos4210.fimd", 1881 .version_id = 1, 1882 .minimum_version_id = 1, 1883 .post_load = exynos4210_fimd_load, 1884 .fields = (VMStateField[]) { 1885 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4), 1886 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4), 1887 VMSTATE_UINT32(shadowcon, Exynos4210fimdState), 1888 VMSTATE_UINT32(winchmap, Exynos4210fimdState), 1889 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2), 1890 VMSTATE_UINT32(dithmode, Exynos4210fimdState), 1891 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2), 1892 VMSTATE_UINT32(trigcon, Exynos4210fimdState), 1893 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4), 1894 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState), 1895 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2), 1896 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3), 1897 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4), 1898 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4), 1899 VMSTATE_UINT32(hueoffset, Exynos4210fimdState), 1900 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12), 1901 VMSTATE_UINT32(blendcon, Exynos4210fimdState), 1902 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1, 1903 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow), 1904 VMSTATE_END_OF_LIST() 1905 } 1906 }; 1907 1908 static const GraphicHwOps exynos4210_fimd_ops = { 1909 .invalidate = exynos4210_fimd_invalidate, 1910 .gfx_update = exynos4210_fimd_update, 1911 }; 1912 1913 static void exynos4210_fimd_init(Object *obj) 1914 { 1915 Exynos4210fimdState *s = EXYNOS4210_FIMD(obj); 1916 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1917 1918 s->ifb = NULL; 1919 1920 sysbus_init_irq(dev, &s->irq[0]); 1921 sysbus_init_irq(dev, &s->irq[1]); 1922 sysbus_init_irq(dev, &s->irq[2]); 1923 1924 memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s, 1925 "exynos4210.fimd", FIMD_REGS_SIZE); 1926 sysbus_init_mmio(dev, &s->iomem); 1927 } 1928 1929 static void exynos4210_fimd_realize(DeviceState *dev, Error **errp) 1930 { 1931 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev); 1932 1933 s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s); 1934 } 1935 1936 static void exynos4210_fimd_class_init(ObjectClass *klass, void *data) 1937 { 1938 DeviceClass *dc = DEVICE_CLASS(klass); 1939 1940 dc->vmsd = &exynos4210_fimd_vmstate; 1941 dc->reset = exynos4210_fimd_reset; 1942 dc->realize = exynos4210_fimd_realize; 1943 } 1944 1945 static const TypeInfo exynos4210_fimd_info = { 1946 .name = TYPE_EXYNOS4210_FIMD, 1947 .parent = TYPE_SYS_BUS_DEVICE, 1948 .instance_size = sizeof(Exynos4210fimdState), 1949 .instance_init = exynos4210_fimd_init, 1950 .class_init = exynos4210_fimd_class_init, 1951 }; 1952 1953 static void exynos4210_fimd_register_types(void) 1954 { 1955 type_register_static(&exynos4210_fimd_info); 1956 } 1957 1958 type_init(exynos4210_fimd_register_types) 1959