1 /* 2 * QEMU G364 framebuffer Emulator. 3 * 4 * Copyright (c) 2007-2011 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "hw/hw.h" 23 #include "hw/irq.h" 24 #include "qemu/error-report.h" 25 #include "qemu/module.h" 26 #include "ui/console.h" 27 #include "ui/pixel_ops.h" 28 #include "trace.h" 29 #include "hw/sysbus.h" 30 31 typedef struct G364State { 32 /* hardware */ 33 uint8_t *vram; 34 uint32_t vram_size; 35 qemu_irq irq; 36 MemoryRegion mem_vram; 37 MemoryRegion mem_ctrl; 38 /* registers */ 39 uint8_t color_palette[256][3]; 40 uint8_t cursor_palette[3][3]; 41 uint16_t cursor[512]; 42 uint32_t cursor_position; 43 uint32_t ctla; 44 uint32_t top_of_screen; 45 uint32_t width, height; /* in pixels */ 46 /* display refresh support */ 47 QemuConsole *con; 48 int depth; 49 int blanked; 50 } G364State; 51 52 #define REG_BOOT 0x000000 53 #define REG_DISPLAY 0x000118 54 #define REG_VDISPLAY 0x000150 55 #define REG_CTLA 0x000300 56 #define REG_TOP 0x000400 57 #define REG_CURS_PAL 0x000508 58 #define REG_CURS_POS 0x000638 59 #define REG_CLR_PAL 0x000800 60 #define REG_CURS_PAT 0x001000 61 #define REG_RESET 0x100000 62 63 #define CTLA_FORCE_BLANK 0x00000400 64 #define CTLA_NO_CURSOR 0x00800000 65 66 #define G364_PAGE_SIZE 4096 67 68 static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page) 69 { 70 return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE); 71 } 72 73 static void g364fb_draw_graphic8(G364State *s) 74 { 75 DisplaySurface *surface = qemu_console_surface(s->con); 76 DirtyBitmapSnapshot *snap; 77 int i, w; 78 uint8_t *vram; 79 uint8_t *data_display, *dd; 80 ram_addr_t page; 81 int x, y; 82 int xmin, xmax; 83 int ymin, ymax; 84 int xcursor, ycursor; 85 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); 86 87 switch (surface_bits_per_pixel(surface)) { 88 case 8: 89 rgb_to_pixel = rgb_to_pixel8; 90 w = 1; 91 break; 92 case 15: 93 rgb_to_pixel = rgb_to_pixel15; 94 w = 2; 95 break; 96 case 16: 97 rgb_to_pixel = rgb_to_pixel16; 98 w = 2; 99 break; 100 case 32: 101 rgb_to_pixel = rgb_to_pixel32; 102 w = 4; 103 break; 104 default: 105 hw_error("g364: unknown host depth %d", 106 surface_bits_per_pixel(surface)); 107 return; 108 } 109 110 page = 0; 111 112 x = y = 0; 113 xmin = s->width; 114 xmax = 0; 115 ymin = s->height; 116 ymax = 0; 117 118 if (!(s->ctla & CTLA_NO_CURSOR)) { 119 xcursor = s->cursor_position >> 12; 120 ycursor = s->cursor_position & 0xfff; 121 } else { 122 xcursor = ycursor = -65; 123 } 124 125 vram = s->vram + s->top_of_screen; 126 /* XXX: out of range in vram? */ 127 data_display = dd = surface_data(surface); 128 snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size, 129 DIRTY_MEMORY_VGA); 130 while (y < s->height) { 131 if (check_dirty(s, snap, page)) { 132 if (y < ymin) 133 ymin = ymax = y; 134 if (x < xmin) 135 xmin = x; 136 for (i = 0; i < G364_PAGE_SIZE; i++) { 137 uint8_t index; 138 unsigned int color; 139 if (unlikely((y >= ycursor && y < ycursor + 64) && 140 (x >= xcursor && x < xcursor + 64))) { 141 /* pointer area */ 142 int xdiff = x - xcursor; 143 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; 144 int op = (curs >> ((xdiff & 7) * 2)) & 3; 145 if (likely(op == 0)) { 146 /* transparent */ 147 index = *vram; 148 color = (*rgb_to_pixel)( 149 s->color_palette[index][0], 150 s->color_palette[index][1], 151 s->color_palette[index][2]); 152 } else { 153 /* get cursor color */ 154 index = op - 1; 155 color = (*rgb_to_pixel)( 156 s->cursor_palette[index][0], 157 s->cursor_palette[index][1], 158 s->cursor_palette[index][2]); 159 } 160 } else { 161 /* normal area */ 162 index = *vram; 163 color = (*rgb_to_pixel)( 164 s->color_palette[index][0], 165 s->color_palette[index][1], 166 s->color_palette[index][2]); 167 } 168 memcpy(dd, &color, w); 169 dd += w; 170 x++; 171 vram++; 172 if (x == s->width) { 173 xmax = s->width - 1; 174 y++; 175 if (y == s->height) { 176 ymax = s->height - 1; 177 goto done; 178 } 179 data_display = dd = data_display + surface_stride(surface); 180 xmin = 0; 181 x = 0; 182 } 183 } 184 if (x > xmax) 185 xmax = x; 186 if (y > ymax) 187 ymax = y; 188 } else { 189 int dy; 190 if (xmax || ymax) { 191 dpy_gfx_update(s->con, xmin, ymin, 192 xmax - xmin + 1, ymax - ymin + 1); 193 xmin = s->width; 194 xmax = 0; 195 ymin = s->height; 196 ymax = 0; 197 } 198 x += G364_PAGE_SIZE; 199 dy = x / s->width; 200 x = x % s->width; 201 y += dy; 202 vram += G364_PAGE_SIZE; 203 data_display += dy * surface_stride(surface); 204 dd = data_display + x * w; 205 } 206 page += G364_PAGE_SIZE; 207 } 208 209 done: 210 if (xmax || ymax) { 211 dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); 212 } 213 g_free(snap); 214 } 215 216 static void g364fb_draw_blank(G364State *s) 217 { 218 DisplaySurface *surface = qemu_console_surface(s->con); 219 int i, w; 220 uint8_t *d; 221 222 if (s->blanked) { 223 /* Screen is already blank. No need to redraw it */ 224 return; 225 } 226 227 w = s->width * surface_bytes_per_pixel(surface); 228 d = surface_data(surface); 229 for (i = 0; i < s->height; i++) { 230 memset(d, 0, w); 231 d += surface_stride(surface); 232 } 233 234 dpy_gfx_update_full(s->con); 235 s->blanked = 1; 236 } 237 238 static void g364fb_update_display(void *opaque) 239 { 240 G364State *s = opaque; 241 DisplaySurface *surface = qemu_console_surface(s->con); 242 243 qemu_flush_coalesced_mmio_buffer(); 244 245 if (s->width == 0 || s->height == 0) 246 return; 247 248 if (s->width != surface_width(surface) || 249 s->height != surface_height(surface)) { 250 qemu_console_resize(s->con, s->width, s->height); 251 } 252 253 if (s->ctla & CTLA_FORCE_BLANK) { 254 g364fb_draw_blank(s); 255 } else if (s->depth == 8) { 256 g364fb_draw_graphic8(s); 257 } else { 258 error_report("g364: unknown guest depth %d", s->depth); 259 } 260 261 qemu_irq_raise(s->irq); 262 } 263 264 static inline void g364fb_invalidate_display(void *opaque) 265 { 266 G364State *s = opaque; 267 268 s->blanked = 0; 269 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); 270 } 271 272 static void g364fb_reset(G364State *s) 273 { 274 qemu_irq_lower(s->irq); 275 276 memset(s->color_palette, 0, sizeof(s->color_palette)); 277 memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); 278 memset(s->cursor, 0, sizeof(s->cursor)); 279 s->cursor_position = 0; 280 s->ctla = 0; 281 s->top_of_screen = 0; 282 s->width = s->height = 0; 283 memset(s->vram, 0, s->vram_size); 284 g364fb_invalidate_display(s); 285 } 286 287 /* called for accesses to io ports */ 288 static uint64_t g364fb_ctrl_read(void *opaque, 289 hwaddr addr, 290 unsigned int size) 291 { 292 G364State *s = opaque; 293 uint32_t val; 294 295 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 296 /* cursor pattern */ 297 int idx = (addr - REG_CURS_PAT) >> 3; 298 val = s->cursor[idx]; 299 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 300 /* cursor palette */ 301 int idx = (addr - REG_CURS_PAL) >> 3; 302 val = ((uint32_t)s->cursor_palette[idx][0] << 16); 303 val |= ((uint32_t)s->cursor_palette[idx][1] << 8); 304 val |= ((uint32_t)s->cursor_palette[idx][2] << 0); 305 } else { 306 switch (addr) { 307 case REG_DISPLAY: 308 val = s->width / 4; 309 break; 310 case REG_VDISPLAY: 311 val = s->height * 2; 312 break; 313 case REG_CTLA: 314 val = s->ctla; 315 break; 316 default: 317 { 318 error_report("g364: invalid read at [" TARGET_FMT_plx "]", 319 addr); 320 val = 0; 321 break; 322 } 323 } 324 } 325 326 trace_g364fb_read(addr, val); 327 328 return val; 329 } 330 331 static void g364fb_update_depth(G364State *s) 332 { 333 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; 334 s->depth = depths[(s->ctla & 0x00700000) >> 20]; 335 } 336 337 static void g364_invalidate_cursor_position(G364State *s) 338 { 339 DisplaySurface *surface = qemu_console_surface(s->con); 340 int ymin, ymax, start, end; 341 342 /* invalidate only near the cursor */ 343 ymin = s->cursor_position & 0xfff; 344 ymax = MIN(s->height, ymin + 64); 345 start = ymin * surface_stride(surface); 346 end = (ymax + 1) * surface_stride(surface); 347 348 memory_region_set_dirty(&s->mem_vram, start, end - start); 349 } 350 351 static void g364fb_ctrl_write(void *opaque, 352 hwaddr addr, 353 uint64_t val, 354 unsigned int size) 355 { 356 G364State *s = opaque; 357 358 trace_g364fb_write(addr, val); 359 360 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { 361 /* color palette */ 362 int idx = (addr - REG_CLR_PAL) >> 3; 363 s->color_palette[idx][0] = (val >> 16) & 0xff; 364 s->color_palette[idx][1] = (val >> 8) & 0xff; 365 s->color_palette[idx][2] = val & 0xff; 366 g364fb_invalidate_display(s); 367 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { 368 /* cursor pattern */ 369 int idx = (addr - REG_CURS_PAT) >> 3; 370 s->cursor[idx] = val; 371 g364fb_invalidate_display(s); 372 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { 373 /* cursor palette */ 374 int idx = (addr - REG_CURS_PAL) >> 3; 375 s->cursor_palette[idx][0] = (val >> 16) & 0xff; 376 s->cursor_palette[idx][1] = (val >> 8) & 0xff; 377 s->cursor_palette[idx][2] = val & 0xff; 378 g364fb_invalidate_display(s); 379 } else { 380 switch (addr) { 381 case REG_BOOT: /* Boot timing */ 382 case 0x00108: /* Line timing: half sync */ 383 case 0x00110: /* Line timing: back porch */ 384 case 0x00120: /* Line timing: short display */ 385 case 0x00128: /* Frame timing: broad pulse */ 386 case 0x00130: /* Frame timing: v sync */ 387 case 0x00138: /* Frame timing: v preequalise */ 388 case 0x00140: /* Frame timing: v postequalise */ 389 case 0x00148: /* Frame timing: v blank */ 390 case 0x00158: /* Line timing: line time */ 391 case 0x00160: /* Frame store: line start */ 392 case 0x00168: /* vram cycle: mem init */ 393 case 0x00170: /* vram cycle: transfer delay */ 394 case 0x00200: /* vram cycle: mask register */ 395 /* ignore */ 396 break; 397 case REG_TOP: 398 s->top_of_screen = val; 399 g364fb_invalidate_display(s); 400 break; 401 case REG_DISPLAY: 402 s->width = val * 4; 403 break; 404 case REG_VDISPLAY: 405 s->height = val / 2; 406 break; 407 case REG_CTLA: 408 s->ctla = val; 409 g364fb_update_depth(s); 410 g364fb_invalidate_display(s); 411 break; 412 case REG_CURS_POS: 413 g364_invalidate_cursor_position(s); 414 s->cursor_position = val; 415 g364_invalidate_cursor_position(s); 416 break; 417 case REG_RESET: 418 g364fb_reset(s); 419 break; 420 default: 421 error_report("g364: invalid write of 0x%" PRIx64 422 " at [" TARGET_FMT_plx "]", val, addr); 423 break; 424 } 425 } 426 qemu_irq_lower(s->irq); 427 } 428 429 static const MemoryRegionOps g364fb_ctrl_ops = { 430 .read = g364fb_ctrl_read, 431 .write = g364fb_ctrl_write, 432 .endianness = DEVICE_LITTLE_ENDIAN, 433 .impl.min_access_size = 4, 434 .impl.max_access_size = 4, 435 }; 436 437 static int g364fb_post_load(void *opaque, int version_id) 438 { 439 G364State *s = opaque; 440 441 /* force refresh */ 442 g364fb_update_depth(s); 443 g364fb_invalidate_display(s); 444 445 return 0; 446 } 447 448 static const VMStateDescription vmstate_g364fb = { 449 .name = "g364fb", 450 .version_id = 1, 451 .minimum_version_id = 1, 452 .post_load = g364fb_post_load, 453 .fields = (VMStateField[]) { 454 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size), 455 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), 456 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), 457 VMSTATE_UINT16_ARRAY(cursor, G364State, 512), 458 VMSTATE_UINT32(cursor_position, G364State), 459 VMSTATE_UINT32(ctla, G364State), 460 VMSTATE_UINT32(top_of_screen, G364State), 461 VMSTATE_UINT32(width, G364State), 462 VMSTATE_UINT32(height, G364State), 463 VMSTATE_END_OF_LIST() 464 } 465 }; 466 467 static const GraphicHwOps g364fb_ops = { 468 .invalidate = g364fb_invalidate_display, 469 .gfx_update = g364fb_update_display, 470 }; 471 472 static void g364fb_init(DeviceState *dev, G364State *s) 473 { 474 s->vram = g_malloc0(s->vram_size); 475 476 s->con = graphic_console_init(dev, 0, &g364fb_ops, s); 477 478 memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000); 479 memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", 480 s->vram_size, s->vram); 481 vmstate_register_ram(&s->mem_vram, dev); 482 memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA); 483 } 484 485 #define TYPE_G364 "sysbus-g364" 486 #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364) 487 488 typedef struct { 489 SysBusDevice parent_obj; 490 491 G364State g364; 492 } G364SysBusState; 493 494 static void g364fb_sysbus_realize(DeviceState *dev, Error **errp) 495 { 496 G364SysBusState *sbs = G364(dev); 497 G364State *s = &sbs->g364; 498 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 499 500 g364fb_init(dev, s); 501 sysbus_init_irq(sbd, &s->irq); 502 sysbus_init_mmio(sbd, &s->mem_ctrl); 503 sysbus_init_mmio(sbd, &s->mem_vram); 504 } 505 506 static void g364fb_sysbus_reset(DeviceState *d) 507 { 508 G364SysBusState *s = G364(d); 509 510 g364fb_reset(&s->g364); 511 } 512 513 static Property g364fb_sysbus_properties[] = { 514 DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB), 515 DEFINE_PROP_END_OF_LIST(), 516 }; 517 518 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) 519 { 520 DeviceClass *dc = DEVICE_CLASS(klass); 521 522 dc->realize = g364fb_sysbus_realize; 523 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 524 dc->desc = "G364 framebuffer"; 525 dc->reset = g364fb_sysbus_reset; 526 dc->vmsd = &vmstate_g364fb; 527 dc->props = g364fb_sysbus_properties; 528 } 529 530 static const TypeInfo g364fb_sysbus_info = { 531 .name = TYPE_G364, 532 .parent = TYPE_SYS_BUS_DEVICE, 533 .instance_size = sizeof(G364SysBusState), 534 .class_init = g364fb_sysbus_class_init, 535 }; 536 537 static void g364fb_register_types(void) 538 { 539 type_register_static(&g364fb_sysbus_info); 540 } 541 542 type_init(g364fb_register_types) 543