1 /* 2 * Arm PrimeCell PL110 Color LCD Controller 3 * 4 * Copyright (c) 2005-2009 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GNU LGPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/irq.h" 12 #include "hw/sysbus.h" 13 #include "migration/vmstate.h" 14 #include "ui/console.h" 15 #include "framebuffer.h" 16 #include "ui/pixel_ops.h" 17 #include "qemu/timer.h" 18 #include "qemu/log.h" 19 #include "qemu/module.h" 20 #include "qom/object.h" 21 22 #define PL110_CR_EN 0x001 23 #define PL110_CR_BGR 0x100 24 #define PL110_CR_BEBO 0x200 25 #define PL110_CR_BEPO 0x400 26 #define PL110_CR_PWR 0x800 27 #define PL110_IE_NB 0x004 28 #define PL110_IE_VC 0x008 29 30 enum pl110_bppmode 31 { 32 BPP_1, 33 BPP_2, 34 BPP_4, 35 BPP_8, 36 BPP_16, 37 BPP_32, 38 BPP_16_565, /* PL111 only */ 39 BPP_12 /* PL111 only */ 40 }; 41 42 43 /* The Versatile/PB uses a slightly modified PL110 controller. */ 44 enum pl110_version 45 { 46 VERSION_PL110, 47 VERSION_PL110_VERSATILE, 48 VERSION_PL111 49 }; 50 51 #define TYPE_PL110 "pl110" 52 typedef struct PL110State PL110State; 53 DECLARE_INSTANCE_CHECKER(PL110State, PL110, 54 TYPE_PL110) 55 56 struct PL110State { 57 SysBusDevice parent_obj; 58 59 MemoryRegion iomem; 60 MemoryRegionSection fbsection; 61 QemuConsole *con; 62 QEMUTimer *vblank_timer; 63 64 int version; 65 uint32_t timing[4]; 66 uint32_t cr; 67 uint32_t upbase; 68 uint32_t lpbase; 69 uint32_t int_status; 70 uint32_t int_mask; 71 int cols; 72 int rows; 73 enum pl110_bppmode bpp; 74 int invalidate; 75 uint32_t mux_ctrl; 76 uint32_t palette[256]; 77 uint32_t raw_palette[128]; 78 qemu_irq irq; 79 }; 80 81 static int vmstate_pl110_post_load(void *opaque, int version_id); 82 83 static const VMStateDescription vmstate_pl110 = { 84 .name = "pl110", 85 .version_id = 2, 86 .minimum_version_id = 1, 87 .post_load = vmstate_pl110_post_load, 88 .fields = (VMStateField[]) { 89 VMSTATE_INT32(version, PL110State), 90 VMSTATE_UINT32_ARRAY(timing, PL110State, 4), 91 VMSTATE_UINT32(cr, PL110State), 92 VMSTATE_UINT32(upbase, PL110State), 93 VMSTATE_UINT32(lpbase, PL110State), 94 VMSTATE_UINT32(int_status, PL110State), 95 VMSTATE_UINT32(int_mask, PL110State), 96 VMSTATE_INT32(cols, PL110State), 97 VMSTATE_INT32(rows, PL110State), 98 VMSTATE_UINT32(bpp, PL110State), 99 VMSTATE_INT32(invalidate, PL110State), 100 VMSTATE_UINT32_ARRAY(palette, PL110State, 256), 101 VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128), 102 VMSTATE_UINT32_V(mux_ctrl, PL110State, 2), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 107 static const unsigned char pl110_id[] = 108 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 109 110 static const unsigned char pl111_id[] = { 111 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1 112 }; 113 114 115 /* Indexed by pl110_version */ 116 static const unsigned char *idregs[] = { 117 pl110_id, 118 /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board 119 * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware 120 * itself has the same ID values as a stock PL110, and guests (in 121 * particular Linux) rely on this. We emulate what the hardware does, 122 * rather than what the docs claim it ought to do. 123 */ 124 pl110_id, 125 pl111_id 126 }; 127 128 #define BITS 8 129 #include "pl110_template.h" 130 #define BITS 15 131 #include "pl110_template.h" 132 #define BITS 16 133 #include "pl110_template.h" 134 #define BITS 24 135 #include "pl110_template.h" 136 #define BITS 32 137 #include "pl110_template.h" 138 139 static int pl110_enabled(PL110State *s) 140 { 141 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); 142 } 143 144 static void pl110_update_display(void *opaque) 145 { 146 PL110State *s = (PL110State *)opaque; 147 SysBusDevice *sbd; 148 DisplaySurface *surface = qemu_console_surface(s->con); 149 drawfn* fntable; 150 drawfn fn; 151 int dest_width; 152 int src_width; 153 int bpp_offset; 154 int first; 155 int last; 156 157 if (!pl110_enabled(s)) { 158 return; 159 } 160 161 sbd = SYS_BUS_DEVICE(s); 162 163 switch (surface_bits_per_pixel(surface)) { 164 case 0: 165 return; 166 case 8: 167 fntable = pl110_draw_fn_8; 168 dest_width = 1; 169 break; 170 case 15: 171 fntable = pl110_draw_fn_15; 172 dest_width = 2; 173 break; 174 case 16: 175 fntable = pl110_draw_fn_16; 176 dest_width = 2; 177 break; 178 case 24: 179 fntable = pl110_draw_fn_24; 180 dest_width = 3; 181 break; 182 case 32: 183 fntable = pl110_draw_fn_32; 184 dest_width = 4; 185 break; 186 default: 187 fprintf(stderr, "pl110: Bad color depth\n"); 188 exit(1); 189 } 190 if (s->cr & PL110_CR_BGR) 191 bpp_offset = 0; 192 else 193 bpp_offset = 24; 194 195 if ((s->version != VERSION_PL111) && (s->bpp == BPP_16)) { 196 /* The PL110's native 16 bit mode is 5551; however 197 * most boards with a PL110 implement an external 198 * mux which allows bits to be reshuffled to give 199 * 565 format. The mux is typically controlled by 200 * an external system register. 201 * This is controlled by a GPIO input pin 202 * so boards can wire it up to their register. 203 * 204 * The PL111 straightforwardly implements both 205 * 5551 and 565 under control of the bpp field 206 * in the LCDControl register. 207 */ 208 switch (s->mux_ctrl) { 209 case 3: /* 565 BGR */ 210 bpp_offset = (BPP_16_565 - BPP_16); 211 break; 212 case 1: /* 5551 */ 213 break; 214 case 0: /* 888; also if we have loaded vmstate from an old version */ 215 case 2: /* 565 RGB */ 216 default: 217 /* treat as 565 but honour BGR bit */ 218 bpp_offset += (BPP_16_565 - BPP_16); 219 break; 220 } 221 } 222 223 if (s->cr & PL110_CR_BEBO) 224 fn = fntable[s->bpp + 8 + bpp_offset]; 225 else if (s->cr & PL110_CR_BEPO) 226 fn = fntable[s->bpp + 16 + bpp_offset]; 227 else 228 fn = fntable[s->bpp + bpp_offset]; 229 230 src_width = s->cols; 231 switch (s->bpp) { 232 case BPP_1: 233 src_width >>= 3; 234 break; 235 case BPP_2: 236 src_width >>= 2; 237 break; 238 case BPP_4: 239 src_width >>= 1; 240 break; 241 case BPP_8: 242 break; 243 case BPP_16: 244 case BPP_16_565: 245 case BPP_12: 246 src_width <<= 1; 247 break; 248 case BPP_32: 249 src_width <<= 2; 250 break; 251 } 252 dest_width *= s->cols; 253 first = 0; 254 if (s->invalidate) { 255 framebuffer_update_memory_section(&s->fbsection, 256 sysbus_address_space(sbd), 257 s->upbase, 258 s->rows, src_width); 259 } 260 261 framebuffer_update_display(surface, &s->fbsection, 262 s->cols, s->rows, 263 src_width, dest_width, 0, 264 s->invalidate, 265 fn, s->palette, 266 &first, &last); 267 268 if (first >= 0) { 269 dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); 270 } 271 s->invalidate = 0; 272 } 273 274 static void pl110_invalidate_display(void * opaque) 275 { 276 PL110State *s = (PL110State *)opaque; 277 s->invalidate = 1; 278 if (pl110_enabled(s)) { 279 qemu_console_resize(s->con, s->cols, s->rows); 280 } 281 } 282 283 static void pl110_update_palette(PL110State *s, int n) 284 { 285 DisplaySurface *surface = qemu_console_surface(s->con); 286 int i; 287 uint32_t raw; 288 unsigned int r, g, b; 289 290 raw = s->raw_palette[n]; 291 n <<= 1; 292 for (i = 0; i < 2; i++) { 293 r = (raw & 0x1f) << 3; 294 raw >>= 5; 295 g = (raw & 0x1f) << 3; 296 raw >>= 5; 297 b = (raw & 0x1f) << 3; 298 /* The I bit is ignored. */ 299 raw >>= 6; 300 switch (surface_bits_per_pixel(surface)) { 301 case 8: 302 s->palette[n] = rgb_to_pixel8(r, g, b); 303 break; 304 case 15: 305 s->palette[n] = rgb_to_pixel15(r, g, b); 306 break; 307 case 16: 308 s->palette[n] = rgb_to_pixel16(r, g, b); 309 break; 310 case 24: 311 case 32: 312 s->palette[n] = rgb_to_pixel32(r, g, b); 313 break; 314 } 315 n++; 316 } 317 } 318 319 static void pl110_resize(PL110State *s, int width, int height) 320 { 321 if (width != s->cols || height != s->rows) { 322 if (pl110_enabled(s)) { 323 qemu_console_resize(s->con, width, height); 324 } 325 } 326 s->cols = width; 327 s->rows = height; 328 } 329 330 /* Update interrupts. */ 331 static void pl110_update(PL110State *s) 332 { 333 /* Raise IRQ if enabled and any status bit is 1 */ 334 if (s->int_status & s->int_mask) { 335 qemu_irq_raise(s->irq); 336 } else { 337 qemu_irq_lower(s->irq); 338 } 339 } 340 341 static void pl110_vblank_interrupt(void *opaque) 342 { 343 PL110State *s = opaque; 344 345 /* Fire the vertical compare and next base IRQs and re-arm */ 346 s->int_status |= (PL110_IE_NB | PL110_IE_VC); 347 timer_mod(s->vblank_timer, 348 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 349 NANOSECONDS_PER_SECOND / 60); 350 pl110_update(s); 351 } 352 353 static uint64_t pl110_read(void *opaque, hwaddr offset, 354 unsigned size) 355 { 356 PL110State *s = (PL110State *)opaque; 357 358 if (offset >= 0xfe0 && offset < 0x1000) { 359 return idregs[s->version][(offset - 0xfe0) >> 2]; 360 } 361 if (offset >= 0x200 && offset < 0x400) { 362 return s->raw_palette[(offset - 0x200) >> 2]; 363 } 364 switch (offset >> 2) { 365 case 0: /* LCDTiming0 */ 366 return s->timing[0]; 367 case 1: /* LCDTiming1 */ 368 return s->timing[1]; 369 case 2: /* LCDTiming2 */ 370 return s->timing[2]; 371 case 3: /* LCDTiming3 */ 372 return s->timing[3]; 373 case 4: /* LCDUPBASE */ 374 return s->upbase; 375 case 5: /* LCDLPBASE */ 376 return s->lpbase; 377 case 6: /* LCDIMSC */ 378 if (s->version != VERSION_PL110) { 379 return s->cr; 380 } 381 return s->int_mask; 382 case 7: /* LCDControl */ 383 if (s->version != VERSION_PL110) { 384 return s->int_mask; 385 } 386 return s->cr; 387 case 8: /* LCDRIS */ 388 return s->int_status; 389 case 9: /* LCDMIS */ 390 return s->int_status & s->int_mask; 391 case 11: /* LCDUPCURR */ 392 /* TODO: Implement vertical refresh. */ 393 return s->upbase; 394 case 12: /* LCDLPCURR */ 395 return s->lpbase; 396 default: 397 qemu_log_mask(LOG_GUEST_ERROR, 398 "pl110_read: Bad offset %x\n", (int)offset); 399 return 0; 400 } 401 } 402 403 static void pl110_write(void *opaque, hwaddr offset, 404 uint64_t val, unsigned size) 405 { 406 PL110State *s = (PL110State *)opaque; 407 int n; 408 409 /* For simplicity invalidate the display whenever a control register 410 is written to. */ 411 s->invalidate = 1; 412 if (offset >= 0x200 && offset < 0x400) { 413 /* Palette. */ 414 n = (offset - 0x200) >> 2; 415 s->raw_palette[(offset - 0x200) >> 2] = val; 416 pl110_update_palette(s, n); 417 return; 418 } 419 switch (offset >> 2) { 420 case 0: /* LCDTiming0 */ 421 s->timing[0] = val; 422 n = ((val & 0xfc) + 4) * 4; 423 pl110_resize(s, n, s->rows); 424 break; 425 case 1: /* LCDTiming1 */ 426 s->timing[1] = val; 427 n = (val & 0x3ff) + 1; 428 pl110_resize(s, s->cols, n); 429 break; 430 case 2: /* LCDTiming2 */ 431 s->timing[2] = val; 432 break; 433 case 3: /* LCDTiming3 */ 434 s->timing[3] = val; 435 break; 436 case 4: /* LCDUPBASE */ 437 s->upbase = val; 438 break; 439 case 5: /* LCDLPBASE */ 440 s->lpbase = val; 441 break; 442 case 6: /* LCDIMSC */ 443 if (s->version != VERSION_PL110) { 444 goto control; 445 } 446 imsc: 447 s->int_mask = val; 448 pl110_update(s); 449 break; 450 case 7: /* LCDControl */ 451 if (s->version != VERSION_PL110) { 452 goto imsc; 453 } 454 control: 455 s->cr = val; 456 s->bpp = (val >> 1) & 7; 457 if (pl110_enabled(s)) { 458 qemu_console_resize(s->con, s->cols, s->rows); 459 timer_mod(s->vblank_timer, 460 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 461 NANOSECONDS_PER_SECOND / 60); 462 } else { 463 timer_del(s->vblank_timer); 464 } 465 break; 466 case 10: /* LCDICR */ 467 s->int_status &= ~val; 468 pl110_update(s); 469 break; 470 default: 471 qemu_log_mask(LOG_GUEST_ERROR, 472 "pl110_write: Bad offset %x\n", (int)offset); 473 } 474 } 475 476 static const MemoryRegionOps pl110_ops = { 477 .read = pl110_read, 478 .write = pl110_write, 479 .endianness = DEVICE_NATIVE_ENDIAN, 480 }; 481 482 static void pl110_mux_ctrl_set(void *opaque, int line, int level) 483 { 484 PL110State *s = (PL110State *)opaque; 485 s->mux_ctrl = level; 486 } 487 488 static int vmstate_pl110_post_load(void *opaque, int version_id) 489 { 490 PL110State *s = opaque; 491 /* Make sure we redraw, and at the right size */ 492 pl110_invalidate_display(s); 493 return 0; 494 } 495 496 static const GraphicHwOps pl110_gfx_ops = { 497 .invalidate = pl110_invalidate_display, 498 .gfx_update = pl110_update_display, 499 }; 500 501 static void pl110_realize(DeviceState *dev, Error **errp) 502 { 503 PL110State *s = PL110(dev); 504 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 505 506 memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000); 507 sysbus_init_mmio(sbd, &s->iomem); 508 sysbus_init_irq(sbd, &s->irq); 509 s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 510 pl110_vblank_interrupt, s); 511 qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1); 512 s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s); 513 } 514 515 static void pl110_init(Object *obj) 516 { 517 PL110State *s = PL110(obj); 518 519 s->version = VERSION_PL110; 520 } 521 522 static void pl110_versatile_init(Object *obj) 523 { 524 PL110State *s = PL110(obj); 525 526 s->version = VERSION_PL110_VERSATILE; 527 } 528 529 static void pl111_init(Object *obj) 530 { 531 PL110State *s = PL110(obj); 532 533 s->version = VERSION_PL111; 534 } 535 536 static void pl110_class_init(ObjectClass *klass, void *data) 537 { 538 DeviceClass *dc = DEVICE_CLASS(klass); 539 540 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 541 dc->vmsd = &vmstate_pl110; 542 dc->realize = pl110_realize; 543 } 544 545 static const TypeInfo pl110_info = { 546 .name = TYPE_PL110, 547 .parent = TYPE_SYS_BUS_DEVICE, 548 .instance_size = sizeof(PL110State), 549 .instance_init = pl110_init, 550 .class_init = pl110_class_init, 551 }; 552 553 static const TypeInfo pl110_versatile_info = { 554 .name = "pl110_versatile", 555 .parent = TYPE_PL110, 556 .instance_init = pl110_versatile_init, 557 }; 558 559 static const TypeInfo pl111_info = { 560 .name = "pl111", 561 .parent = TYPE_PL110, 562 .instance_init = pl111_init, 563 }; 564 565 static void pl110_register_types(void) 566 { 567 type_register_static(&pl110_info); 568 type_register_static(&pl110_versatile_info); 569 type_register_static(&pl111_info); 570 } 571 572 type_init(pl110_register_types) 573