1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include <zlib.h> 23 24 #include "qemu-common.h" 25 #include "qemu/timer.h" 26 #include "qemu/queue.h" 27 #include "qemu/atomic.h" 28 #include "sysemu/sysemu.h" 29 #include "trace.h" 30 31 #include "qxl.h" 32 33 /* 34 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 35 * such can be changed by the guest, so to avoid a guest trigerrable 36 * abort we just qxl_set_guest_bug and set the return to NULL. Still 37 * it may happen as a result of emulator bug as well. 38 */ 39 #undef SPICE_RING_PROD_ITEM 40 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 41 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 42 if (prod >= ARRAY_SIZE((r)->items)) { \ 43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 44 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 45 ret = NULL; \ 46 } else { \ 47 ret = &(r)->items[prod].el; \ 48 } \ 49 } 50 51 #undef SPICE_RING_CONS_ITEM 52 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 53 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 54 if (cons >= ARRAY_SIZE((r)->items)) { \ 55 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 56 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 57 ret = NULL; \ 58 } else { \ 59 ret = &(r)->items[cons].el; \ 60 } \ 61 } 62 63 #undef ALIGN 64 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 65 66 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 67 68 #define QXL_MODE(_x, _y, _b, _o) \ 69 { .x_res = _x, \ 70 .y_res = _y, \ 71 .bits = _b, \ 72 .stride = (_x) * (_b) / 8, \ 73 .x_mili = PIXEL_SIZE * (_x), \ 74 .y_mili = PIXEL_SIZE * (_y), \ 75 .orientation = _o, \ 76 } 77 78 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 79 QXL_MODE(x_res, y_res, 16, orientation), \ 80 QXL_MODE(x_res, y_res, 32, orientation) 81 82 #define QXL_MODE_EX(x_res, y_res) \ 83 QXL_MODE_16_32(x_res, y_res, 0), \ 84 QXL_MODE_16_32(x_res, y_res, 1) 85 86 static QXLMode qxl_modes[] = { 87 QXL_MODE_EX(640, 480), 88 QXL_MODE_EX(800, 480), 89 QXL_MODE_EX(800, 600), 90 QXL_MODE_EX(832, 624), 91 QXL_MODE_EX(960, 640), 92 QXL_MODE_EX(1024, 600), 93 QXL_MODE_EX(1024, 768), 94 QXL_MODE_EX(1152, 864), 95 QXL_MODE_EX(1152, 870), 96 QXL_MODE_EX(1280, 720), 97 QXL_MODE_EX(1280, 760), 98 QXL_MODE_EX(1280, 768), 99 QXL_MODE_EX(1280, 800), 100 QXL_MODE_EX(1280, 960), 101 QXL_MODE_EX(1280, 1024), 102 QXL_MODE_EX(1360, 768), 103 QXL_MODE_EX(1366, 768), 104 QXL_MODE_EX(1400, 1050), 105 QXL_MODE_EX(1440, 900), 106 QXL_MODE_EX(1600, 900), 107 QXL_MODE_EX(1600, 1200), 108 QXL_MODE_EX(1680, 1050), 109 QXL_MODE_EX(1920, 1080), 110 /* these modes need more than 8 MB video memory */ 111 QXL_MODE_EX(1920, 1200), 112 QXL_MODE_EX(1920, 1440), 113 QXL_MODE_EX(2000, 2000), 114 QXL_MODE_EX(2048, 1536), 115 QXL_MODE_EX(2048, 2048), 116 QXL_MODE_EX(2560, 1440), 117 QXL_MODE_EX(2560, 1600), 118 /* these modes need more than 16 MB video memory */ 119 QXL_MODE_EX(2560, 2048), 120 QXL_MODE_EX(2800, 2100), 121 QXL_MODE_EX(3200, 2400), 122 /* these modes need more than 32 MB video memory */ 123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 124 QXL_MODE_EX(4096, 2160), /* 4k */ 125 /* these modes need more than 64 MB video memory */ 126 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 127 /* these modes need more than 128 MB video memory */ 128 QXL_MODE_EX(8192, 4320), /* 8k */ 129 }; 130 131 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 132 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 133 static void qxl_reset_memslots(PCIQXLDevice *d); 134 static void qxl_reset_surfaces(PCIQXLDevice *d); 135 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 136 137 static void qxl_hw_update(void *opaque); 138 139 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 140 { 141 trace_qxl_set_guest_bug(qxl->id); 142 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 143 qxl->guest_bug = 1; 144 if (qxl->guestdebug) { 145 va_list ap; 146 va_start(ap, msg); 147 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 148 vfprintf(stderr, msg, ap); 149 fprintf(stderr, "\n"); 150 va_end(ap); 151 } 152 } 153 154 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 155 { 156 qxl->guest_bug = 0; 157 } 158 159 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 160 struct QXLRect *area, struct QXLRect *dirty_rects, 161 uint32_t num_dirty_rects, 162 uint32_t clear_dirty_region, 163 qxl_async_io async, struct QXLCookie *cookie) 164 { 165 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 166 area->top, area->bottom); 167 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 168 clear_dirty_region); 169 if (async == QXL_SYNC) { 170 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 171 dirty_rects, num_dirty_rects, clear_dirty_region); 172 } else { 173 assert(cookie != NULL); 174 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 175 clear_dirty_region, (uintptr_t)cookie); 176 } 177 } 178 179 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 180 uint32_t id) 181 { 182 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 183 qemu_mutex_lock(&qxl->track_lock); 184 qxl->guest_surfaces.cmds[id] = 0; 185 qxl->guest_surfaces.count--; 186 qemu_mutex_unlock(&qxl->track_lock); 187 } 188 189 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 190 qxl_async_io async) 191 { 192 QXLCookie *cookie; 193 194 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 195 if (async) { 196 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 197 QXL_IO_DESTROY_SURFACE_ASYNC); 198 cookie->u.surface_id = id; 199 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 200 } else { 201 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 202 qxl_spice_destroy_surface_wait_complete(qxl, id); 203 } 204 } 205 206 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 207 { 208 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 209 qxl->num_free_res); 210 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 211 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 212 QXL_IO_FLUSH_SURFACES_ASYNC)); 213 } 214 215 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 216 uint32_t count) 217 { 218 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 219 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 220 } 221 222 void qxl_spice_oom(PCIQXLDevice *qxl) 223 { 224 trace_qxl_spice_oom(qxl->id); 225 spice_qxl_oom(&qxl->ssd.qxl); 226 } 227 228 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 229 { 230 trace_qxl_spice_reset_memslots(qxl->id); 231 spice_qxl_reset_memslots(&qxl->ssd.qxl); 232 } 233 234 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 235 { 236 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 237 qemu_mutex_lock(&qxl->track_lock); 238 memset(qxl->guest_surfaces.cmds, 0, 239 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 240 qxl->guest_surfaces.count = 0; 241 qemu_mutex_unlock(&qxl->track_lock); 242 } 243 244 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 245 { 246 trace_qxl_spice_destroy_surfaces(qxl->id, async); 247 if (async) { 248 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 249 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 250 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 251 } else { 252 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 253 qxl_spice_destroy_surfaces_complete(qxl); 254 } 255 } 256 257 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 258 { 259 trace_qxl_spice_monitors_config(qxl->id); 260 if (replay) { 261 /* 262 * don't use QXL_COOKIE_TYPE_IO: 263 * - we are not running yet (post_load), we will assert 264 * in send_events 265 * - this is not a guest io, but a reply, so async_io isn't set. 266 */ 267 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 268 qxl->guest_monitors_config, 269 MEMSLOT_GROUP_GUEST, 270 (uintptr_t)qxl_cookie_new( 271 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 272 0)); 273 } else { 274 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 275 if (qxl->max_outputs) { 276 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs); 277 } 278 #endif 279 qxl->guest_monitors_config = qxl->ram->monitors_config; 280 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 281 qxl->ram->monitors_config, 282 MEMSLOT_GROUP_GUEST, 283 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 284 QXL_IO_MONITORS_CONFIG_ASYNC)); 285 } 286 } 287 288 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 289 { 290 trace_qxl_spice_reset_image_cache(qxl->id); 291 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 292 } 293 294 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 295 { 296 trace_qxl_spice_reset_cursor(qxl->id); 297 spice_qxl_reset_cursor(&qxl->ssd.qxl); 298 qemu_mutex_lock(&qxl->track_lock); 299 qxl->guest_cursor = 0; 300 qemu_mutex_unlock(&qxl->track_lock); 301 if (qxl->ssd.cursor) { 302 cursor_put(qxl->ssd.cursor); 303 } 304 qxl->ssd.cursor = cursor_builtin_hidden(); 305 } 306 307 static ram_addr_t qxl_rom_size(void) 308 { 309 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + 310 sizeof(qxl_modes); 311 uint32_t rom_size = 8192; /* two pages */ 312 313 QEMU_BUILD_BUG_ON(required_rom_size > rom_size); 314 return rom_size; 315 } 316 317 static void init_qxl_rom(PCIQXLDevice *d) 318 { 319 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 320 QXLModes *modes = (QXLModes *)(rom + 1); 321 uint32_t ram_header_size; 322 uint32_t surface0_area_size; 323 uint32_t num_pages; 324 uint32_t fb; 325 int i, n; 326 327 memset(rom, 0, d->rom_size); 328 329 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 330 rom->id = cpu_to_le32(d->id); 331 rom->log_level = cpu_to_le32(d->guestdebug); 332 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 333 334 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 335 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 336 rom->slots_start = 1; 337 rom->slots_end = NUM_MEMSLOTS - 1; 338 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 339 340 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 341 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 342 if (fb > d->vgamem_size) { 343 continue; 344 } 345 modes->modes[n].id = cpu_to_le32(i); 346 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 347 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 348 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 349 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 350 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 351 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 352 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 353 n++; 354 } 355 modes->n_modes = cpu_to_le32(n); 356 357 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 358 surface0_area_size = ALIGN(d->vgamem_size, 4096); 359 num_pages = d->vga.vram_size; 360 num_pages -= ram_header_size; 361 num_pages -= surface0_area_size; 362 num_pages = num_pages / QXL_PAGE_SIZE; 363 364 assert(ram_header_size + surface0_area_size <= d->vga.vram_size); 365 366 rom->draw_area_offset = cpu_to_le32(0); 367 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 368 rom->pages_offset = cpu_to_le32(surface0_area_size); 369 rom->num_pages = cpu_to_le32(num_pages); 370 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 371 372 d->shadow_rom = *rom; 373 d->rom = rom; 374 d->modes = modes; 375 } 376 377 static void init_qxl_ram(PCIQXLDevice *d) 378 { 379 uint8_t *buf; 380 uint64_t *item; 381 382 buf = d->vga.vram_ptr; 383 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 384 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 385 d->ram->int_pending = cpu_to_le32(0); 386 d->ram->int_mask = cpu_to_le32(0); 387 d->ram->update_surface = 0; 388 d->ram->monitors_config = 0; 389 SPICE_RING_INIT(&d->ram->cmd_ring); 390 SPICE_RING_INIT(&d->ram->cursor_ring); 391 SPICE_RING_INIT(&d->ram->release_ring); 392 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 393 assert(item); 394 *item = 0; 395 qxl_ring_set_dirty(d); 396 } 397 398 /* can be called from spice server thread context */ 399 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 400 { 401 memory_region_set_dirty(mr, addr, end - addr); 402 } 403 404 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 405 { 406 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 407 } 408 409 /* called from spice server thread context only */ 410 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 411 { 412 void *base = qxl->vga.vram_ptr; 413 intptr_t offset; 414 415 offset = ptr - base; 416 assert(offset < qxl->vga.vram_size); 417 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 418 } 419 420 /* can be called from spice server thread context */ 421 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 422 { 423 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 424 ram_addr_t end = qxl->vga.vram_size; 425 qxl_set_dirty(&qxl->vga.vram, addr, end); 426 } 427 428 /* 429 * keep track of some command state, for savevm/loadvm. 430 * called from spice server thread context only 431 */ 432 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 433 { 434 switch (le32_to_cpu(ext->cmd.type)) { 435 case QXL_CMD_SURFACE: 436 { 437 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 438 439 if (!cmd) { 440 return 1; 441 } 442 uint32_t id = le32_to_cpu(cmd->surface_id); 443 444 if (id >= qxl->ssd.num_surfaces) { 445 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 446 qxl->ssd.num_surfaces); 447 return 1; 448 } 449 if (cmd->type == QXL_SURFACE_CMD_CREATE && 450 (cmd->u.surface_create.stride & 0x03) != 0) { 451 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 452 cmd->u.surface_create.stride); 453 return 1; 454 } 455 qemu_mutex_lock(&qxl->track_lock); 456 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 457 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 458 qxl->guest_surfaces.count++; 459 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 460 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 461 } 462 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 463 qxl->guest_surfaces.cmds[id] = 0; 464 qxl->guest_surfaces.count--; 465 } 466 qemu_mutex_unlock(&qxl->track_lock); 467 break; 468 } 469 case QXL_CMD_CURSOR: 470 { 471 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 472 473 if (!cmd) { 474 return 1; 475 } 476 if (cmd->type == QXL_CURSOR_SET) { 477 qemu_mutex_lock(&qxl->track_lock); 478 qxl->guest_cursor = ext->cmd.data; 479 qemu_mutex_unlock(&qxl->track_lock); 480 } 481 break; 482 } 483 } 484 return 0; 485 } 486 487 /* spice display interface callbacks */ 488 489 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 490 { 491 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 492 493 trace_qxl_interface_attach_worker(qxl->id); 494 qxl->ssd.worker = qxl_worker; 495 } 496 497 static void interface_set_compression_level(QXLInstance *sin, int level) 498 { 499 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 500 501 trace_qxl_interface_set_compression_level(qxl->id, level); 502 qxl->shadow_rom.compression_level = cpu_to_le32(level); 503 qxl->rom->compression_level = cpu_to_le32(level); 504 qxl_rom_set_dirty(qxl); 505 } 506 507 #if SPICE_NEEDS_SET_MM_TIME 508 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 509 { 510 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 511 512 if (!qemu_spice_display_is_running(&qxl->ssd)) { 513 return; 514 } 515 516 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 517 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 518 qxl->rom->mm_clock = cpu_to_le32(mm_time); 519 qxl_rom_set_dirty(qxl); 520 } 521 #endif 522 523 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 524 { 525 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 526 527 trace_qxl_interface_get_init_info(qxl->id); 528 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 529 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 530 info->num_memslots = NUM_MEMSLOTS; 531 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 532 info->internal_groupslot_id = 0; 533 info->qxl_ram_size = 534 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 535 info->n_surfaces = qxl->ssd.num_surfaces; 536 } 537 538 static const char *qxl_mode_to_string(int mode) 539 { 540 switch (mode) { 541 case QXL_MODE_COMPAT: 542 return "compat"; 543 case QXL_MODE_NATIVE: 544 return "native"; 545 case QXL_MODE_UNDEFINED: 546 return "undefined"; 547 case QXL_MODE_VGA: 548 return "vga"; 549 } 550 return "INVALID"; 551 } 552 553 static const char *io_port_to_string(uint32_t io_port) 554 { 555 if (io_port >= QXL_IO_RANGE_SIZE) { 556 return "out of range"; 557 } 558 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 559 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 560 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 561 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 562 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 563 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 564 [QXL_IO_RESET] = "QXL_IO_RESET", 565 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 566 [QXL_IO_LOG] = "QXL_IO_LOG", 567 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 568 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 569 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 570 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 571 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 572 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 573 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 574 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 575 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 576 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 577 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 578 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 579 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 580 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 581 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 582 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 583 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 584 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 585 }; 586 return io_port_to_string[io_port]; 587 } 588 589 /* called from spice server thread context only */ 590 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 591 { 592 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 593 SimpleSpiceUpdate *update; 594 QXLCommandRing *ring; 595 QXLCommand *cmd; 596 int notify, ret; 597 598 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 599 600 switch (qxl->mode) { 601 case QXL_MODE_VGA: 602 ret = false; 603 qemu_mutex_lock(&qxl->ssd.lock); 604 update = QTAILQ_FIRST(&qxl->ssd.updates); 605 if (update != NULL) { 606 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 607 *ext = update->ext; 608 ret = true; 609 } 610 qemu_mutex_unlock(&qxl->ssd.lock); 611 if (ret) { 612 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 613 qxl_log_command(qxl, "vga", ext); 614 } 615 return ret; 616 case QXL_MODE_COMPAT: 617 case QXL_MODE_NATIVE: 618 case QXL_MODE_UNDEFINED: 619 ring = &qxl->ram->cmd_ring; 620 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 621 return false; 622 } 623 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 624 if (!cmd) { 625 return false; 626 } 627 ext->cmd = *cmd; 628 ext->group_id = MEMSLOT_GROUP_GUEST; 629 ext->flags = qxl->cmdflags; 630 SPICE_RING_POP(ring, notify); 631 qxl_ring_set_dirty(qxl); 632 if (notify) { 633 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 634 } 635 qxl->guest_primary.commands++; 636 qxl_track_command(qxl, ext); 637 qxl_log_command(qxl, "cmd", ext); 638 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 639 return true; 640 default: 641 return false; 642 } 643 } 644 645 /* called from spice server thread context only */ 646 static int interface_req_cmd_notification(QXLInstance *sin) 647 { 648 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 649 int wait = 1; 650 651 trace_qxl_ring_command_req_notification(qxl->id); 652 switch (qxl->mode) { 653 case QXL_MODE_COMPAT: 654 case QXL_MODE_NATIVE: 655 case QXL_MODE_UNDEFINED: 656 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 657 qxl_ring_set_dirty(qxl); 658 break; 659 default: 660 /* nothing */ 661 break; 662 } 663 return wait; 664 } 665 666 /* called from spice server thread context only */ 667 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 668 { 669 QXLReleaseRing *ring = &d->ram->release_ring; 670 uint64_t *item; 671 int notify; 672 673 #define QXL_FREE_BUNCH_SIZE 32 674 675 if (ring->prod - ring->cons + 1 == ring->num_items) { 676 /* ring full -- can't push */ 677 return; 678 } 679 if (!flush && d->oom_running) { 680 /* collect everything from oom handler before pushing */ 681 return; 682 } 683 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 684 /* collect a bit more before pushing */ 685 return; 686 } 687 688 SPICE_RING_PUSH(ring, notify); 689 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 690 d->guest_surfaces.count, d->num_free_res, 691 d->last_release, notify ? "yes" : "no"); 692 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 693 ring->num_items, ring->prod, ring->cons); 694 if (notify) { 695 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 696 } 697 SPICE_RING_PROD_ITEM(d, ring, item); 698 if (!item) { 699 return; 700 } 701 *item = 0; 702 d->num_free_res = 0; 703 d->last_release = NULL; 704 qxl_ring_set_dirty(d); 705 } 706 707 /* called from spice server thread context only */ 708 static void interface_release_resource(QXLInstance *sin, 709 QXLReleaseInfoExt ext) 710 { 711 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 712 QXLReleaseRing *ring; 713 uint64_t *item, id; 714 715 if (ext.group_id == MEMSLOT_GROUP_HOST) { 716 /* host group -> vga mode update request */ 717 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 718 SimpleSpiceUpdate *update; 719 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 720 update = container_of(cmdext, SimpleSpiceUpdate, ext); 721 qemu_spice_destroy_update(&qxl->ssd, update); 722 return; 723 } 724 725 /* 726 * ext->info points into guest-visible memory 727 * pci bar 0, $command.release_info 728 */ 729 ring = &qxl->ram->release_ring; 730 SPICE_RING_PROD_ITEM(qxl, ring, item); 731 if (!item) { 732 return; 733 } 734 if (*item == 0) { 735 /* stick head into the ring */ 736 id = ext.info->id; 737 ext.info->next = 0; 738 qxl_ram_set_dirty(qxl, &ext.info->next); 739 *item = id; 740 qxl_ring_set_dirty(qxl); 741 } else { 742 /* append item to the list */ 743 qxl->last_release->next = ext.info->id; 744 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 745 ext.info->next = 0; 746 qxl_ram_set_dirty(qxl, &ext.info->next); 747 } 748 qxl->last_release = ext.info; 749 qxl->num_free_res++; 750 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 751 qxl_push_free_res(qxl, 0); 752 } 753 754 /* called from spice server thread context only */ 755 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 756 { 757 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 758 QXLCursorRing *ring; 759 QXLCommand *cmd; 760 int notify; 761 762 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 763 764 switch (qxl->mode) { 765 case QXL_MODE_COMPAT: 766 case QXL_MODE_NATIVE: 767 case QXL_MODE_UNDEFINED: 768 ring = &qxl->ram->cursor_ring; 769 if (SPICE_RING_IS_EMPTY(ring)) { 770 return false; 771 } 772 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 773 if (!cmd) { 774 return false; 775 } 776 ext->cmd = *cmd; 777 ext->group_id = MEMSLOT_GROUP_GUEST; 778 ext->flags = qxl->cmdflags; 779 SPICE_RING_POP(ring, notify); 780 qxl_ring_set_dirty(qxl); 781 if (notify) { 782 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 783 } 784 qxl->guest_primary.commands++; 785 qxl_track_command(qxl, ext); 786 qxl_log_command(qxl, "csr", ext); 787 if (qxl->id == 0) { 788 qxl_render_cursor(qxl, ext); 789 } 790 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 791 return true; 792 default: 793 return false; 794 } 795 } 796 797 /* called from spice server thread context only */ 798 static int interface_req_cursor_notification(QXLInstance *sin) 799 { 800 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 801 int wait = 1; 802 803 trace_qxl_ring_cursor_req_notification(qxl->id); 804 switch (qxl->mode) { 805 case QXL_MODE_COMPAT: 806 case QXL_MODE_NATIVE: 807 case QXL_MODE_UNDEFINED: 808 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 809 qxl_ring_set_dirty(qxl); 810 break; 811 default: 812 /* nothing */ 813 break; 814 } 815 return wait; 816 } 817 818 /* called from spice server thread context */ 819 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 820 { 821 /* 822 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 823 * use by xf86-video-qxl and is defined out in the qxl windows driver. 824 * Probably was at some earlier version that is prior to git start (2009), 825 * and is still guest trigerrable. 826 */ 827 fprintf(stderr, "%s: deprecated\n", __func__); 828 } 829 830 /* called from spice server thread context only */ 831 static int interface_flush_resources(QXLInstance *sin) 832 { 833 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 834 int ret; 835 836 ret = qxl->num_free_res; 837 if (ret) { 838 qxl_push_free_res(qxl, 1); 839 } 840 return ret; 841 } 842 843 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 844 845 /* called from spice server thread context only */ 846 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 847 { 848 uint32_t current_async; 849 850 qemu_mutex_lock(&qxl->async_lock); 851 current_async = qxl->current_async; 852 qxl->current_async = QXL_UNDEFINED_IO; 853 qemu_mutex_unlock(&qxl->async_lock); 854 855 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 856 if (!cookie) { 857 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 858 return; 859 } 860 if (cookie && current_async != cookie->io) { 861 fprintf(stderr, 862 "qxl: %s: error: current_async = %d != %" 863 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 864 } 865 switch (current_async) { 866 case QXL_IO_MEMSLOT_ADD_ASYNC: 867 case QXL_IO_DESTROY_PRIMARY_ASYNC: 868 case QXL_IO_UPDATE_AREA_ASYNC: 869 case QXL_IO_FLUSH_SURFACES_ASYNC: 870 case QXL_IO_MONITORS_CONFIG_ASYNC: 871 break; 872 case QXL_IO_CREATE_PRIMARY_ASYNC: 873 qxl_create_guest_primary_complete(qxl); 874 break; 875 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 876 qxl_spice_destroy_surfaces_complete(qxl); 877 break; 878 case QXL_IO_DESTROY_SURFACE_ASYNC: 879 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 880 break; 881 default: 882 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 883 current_async); 884 } 885 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 886 } 887 888 /* called from spice server thread context only */ 889 static void interface_update_area_complete(QXLInstance *sin, 890 uint32_t surface_id, 891 QXLRect *dirty, uint32_t num_updated_rects) 892 { 893 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 894 int i; 895 int qxl_i; 896 897 qemu_mutex_lock(&qxl->ssd.lock); 898 if (surface_id != 0 || !num_updated_rects || 899 !qxl->render_update_cookie_num) { 900 qemu_mutex_unlock(&qxl->ssd.lock); 901 return; 902 } 903 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 904 dirty->right, dirty->top, dirty->bottom); 905 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 906 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 907 /* 908 * overflow - treat this as a full update. Not expected to be common. 909 */ 910 trace_qxl_interface_update_area_complete_overflow(qxl->id, 911 QXL_NUM_DIRTY_RECTS); 912 qxl->guest_primary.resized = 1; 913 } 914 if (qxl->guest_primary.resized) { 915 /* 916 * Don't bother copying or scheduling the bh since we will flip 917 * the whole area anyway on completion of the update_area async call 918 */ 919 qemu_mutex_unlock(&qxl->ssd.lock); 920 return; 921 } 922 qxl_i = qxl->num_dirty_rects; 923 for (i = 0; i < num_updated_rects; i++) { 924 qxl->dirty[qxl_i++] = dirty[i]; 925 } 926 qxl->num_dirty_rects += num_updated_rects; 927 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 928 qxl->num_dirty_rects); 929 qemu_bh_schedule(qxl->update_area_bh); 930 qemu_mutex_unlock(&qxl->ssd.lock); 931 } 932 933 /* called from spice server thread context only */ 934 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 935 { 936 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 937 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 938 939 switch (cookie->type) { 940 case QXL_COOKIE_TYPE_IO: 941 interface_async_complete_io(qxl, cookie); 942 g_free(cookie); 943 break; 944 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 945 qxl_render_update_area_done(qxl, cookie); 946 break; 947 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 948 break; 949 default: 950 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 951 __func__, cookie->type); 952 g_free(cookie); 953 } 954 } 955 956 /* called from spice server thread context only */ 957 static void interface_set_client_capabilities(QXLInstance *sin, 958 uint8_t client_present, 959 uint8_t caps[58]) 960 { 961 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 962 963 if (qxl->revision < 4) { 964 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 965 qxl->revision); 966 return; 967 } 968 969 if (runstate_check(RUN_STATE_INMIGRATE) || 970 runstate_check(RUN_STATE_POSTMIGRATE)) { 971 return; 972 } 973 974 qxl->shadow_rom.client_present = client_present; 975 memcpy(qxl->shadow_rom.client_capabilities, caps, 976 sizeof(qxl->shadow_rom.client_capabilities)); 977 qxl->rom->client_present = client_present; 978 memcpy(qxl->rom->client_capabilities, caps, 979 sizeof(qxl->rom->client_capabilities)); 980 qxl_rom_set_dirty(qxl); 981 982 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 983 } 984 985 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 986 { 987 /* 988 * zlib xors the seed with 0xffffffff, and xors the result 989 * again with 0xffffffff; Both are not done with linux's crc32, 990 * which we want to be compatible with, so undo that. 991 */ 992 return crc32(0xffffffff, p, len) ^ 0xffffffff; 993 } 994 995 static bool qxl_rom_monitors_config_changed(QXLRom *rom, 996 VDAgentMonitorsConfig *monitors_config, 997 unsigned int max_outputs) 998 { 999 int i; 1000 unsigned int monitors_count; 1001 1002 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs); 1003 1004 if (rom->client_monitors_config.count != monitors_count) { 1005 return true; 1006 } 1007 1008 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1009 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1010 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1011 /* monitor->depth ignored */ 1012 if ((rect->left != monitor->x) || 1013 (rect->top != monitor->y) || 1014 (rect->right != monitor->x + monitor->width) || 1015 (rect->bottom != monitor->y + monitor->height)) { 1016 return true; 1017 } 1018 } 1019 1020 return false; 1021 } 1022 1023 /* called from main context only */ 1024 static int interface_client_monitors_config(QXLInstance *sin, 1025 VDAgentMonitorsConfig *monitors_config) 1026 { 1027 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1028 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 1029 int i; 1030 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads); 1031 bool config_changed = false; 1032 1033 if (qxl->revision < 4) { 1034 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 1035 qxl->revision); 1036 return 0; 1037 } 1038 /* 1039 * Older windows drivers set int_mask to 0 when their ISR is called, 1040 * then later set it to ~0. So it doesn't relate to the actual interrupts 1041 * handled. However, they are old, so clearly they don't support this 1042 * interrupt 1043 */ 1044 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1045 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1046 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1047 qxl->ram->int_mask, 1048 monitors_config); 1049 return 0; 1050 } 1051 if (!monitors_config) { 1052 return 1; 1053 } 1054 1055 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 1056 /* limit number of outputs based on setting limit */ 1057 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) { 1058 max_outputs = qxl->max_outputs; 1059 } 1060 #endif 1061 1062 config_changed = qxl_rom_monitors_config_changed(rom, 1063 monitors_config, 1064 max_outputs); 1065 1066 memset(&rom->client_monitors_config, 0, 1067 sizeof(rom->client_monitors_config)); 1068 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1069 /* monitors_config->flags ignored */ 1070 if (rom->client_monitors_config.count >= max_outputs) { 1071 trace_qxl_client_monitors_config_capped(qxl->id, 1072 monitors_config->num_of_monitors, 1073 max_outputs); 1074 rom->client_monitors_config.count = max_outputs; 1075 } 1076 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1077 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1078 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1079 /* monitor->depth ignored */ 1080 rect->left = monitor->x; 1081 rect->top = monitor->y; 1082 rect->right = monitor->x + monitor->width; 1083 rect->bottom = monitor->y + monitor->height; 1084 } 1085 rom->client_monitors_config_crc = qxl_crc32( 1086 (const uint8_t *)&rom->client_monitors_config, 1087 sizeof(rom->client_monitors_config)); 1088 trace_qxl_client_monitors_config_crc(qxl->id, 1089 sizeof(rom->client_monitors_config), 1090 rom->client_monitors_config_crc); 1091 1092 trace_qxl_interrupt_client_monitors_config(qxl->id, 1093 rom->client_monitors_config.count, 1094 rom->client_monitors_config.heads); 1095 if (config_changed) { 1096 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1097 } 1098 return 1; 1099 } 1100 1101 static const QXLInterface qxl_interface = { 1102 .base.type = SPICE_INTERFACE_QXL, 1103 .base.description = "qxl gpu", 1104 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1105 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1106 1107 .attache_worker = interface_attach_worker, 1108 .set_compression_level = interface_set_compression_level, 1109 #if SPICE_NEEDS_SET_MM_TIME 1110 .set_mm_time = interface_set_mm_time, 1111 #endif 1112 .get_init_info = interface_get_init_info, 1113 1114 /* the callbacks below are called from spice server thread context */ 1115 .get_command = interface_get_command, 1116 .req_cmd_notification = interface_req_cmd_notification, 1117 .release_resource = interface_release_resource, 1118 .get_cursor_command = interface_get_cursor_command, 1119 .req_cursor_notification = interface_req_cursor_notification, 1120 .notify_update = interface_notify_update, 1121 .flush_resources = interface_flush_resources, 1122 .async_complete = interface_async_complete, 1123 .update_area_complete = interface_update_area_complete, 1124 .set_client_capabilities = interface_set_client_capabilities, 1125 .client_monitors_config = interface_client_monitors_config, 1126 }; 1127 1128 static const GraphicHwOps qxl_ops = { 1129 .gfx_update = qxl_hw_update, 1130 }; 1131 1132 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1133 { 1134 if (d->mode == QXL_MODE_VGA) { 1135 return; 1136 } 1137 trace_qxl_enter_vga_mode(d->id); 1138 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ 1139 spice_qxl_driver_unload(&d->ssd.qxl); 1140 #endif 1141 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); 1142 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); 1143 qemu_spice_create_host_primary(&d->ssd); 1144 d->mode = QXL_MODE_VGA; 1145 vga_dirty_log_start(&d->vga); 1146 graphic_hw_update(d->vga.con); 1147 } 1148 1149 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1150 { 1151 if (d->mode != QXL_MODE_VGA) { 1152 return; 1153 } 1154 trace_qxl_exit_vga_mode(d->id); 1155 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); 1156 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1157 vga_dirty_log_stop(&d->vga); 1158 qxl_destroy_primary(d, QXL_SYNC); 1159 } 1160 1161 static void qxl_update_irq(PCIQXLDevice *d) 1162 { 1163 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1164 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1165 int level = !!(pending & mask); 1166 pci_set_irq(&d->pci, level); 1167 qxl_ring_set_dirty(d); 1168 } 1169 1170 static void qxl_check_state(PCIQXLDevice *d) 1171 { 1172 QXLRam *ram = d->ram; 1173 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1174 1175 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1176 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1177 } 1178 1179 static void qxl_reset_state(PCIQXLDevice *d) 1180 { 1181 QXLRom *rom = d->rom; 1182 1183 qxl_check_state(d); 1184 d->shadow_rom.update_id = cpu_to_le32(0); 1185 *rom = d->shadow_rom; 1186 qxl_rom_set_dirty(d); 1187 init_qxl_ram(d); 1188 d->num_free_res = 0; 1189 d->last_release = NULL; 1190 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1191 qxl_update_irq(d); 1192 } 1193 1194 static void qxl_soft_reset(PCIQXLDevice *d) 1195 { 1196 trace_qxl_soft_reset(d->id); 1197 qxl_check_state(d); 1198 qxl_clear_guest_bug(d); 1199 qemu_mutex_lock(&d->async_lock); 1200 d->current_async = QXL_UNDEFINED_IO; 1201 qemu_mutex_unlock(&d->async_lock); 1202 1203 if (d->id == 0) { 1204 qxl_enter_vga_mode(d); 1205 } else { 1206 d->mode = QXL_MODE_UNDEFINED; 1207 } 1208 } 1209 1210 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1211 { 1212 bool startstop = qemu_spice_display_is_running(&d->ssd); 1213 1214 trace_qxl_hard_reset(d->id, loadvm); 1215 1216 if (startstop) { 1217 qemu_spice_display_stop(); 1218 } 1219 1220 qxl_spice_reset_cursor(d); 1221 qxl_spice_reset_image_cache(d); 1222 qxl_reset_surfaces(d); 1223 qxl_reset_memslots(d); 1224 1225 /* pre loadvm reset must not touch QXLRam. This lives in 1226 * device memory, is migrated together with RAM and thus 1227 * already loaded at this point */ 1228 if (!loadvm) { 1229 qxl_reset_state(d); 1230 } 1231 qemu_spice_create_host_memslot(&d->ssd); 1232 qxl_soft_reset(d); 1233 1234 if (startstop) { 1235 qemu_spice_display_start(); 1236 } 1237 } 1238 1239 static void qxl_reset_handler(DeviceState *dev) 1240 { 1241 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev)); 1242 1243 qxl_hard_reset(d, 0); 1244 } 1245 1246 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1247 { 1248 VGACommonState *vga = opaque; 1249 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1250 1251 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1252 if (qxl->mode != QXL_MODE_VGA) { 1253 qxl_destroy_primary(qxl, QXL_SYNC); 1254 qxl_soft_reset(qxl); 1255 } 1256 vga_ioport_write(opaque, addr, val); 1257 } 1258 1259 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1260 { 0x04, 2, 1, .read = vga_ioport_read, 1261 .write = qxl_vga_ioport_write }, /* 3b4 */ 1262 { 0x0a, 1, 1, .read = vga_ioport_read, 1263 .write = qxl_vga_ioport_write }, /* 3ba */ 1264 { 0x10, 16, 1, .read = vga_ioport_read, 1265 .write = qxl_vga_ioport_write }, /* 3c0 */ 1266 { 0x24, 2, 1, .read = vga_ioport_read, 1267 .write = qxl_vga_ioport_write }, /* 3d4 */ 1268 { 0x2a, 1, 1, .read = vga_ioport_read, 1269 .write = qxl_vga_ioport_write }, /* 3da */ 1270 PORTIO_END_OF_LIST(), 1271 }; 1272 1273 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1274 qxl_async_io async) 1275 { 1276 static const int regions[] = { 1277 QXL_RAM_RANGE_INDEX, 1278 QXL_VRAM_RANGE_INDEX, 1279 QXL_VRAM64_RANGE_INDEX, 1280 }; 1281 uint64_t guest_start; 1282 uint64_t guest_end; 1283 int pci_region; 1284 pcibus_t pci_start; 1285 pcibus_t pci_end; 1286 MemoryRegion *mr; 1287 intptr_t virt_start; 1288 QXLDevMemSlot memslot; 1289 int i; 1290 1291 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1292 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1293 1294 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1295 1296 if (slot_id >= NUM_MEMSLOTS) { 1297 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1298 slot_id, NUM_MEMSLOTS); 1299 return 1; 1300 } 1301 if (guest_start > guest_end) { 1302 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1303 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1304 return 1; 1305 } 1306 1307 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1308 pci_region = regions[i]; 1309 pci_start = d->pci.io_regions[pci_region].addr; 1310 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1311 /* mapped? */ 1312 if (pci_start == -1) { 1313 continue; 1314 } 1315 /* start address in range ? */ 1316 if (guest_start < pci_start || guest_start > pci_end) { 1317 continue; 1318 } 1319 /* end address in range ? */ 1320 if (guest_end > pci_end) { 1321 continue; 1322 } 1323 /* passed */ 1324 break; 1325 } 1326 if (i == ARRAY_SIZE(regions)) { 1327 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1328 return 1; 1329 } 1330 1331 switch (pci_region) { 1332 case QXL_RAM_RANGE_INDEX: 1333 mr = &d->vga.vram; 1334 break; 1335 case QXL_VRAM_RANGE_INDEX: 1336 case 4 /* vram 64bit */: 1337 mr = &d->vram_bar; 1338 break; 1339 default: 1340 /* should not happen */ 1341 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1342 return 1; 1343 } 1344 1345 virt_start = (intptr_t)memory_region_get_ram_ptr(mr); 1346 memslot.slot_id = slot_id; 1347 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1348 memslot.virt_start = virt_start + (guest_start - pci_start); 1349 memslot.virt_end = virt_start + (guest_end - pci_start); 1350 memslot.addr_delta = memslot.virt_start - delta; 1351 memslot.generation = d->rom->slot_generation = 0; 1352 qxl_rom_set_dirty(d); 1353 1354 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1355 d->guest_slots[slot_id].mr = mr; 1356 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start; 1357 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1358 d->guest_slots[slot_id].delta = delta; 1359 d->guest_slots[slot_id].active = 1; 1360 return 0; 1361 } 1362 1363 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1364 { 1365 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1366 d->guest_slots[slot_id].active = 0; 1367 } 1368 1369 static void qxl_reset_memslots(PCIQXLDevice *d) 1370 { 1371 qxl_spice_reset_memslots(d); 1372 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1373 } 1374 1375 static void qxl_reset_surfaces(PCIQXLDevice *d) 1376 { 1377 trace_qxl_reset_surfaces(d->id); 1378 d->mode = QXL_MODE_UNDEFINED; 1379 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1380 } 1381 1382 /* can be also called from spice server thread context */ 1383 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1384 uint32_t *s, uint64_t *o) 1385 { 1386 uint64_t phys = le64_to_cpu(pqxl); 1387 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1388 uint64_t offset = phys & 0xffffffffffff; 1389 1390 if (slot >= NUM_MEMSLOTS) { 1391 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1392 NUM_MEMSLOTS); 1393 return false; 1394 } 1395 if (!qxl->guest_slots[slot].active) { 1396 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1397 return false; 1398 } 1399 if (offset < qxl->guest_slots[slot].delta) { 1400 qxl_set_guest_bug(qxl, 1401 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1402 slot, offset, qxl->guest_slots[slot].delta); 1403 return false; 1404 } 1405 offset -= qxl->guest_slots[slot].delta; 1406 if (offset > qxl->guest_slots[slot].size) { 1407 qxl_set_guest_bug(qxl, 1408 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1409 slot, offset, qxl->guest_slots[slot].size); 1410 return false; 1411 } 1412 1413 *s = slot; 1414 *o = offset; 1415 return true; 1416 } 1417 1418 /* can be also called from spice server thread context */ 1419 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1420 { 1421 uint64_t offset; 1422 uint32_t slot; 1423 void *ptr; 1424 1425 switch (group_id) { 1426 case MEMSLOT_GROUP_HOST: 1427 offset = le64_to_cpu(pqxl) & 0xffffffffffff; 1428 return (void *)(intptr_t)offset; 1429 case MEMSLOT_GROUP_GUEST: 1430 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) { 1431 return NULL; 1432 } 1433 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr); 1434 ptr += qxl->guest_slots[slot].offset; 1435 ptr += offset; 1436 return ptr; 1437 } 1438 return NULL; 1439 } 1440 1441 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1442 { 1443 /* for local rendering */ 1444 qxl_render_resize(qxl); 1445 } 1446 1447 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1448 qxl_async_io async) 1449 { 1450 QXLDevSurfaceCreate surface; 1451 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1452 uint32_t requested_height = le32_to_cpu(sc->height); 1453 int requested_stride = le32_to_cpu(sc->stride); 1454 1455 if (requested_stride == INT32_MIN || 1456 abs(requested_stride) * (uint64_t)requested_height 1457 > qxl->vgamem_size) { 1458 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1459 " stride %d x height %" PRIu32 " > %" PRIu32, 1460 __func__, requested_stride, requested_height, 1461 qxl->vgamem_size); 1462 return; 1463 } 1464 1465 if (qxl->mode == QXL_MODE_NATIVE) { 1466 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1467 __func__); 1468 } 1469 qxl_exit_vga_mode(qxl); 1470 1471 surface.format = le32_to_cpu(sc->format); 1472 surface.height = le32_to_cpu(sc->height); 1473 surface.mem = le64_to_cpu(sc->mem); 1474 surface.position = le32_to_cpu(sc->position); 1475 surface.stride = le32_to_cpu(sc->stride); 1476 surface.width = le32_to_cpu(sc->width); 1477 surface.type = le32_to_cpu(sc->type); 1478 surface.flags = le32_to_cpu(sc->flags); 1479 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1480 sc->format, sc->position); 1481 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1482 sc->flags); 1483 1484 if ((surface.stride & 0x3) != 0) { 1485 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1486 surface.stride); 1487 return; 1488 } 1489 1490 surface.mouse_mode = true; 1491 surface.group_id = MEMSLOT_GROUP_GUEST; 1492 if (loadvm) { 1493 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1494 } 1495 1496 qxl->mode = QXL_MODE_NATIVE; 1497 qxl->cmdflags = 0; 1498 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1499 1500 if (async == QXL_SYNC) { 1501 qxl_create_guest_primary_complete(qxl); 1502 } 1503 } 1504 1505 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1506 * done (in QXL_SYNC case), 0 otherwise. */ 1507 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1508 { 1509 if (d->mode == QXL_MODE_UNDEFINED) { 1510 return 0; 1511 } 1512 trace_qxl_destroy_primary(d->id); 1513 d->mode = QXL_MODE_UNDEFINED; 1514 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1515 qxl_spice_reset_cursor(d); 1516 return 1; 1517 } 1518 1519 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1520 { 1521 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1522 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1523 QXLMode *mode = d->modes->modes + modenr; 1524 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1525 QXLMemSlot slot = { 1526 .mem_start = start, 1527 .mem_end = end 1528 }; 1529 1530 if (modenr >= d->modes->n_modes) { 1531 qxl_set_guest_bug(d, "mode number out of range"); 1532 return; 1533 } 1534 1535 QXLSurfaceCreate surface = { 1536 .width = mode->x_res, 1537 .height = mode->y_res, 1538 .stride = -mode->x_res * 4, 1539 .format = SPICE_SURFACE_FMT_32_xRGB, 1540 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1541 .mouse_mode = true, 1542 .mem = devmem + d->shadow_rom.draw_area_offset, 1543 }; 1544 1545 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1546 devmem); 1547 if (!loadvm) { 1548 qxl_hard_reset(d, 0); 1549 } 1550 1551 d->guest_slots[0].slot = slot; 1552 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1553 1554 d->guest_primary.surface = surface; 1555 qxl_create_guest_primary(d, 0, QXL_SYNC); 1556 1557 d->mode = QXL_MODE_COMPAT; 1558 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1559 if (mode->bits == 16) { 1560 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1561 } 1562 d->shadow_rom.mode = cpu_to_le32(modenr); 1563 d->rom->mode = cpu_to_le32(modenr); 1564 qxl_rom_set_dirty(d); 1565 } 1566 1567 static void ioport_write(void *opaque, hwaddr addr, 1568 uint64_t val, unsigned size) 1569 { 1570 PCIQXLDevice *d = opaque; 1571 uint32_t io_port = addr; 1572 qxl_async_io async = QXL_SYNC; 1573 uint32_t orig_io_port = io_port; 1574 1575 if (d->guest_bug && io_port != QXL_IO_RESET) { 1576 return; 1577 } 1578 1579 if (d->revision <= QXL_REVISION_STABLE_V10 && 1580 io_port > QXL_IO_FLUSH_RELEASE) { 1581 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1582 io_port, d->revision); 1583 return; 1584 } 1585 1586 switch (io_port) { 1587 case QXL_IO_RESET: 1588 case QXL_IO_SET_MODE: 1589 case QXL_IO_MEMSLOT_ADD: 1590 case QXL_IO_MEMSLOT_DEL: 1591 case QXL_IO_CREATE_PRIMARY: 1592 case QXL_IO_UPDATE_IRQ: 1593 case QXL_IO_LOG: 1594 case QXL_IO_MEMSLOT_ADD_ASYNC: 1595 case QXL_IO_CREATE_PRIMARY_ASYNC: 1596 break; 1597 default: 1598 if (d->mode != QXL_MODE_VGA) { 1599 break; 1600 } 1601 trace_qxl_io_unexpected_vga_mode(d->id, 1602 addr, val, io_port_to_string(io_port)); 1603 /* be nice to buggy guest drivers */ 1604 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1605 io_port < QXL_IO_RANGE_SIZE) { 1606 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1607 } 1608 return; 1609 } 1610 1611 /* we change the io_port to avoid ifdeffery in the main switch */ 1612 orig_io_port = io_port; 1613 switch (io_port) { 1614 case QXL_IO_UPDATE_AREA_ASYNC: 1615 io_port = QXL_IO_UPDATE_AREA; 1616 goto async_common; 1617 case QXL_IO_MEMSLOT_ADD_ASYNC: 1618 io_port = QXL_IO_MEMSLOT_ADD; 1619 goto async_common; 1620 case QXL_IO_CREATE_PRIMARY_ASYNC: 1621 io_port = QXL_IO_CREATE_PRIMARY; 1622 goto async_common; 1623 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1624 io_port = QXL_IO_DESTROY_PRIMARY; 1625 goto async_common; 1626 case QXL_IO_DESTROY_SURFACE_ASYNC: 1627 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1628 goto async_common; 1629 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1630 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1631 goto async_common; 1632 case QXL_IO_FLUSH_SURFACES_ASYNC: 1633 case QXL_IO_MONITORS_CONFIG_ASYNC: 1634 async_common: 1635 async = QXL_ASYNC; 1636 qemu_mutex_lock(&d->async_lock); 1637 if (d->current_async != QXL_UNDEFINED_IO) { 1638 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1639 io_port, d->current_async); 1640 qemu_mutex_unlock(&d->async_lock); 1641 return; 1642 } 1643 d->current_async = orig_io_port; 1644 qemu_mutex_unlock(&d->async_lock); 1645 break; 1646 default: 1647 break; 1648 } 1649 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1650 addr, io_port_to_string(addr), 1651 val, size, async); 1652 1653 switch (io_port) { 1654 case QXL_IO_UPDATE_AREA: 1655 { 1656 QXLCookie *cookie = NULL; 1657 QXLRect update = d->ram->update_area; 1658 1659 if (d->ram->update_surface > d->ssd.num_surfaces) { 1660 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1661 d->ram->update_surface); 1662 break; 1663 } 1664 if (update.left >= update.right || update.top >= update.bottom || 1665 update.left < 0 || update.top < 0) { 1666 qxl_set_guest_bug(d, 1667 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1668 update.left, update.top, update.right, update.bottom); 1669 if (update.left == update.right || update.top == update.bottom) { 1670 /* old drivers may provide empty area, keep going */ 1671 qxl_clear_guest_bug(d); 1672 goto cancel_async; 1673 } 1674 break; 1675 } 1676 if (async == QXL_ASYNC) { 1677 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1678 QXL_IO_UPDATE_AREA_ASYNC); 1679 cookie->u.area = update; 1680 } 1681 qxl_spice_update_area(d, d->ram->update_surface, 1682 cookie ? &cookie->u.area : &update, 1683 NULL, 0, 0, async, cookie); 1684 break; 1685 } 1686 case QXL_IO_NOTIFY_CMD: 1687 qemu_spice_wakeup(&d->ssd); 1688 break; 1689 case QXL_IO_NOTIFY_CURSOR: 1690 qemu_spice_wakeup(&d->ssd); 1691 break; 1692 case QXL_IO_UPDATE_IRQ: 1693 qxl_update_irq(d); 1694 break; 1695 case QXL_IO_NOTIFY_OOM: 1696 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1697 break; 1698 } 1699 d->oom_running = 1; 1700 qxl_spice_oom(d); 1701 d->oom_running = 0; 1702 break; 1703 case QXL_IO_SET_MODE: 1704 qxl_set_mode(d, val, 0); 1705 break; 1706 case QXL_IO_LOG: 1707 trace_qxl_io_log(d->id, d->ram->log_buf); 1708 if (d->guestdebug) { 1709 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1710 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf); 1711 } 1712 break; 1713 case QXL_IO_RESET: 1714 qxl_hard_reset(d, 0); 1715 break; 1716 case QXL_IO_MEMSLOT_ADD: 1717 if (val >= NUM_MEMSLOTS) { 1718 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1719 break; 1720 } 1721 if (d->guest_slots[val].active) { 1722 qxl_set_guest_bug(d, 1723 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1724 break; 1725 } 1726 d->guest_slots[val].slot = d->ram->mem_slot; 1727 qxl_add_memslot(d, val, 0, async); 1728 break; 1729 case QXL_IO_MEMSLOT_DEL: 1730 if (val >= NUM_MEMSLOTS) { 1731 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1732 break; 1733 } 1734 qxl_del_memslot(d, val); 1735 break; 1736 case QXL_IO_CREATE_PRIMARY: 1737 if (val != 0) { 1738 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1739 async); 1740 goto cancel_async; 1741 } 1742 d->guest_primary.surface = d->ram->create_surface; 1743 qxl_create_guest_primary(d, 0, async); 1744 break; 1745 case QXL_IO_DESTROY_PRIMARY: 1746 if (val != 0) { 1747 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1748 async); 1749 goto cancel_async; 1750 } 1751 if (!qxl_destroy_primary(d, async)) { 1752 trace_qxl_io_destroy_primary_ignored(d->id, 1753 qxl_mode_to_string(d->mode)); 1754 goto cancel_async; 1755 } 1756 break; 1757 case QXL_IO_DESTROY_SURFACE_WAIT: 1758 if (val >= d->ssd.num_surfaces) { 1759 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1760 "%" PRIu64 " >= NUM_SURFACES", async, val); 1761 goto cancel_async; 1762 } 1763 qxl_spice_destroy_surface_wait(d, val, async); 1764 break; 1765 case QXL_IO_FLUSH_RELEASE: { 1766 QXLReleaseRing *ring = &d->ram->release_ring; 1767 if (ring->prod - ring->cons + 1 == ring->num_items) { 1768 fprintf(stderr, 1769 "ERROR: no flush, full release ring [p%d,%dc]\n", 1770 ring->prod, ring->cons); 1771 } 1772 qxl_push_free_res(d, 1 /* flush */); 1773 break; 1774 } 1775 case QXL_IO_FLUSH_SURFACES_ASYNC: 1776 qxl_spice_flush_surfaces_async(d); 1777 break; 1778 case QXL_IO_DESTROY_ALL_SURFACES: 1779 d->mode = QXL_MODE_UNDEFINED; 1780 qxl_spice_destroy_surfaces(d, async); 1781 break; 1782 case QXL_IO_MONITORS_CONFIG_ASYNC: 1783 qxl_spice_monitors_config_async(d, 0); 1784 break; 1785 default: 1786 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1787 } 1788 return; 1789 cancel_async: 1790 if (async) { 1791 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1792 qemu_mutex_lock(&d->async_lock); 1793 d->current_async = QXL_UNDEFINED_IO; 1794 qemu_mutex_unlock(&d->async_lock); 1795 } 1796 } 1797 1798 static uint64_t ioport_read(void *opaque, hwaddr addr, 1799 unsigned size) 1800 { 1801 PCIQXLDevice *qxl = opaque; 1802 1803 trace_qxl_io_read_unexpected(qxl->id); 1804 return 0xff; 1805 } 1806 1807 static const MemoryRegionOps qxl_io_ops = { 1808 .read = ioport_read, 1809 .write = ioport_write, 1810 .valid = { 1811 .min_access_size = 1, 1812 .max_access_size = 1, 1813 }, 1814 }; 1815 1816 static void qxl_update_irq_bh(void *opaque) 1817 { 1818 PCIQXLDevice *d = opaque; 1819 qxl_update_irq(d); 1820 } 1821 1822 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1823 { 1824 uint32_t old_pending; 1825 uint32_t le_events = cpu_to_le32(events); 1826 1827 trace_qxl_send_events(d->id, events); 1828 if (!qemu_spice_display_is_running(&d->ssd)) { 1829 /* spice-server tracks guest running state and should not do this */ 1830 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1831 __func__); 1832 trace_qxl_send_events_vm_stopped(d->id, events); 1833 return; 1834 } 1835 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events); 1836 if ((old_pending & le_events) == le_events) { 1837 return; 1838 } 1839 qemu_bh_schedule(d->update_irq); 1840 } 1841 1842 /* graphics console */ 1843 1844 static void qxl_hw_update(void *opaque) 1845 { 1846 PCIQXLDevice *qxl = opaque; 1847 1848 qxl_render_update(qxl); 1849 } 1850 1851 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1852 uint32_t height, int32_t stride) 1853 { 1854 uint64_t offset, size; 1855 uint32_t slot; 1856 bool rc; 1857 1858 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset); 1859 assert(rc == true); 1860 size = (uint64_t)height * abs(stride); 1861 trace_qxl_surfaces_dirty(qxl->id, offset, size); 1862 qxl_set_dirty(qxl->guest_slots[slot].mr, 1863 qxl->guest_slots[slot].offset + offset, 1864 qxl->guest_slots[slot].offset + offset + size); 1865 } 1866 1867 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1868 { 1869 int i; 1870 1871 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1872 return; 1873 } 1874 1875 /* dirty the primary surface */ 1876 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem, 1877 qxl->guest_primary.surface.height, 1878 qxl->guest_primary.surface.stride); 1879 1880 /* dirty the off-screen surfaces */ 1881 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1882 QXLSurfaceCmd *cmd; 1883 1884 if (qxl->guest_surfaces.cmds[i] == 0) { 1885 continue; 1886 } 1887 1888 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1889 MEMSLOT_GROUP_GUEST); 1890 assert(cmd); 1891 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1892 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data, 1893 cmd->u.surface_create.height, 1894 cmd->u.surface_create.stride); 1895 } 1896 } 1897 1898 static void qxl_vm_change_state_handler(void *opaque, int running, 1899 RunState state) 1900 { 1901 PCIQXLDevice *qxl = opaque; 1902 1903 if (running) { 1904 /* 1905 * if qxl_send_events was called from spice server context before 1906 * migration ended, qxl_update_irq for these events might not have been 1907 * called 1908 */ 1909 qxl_update_irq(qxl); 1910 } else { 1911 /* make sure surfaces are saved before migration */ 1912 qxl_dirty_surfaces(qxl); 1913 } 1914 } 1915 1916 /* display change listener */ 1917 1918 static void display_update(DisplayChangeListener *dcl, 1919 int x, int y, int w, int h) 1920 { 1921 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1922 1923 if (qxl->mode == QXL_MODE_VGA) { 1924 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 1925 } 1926 } 1927 1928 static void display_switch(DisplayChangeListener *dcl, 1929 struct DisplaySurface *surface) 1930 { 1931 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1932 1933 qxl->ssd.ds = surface; 1934 if (qxl->mode == QXL_MODE_VGA) { 1935 qemu_spice_display_switch(&qxl->ssd, surface); 1936 } 1937 } 1938 1939 static void display_refresh(DisplayChangeListener *dcl) 1940 { 1941 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1942 1943 if (qxl->mode == QXL_MODE_VGA) { 1944 qemu_spice_display_refresh(&qxl->ssd); 1945 } 1946 } 1947 1948 static DisplayChangeListenerOps display_listener_ops = { 1949 .dpy_name = "spice/qxl", 1950 .dpy_gfx_update = display_update, 1951 .dpy_gfx_switch = display_switch, 1952 .dpy_refresh = display_refresh, 1953 }; 1954 1955 static void qxl_init_ramsize(PCIQXLDevice *qxl) 1956 { 1957 /* vga mode framebuffer / primary surface (bar 0, first part) */ 1958 if (qxl->vgamem_size_mb < 8) { 1959 qxl->vgamem_size_mb = 8; 1960 } 1961 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be 1962 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now). 1963 */ 1964 if (qxl->vgamem_size_mb > 256) { 1965 qxl->vgamem_size_mb = 256; 1966 } 1967 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; 1968 1969 /* vga ram (bar 0, total) */ 1970 if (qxl->ram_size_mb != -1) { 1971 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; 1972 } 1973 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 1974 qxl->vga.vram_size = qxl->vgamem_size * 2; 1975 } 1976 1977 /* vram32 (surfaces, 32bit, bar 1) */ 1978 if (qxl->vram32_size_mb != -1) { 1979 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; 1980 } 1981 if (qxl->vram32_size < 4096) { 1982 qxl->vram32_size = 4096; 1983 } 1984 1985 /* vram (surfaces, 64bit, bar 4+5) */ 1986 if (qxl->vram_size_mb != -1) { 1987 qxl->vram_size = (uint64_t)qxl->vram_size_mb * 1024 * 1024; 1988 } 1989 if (qxl->vram_size < qxl->vram32_size) { 1990 qxl->vram_size = qxl->vram32_size; 1991 } 1992 1993 if (qxl->revision == 1) { 1994 qxl->vram32_size = 4096; 1995 qxl->vram_size = 4096; 1996 } 1997 qxl->vgamem_size = pow2ceil(qxl->vgamem_size); 1998 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size); 1999 qxl->vram32_size = pow2ceil(qxl->vram32_size); 2000 qxl->vram_size = pow2ceil(qxl->vram_size); 2001 } 2002 2003 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) 2004 { 2005 uint8_t* config = qxl->pci.config; 2006 uint32_t pci_device_rev; 2007 uint32_t io_size; 2008 2009 qxl->mode = QXL_MODE_UNDEFINED; 2010 qxl->generation = 1; 2011 qxl->num_memslots = NUM_MEMSLOTS; 2012 qemu_mutex_init(&qxl->track_lock); 2013 qemu_mutex_init(&qxl->async_lock); 2014 qxl->current_async = QXL_UNDEFINED_IO; 2015 qxl->guest_bug = 0; 2016 2017 switch (qxl->revision) { 2018 case 1: /* spice 0.4 -- qxl-1 */ 2019 pci_device_rev = QXL_REVISION_STABLE_V04; 2020 io_size = 8; 2021 break; 2022 case 2: /* spice 0.6 -- qxl-2 */ 2023 pci_device_rev = QXL_REVISION_STABLE_V06; 2024 io_size = 16; 2025 break; 2026 case 3: /* qxl-3 */ 2027 pci_device_rev = QXL_REVISION_STABLE_V10; 2028 io_size = 32; /* PCI region size must be pow2 */ 2029 break; 2030 case 4: /* qxl-4 */ 2031 pci_device_rev = QXL_REVISION_STABLE_V12; 2032 io_size = pow2ceil(QXL_IO_RANGE_SIZE); 2033 break; 2034 default: 2035 error_setg(errp, "Invalid revision %d for qxl device (max %d)", 2036 qxl->revision, QXL_DEFAULT_REVISION); 2037 return; 2038 } 2039 2040 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 2041 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 2042 2043 qxl->rom_size = qxl_rom_size(); 2044 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 2045 qxl->rom_size, &error_fatal); 2046 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); 2047 init_qxl_rom(qxl); 2048 init_qxl_ram(qxl); 2049 2050 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 2051 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 2052 qxl->vram_size, &error_fatal); 2053 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); 2054 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 2055 &qxl->vram_bar, 0, qxl->vram32_size); 2056 2057 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 2058 "qxl-ioports", io_size); 2059 if (qxl->id == 0) { 2060 vga_dirty_log_start(&qxl->vga); 2061 } 2062 memory_region_set_flush_coalesced(&qxl->io_bar); 2063 2064 2065 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2066 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2067 2068 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2069 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2070 2071 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2072 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2073 2074 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2075 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2076 2077 if (qxl->vram32_size < qxl->vram_size) { 2078 /* 2079 * Make the 64bit vram bar show up only in case it is 2080 * configured to be larger than the 32bit vram bar. 2081 */ 2082 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2083 PCI_BASE_ADDRESS_SPACE_MEMORY | 2084 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2085 PCI_BASE_ADDRESS_MEM_PREFETCH, 2086 &qxl->vram_bar); 2087 } 2088 2089 /* print pci bar details */ 2090 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", 2091 qxl->id == 0 ? "pri" : "sec", 2092 qxl->vga.vram_size / (1024*1024)); 2093 dprint(qxl, 1, "vram/32: %" PRIx64 "d MB [region 1]\n", 2094 qxl->vram32_size / (1024*1024)); 2095 dprint(qxl, 1, "vram/64: %" PRIx64 "d MB %s\n", 2096 qxl->vram_size / (1024*1024), 2097 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2098 2099 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2100 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2101 error_setg(errp, "qxl interface %d.%d not supported by spice-server", 2102 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2103 return; 2104 } 2105 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2106 2107 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2108 qxl_reset_state(qxl); 2109 2110 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2111 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd); 2112 } 2113 2114 static void qxl_realize_primary(PCIDevice *dev, Error **errp) 2115 { 2116 PCIQXLDevice *qxl = PCI_QXL(dev); 2117 VGACommonState *vga = &qxl->vga; 2118 Error *local_err = NULL; 2119 2120 qxl->id = 0; 2121 qxl_init_ramsize(qxl); 2122 vga->vbe_size = qxl->vgamem_size; 2123 vga->vram_size_mb = qxl->vga.vram_size >> 20; 2124 vga_common_init(vga, OBJECT(dev), true); 2125 vga_init(vga, OBJECT(dev), 2126 pci_address_space(dev), pci_address_space_io(dev), false); 2127 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2128 vga, "vga"); 2129 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2130 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2131 2132 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2133 qemu_spice_display_init_common(&qxl->ssd); 2134 2135 qxl_realize_common(qxl, &local_err); 2136 if (local_err) { 2137 error_propagate(errp, local_err); 2138 return; 2139 } 2140 2141 qxl->ssd.dcl.ops = &display_listener_ops; 2142 qxl->ssd.dcl.con = vga->con; 2143 register_displaychangelistener(&qxl->ssd.dcl); 2144 } 2145 2146 static void qxl_realize_secondary(PCIDevice *dev, Error **errp) 2147 { 2148 static int device_id = 1; 2149 PCIQXLDevice *qxl = PCI_QXL(dev); 2150 2151 qxl->id = device_id++; 2152 qxl_init_ramsize(qxl); 2153 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2154 qxl->vga.vram_size, &error_fatal); 2155 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); 2156 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2157 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2158 2159 qxl_realize_common(qxl, errp); 2160 } 2161 2162 static void qxl_pre_save(void *opaque) 2163 { 2164 PCIQXLDevice* d = opaque; 2165 uint8_t *ram_start = d->vga.vram_ptr; 2166 2167 trace_qxl_pre_save(d->id); 2168 if (d->last_release == NULL) { 2169 d->last_release_offset = 0; 2170 } else { 2171 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2172 } 2173 assert(d->last_release_offset < d->vga.vram_size); 2174 } 2175 2176 static int qxl_pre_load(void *opaque) 2177 { 2178 PCIQXLDevice* d = opaque; 2179 2180 trace_qxl_pre_load(d->id); 2181 qxl_hard_reset(d, 1); 2182 qxl_exit_vga_mode(d); 2183 return 0; 2184 } 2185 2186 static void qxl_create_memslots(PCIQXLDevice *d) 2187 { 2188 int i; 2189 2190 for (i = 0; i < NUM_MEMSLOTS; i++) { 2191 if (!d->guest_slots[i].active) { 2192 continue; 2193 } 2194 qxl_add_memslot(d, i, 0, QXL_SYNC); 2195 } 2196 } 2197 2198 static int qxl_post_load(void *opaque, int version) 2199 { 2200 PCIQXLDevice* d = opaque; 2201 uint8_t *ram_start = d->vga.vram_ptr; 2202 QXLCommandExt *cmds; 2203 int in, out, newmode; 2204 2205 assert(d->last_release_offset < d->vga.vram_size); 2206 if (d->last_release_offset == 0) { 2207 d->last_release = NULL; 2208 } else { 2209 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2210 } 2211 2212 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2213 2214 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2215 newmode = d->mode; 2216 d->mode = QXL_MODE_UNDEFINED; 2217 2218 switch (newmode) { 2219 case QXL_MODE_UNDEFINED: 2220 qxl_create_memslots(d); 2221 break; 2222 case QXL_MODE_VGA: 2223 qxl_create_memslots(d); 2224 qxl_enter_vga_mode(d); 2225 break; 2226 case QXL_MODE_NATIVE: 2227 qxl_create_memslots(d); 2228 qxl_create_guest_primary(d, 1, QXL_SYNC); 2229 2230 /* replay surface-create and cursor-set commands */ 2231 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1); 2232 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2233 if (d->guest_surfaces.cmds[in] == 0) { 2234 continue; 2235 } 2236 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2237 cmds[out].cmd.type = QXL_CMD_SURFACE; 2238 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2239 out++; 2240 } 2241 if (d->guest_cursor) { 2242 cmds[out].cmd.data = d->guest_cursor; 2243 cmds[out].cmd.type = QXL_CMD_CURSOR; 2244 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2245 out++; 2246 } 2247 qxl_spice_loadvm_commands(d, cmds, out); 2248 g_free(cmds); 2249 if (d->guest_monitors_config) { 2250 qxl_spice_monitors_config_async(d, 1); 2251 } 2252 break; 2253 case QXL_MODE_COMPAT: 2254 /* note: no need to call qxl_create_memslots, qxl_set_mode 2255 * creates the mem slot. */ 2256 qxl_set_mode(d, d->shadow_rom.mode, 1); 2257 break; 2258 } 2259 return 0; 2260 } 2261 2262 #define QXL_SAVE_VERSION 21 2263 2264 static bool qxl_monitors_config_needed(void *opaque) 2265 { 2266 PCIQXLDevice *qxl = opaque; 2267 2268 return qxl->guest_monitors_config != 0; 2269 } 2270 2271 2272 static VMStateDescription qxl_memslot = { 2273 .name = "qxl-memslot", 2274 .version_id = QXL_SAVE_VERSION, 2275 .minimum_version_id = QXL_SAVE_VERSION, 2276 .fields = (VMStateField[]) { 2277 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2278 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2279 VMSTATE_UINT32(active, struct guest_slots), 2280 VMSTATE_END_OF_LIST() 2281 } 2282 }; 2283 2284 static VMStateDescription qxl_surface = { 2285 .name = "qxl-surface", 2286 .version_id = QXL_SAVE_VERSION, 2287 .minimum_version_id = QXL_SAVE_VERSION, 2288 .fields = (VMStateField[]) { 2289 VMSTATE_UINT32(width, QXLSurfaceCreate), 2290 VMSTATE_UINT32(height, QXLSurfaceCreate), 2291 VMSTATE_INT32(stride, QXLSurfaceCreate), 2292 VMSTATE_UINT32(format, QXLSurfaceCreate), 2293 VMSTATE_UINT32(position, QXLSurfaceCreate), 2294 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2295 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2296 VMSTATE_UINT32(type, QXLSurfaceCreate), 2297 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2298 VMSTATE_END_OF_LIST() 2299 } 2300 }; 2301 2302 static VMStateDescription qxl_vmstate_monitors_config = { 2303 .name = "qxl/monitors-config", 2304 .version_id = 1, 2305 .minimum_version_id = 1, 2306 .needed = qxl_monitors_config_needed, 2307 .fields = (VMStateField[]) { 2308 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2309 VMSTATE_END_OF_LIST() 2310 }, 2311 }; 2312 2313 static VMStateDescription qxl_vmstate = { 2314 .name = "qxl", 2315 .version_id = QXL_SAVE_VERSION, 2316 .minimum_version_id = QXL_SAVE_VERSION, 2317 .pre_save = qxl_pre_save, 2318 .pre_load = qxl_pre_load, 2319 .post_load = qxl_post_load, 2320 .fields = (VMStateField[]) { 2321 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2322 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2323 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2324 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2325 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2326 VMSTATE_UINT32(mode, PCIQXLDevice), 2327 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2328 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), 2329 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2330 qxl_memslot, struct guest_slots), 2331 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2332 qxl_surface, QXLSurfaceCreate), 2333 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), 2334 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2335 ssd.num_surfaces, 0, 2336 vmstate_info_uint64, uint64_t), 2337 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2338 VMSTATE_END_OF_LIST() 2339 }, 2340 .subsections = (const VMStateDescription*[]) { 2341 &qxl_vmstate_monitors_config, 2342 NULL 2343 } 2344 }; 2345 2346 static Property qxl_properties[] = { 2347 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 2348 64 * 1024 * 1024), 2349 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 2350 64 * 1024 * 1024), 2351 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2352 QXL_DEFAULT_REVISION), 2353 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2354 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2355 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2356 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2357 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2358 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2359 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2360 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2361 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 2362 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0), 2363 #endif 2364 DEFINE_PROP_END_OF_LIST(), 2365 }; 2366 2367 static void qxl_pci_class_init(ObjectClass *klass, void *data) 2368 { 2369 DeviceClass *dc = DEVICE_CLASS(klass); 2370 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2371 2372 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2373 k->device_id = QXL_DEVICE_ID_STABLE; 2374 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2375 dc->reset = qxl_reset_handler; 2376 dc->vmsd = &qxl_vmstate; 2377 dc->props = qxl_properties; 2378 } 2379 2380 static const TypeInfo qxl_pci_type_info = { 2381 .name = TYPE_PCI_QXL, 2382 .parent = TYPE_PCI_DEVICE, 2383 .instance_size = sizeof(PCIQXLDevice), 2384 .abstract = true, 2385 .class_init = qxl_pci_class_init, 2386 }; 2387 2388 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2389 { 2390 DeviceClass *dc = DEVICE_CLASS(klass); 2391 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2392 2393 k->realize = qxl_realize_primary; 2394 k->romfile = "vgabios-qxl.bin"; 2395 k->class_id = PCI_CLASS_DISPLAY_VGA; 2396 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2397 dc->hotpluggable = false; 2398 } 2399 2400 static const TypeInfo qxl_primary_info = { 2401 .name = "qxl-vga", 2402 .parent = TYPE_PCI_QXL, 2403 .class_init = qxl_primary_class_init, 2404 }; 2405 2406 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2407 { 2408 DeviceClass *dc = DEVICE_CLASS(klass); 2409 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2410 2411 k->realize = qxl_realize_secondary; 2412 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2413 dc->desc = "Spice QXL GPU (secondary)"; 2414 } 2415 2416 static const TypeInfo qxl_secondary_info = { 2417 .name = "qxl", 2418 .parent = TYPE_PCI_QXL, 2419 .class_init = qxl_secondary_class_init, 2420 }; 2421 2422 static void qxl_register_types(void) 2423 { 2424 type_register_static(&qxl_pci_type_info); 2425 type_register_static(&qxl_primary_info); 2426 type_register_static(&qxl_secondary_info); 2427 } 2428 2429 type_init(qxl_register_types) 2430