1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <zlib.h> 22 #include <stdint.h> 23 24 #include "qemu-common.h" 25 #include "qemu/timer.h" 26 #include "qemu/queue.h" 27 #include "qemu/atomic.h" 28 #include "monitor/monitor.h" 29 #include "sysemu/sysemu.h" 30 #include "trace.h" 31 32 #include "qxl.h" 33 34 /* 35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as 36 * such can be changed by the guest, so to avoid a guest trigerrable 37 * abort we just qxl_set_guest_bug and set the return to NULL. Still 38 * it may happen as a result of emulator bug as well. 39 */ 40 #undef SPICE_RING_PROD_ITEM 41 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ 42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ 43 if (prod >= ARRAY_SIZE((r)->items)) { \ 44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ 45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \ 46 ret = NULL; \ 47 } else { \ 48 ret = &(r)->items[prod].el; \ 49 } \ 50 } 51 52 #undef SPICE_RING_CONS_ITEM 53 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 55 if (cons >= ARRAY_SIZE((r)->items)) { \ 56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 58 ret = NULL; \ 59 } else { \ 60 ret = &(r)->items[cons].el; \ 61 } \ 62 } 63 64 #undef ALIGN 65 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 66 67 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 68 69 #define QXL_MODE(_x, _y, _b, _o) \ 70 { .x_res = _x, \ 71 .y_res = _y, \ 72 .bits = _b, \ 73 .stride = (_x) * (_b) / 8, \ 74 .x_mili = PIXEL_SIZE * (_x), \ 75 .y_mili = PIXEL_SIZE * (_y), \ 76 .orientation = _o, \ 77 } 78 79 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 80 QXL_MODE(x_res, y_res, 16, orientation), \ 81 QXL_MODE(x_res, y_res, 32, orientation) 82 83 #define QXL_MODE_EX(x_res, y_res) \ 84 QXL_MODE_16_32(x_res, y_res, 0), \ 85 QXL_MODE_16_32(x_res, y_res, 1) 86 87 static QXLMode qxl_modes[] = { 88 QXL_MODE_EX(640, 480), 89 QXL_MODE_EX(800, 480), 90 QXL_MODE_EX(800, 600), 91 QXL_MODE_EX(832, 624), 92 QXL_MODE_EX(960, 640), 93 QXL_MODE_EX(1024, 600), 94 QXL_MODE_EX(1024, 768), 95 QXL_MODE_EX(1152, 864), 96 QXL_MODE_EX(1152, 870), 97 QXL_MODE_EX(1280, 720), 98 QXL_MODE_EX(1280, 760), 99 QXL_MODE_EX(1280, 768), 100 QXL_MODE_EX(1280, 800), 101 QXL_MODE_EX(1280, 960), 102 QXL_MODE_EX(1280, 1024), 103 QXL_MODE_EX(1360, 768), 104 QXL_MODE_EX(1366, 768), 105 QXL_MODE_EX(1400, 1050), 106 QXL_MODE_EX(1440, 900), 107 QXL_MODE_EX(1600, 900), 108 QXL_MODE_EX(1600, 1200), 109 QXL_MODE_EX(1680, 1050), 110 QXL_MODE_EX(1920, 1080), 111 /* these modes need more than 8 MB video memory */ 112 QXL_MODE_EX(1920, 1200), 113 QXL_MODE_EX(1920, 1440), 114 QXL_MODE_EX(2000, 2000), 115 QXL_MODE_EX(2048, 1536), 116 QXL_MODE_EX(2048, 2048), 117 QXL_MODE_EX(2560, 1440), 118 QXL_MODE_EX(2560, 1600), 119 /* these modes need more than 16 MB video memory */ 120 QXL_MODE_EX(2560, 2048), 121 QXL_MODE_EX(2800, 2100), 122 QXL_MODE_EX(3200, 2400), 123 /* these modes need more than 32 MB video memory */ 124 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 125 QXL_MODE_EX(4096, 2160), /* 4k */ 126 /* these modes need more than 64 MB video memory */ 127 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 128 /* these modes need more than 128 MB video memory */ 129 QXL_MODE_EX(8192, 4320), /* 8k */ 130 }; 131 132 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 133 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 134 static void qxl_reset_memslots(PCIQXLDevice *d); 135 static void qxl_reset_surfaces(PCIQXLDevice *d); 136 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 137 138 static void qxl_hw_update(void *opaque); 139 140 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 141 { 142 trace_qxl_set_guest_bug(qxl->id); 143 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 144 qxl->guest_bug = 1; 145 if (qxl->guestdebug) { 146 va_list ap; 147 va_start(ap, msg); 148 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 149 vfprintf(stderr, msg, ap); 150 fprintf(stderr, "\n"); 151 va_end(ap); 152 } 153 } 154 155 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 156 { 157 qxl->guest_bug = 0; 158 } 159 160 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 161 struct QXLRect *area, struct QXLRect *dirty_rects, 162 uint32_t num_dirty_rects, 163 uint32_t clear_dirty_region, 164 qxl_async_io async, struct QXLCookie *cookie) 165 { 166 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 167 area->top, area->bottom); 168 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 169 clear_dirty_region); 170 if (async == QXL_SYNC) { 171 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 172 dirty_rects, num_dirty_rects, clear_dirty_region); 173 } else { 174 assert(cookie != NULL); 175 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 176 clear_dirty_region, (uintptr_t)cookie); 177 } 178 } 179 180 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 181 uint32_t id) 182 { 183 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 184 qemu_mutex_lock(&qxl->track_lock); 185 qxl->guest_surfaces.cmds[id] = 0; 186 qxl->guest_surfaces.count--; 187 qemu_mutex_unlock(&qxl->track_lock); 188 } 189 190 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 191 qxl_async_io async) 192 { 193 QXLCookie *cookie; 194 195 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 196 if (async) { 197 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 198 QXL_IO_DESTROY_SURFACE_ASYNC); 199 cookie->u.surface_id = id; 200 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 201 } else { 202 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 203 qxl_spice_destroy_surface_wait_complete(qxl, id); 204 } 205 } 206 207 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 208 { 209 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 210 qxl->num_free_res); 211 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 212 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 213 QXL_IO_FLUSH_SURFACES_ASYNC)); 214 } 215 216 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 217 uint32_t count) 218 { 219 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 220 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 221 } 222 223 void qxl_spice_oom(PCIQXLDevice *qxl) 224 { 225 trace_qxl_spice_oom(qxl->id); 226 spice_qxl_oom(&qxl->ssd.qxl); 227 } 228 229 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 230 { 231 trace_qxl_spice_reset_memslots(qxl->id); 232 spice_qxl_reset_memslots(&qxl->ssd.qxl); 233 } 234 235 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 236 { 237 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 238 qemu_mutex_lock(&qxl->track_lock); 239 memset(qxl->guest_surfaces.cmds, 0, 240 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 241 qxl->guest_surfaces.count = 0; 242 qemu_mutex_unlock(&qxl->track_lock); 243 } 244 245 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 246 { 247 trace_qxl_spice_destroy_surfaces(qxl->id, async); 248 if (async) { 249 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 250 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 251 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 252 } else { 253 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 254 qxl_spice_destroy_surfaces_complete(qxl); 255 } 256 } 257 258 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 259 { 260 trace_qxl_spice_monitors_config(qxl->id); 261 if (replay) { 262 /* 263 * don't use QXL_COOKIE_TYPE_IO: 264 * - we are not running yet (post_load), we will assert 265 * in send_events 266 * - this is not a guest io, but a reply, so async_io isn't set. 267 */ 268 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 269 qxl->guest_monitors_config, 270 MEMSLOT_GROUP_GUEST, 271 (uintptr_t)qxl_cookie_new( 272 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 273 0)); 274 } else { 275 qxl->guest_monitors_config = qxl->ram->monitors_config; 276 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 277 qxl->ram->monitors_config, 278 MEMSLOT_GROUP_GUEST, 279 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 280 QXL_IO_MONITORS_CONFIG_ASYNC)); 281 } 282 } 283 284 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 285 { 286 trace_qxl_spice_reset_image_cache(qxl->id); 287 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 288 } 289 290 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 291 { 292 trace_qxl_spice_reset_cursor(qxl->id); 293 spice_qxl_reset_cursor(&qxl->ssd.qxl); 294 qemu_mutex_lock(&qxl->track_lock); 295 qxl->guest_cursor = 0; 296 qemu_mutex_unlock(&qxl->track_lock); 297 if (qxl->ssd.cursor) { 298 cursor_put(qxl->ssd.cursor); 299 } 300 qxl->ssd.cursor = cursor_builtin_hidden(); 301 } 302 303 static ram_addr_t qxl_rom_size(void) 304 { 305 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) + 306 sizeof(qxl_modes); 307 uint32_t rom_size = 8192; /* two pages */ 308 309 QEMU_BUILD_BUG_ON(required_rom_size > rom_size); 310 return rom_size; 311 } 312 313 static void init_qxl_rom(PCIQXLDevice *d) 314 { 315 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 316 QXLModes *modes = (QXLModes *)(rom + 1); 317 uint32_t ram_header_size; 318 uint32_t surface0_area_size; 319 uint32_t num_pages; 320 uint32_t fb; 321 int i, n; 322 323 memset(rom, 0, d->rom_size); 324 325 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 326 rom->id = cpu_to_le32(d->id); 327 rom->log_level = cpu_to_le32(d->guestdebug); 328 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 329 330 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 331 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 332 rom->slots_start = 1; 333 rom->slots_end = NUM_MEMSLOTS - 1; 334 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 335 336 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 337 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 338 if (fb > d->vgamem_size) { 339 continue; 340 } 341 modes->modes[n].id = cpu_to_le32(i); 342 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 343 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 344 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 345 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 346 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 347 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 348 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 349 n++; 350 } 351 modes->n_modes = cpu_to_le32(n); 352 353 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 354 surface0_area_size = ALIGN(d->vgamem_size, 4096); 355 num_pages = d->vga.vram_size; 356 num_pages -= ram_header_size; 357 num_pages -= surface0_area_size; 358 num_pages = num_pages / QXL_PAGE_SIZE; 359 360 assert(ram_header_size + surface0_area_size <= d->vga.vram_size); 361 362 rom->draw_area_offset = cpu_to_le32(0); 363 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 364 rom->pages_offset = cpu_to_le32(surface0_area_size); 365 rom->num_pages = cpu_to_le32(num_pages); 366 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 367 368 d->shadow_rom = *rom; 369 d->rom = rom; 370 d->modes = modes; 371 } 372 373 static void init_qxl_ram(PCIQXLDevice *d) 374 { 375 uint8_t *buf; 376 uint64_t *item; 377 378 buf = d->vga.vram_ptr; 379 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 380 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 381 d->ram->int_pending = cpu_to_le32(0); 382 d->ram->int_mask = cpu_to_le32(0); 383 d->ram->update_surface = 0; 384 d->ram->monitors_config = 0; 385 SPICE_RING_INIT(&d->ram->cmd_ring); 386 SPICE_RING_INIT(&d->ram->cursor_ring); 387 SPICE_RING_INIT(&d->ram->release_ring); 388 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); 389 assert(item); 390 *item = 0; 391 qxl_ring_set_dirty(d); 392 } 393 394 /* can be called from spice server thread context */ 395 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 396 { 397 memory_region_set_dirty(mr, addr, end - addr); 398 } 399 400 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 401 { 402 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 403 } 404 405 /* called from spice server thread context only */ 406 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 407 { 408 void *base = qxl->vga.vram_ptr; 409 intptr_t offset; 410 411 offset = ptr - base; 412 assert(offset < qxl->vga.vram_size); 413 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 414 } 415 416 /* can be called from spice server thread context */ 417 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 418 { 419 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 420 ram_addr_t end = qxl->vga.vram_size; 421 qxl_set_dirty(&qxl->vga.vram, addr, end); 422 } 423 424 /* 425 * keep track of some command state, for savevm/loadvm. 426 * called from spice server thread context only 427 */ 428 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 429 { 430 switch (le32_to_cpu(ext->cmd.type)) { 431 case QXL_CMD_SURFACE: 432 { 433 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 434 435 if (!cmd) { 436 return 1; 437 } 438 uint32_t id = le32_to_cpu(cmd->surface_id); 439 440 if (id >= qxl->ssd.num_surfaces) { 441 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 442 qxl->ssd.num_surfaces); 443 return 1; 444 } 445 if (cmd->type == QXL_SURFACE_CMD_CREATE && 446 (cmd->u.surface_create.stride & 0x03) != 0) { 447 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 448 cmd->u.surface_create.stride); 449 return 1; 450 } 451 qemu_mutex_lock(&qxl->track_lock); 452 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 453 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 454 qxl->guest_surfaces.count++; 455 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 456 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 457 } 458 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 459 qxl->guest_surfaces.cmds[id] = 0; 460 qxl->guest_surfaces.count--; 461 } 462 qemu_mutex_unlock(&qxl->track_lock); 463 break; 464 } 465 case QXL_CMD_CURSOR: 466 { 467 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 468 469 if (!cmd) { 470 return 1; 471 } 472 if (cmd->type == QXL_CURSOR_SET) { 473 qemu_mutex_lock(&qxl->track_lock); 474 qxl->guest_cursor = ext->cmd.data; 475 qemu_mutex_unlock(&qxl->track_lock); 476 } 477 break; 478 } 479 } 480 return 0; 481 } 482 483 /* spice display interface callbacks */ 484 485 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 486 { 487 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 488 489 trace_qxl_interface_attach_worker(qxl->id); 490 qxl->ssd.worker = qxl_worker; 491 } 492 493 static void interface_set_compression_level(QXLInstance *sin, int level) 494 { 495 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 496 497 trace_qxl_interface_set_compression_level(qxl->id, level); 498 qxl->shadow_rom.compression_level = cpu_to_le32(level); 499 qxl->rom->compression_level = cpu_to_le32(level); 500 qxl_rom_set_dirty(qxl); 501 } 502 503 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 504 { 505 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 506 507 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 508 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 509 qxl->rom->mm_clock = cpu_to_le32(mm_time); 510 qxl_rom_set_dirty(qxl); 511 } 512 513 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 514 { 515 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 516 517 trace_qxl_interface_get_init_info(qxl->id); 518 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 519 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 520 info->num_memslots = NUM_MEMSLOTS; 521 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 522 info->internal_groupslot_id = 0; 523 info->qxl_ram_size = 524 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 525 info->n_surfaces = qxl->ssd.num_surfaces; 526 } 527 528 static const char *qxl_mode_to_string(int mode) 529 { 530 switch (mode) { 531 case QXL_MODE_COMPAT: 532 return "compat"; 533 case QXL_MODE_NATIVE: 534 return "native"; 535 case QXL_MODE_UNDEFINED: 536 return "undefined"; 537 case QXL_MODE_VGA: 538 return "vga"; 539 } 540 return "INVALID"; 541 } 542 543 static const char *io_port_to_string(uint32_t io_port) 544 { 545 if (io_port >= QXL_IO_RANGE_SIZE) { 546 return "out of range"; 547 } 548 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 549 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 550 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 551 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 552 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 553 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 554 [QXL_IO_RESET] = "QXL_IO_RESET", 555 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 556 [QXL_IO_LOG] = "QXL_IO_LOG", 557 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 558 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 559 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 560 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 561 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 562 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 563 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 564 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 565 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 566 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 567 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 568 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 569 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 570 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 571 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 572 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 573 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 574 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 575 }; 576 return io_port_to_string[io_port]; 577 } 578 579 /* called from spice server thread context only */ 580 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 581 { 582 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 583 SimpleSpiceUpdate *update; 584 QXLCommandRing *ring; 585 QXLCommand *cmd; 586 int notify, ret; 587 588 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 589 590 switch (qxl->mode) { 591 case QXL_MODE_VGA: 592 ret = false; 593 qemu_mutex_lock(&qxl->ssd.lock); 594 update = QTAILQ_FIRST(&qxl->ssd.updates); 595 if (update != NULL) { 596 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 597 *ext = update->ext; 598 ret = true; 599 } 600 qemu_mutex_unlock(&qxl->ssd.lock); 601 if (ret) { 602 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 603 qxl_log_command(qxl, "vga", ext); 604 } 605 return ret; 606 case QXL_MODE_COMPAT: 607 case QXL_MODE_NATIVE: 608 case QXL_MODE_UNDEFINED: 609 ring = &qxl->ram->cmd_ring; 610 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 611 return false; 612 } 613 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 614 if (!cmd) { 615 return false; 616 } 617 ext->cmd = *cmd; 618 ext->group_id = MEMSLOT_GROUP_GUEST; 619 ext->flags = qxl->cmdflags; 620 SPICE_RING_POP(ring, notify); 621 qxl_ring_set_dirty(qxl); 622 if (notify) { 623 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 624 } 625 qxl->guest_primary.commands++; 626 qxl_track_command(qxl, ext); 627 qxl_log_command(qxl, "cmd", ext); 628 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 629 return true; 630 default: 631 return false; 632 } 633 } 634 635 /* called from spice server thread context only */ 636 static int interface_req_cmd_notification(QXLInstance *sin) 637 { 638 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 639 int wait = 1; 640 641 trace_qxl_ring_command_req_notification(qxl->id); 642 switch (qxl->mode) { 643 case QXL_MODE_COMPAT: 644 case QXL_MODE_NATIVE: 645 case QXL_MODE_UNDEFINED: 646 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 647 qxl_ring_set_dirty(qxl); 648 break; 649 default: 650 /* nothing */ 651 break; 652 } 653 return wait; 654 } 655 656 /* called from spice server thread context only */ 657 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 658 { 659 QXLReleaseRing *ring = &d->ram->release_ring; 660 uint64_t *item; 661 int notify; 662 663 #define QXL_FREE_BUNCH_SIZE 32 664 665 if (ring->prod - ring->cons + 1 == ring->num_items) { 666 /* ring full -- can't push */ 667 return; 668 } 669 if (!flush && d->oom_running) { 670 /* collect everything from oom handler before pushing */ 671 return; 672 } 673 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 674 /* collect a bit more before pushing */ 675 return; 676 } 677 678 SPICE_RING_PUSH(ring, notify); 679 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 680 d->guest_surfaces.count, d->num_free_res, 681 d->last_release, notify ? "yes" : "no"); 682 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 683 ring->num_items, ring->prod, ring->cons); 684 if (notify) { 685 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 686 } 687 SPICE_RING_PROD_ITEM(d, ring, item); 688 if (!item) { 689 return; 690 } 691 *item = 0; 692 d->num_free_res = 0; 693 d->last_release = NULL; 694 qxl_ring_set_dirty(d); 695 } 696 697 /* called from spice server thread context only */ 698 static void interface_release_resource(QXLInstance *sin, 699 struct QXLReleaseInfoExt ext) 700 { 701 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 702 QXLReleaseRing *ring; 703 uint64_t *item, id; 704 705 if (ext.group_id == MEMSLOT_GROUP_HOST) { 706 /* host group -> vga mode update request */ 707 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 708 SimpleSpiceUpdate *update; 709 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 710 update = container_of(cmdext, SimpleSpiceUpdate, ext); 711 qemu_spice_destroy_update(&qxl->ssd, update); 712 return; 713 } 714 715 /* 716 * ext->info points into guest-visible memory 717 * pci bar 0, $command.release_info 718 */ 719 ring = &qxl->ram->release_ring; 720 SPICE_RING_PROD_ITEM(qxl, ring, item); 721 if (!item) { 722 return; 723 } 724 if (*item == 0) { 725 /* stick head into the ring */ 726 id = ext.info->id; 727 ext.info->next = 0; 728 qxl_ram_set_dirty(qxl, &ext.info->next); 729 *item = id; 730 qxl_ring_set_dirty(qxl); 731 } else { 732 /* append item to the list */ 733 qxl->last_release->next = ext.info->id; 734 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 735 ext.info->next = 0; 736 qxl_ram_set_dirty(qxl, &ext.info->next); 737 } 738 qxl->last_release = ext.info; 739 qxl->num_free_res++; 740 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 741 qxl_push_free_res(qxl, 0); 742 } 743 744 /* called from spice server thread context only */ 745 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 746 { 747 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 748 QXLCursorRing *ring; 749 QXLCommand *cmd; 750 int notify; 751 752 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 753 754 switch (qxl->mode) { 755 case QXL_MODE_COMPAT: 756 case QXL_MODE_NATIVE: 757 case QXL_MODE_UNDEFINED: 758 ring = &qxl->ram->cursor_ring; 759 if (SPICE_RING_IS_EMPTY(ring)) { 760 return false; 761 } 762 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 763 if (!cmd) { 764 return false; 765 } 766 ext->cmd = *cmd; 767 ext->group_id = MEMSLOT_GROUP_GUEST; 768 ext->flags = qxl->cmdflags; 769 SPICE_RING_POP(ring, notify); 770 qxl_ring_set_dirty(qxl); 771 if (notify) { 772 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 773 } 774 qxl->guest_primary.commands++; 775 qxl_track_command(qxl, ext); 776 qxl_log_command(qxl, "csr", ext); 777 if (qxl->id == 0) { 778 qxl_render_cursor(qxl, ext); 779 } 780 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 781 return true; 782 default: 783 return false; 784 } 785 } 786 787 /* called from spice server thread context only */ 788 static int interface_req_cursor_notification(QXLInstance *sin) 789 { 790 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 791 int wait = 1; 792 793 trace_qxl_ring_cursor_req_notification(qxl->id); 794 switch (qxl->mode) { 795 case QXL_MODE_COMPAT: 796 case QXL_MODE_NATIVE: 797 case QXL_MODE_UNDEFINED: 798 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 799 qxl_ring_set_dirty(qxl); 800 break; 801 default: 802 /* nothing */ 803 break; 804 } 805 return wait; 806 } 807 808 /* called from spice server thread context */ 809 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 810 { 811 /* 812 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 813 * use by xf86-video-qxl and is defined out in the qxl windows driver. 814 * Probably was at some earlier version that is prior to git start (2009), 815 * and is still guest trigerrable. 816 */ 817 fprintf(stderr, "%s: deprecated\n", __func__); 818 } 819 820 /* called from spice server thread context only */ 821 static int interface_flush_resources(QXLInstance *sin) 822 { 823 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 824 int ret; 825 826 ret = qxl->num_free_res; 827 if (ret) { 828 qxl_push_free_res(qxl, 1); 829 } 830 return ret; 831 } 832 833 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 834 835 /* called from spice server thread context only */ 836 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 837 { 838 uint32_t current_async; 839 840 qemu_mutex_lock(&qxl->async_lock); 841 current_async = qxl->current_async; 842 qxl->current_async = QXL_UNDEFINED_IO; 843 qemu_mutex_unlock(&qxl->async_lock); 844 845 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 846 if (!cookie) { 847 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 848 return; 849 } 850 if (cookie && current_async != cookie->io) { 851 fprintf(stderr, 852 "qxl: %s: error: current_async = %d != %" 853 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 854 } 855 switch (current_async) { 856 case QXL_IO_MEMSLOT_ADD_ASYNC: 857 case QXL_IO_DESTROY_PRIMARY_ASYNC: 858 case QXL_IO_UPDATE_AREA_ASYNC: 859 case QXL_IO_FLUSH_SURFACES_ASYNC: 860 case QXL_IO_MONITORS_CONFIG_ASYNC: 861 break; 862 case QXL_IO_CREATE_PRIMARY_ASYNC: 863 qxl_create_guest_primary_complete(qxl); 864 break; 865 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 866 qxl_spice_destroy_surfaces_complete(qxl); 867 break; 868 case QXL_IO_DESTROY_SURFACE_ASYNC: 869 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 870 break; 871 default: 872 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 873 current_async); 874 } 875 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 876 } 877 878 /* called from spice server thread context only */ 879 static void interface_update_area_complete(QXLInstance *sin, 880 uint32_t surface_id, 881 QXLRect *dirty, uint32_t num_updated_rects) 882 { 883 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 884 int i; 885 int qxl_i; 886 887 qemu_mutex_lock(&qxl->ssd.lock); 888 if (surface_id != 0 || !qxl->render_update_cookie_num) { 889 qemu_mutex_unlock(&qxl->ssd.lock); 890 return; 891 } 892 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 893 dirty->right, dirty->top, dirty->bottom); 894 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 895 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 896 /* 897 * overflow - treat this as a full update. Not expected to be common. 898 */ 899 trace_qxl_interface_update_area_complete_overflow(qxl->id, 900 QXL_NUM_DIRTY_RECTS); 901 qxl->guest_primary.resized = 1; 902 } 903 if (qxl->guest_primary.resized) { 904 /* 905 * Don't bother copying or scheduling the bh since we will flip 906 * the whole area anyway on completion of the update_area async call 907 */ 908 qemu_mutex_unlock(&qxl->ssd.lock); 909 return; 910 } 911 qxl_i = qxl->num_dirty_rects; 912 for (i = 0; i < num_updated_rects; i++) { 913 qxl->dirty[qxl_i++] = dirty[i]; 914 } 915 qxl->num_dirty_rects += num_updated_rects; 916 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 917 qxl->num_dirty_rects); 918 qemu_bh_schedule(qxl->update_area_bh); 919 qemu_mutex_unlock(&qxl->ssd.lock); 920 } 921 922 /* called from spice server thread context only */ 923 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 924 { 925 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 926 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 927 928 switch (cookie->type) { 929 case QXL_COOKIE_TYPE_IO: 930 interface_async_complete_io(qxl, cookie); 931 g_free(cookie); 932 break; 933 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 934 qxl_render_update_area_done(qxl, cookie); 935 break; 936 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 937 break; 938 default: 939 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 940 __func__, cookie->type); 941 g_free(cookie); 942 } 943 } 944 945 /* called from spice server thread context only */ 946 static void interface_set_client_capabilities(QXLInstance *sin, 947 uint8_t client_present, 948 uint8_t caps[58]) 949 { 950 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 951 952 if (qxl->revision < 4) { 953 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 954 qxl->revision); 955 return; 956 } 957 958 if (runstate_check(RUN_STATE_INMIGRATE) || 959 runstate_check(RUN_STATE_POSTMIGRATE)) { 960 return; 961 } 962 963 qxl->shadow_rom.client_present = client_present; 964 memcpy(qxl->shadow_rom.client_capabilities, caps, 965 sizeof(qxl->shadow_rom.client_capabilities)); 966 qxl->rom->client_present = client_present; 967 memcpy(qxl->rom->client_capabilities, caps, 968 sizeof(qxl->rom->client_capabilities)); 969 qxl_rom_set_dirty(qxl); 970 971 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 972 } 973 974 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 975 { 976 /* 977 * zlib xors the seed with 0xffffffff, and xors the result 978 * again with 0xffffffff; Both are not done with linux's crc32, 979 * which we want to be compatible with, so undo that. 980 */ 981 return crc32(0xffffffff, p, len) ^ 0xffffffff; 982 } 983 984 /* called from main context only */ 985 static int interface_client_monitors_config(QXLInstance *sin, 986 VDAgentMonitorsConfig *monitors_config) 987 { 988 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 989 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 990 int i; 991 992 if (qxl->revision < 4) { 993 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 994 qxl->revision); 995 return 0; 996 } 997 /* 998 * Older windows drivers set int_mask to 0 when their ISR is called, 999 * then later set it to ~0. So it doesn't relate to the actual interrupts 1000 * handled. However, they are old, so clearly they don't support this 1001 * interrupt 1002 */ 1003 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1004 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1005 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1006 qxl->ram->int_mask, 1007 monitors_config); 1008 return 0; 1009 } 1010 if (!monitors_config) { 1011 return 1; 1012 } 1013 memset(&rom->client_monitors_config, 0, 1014 sizeof(rom->client_monitors_config)); 1015 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1016 /* monitors_config->flags ignored */ 1017 if (rom->client_monitors_config.count >= 1018 ARRAY_SIZE(rom->client_monitors_config.heads)) { 1019 trace_qxl_client_monitors_config_capped(qxl->id, 1020 monitors_config->num_of_monitors, 1021 ARRAY_SIZE(rom->client_monitors_config.heads)); 1022 rom->client_monitors_config.count = 1023 ARRAY_SIZE(rom->client_monitors_config.heads); 1024 } 1025 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1026 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1027 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1028 /* monitor->depth ignored */ 1029 rect->left = monitor->x; 1030 rect->top = monitor->y; 1031 rect->right = monitor->x + monitor->width; 1032 rect->bottom = monitor->y + monitor->height; 1033 } 1034 rom->client_monitors_config_crc = qxl_crc32( 1035 (const uint8_t *)&rom->client_monitors_config, 1036 sizeof(rom->client_monitors_config)); 1037 trace_qxl_client_monitors_config_crc(qxl->id, 1038 sizeof(rom->client_monitors_config), 1039 rom->client_monitors_config_crc); 1040 1041 trace_qxl_interrupt_client_monitors_config(qxl->id, 1042 rom->client_monitors_config.count, 1043 rom->client_monitors_config.heads); 1044 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1045 return 1; 1046 } 1047 1048 static const QXLInterface qxl_interface = { 1049 .base.type = SPICE_INTERFACE_QXL, 1050 .base.description = "qxl gpu", 1051 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1052 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1053 1054 .attache_worker = interface_attach_worker, 1055 .set_compression_level = interface_set_compression_level, 1056 .set_mm_time = interface_set_mm_time, 1057 .get_init_info = interface_get_init_info, 1058 1059 /* the callbacks below are called from spice server thread context */ 1060 .get_command = interface_get_command, 1061 .req_cmd_notification = interface_req_cmd_notification, 1062 .release_resource = interface_release_resource, 1063 .get_cursor_command = interface_get_cursor_command, 1064 .req_cursor_notification = interface_req_cursor_notification, 1065 .notify_update = interface_notify_update, 1066 .flush_resources = interface_flush_resources, 1067 .async_complete = interface_async_complete, 1068 .update_area_complete = interface_update_area_complete, 1069 .set_client_capabilities = interface_set_client_capabilities, 1070 .client_monitors_config = interface_client_monitors_config, 1071 }; 1072 1073 static const GraphicHwOps qxl_ops = { 1074 .gfx_update = qxl_hw_update, 1075 }; 1076 1077 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1078 { 1079 if (d->mode == QXL_MODE_VGA) { 1080 return; 1081 } 1082 trace_qxl_enter_vga_mode(d->id); 1083 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ 1084 spice_qxl_driver_unload(&d->ssd.qxl); 1085 #endif 1086 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); 1087 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); 1088 qemu_spice_create_host_primary(&d->ssd); 1089 d->mode = QXL_MODE_VGA; 1090 vga_dirty_log_start(&d->vga); 1091 graphic_hw_update(d->vga.con); 1092 } 1093 1094 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1095 { 1096 if (d->mode != QXL_MODE_VGA) { 1097 return; 1098 } 1099 trace_qxl_exit_vga_mode(d->id); 1100 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); 1101 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1102 vga_dirty_log_stop(&d->vga); 1103 qxl_destroy_primary(d, QXL_SYNC); 1104 } 1105 1106 static void qxl_update_irq(PCIQXLDevice *d) 1107 { 1108 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1109 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1110 int level = !!(pending & mask); 1111 pci_set_irq(&d->pci, level); 1112 qxl_ring_set_dirty(d); 1113 } 1114 1115 static void qxl_check_state(PCIQXLDevice *d) 1116 { 1117 QXLRam *ram = d->ram; 1118 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1119 1120 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1121 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1122 } 1123 1124 static void qxl_reset_state(PCIQXLDevice *d) 1125 { 1126 QXLRom *rom = d->rom; 1127 1128 qxl_check_state(d); 1129 d->shadow_rom.update_id = cpu_to_le32(0); 1130 *rom = d->shadow_rom; 1131 qxl_rom_set_dirty(d); 1132 init_qxl_ram(d); 1133 d->num_free_res = 0; 1134 d->last_release = NULL; 1135 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1136 qxl_update_irq(d); 1137 } 1138 1139 static void qxl_soft_reset(PCIQXLDevice *d) 1140 { 1141 trace_qxl_soft_reset(d->id); 1142 qxl_check_state(d); 1143 qxl_clear_guest_bug(d); 1144 d->current_async = QXL_UNDEFINED_IO; 1145 1146 if (d->id == 0) { 1147 qxl_enter_vga_mode(d); 1148 } else { 1149 d->mode = QXL_MODE_UNDEFINED; 1150 } 1151 } 1152 1153 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1154 { 1155 bool startstop = qemu_spice_display_is_running(&d->ssd); 1156 1157 trace_qxl_hard_reset(d->id, loadvm); 1158 1159 if (startstop) { 1160 qemu_spice_display_stop(); 1161 } 1162 1163 qxl_spice_reset_cursor(d); 1164 qxl_spice_reset_image_cache(d); 1165 qxl_reset_surfaces(d); 1166 qxl_reset_memslots(d); 1167 1168 /* pre loadvm reset must not touch QXLRam. This lives in 1169 * device memory, is migrated together with RAM and thus 1170 * already loaded at this point */ 1171 if (!loadvm) { 1172 qxl_reset_state(d); 1173 } 1174 qemu_spice_create_host_memslot(&d->ssd); 1175 qxl_soft_reset(d); 1176 1177 if (startstop) { 1178 qemu_spice_display_start(); 1179 } 1180 } 1181 1182 static void qxl_reset_handler(DeviceState *dev) 1183 { 1184 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); 1185 1186 qxl_hard_reset(d, 0); 1187 } 1188 1189 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1190 { 1191 VGACommonState *vga = opaque; 1192 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1193 1194 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1195 if (qxl->mode != QXL_MODE_VGA) { 1196 qxl_destroy_primary(qxl, QXL_SYNC); 1197 qxl_soft_reset(qxl); 1198 } 1199 vga_ioport_write(opaque, addr, val); 1200 } 1201 1202 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1203 { 0x04, 2, 1, .read = vga_ioport_read, 1204 .write = qxl_vga_ioport_write }, /* 3b4 */ 1205 { 0x0a, 1, 1, .read = vga_ioport_read, 1206 .write = qxl_vga_ioport_write }, /* 3ba */ 1207 { 0x10, 16, 1, .read = vga_ioport_read, 1208 .write = qxl_vga_ioport_write }, /* 3c0 */ 1209 { 0x24, 2, 1, .read = vga_ioport_read, 1210 .write = qxl_vga_ioport_write }, /* 3d4 */ 1211 { 0x2a, 1, 1, .read = vga_ioport_read, 1212 .write = qxl_vga_ioport_write }, /* 3da */ 1213 PORTIO_END_OF_LIST(), 1214 }; 1215 1216 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1217 qxl_async_io async) 1218 { 1219 static const int regions[] = { 1220 QXL_RAM_RANGE_INDEX, 1221 QXL_VRAM_RANGE_INDEX, 1222 QXL_VRAM64_RANGE_INDEX, 1223 }; 1224 uint64_t guest_start; 1225 uint64_t guest_end; 1226 int pci_region; 1227 pcibus_t pci_start; 1228 pcibus_t pci_end; 1229 intptr_t virt_start; 1230 QXLDevMemSlot memslot; 1231 int i; 1232 1233 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1234 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1235 1236 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1237 1238 if (slot_id >= NUM_MEMSLOTS) { 1239 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1240 slot_id, NUM_MEMSLOTS); 1241 return 1; 1242 } 1243 if (guest_start > guest_end) { 1244 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1245 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1246 return 1; 1247 } 1248 1249 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1250 pci_region = regions[i]; 1251 pci_start = d->pci.io_regions[pci_region].addr; 1252 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1253 /* mapped? */ 1254 if (pci_start == -1) { 1255 continue; 1256 } 1257 /* start address in range ? */ 1258 if (guest_start < pci_start || guest_start > pci_end) { 1259 continue; 1260 } 1261 /* end address in range ? */ 1262 if (guest_end > pci_end) { 1263 continue; 1264 } 1265 /* passed */ 1266 break; 1267 } 1268 if (i == ARRAY_SIZE(regions)) { 1269 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1270 return 1; 1271 } 1272 1273 switch (pci_region) { 1274 case QXL_RAM_RANGE_INDEX: 1275 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); 1276 break; 1277 case QXL_VRAM_RANGE_INDEX: 1278 case 4 /* vram 64bit */: 1279 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); 1280 break; 1281 default: 1282 /* should not happen */ 1283 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1284 return 1; 1285 } 1286 1287 memslot.slot_id = slot_id; 1288 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1289 memslot.virt_start = virt_start + (guest_start - pci_start); 1290 memslot.virt_end = virt_start + (guest_end - pci_start); 1291 memslot.addr_delta = memslot.virt_start - delta; 1292 memslot.generation = d->rom->slot_generation = 0; 1293 qxl_rom_set_dirty(d); 1294 1295 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1296 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; 1297 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1298 d->guest_slots[slot_id].delta = delta; 1299 d->guest_slots[slot_id].active = 1; 1300 return 0; 1301 } 1302 1303 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1304 { 1305 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1306 d->guest_slots[slot_id].active = 0; 1307 } 1308 1309 static void qxl_reset_memslots(PCIQXLDevice *d) 1310 { 1311 qxl_spice_reset_memslots(d); 1312 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1313 } 1314 1315 static void qxl_reset_surfaces(PCIQXLDevice *d) 1316 { 1317 trace_qxl_reset_surfaces(d->id); 1318 d->mode = QXL_MODE_UNDEFINED; 1319 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1320 } 1321 1322 /* can be also called from spice server thread context */ 1323 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1324 { 1325 uint64_t phys = le64_to_cpu(pqxl); 1326 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1327 uint64_t offset = phys & 0xffffffffffff; 1328 1329 switch (group_id) { 1330 case MEMSLOT_GROUP_HOST: 1331 return (void *)(intptr_t)offset; 1332 case MEMSLOT_GROUP_GUEST: 1333 if (slot >= NUM_MEMSLOTS) { 1334 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1335 NUM_MEMSLOTS); 1336 return NULL; 1337 } 1338 if (!qxl->guest_slots[slot].active) { 1339 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1340 return NULL; 1341 } 1342 if (offset < qxl->guest_slots[slot].delta) { 1343 qxl_set_guest_bug(qxl, 1344 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1345 slot, offset, qxl->guest_slots[slot].delta); 1346 return NULL; 1347 } 1348 offset -= qxl->guest_slots[slot].delta; 1349 if (offset > qxl->guest_slots[slot].size) { 1350 qxl_set_guest_bug(qxl, 1351 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1352 slot, offset, qxl->guest_slots[slot].size); 1353 return NULL; 1354 } 1355 return qxl->guest_slots[slot].ptr + offset; 1356 } 1357 return NULL; 1358 } 1359 1360 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1361 { 1362 /* for local rendering */ 1363 qxl_render_resize(qxl); 1364 } 1365 1366 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1367 qxl_async_io async) 1368 { 1369 QXLDevSurfaceCreate surface; 1370 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1371 uint32_t requested_height = le32_to_cpu(sc->height); 1372 int requested_stride = le32_to_cpu(sc->stride); 1373 1374 if (requested_stride == INT32_MIN || 1375 abs(requested_stride) * (uint64_t)requested_height 1376 > qxl->vgamem_size) { 1377 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1378 " stride %d x height %" PRIu32 " > %" PRIu32, 1379 __func__, requested_stride, requested_height, 1380 qxl->vgamem_size); 1381 return; 1382 } 1383 1384 if (qxl->mode == QXL_MODE_NATIVE) { 1385 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1386 __func__); 1387 } 1388 qxl_exit_vga_mode(qxl); 1389 1390 surface.format = le32_to_cpu(sc->format); 1391 surface.height = le32_to_cpu(sc->height); 1392 surface.mem = le64_to_cpu(sc->mem); 1393 surface.position = le32_to_cpu(sc->position); 1394 surface.stride = le32_to_cpu(sc->stride); 1395 surface.width = le32_to_cpu(sc->width); 1396 surface.type = le32_to_cpu(sc->type); 1397 surface.flags = le32_to_cpu(sc->flags); 1398 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1399 sc->format, sc->position); 1400 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1401 sc->flags); 1402 1403 if ((surface.stride & 0x3) != 0) { 1404 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1405 surface.stride); 1406 return; 1407 } 1408 1409 surface.mouse_mode = true; 1410 surface.group_id = MEMSLOT_GROUP_GUEST; 1411 if (loadvm) { 1412 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1413 } 1414 1415 qxl->mode = QXL_MODE_NATIVE; 1416 qxl->cmdflags = 0; 1417 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1418 1419 if (async == QXL_SYNC) { 1420 qxl_create_guest_primary_complete(qxl); 1421 } 1422 } 1423 1424 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1425 * done (in QXL_SYNC case), 0 otherwise. */ 1426 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1427 { 1428 if (d->mode == QXL_MODE_UNDEFINED) { 1429 return 0; 1430 } 1431 trace_qxl_destroy_primary(d->id); 1432 d->mode = QXL_MODE_UNDEFINED; 1433 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1434 qxl_spice_reset_cursor(d); 1435 return 1; 1436 } 1437 1438 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1439 { 1440 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1441 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1442 QXLMode *mode = d->modes->modes + modenr; 1443 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1444 QXLMemSlot slot = { 1445 .mem_start = start, 1446 .mem_end = end 1447 }; 1448 1449 if (modenr >= d->modes->n_modes) { 1450 qxl_set_guest_bug(d, "mode number out of range"); 1451 return; 1452 } 1453 1454 QXLSurfaceCreate surface = { 1455 .width = mode->x_res, 1456 .height = mode->y_res, 1457 .stride = -mode->x_res * 4, 1458 .format = SPICE_SURFACE_FMT_32_xRGB, 1459 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1460 .mouse_mode = true, 1461 .mem = devmem + d->shadow_rom.draw_area_offset, 1462 }; 1463 1464 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1465 devmem); 1466 if (!loadvm) { 1467 qxl_hard_reset(d, 0); 1468 } 1469 1470 d->guest_slots[0].slot = slot; 1471 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1472 1473 d->guest_primary.surface = surface; 1474 qxl_create_guest_primary(d, 0, QXL_SYNC); 1475 1476 d->mode = QXL_MODE_COMPAT; 1477 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1478 if (mode->bits == 16) { 1479 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1480 } 1481 d->shadow_rom.mode = cpu_to_le32(modenr); 1482 d->rom->mode = cpu_to_le32(modenr); 1483 qxl_rom_set_dirty(d); 1484 } 1485 1486 static void ioport_write(void *opaque, hwaddr addr, 1487 uint64_t val, unsigned size) 1488 { 1489 PCIQXLDevice *d = opaque; 1490 uint32_t io_port = addr; 1491 qxl_async_io async = QXL_SYNC; 1492 uint32_t orig_io_port = io_port; 1493 1494 if (d->guest_bug && io_port != QXL_IO_RESET) { 1495 return; 1496 } 1497 1498 if (d->revision <= QXL_REVISION_STABLE_V10 && 1499 io_port > QXL_IO_FLUSH_RELEASE) { 1500 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1501 io_port, d->revision); 1502 return; 1503 } 1504 1505 switch (io_port) { 1506 case QXL_IO_RESET: 1507 case QXL_IO_SET_MODE: 1508 case QXL_IO_MEMSLOT_ADD: 1509 case QXL_IO_MEMSLOT_DEL: 1510 case QXL_IO_CREATE_PRIMARY: 1511 case QXL_IO_UPDATE_IRQ: 1512 case QXL_IO_LOG: 1513 case QXL_IO_MEMSLOT_ADD_ASYNC: 1514 case QXL_IO_CREATE_PRIMARY_ASYNC: 1515 break; 1516 default: 1517 if (d->mode != QXL_MODE_VGA) { 1518 break; 1519 } 1520 trace_qxl_io_unexpected_vga_mode(d->id, 1521 addr, val, io_port_to_string(io_port)); 1522 /* be nice to buggy guest drivers */ 1523 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1524 io_port < QXL_IO_RANGE_SIZE) { 1525 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1526 } 1527 return; 1528 } 1529 1530 /* we change the io_port to avoid ifdeffery in the main switch */ 1531 orig_io_port = io_port; 1532 switch (io_port) { 1533 case QXL_IO_UPDATE_AREA_ASYNC: 1534 io_port = QXL_IO_UPDATE_AREA; 1535 goto async_common; 1536 case QXL_IO_MEMSLOT_ADD_ASYNC: 1537 io_port = QXL_IO_MEMSLOT_ADD; 1538 goto async_common; 1539 case QXL_IO_CREATE_PRIMARY_ASYNC: 1540 io_port = QXL_IO_CREATE_PRIMARY; 1541 goto async_common; 1542 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1543 io_port = QXL_IO_DESTROY_PRIMARY; 1544 goto async_common; 1545 case QXL_IO_DESTROY_SURFACE_ASYNC: 1546 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1547 goto async_common; 1548 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1549 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1550 goto async_common; 1551 case QXL_IO_FLUSH_SURFACES_ASYNC: 1552 case QXL_IO_MONITORS_CONFIG_ASYNC: 1553 async_common: 1554 async = QXL_ASYNC; 1555 qemu_mutex_lock(&d->async_lock); 1556 if (d->current_async != QXL_UNDEFINED_IO) { 1557 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1558 io_port, d->current_async); 1559 qemu_mutex_unlock(&d->async_lock); 1560 return; 1561 } 1562 d->current_async = orig_io_port; 1563 qemu_mutex_unlock(&d->async_lock); 1564 break; 1565 default: 1566 break; 1567 } 1568 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1569 addr, io_port_to_string(addr), 1570 val, size, async); 1571 1572 switch (io_port) { 1573 case QXL_IO_UPDATE_AREA: 1574 { 1575 QXLCookie *cookie = NULL; 1576 QXLRect update = d->ram->update_area; 1577 1578 if (d->ram->update_surface > d->ssd.num_surfaces) { 1579 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1580 d->ram->update_surface); 1581 break; 1582 } 1583 if (update.left >= update.right || update.top >= update.bottom || 1584 update.left < 0 || update.top < 0) { 1585 qxl_set_guest_bug(d, 1586 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1587 update.left, update.top, update.right, update.bottom); 1588 if (update.left == update.right || update.top == update.bottom) { 1589 /* old drivers may provide empty area, keep going */ 1590 qxl_clear_guest_bug(d); 1591 goto cancel_async; 1592 } 1593 break; 1594 } 1595 if (async == QXL_ASYNC) { 1596 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1597 QXL_IO_UPDATE_AREA_ASYNC); 1598 cookie->u.area = update; 1599 } 1600 qxl_spice_update_area(d, d->ram->update_surface, 1601 cookie ? &cookie->u.area : &update, 1602 NULL, 0, 0, async, cookie); 1603 break; 1604 } 1605 case QXL_IO_NOTIFY_CMD: 1606 qemu_spice_wakeup(&d->ssd); 1607 break; 1608 case QXL_IO_NOTIFY_CURSOR: 1609 qemu_spice_wakeup(&d->ssd); 1610 break; 1611 case QXL_IO_UPDATE_IRQ: 1612 qxl_update_irq(d); 1613 break; 1614 case QXL_IO_NOTIFY_OOM: 1615 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1616 break; 1617 } 1618 d->oom_running = 1; 1619 qxl_spice_oom(d); 1620 d->oom_running = 0; 1621 break; 1622 case QXL_IO_SET_MODE: 1623 qxl_set_mode(d, val, 0); 1624 break; 1625 case QXL_IO_LOG: 1626 trace_qxl_io_log(d->id, d->ram->log_buf); 1627 if (d->guestdebug) { 1628 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1629 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->ram->log_buf); 1630 } 1631 break; 1632 case QXL_IO_RESET: 1633 qxl_hard_reset(d, 0); 1634 break; 1635 case QXL_IO_MEMSLOT_ADD: 1636 if (val >= NUM_MEMSLOTS) { 1637 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1638 break; 1639 } 1640 if (d->guest_slots[val].active) { 1641 qxl_set_guest_bug(d, 1642 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1643 break; 1644 } 1645 d->guest_slots[val].slot = d->ram->mem_slot; 1646 qxl_add_memslot(d, val, 0, async); 1647 break; 1648 case QXL_IO_MEMSLOT_DEL: 1649 if (val >= NUM_MEMSLOTS) { 1650 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1651 break; 1652 } 1653 qxl_del_memslot(d, val); 1654 break; 1655 case QXL_IO_CREATE_PRIMARY: 1656 if (val != 0) { 1657 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1658 async); 1659 goto cancel_async; 1660 } 1661 d->guest_primary.surface = d->ram->create_surface; 1662 qxl_create_guest_primary(d, 0, async); 1663 break; 1664 case QXL_IO_DESTROY_PRIMARY: 1665 if (val != 0) { 1666 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1667 async); 1668 goto cancel_async; 1669 } 1670 if (!qxl_destroy_primary(d, async)) { 1671 trace_qxl_io_destroy_primary_ignored(d->id, 1672 qxl_mode_to_string(d->mode)); 1673 goto cancel_async; 1674 } 1675 break; 1676 case QXL_IO_DESTROY_SURFACE_WAIT: 1677 if (val >= d->ssd.num_surfaces) { 1678 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1679 "%" PRIu64 " >= NUM_SURFACES", async, val); 1680 goto cancel_async; 1681 } 1682 qxl_spice_destroy_surface_wait(d, val, async); 1683 break; 1684 case QXL_IO_FLUSH_RELEASE: { 1685 QXLReleaseRing *ring = &d->ram->release_ring; 1686 if (ring->prod - ring->cons + 1 == ring->num_items) { 1687 fprintf(stderr, 1688 "ERROR: no flush, full release ring [p%d,%dc]\n", 1689 ring->prod, ring->cons); 1690 } 1691 qxl_push_free_res(d, 1 /* flush */); 1692 break; 1693 } 1694 case QXL_IO_FLUSH_SURFACES_ASYNC: 1695 qxl_spice_flush_surfaces_async(d); 1696 break; 1697 case QXL_IO_DESTROY_ALL_SURFACES: 1698 d->mode = QXL_MODE_UNDEFINED; 1699 qxl_spice_destroy_surfaces(d, async); 1700 break; 1701 case QXL_IO_MONITORS_CONFIG_ASYNC: 1702 qxl_spice_monitors_config_async(d, 0); 1703 break; 1704 default: 1705 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1706 } 1707 return; 1708 cancel_async: 1709 if (async) { 1710 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1711 qemu_mutex_lock(&d->async_lock); 1712 d->current_async = QXL_UNDEFINED_IO; 1713 qemu_mutex_unlock(&d->async_lock); 1714 } 1715 } 1716 1717 static uint64_t ioport_read(void *opaque, hwaddr addr, 1718 unsigned size) 1719 { 1720 PCIQXLDevice *qxl = opaque; 1721 1722 trace_qxl_io_read_unexpected(qxl->id); 1723 return 0xff; 1724 } 1725 1726 static const MemoryRegionOps qxl_io_ops = { 1727 .read = ioport_read, 1728 .write = ioport_write, 1729 .valid = { 1730 .min_access_size = 1, 1731 .max_access_size = 1, 1732 }, 1733 }; 1734 1735 static void qxl_update_irq_bh(void *opaque) 1736 { 1737 PCIQXLDevice *d = opaque; 1738 qxl_update_irq(d); 1739 } 1740 1741 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1742 { 1743 uint32_t old_pending; 1744 uint32_t le_events = cpu_to_le32(events); 1745 1746 trace_qxl_send_events(d->id, events); 1747 if (!qemu_spice_display_is_running(&d->ssd)) { 1748 /* spice-server tracks guest running state and should not do this */ 1749 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1750 __func__); 1751 trace_qxl_send_events_vm_stopped(d->id, events); 1752 return; 1753 } 1754 old_pending = atomic_fetch_or(&d->ram->int_pending, le_events); 1755 if ((old_pending & le_events) == le_events) { 1756 return; 1757 } 1758 qemu_bh_schedule(d->update_irq); 1759 } 1760 1761 /* graphics console */ 1762 1763 static void qxl_hw_update(void *opaque) 1764 { 1765 PCIQXLDevice *qxl = opaque; 1766 1767 qxl_render_update(qxl); 1768 } 1769 1770 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1771 { 1772 uintptr_t vram_start; 1773 int i; 1774 1775 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1776 return; 1777 } 1778 1779 /* dirty the primary surface */ 1780 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, 1781 qxl->shadow_rom.surface0_area_size); 1782 1783 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); 1784 1785 /* dirty the off-screen surfaces */ 1786 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1787 QXLSurfaceCmd *cmd; 1788 intptr_t surface_offset; 1789 int surface_size; 1790 1791 if (qxl->guest_surfaces.cmds[i] == 0) { 1792 continue; 1793 } 1794 1795 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1796 MEMSLOT_GROUP_GUEST); 1797 assert(cmd); 1798 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1799 surface_offset = (intptr_t)qxl_phys2virt(qxl, 1800 cmd->u.surface_create.data, 1801 MEMSLOT_GROUP_GUEST); 1802 assert(surface_offset); 1803 surface_offset -= vram_start; 1804 surface_size = cmd->u.surface_create.height * 1805 abs(cmd->u.surface_create.stride); 1806 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); 1807 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); 1808 } 1809 } 1810 1811 static void qxl_vm_change_state_handler(void *opaque, int running, 1812 RunState state) 1813 { 1814 PCIQXLDevice *qxl = opaque; 1815 1816 if (running) { 1817 /* 1818 * if qxl_send_events was called from spice server context before 1819 * migration ended, qxl_update_irq for these events might not have been 1820 * called 1821 */ 1822 qxl_update_irq(qxl); 1823 } else { 1824 /* make sure surfaces are saved before migration */ 1825 qxl_dirty_surfaces(qxl); 1826 } 1827 } 1828 1829 /* display change listener */ 1830 1831 static void display_update(DisplayChangeListener *dcl, 1832 int x, int y, int w, int h) 1833 { 1834 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1835 1836 if (qxl->mode == QXL_MODE_VGA) { 1837 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 1838 } 1839 } 1840 1841 static void display_switch(DisplayChangeListener *dcl, 1842 struct DisplaySurface *surface) 1843 { 1844 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1845 1846 qxl->ssd.ds = surface; 1847 if (qxl->mode == QXL_MODE_VGA) { 1848 qemu_spice_display_switch(&qxl->ssd, surface); 1849 } 1850 } 1851 1852 static void display_refresh(DisplayChangeListener *dcl) 1853 { 1854 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 1855 1856 if (qxl->mode == QXL_MODE_VGA) { 1857 qemu_spice_display_refresh(&qxl->ssd); 1858 } 1859 } 1860 1861 static DisplayChangeListenerOps display_listener_ops = { 1862 .dpy_name = "spice/qxl", 1863 .dpy_gfx_update = display_update, 1864 .dpy_gfx_switch = display_switch, 1865 .dpy_refresh = display_refresh, 1866 }; 1867 1868 static void qxl_init_ramsize(PCIQXLDevice *qxl) 1869 { 1870 /* vga mode framebuffer / primary surface (bar 0, first part) */ 1871 if (qxl->vgamem_size_mb < 8) { 1872 qxl->vgamem_size_mb = 8; 1873 } 1874 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be 1875 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now). 1876 */ 1877 if (qxl->vgamem_size_mb > 256) { 1878 qxl->vgamem_size_mb = 256; 1879 } 1880 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024; 1881 1882 /* vga ram (bar 0, total) */ 1883 if (qxl->ram_size_mb != -1) { 1884 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; 1885 } 1886 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 1887 qxl->vga.vram_size = qxl->vgamem_size * 2; 1888 } 1889 1890 /* vram32 (surfaces, 32bit, bar 1) */ 1891 if (qxl->vram32_size_mb != -1) { 1892 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; 1893 } 1894 if (qxl->vram32_size < 4096) { 1895 qxl->vram32_size = 4096; 1896 } 1897 1898 /* vram (surfaces, 64bit, bar 4+5) */ 1899 if (qxl->vram_size_mb != -1) { 1900 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; 1901 } 1902 if (qxl->vram_size < qxl->vram32_size) { 1903 qxl->vram_size = qxl->vram32_size; 1904 } 1905 1906 if (qxl->revision == 1) { 1907 qxl->vram32_size = 4096; 1908 qxl->vram_size = 4096; 1909 } 1910 qxl->vgamem_size = pow2ceil(qxl->vgamem_size); 1911 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size); 1912 qxl->vram32_size = pow2ceil(qxl->vram32_size); 1913 qxl->vram_size = pow2ceil(qxl->vram_size); 1914 } 1915 1916 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) 1917 { 1918 uint8_t* config = qxl->pci.config; 1919 uint32_t pci_device_rev; 1920 uint32_t io_size; 1921 1922 qxl->mode = QXL_MODE_UNDEFINED; 1923 qxl->generation = 1; 1924 qxl->num_memslots = NUM_MEMSLOTS; 1925 qemu_mutex_init(&qxl->track_lock); 1926 qemu_mutex_init(&qxl->async_lock); 1927 qxl->current_async = QXL_UNDEFINED_IO; 1928 qxl->guest_bug = 0; 1929 1930 switch (qxl->revision) { 1931 case 1: /* spice 0.4 -- qxl-1 */ 1932 pci_device_rev = QXL_REVISION_STABLE_V04; 1933 io_size = 8; 1934 break; 1935 case 2: /* spice 0.6 -- qxl-2 */ 1936 pci_device_rev = QXL_REVISION_STABLE_V06; 1937 io_size = 16; 1938 break; 1939 case 3: /* qxl-3 */ 1940 pci_device_rev = QXL_REVISION_STABLE_V10; 1941 io_size = 32; /* PCI region size must be pow2 */ 1942 break; 1943 case 4: /* qxl-4 */ 1944 pci_device_rev = QXL_REVISION_STABLE_V12; 1945 io_size = pow2ceil(QXL_IO_RANGE_SIZE); 1946 break; 1947 default: 1948 error_setg(errp, "Invalid revision %d for qxl device (max %d)", 1949 qxl->revision, QXL_DEFAULT_REVISION); 1950 return; 1951 } 1952 1953 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 1954 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 1955 1956 qxl->rom_size = qxl_rom_size(); 1957 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 1958 qxl->rom_size, &error_abort); 1959 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); 1960 init_qxl_rom(qxl); 1961 init_qxl_ram(qxl); 1962 1963 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 1964 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 1965 qxl->vram_size, &error_abort); 1966 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); 1967 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 1968 &qxl->vram_bar, 0, qxl->vram32_size); 1969 1970 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 1971 "qxl-ioports", io_size); 1972 if (qxl->id == 0) { 1973 vga_dirty_log_start(&qxl->vga); 1974 } 1975 memory_region_set_flush_coalesced(&qxl->io_bar); 1976 1977 1978 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 1979 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 1980 1981 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 1982 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 1983 1984 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 1985 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 1986 1987 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 1988 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 1989 1990 if (qxl->vram32_size < qxl->vram_size) { 1991 /* 1992 * Make the 64bit vram bar show up only in case it is 1993 * configured to be larger than the 32bit vram bar. 1994 */ 1995 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 1996 PCI_BASE_ADDRESS_SPACE_MEMORY | 1997 PCI_BASE_ADDRESS_MEM_TYPE_64 | 1998 PCI_BASE_ADDRESS_MEM_PREFETCH, 1999 &qxl->vram_bar); 2000 } 2001 2002 /* print pci bar details */ 2003 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", 2004 qxl->id == 0 ? "pri" : "sec", 2005 qxl->vga.vram_size / (1024*1024)); 2006 dprint(qxl, 1, "vram/32: %d MB [region 1]\n", 2007 qxl->vram32_size / (1024*1024)); 2008 dprint(qxl, 1, "vram/64: %d MB %s\n", 2009 qxl->vram_size / (1024*1024), 2010 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2011 2012 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2013 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2014 error_setg(errp, "qxl interface %d.%d not supported by spice-server", 2015 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2016 return; 2017 } 2018 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2019 2020 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2021 qxl_reset_state(qxl); 2022 2023 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2024 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd); 2025 } 2026 2027 static void qxl_realize_primary(PCIDevice *dev, Error **errp) 2028 { 2029 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2030 VGACommonState *vga = &qxl->vga; 2031 Error *local_err = NULL; 2032 2033 qxl->id = 0; 2034 qxl_init_ramsize(qxl); 2035 vga->vbe_size = qxl->vgamem_size; 2036 vga->vram_size_mb = qxl->vga.vram_size >> 20; 2037 vga_common_init(vga, OBJECT(dev), true); 2038 vga_init(vga, OBJECT(dev), 2039 pci_address_space(dev), pci_address_space_io(dev), false); 2040 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2041 vga, "vga"); 2042 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2043 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2044 2045 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2046 qemu_spice_display_init_common(&qxl->ssd); 2047 2048 qxl_realize_common(qxl, &local_err); 2049 if (local_err) { 2050 error_propagate(errp, local_err); 2051 return; 2052 } 2053 2054 qxl->ssd.dcl.ops = &display_listener_ops; 2055 qxl->ssd.dcl.con = vga->con; 2056 register_displaychangelistener(&qxl->ssd.dcl); 2057 } 2058 2059 static void qxl_realize_secondary(PCIDevice *dev, Error **errp) 2060 { 2061 static int device_id = 1; 2062 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); 2063 2064 qxl->id = device_id++; 2065 qxl_init_ramsize(qxl); 2066 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2067 qxl->vga.vram_size, &error_abort); 2068 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); 2069 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2070 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2071 2072 qxl_realize_common(qxl, errp); 2073 } 2074 2075 static void qxl_pre_save(void *opaque) 2076 { 2077 PCIQXLDevice* d = opaque; 2078 uint8_t *ram_start = d->vga.vram_ptr; 2079 2080 trace_qxl_pre_save(d->id); 2081 if (d->last_release == NULL) { 2082 d->last_release_offset = 0; 2083 } else { 2084 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2085 } 2086 assert(d->last_release_offset < d->vga.vram_size); 2087 } 2088 2089 static int qxl_pre_load(void *opaque) 2090 { 2091 PCIQXLDevice* d = opaque; 2092 2093 trace_qxl_pre_load(d->id); 2094 qxl_hard_reset(d, 1); 2095 qxl_exit_vga_mode(d); 2096 return 0; 2097 } 2098 2099 static void qxl_create_memslots(PCIQXLDevice *d) 2100 { 2101 int i; 2102 2103 for (i = 0; i < NUM_MEMSLOTS; i++) { 2104 if (!d->guest_slots[i].active) { 2105 continue; 2106 } 2107 qxl_add_memslot(d, i, 0, QXL_SYNC); 2108 } 2109 } 2110 2111 static int qxl_post_load(void *opaque, int version) 2112 { 2113 PCIQXLDevice* d = opaque; 2114 uint8_t *ram_start = d->vga.vram_ptr; 2115 QXLCommandExt *cmds; 2116 int in, out, newmode; 2117 2118 assert(d->last_release_offset < d->vga.vram_size); 2119 if (d->last_release_offset == 0) { 2120 d->last_release = NULL; 2121 } else { 2122 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2123 } 2124 2125 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2126 2127 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2128 newmode = d->mode; 2129 d->mode = QXL_MODE_UNDEFINED; 2130 2131 switch (newmode) { 2132 case QXL_MODE_UNDEFINED: 2133 qxl_create_memslots(d); 2134 break; 2135 case QXL_MODE_VGA: 2136 qxl_create_memslots(d); 2137 qxl_enter_vga_mode(d); 2138 break; 2139 case QXL_MODE_NATIVE: 2140 qxl_create_memslots(d); 2141 qxl_create_guest_primary(d, 1, QXL_SYNC); 2142 2143 /* replay surface-create and cursor-set commands */ 2144 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1)); 2145 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2146 if (d->guest_surfaces.cmds[in] == 0) { 2147 continue; 2148 } 2149 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2150 cmds[out].cmd.type = QXL_CMD_SURFACE; 2151 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2152 out++; 2153 } 2154 if (d->guest_cursor) { 2155 cmds[out].cmd.data = d->guest_cursor; 2156 cmds[out].cmd.type = QXL_CMD_CURSOR; 2157 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2158 out++; 2159 } 2160 qxl_spice_loadvm_commands(d, cmds, out); 2161 g_free(cmds); 2162 if (d->guest_monitors_config) { 2163 qxl_spice_monitors_config_async(d, 1); 2164 } 2165 break; 2166 case QXL_MODE_COMPAT: 2167 /* note: no need to call qxl_create_memslots, qxl_set_mode 2168 * creates the mem slot. */ 2169 qxl_set_mode(d, d->shadow_rom.mode, 1); 2170 break; 2171 } 2172 return 0; 2173 } 2174 2175 #define QXL_SAVE_VERSION 21 2176 2177 static bool qxl_monitors_config_needed(void *opaque) 2178 { 2179 PCIQXLDevice *qxl = opaque; 2180 2181 return qxl->guest_monitors_config != 0; 2182 } 2183 2184 2185 static VMStateDescription qxl_memslot = { 2186 .name = "qxl-memslot", 2187 .version_id = QXL_SAVE_VERSION, 2188 .minimum_version_id = QXL_SAVE_VERSION, 2189 .fields = (VMStateField[]) { 2190 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2191 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2192 VMSTATE_UINT32(active, struct guest_slots), 2193 VMSTATE_END_OF_LIST() 2194 } 2195 }; 2196 2197 static VMStateDescription qxl_surface = { 2198 .name = "qxl-surface", 2199 .version_id = QXL_SAVE_VERSION, 2200 .minimum_version_id = QXL_SAVE_VERSION, 2201 .fields = (VMStateField[]) { 2202 VMSTATE_UINT32(width, QXLSurfaceCreate), 2203 VMSTATE_UINT32(height, QXLSurfaceCreate), 2204 VMSTATE_INT32(stride, QXLSurfaceCreate), 2205 VMSTATE_UINT32(format, QXLSurfaceCreate), 2206 VMSTATE_UINT32(position, QXLSurfaceCreate), 2207 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2208 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2209 VMSTATE_UINT32(type, QXLSurfaceCreate), 2210 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2211 VMSTATE_END_OF_LIST() 2212 } 2213 }; 2214 2215 static VMStateDescription qxl_vmstate_monitors_config = { 2216 .name = "qxl/monitors-config", 2217 .version_id = 1, 2218 .minimum_version_id = 1, 2219 .fields = (VMStateField[]) { 2220 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2221 VMSTATE_END_OF_LIST() 2222 }, 2223 }; 2224 2225 static VMStateDescription qxl_vmstate = { 2226 .name = "qxl", 2227 .version_id = QXL_SAVE_VERSION, 2228 .minimum_version_id = QXL_SAVE_VERSION, 2229 .pre_save = qxl_pre_save, 2230 .pre_load = qxl_pre_load, 2231 .post_load = qxl_post_load, 2232 .fields = (VMStateField[]) { 2233 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2234 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2235 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2236 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2237 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2238 VMSTATE_UINT32(mode, PCIQXLDevice), 2239 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2240 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), 2241 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2242 qxl_memslot, struct guest_slots), 2243 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2244 qxl_surface, QXLSurfaceCreate), 2245 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice), 2246 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2247 ssd.num_surfaces, 0, 2248 vmstate_info_uint64, uint64_t), 2249 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2250 VMSTATE_END_OF_LIST() 2251 }, 2252 .subsections = (VMStateSubsection[]) { 2253 { 2254 .vmsd = &qxl_vmstate_monitors_config, 2255 .needed = qxl_monitors_config_needed, 2256 }, { 2257 /* empty */ 2258 } 2259 } 2260 }; 2261 2262 static Property qxl_properties[] = { 2263 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 2264 64 * 1024 * 1024), 2265 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, 2266 64 * 1024 * 1024), 2267 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2268 QXL_DEFAULT_REVISION), 2269 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2270 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2271 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2272 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2273 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2274 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2275 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2276 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2277 DEFINE_PROP_END_OF_LIST(), 2278 }; 2279 2280 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2281 { 2282 DeviceClass *dc = DEVICE_CLASS(klass); 2283 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2284 2285 k->realize = qxl_realize_primary; 2286 k->romfile = "vgabios-qxl.bin"; 2287 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2288 k->device_id = QXL_DEVICE_ID_STABLE; 2289 k->class_id = PCI_CLASS_DISPLAY_VGA; 2290 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2291 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2292 dc->reset = qxl_reset_handler; 2293 dc->vmsd = &qxl_vmstate; 2294 dc->props = qxl_properties; 2295 dc->hotpluggable = false; 2296 } 2297 2298 static const TypeInfo qxl_primary_info = { 2299 .name = "qxl-vga", 2300 .parent = TYPE_PCI_DEVICE, 2301 .instance_size = sizeof(PCIQXLDevice), 2302 .class_init = qxl_primary_class_init, 2303 }; 2304 2305 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2306 { 2307 DeviceClass *dc = DEVICE_CLASS(klass); 2308 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2309 2310 k->realize = qxl_realize_secondary; 2311 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2312 k->device_id = QXL_DEVICE_ID_STABLE; 2313 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2314 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2315 dc->desc = "Spice QXL GPU (secondary)"; 2316 dc->reset = qxl_reset_handler; 2317 dc->vmsd = &qxl_vmstate; 2318 dc->props = qxl_properties; 2319 } 2320 2321 static const TypeInfo qxl_secondary_info = { 2322 .name = "qxl", 2323 .parent = TYPE_PCI_DEVICE, 2324 .instance_size = sizeof(PCIQXLDevice), 2325 .class_init = qxl_secondary_class_init, 2326 }; 2327 2328 static void qxl_register_types(void) 2329 { 2330 type_register_static(&qxl_primary_info); 2331 type_register_static(&qxl_secondary_info); 2332 } 2333 2334 type_init(qxl_register_types) 2335