1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include <zlib.h> 24 25 #include "qapi/error.h" 26 #include "qemu/timer.h" 27 #include "qemu/queue.h" 28 #include "qemu/atomic.h" 29 #include "qemu/main-loop.h" 30 #include "qemu/module.h" 31 #include "hw/qdev-properties.h" 32 #include "sysemu/runstate.h" 33 #include "migration/blocker.h" 34 #include "migration/vmstate.h" 35 #include "trace.h" 36 37 #include "qxl.h" 38 39 #undef SPICE_RING_CONS_ITEM 40 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 41 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 42 if (cons >= ARRAY_SIZE((r)->items)) { \ 43 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 44 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 45 ret = NULL; \ 46 } else { \ 47 ret = &(r)->items[cons].el; \ 48 } \ 49 } 50 51 #undef ALIGN 52 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 53 54 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 55 56 #define QXL_MODE(_x, _y, _b, _o) \ 57 { .x_res = _x, \ 58 .y_res = _y, \ 59 .bits = _b, \ 60 .stride = (_x) * (_b) / 8, \ 61 .x_mili = PIXEL_SIZE * (_x), \ 62 .y_mili = PIXEL_SIZE * (_y), \ 63 .orientation = _o, \ 64 } 65 66 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 67 QXL_MODE(x_res, y_res, 16, orientation), \ 68 QXL_MODE(x_res, y_res, 32, orientation) 69 70 #define QXL_MODE_EX(x_res, y_res) \ 71 QXL_MODE_16_32(x_res, y_res, 0), \ 72 QXL_MODE_16_32(x_res, y_res, 1) 73 74 static QXLMode qxl_modes[] = { 75 QXL_MODE_EX(640, 480), 76 QXL_MODE_EX(800, 480), 77 QXL_MODE_EX(800, 600), 78 QXL_MODE_EX(832, 624), 79 QXL_MODE_EX(960, 640), 80 QXL_MODE_EX(1024, 600), 81 QXL_MODE_EX(1024, 768), 82 QXL_MODE_EX(1152, 864), 83 QXL_MODE_EX(1152, 870), 84 QXL_MODE_EX(1280, 720), 85 QXL_MODE_EX(1280, 760), 86 QXL_MODE_EX(1280, 768), 87 QXL_MODE_EX(1280, 800), 88 QXL_MODE_EX(1280, 960), 89 QXL_MODE_EX(1280, 1024), 90 QXL_MODE_EX(1360, 768), 91 QXL_MODE_EX(1366, 768), 92 QXL_MODE_EX(1400, 1050), 93 QXL_MODE_EX(1440, 900), 94 QXL_MODE_EX(1600, 900), 95 QXL_MODE_EX(1600, 1200), 96 QXL_MODE_EX(1680, 1050), 97 QXL_MODE_EX(1920, 1080), 98 /* these modes need more than 8 MB video memory */ 99 QXL_MODE_EX(1920, 1200), 100 QXL_MODE_EX(1920, 1440), 101 QXL_MODE_EX(2000, 2000), 102 QXL_MODE_EX(2048, 1536), 103 QXL_MODE_EX(2048, 2048), 104 QXL_MODE_EX(2560, 1440), 105 QXL_MODE_EX(2560, 1600), 106 /* these modes need more than 16 MB video memory */ 107 QXL_MODE_EX(2560, 2048), 108 QXL_MODE_EX(2800, 2100), 109 QXL_MODE_EX(3200, 2400), 110 /* these modes need more than 32 MB video memory */ 111 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 112 QXL_MODE_EX(4096, 2160), /* 4k */ 113 /* these modes need more than 64 MB video memory */ 114 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 115 /* these modes need more than 128 MB video memory */ 116 QXL_MODE_EX(8192, 4320), /* 8k */ 117 }; 118 119 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 120 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 121 static void qxl_reset_memslots(PCIQXLDevice *d); 122 static void qxl_reset_surfaces(PCIQXLDevice *d); 123 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 124 125 static void qxl_hw_update(void *opaque); 126 127 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 128 { 129 trace_qxl_set_guest_bug(qxl->id); 130 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 131 qxl->guest_bug = 1; 132 if (qxl->guestdebug) { 133 va_list ap; 134 va_start(ap, msg); 135 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 136 vfprintf(stderr, msg, ap); 137 fprintf(stderr, "\n"); 138 va_end(ap); 139 } 140 } 141 142 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 143 { 144 qxl->guest_bug = 0; 145 } 146 147 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 148 struct QXLRect *area, struct QXLRect *dirty_rects, 149 uint32_t num_dirty_rects, 150 uint32_t clear_dirty_region, 151 qxl_async_io async, struct QXLCookie *cookie) 152 { 153 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 154 area->top, area->bottom); 155 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 156 clear_dirty_region); 157 if (async == QXL_SYNC) { 158 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 159 dirty_rects, num_dirty_rects, clear_dirty_region); 160 } else { 161 assert(cookie != NULL); 162 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 163 clear_dirty_region, (uintptr_t)cookie); 164 } 165 } 166 167 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 168 uint32_t id) 169 { 170 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 171 qemu_mutex_lock(&qxl->track_lock); 172 qxl->guest_surfaces.cmds[id] = 0; 173 qxl->guest_surfaces.count--; 174 qemu_mutex_unlock(&qxl->track_lock); 175 } 176 177 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 178 qxl_async_io async) 179 { 180 QXLCookie *cookie; 181 182 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 183 if (async) { 184 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 185 QXL_IO_DESTROY_SURFACE_ASYNC); 186 cookie->u.surface_id = id; 187 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 188 } else { 189 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 190 qxl_spice_destroy_surface_wait_complete(qxl, id); 191 } 192 } 193 194 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 195 { 196 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 197 qxl->num_free_res); 198 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 199 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 200 QXL_IO_FLUSH_SURFACES_ASYNC)); 201 } 202 203 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 204 uint32_t count) 205 { 206 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 207 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 208 } 209 210 void qxl_spice_oom(PCIQXLDevice *qxl) 211 { 212 trace_qxl_spice_oom(qxl->id); 213 spice_qxl_oom(&qxl->ssd.qxl); 214 } 215 216 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 217 { 218 trace_qxl_spice_reset_memslots(qxl->id); 219 spice_qxl_reset_memslots(&qxl->ssd.qxl); 220 } 221 222 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 223 { 224 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 225 qemu_mutex_lock(&qxl->track_lock); 226 memset(qxl->guest_surfaces.cmds, 0, 227 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 228 qxl->guest_surfaces.count = 0; 229 qemu_mutex_unlock(&qxl->track_lock); 230 } 231 232 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 233 { 234 trace_qxl_spice_destroy_surfaces(qxl->id, async); 235 if (async) { 236 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 237 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 238 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 239 } else { 240 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 241 qxl_spice_destroy_surfaces_complete(qxl); 242 } 243 } 244 245 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 246 { 247 QXLMonitorsConfig *cfg; 248 249 trace_qxl_spice_monitors_config(qxl->id); 250 if (replay) { 251 /* 252 * don't use QXL_COOKIE_TYPE_IO: 253 * - we are not running yet (post_load), we will assert 254 * in send_events 255 * - this is not a guest io, but a reply, so async_io isn't set. 256 */ 257 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 258 qxl->guest_monitors_config, 259 MEMSLOT_GROUP_GUEST, 260 (uintptr_t)qxl_cookie_new( 261 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 262 0)); 263 } else { 264 /* >= release 0.12.6, < release 0.14.2 */ 265 #if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02 266 if (qxl->max_outputs) { 267 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs); 268 } 269 #endif 270 qxl->guest_monitors_config = qxl->ram->monitors_config; 271 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 272 qxl->ram->monitors_config, 273 MEMSLOT_GROUP_GUEST, 274 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 275 QXL_IO_MONITORS_CONFIG_ASYNC)); 276 } 277 278 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST); 279 if (cfg != NULL && cfg->count == 1) { 280 qxl->guest_primary.resized = 1; 281 qxl->guest_head0_width = cfg->heads[0].width; 282 qxl->guest_head0_height = cfg->heads[0].height; 283 } else { 284 qxl->guest_head0_width = 0; 285 qxl->guest_head0_height = 0; 286 } 287 } 288 289 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 290 { 291 trace_qxl_spice_reset_image_cache(qxl->id); 292 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 293 } 294 295 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 296 { 297 trace_qxl_spice_reset_cursor(qxl->id); 298 spice_qxl_reset_cursor(&qxl->ssd.qxl); 299 qemu_mutex_lock(&qxl->track_lock); 300 qxl->guest_cursor = 0; 301 qemu_mutex_unlock(&qxl->track_lock); 302 if (qxl->ssd.cursor) { 303 cursor_put(qxl->ssd.cursor); 304 } 305 qxl->ssd.cursor = cursor_builtin_hidden(); 306 } 307 308 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 309 { 310 /* 311 * zlib xors the seed with 0xffffffff, and xors the result 312 * again with 0xffffffff; Both are not done with linux's crc32, 313 * which we want to be compatible with, so undo that. 314 */ 315 return crc32(0xffffffff, p, len) ^ 0xffffffff; 316 } 317 318 static ram_addr_t qxl_rom_size(void) 319 { 320 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes)) 321 #define QXL_ROM_SZ 8192 322 323 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ); 324 return QXL_ROM_SZ; 325 } 326 327 static void init_qxl_rom(PCIQXLDevice *d) 328 { 329 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 330 QXLModes *modes = (QXLModes *)(rom + 1); 331 uint32_t ram_header_size; 332 uint32_t surface0_area_size; 333 uint32_t num_pages; 334 uint32_t fb; 335 int i, n; 336 337 memset(rom, 0, d->rom_size); 338 339 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 340 rom->id = cpu_to_le32(d->id); 341 rom->log_level = cpu_to_le32(d->guestdebug); 342 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 343 344 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 345 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 346 rom->slots_start = 1; 347 rom->slots_end = NUM_MEMSLOTS - 1; 348 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 349 350 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 351 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 352 if (fb > d->vgamem_size) { 353 continue; 354 } 355 modes->modes[n].id = cpu_to_le32(i); 356 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 357 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 358 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 359 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 360 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 361 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 362 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 363 n++; 364 } 365 modes->n_modes = cpu_to_le32(n); 366 367 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 368 surface0_area_size = ALIGN(d->vgamem_size, 4096); 369 num_pages = d->vga.vram_size; 370 num_pages -= ram_header_size; 371 num_pages -= surface0_area_size; 372 num_pages = num_pages / QXL_PAGE_SIZE; 373 374 assert(ram_header_size + surface0_area_size <= d->vga.vram_size); 375 376 rom->draw_area_offset = cpu_to_le32(0); 377 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 378 rom->pages_offset = cpu_to_le32(surface0_area_size); 379 rom->num_pages = cpu_to_le32(num_pages); 380 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 381 382 if (d->xres && d->yres) { 383 /* needs linux kernel 4.12+ to work */ 384 rom->client_monitors_config.count = 1; 385 rom->client_monitors_config.heads[0].left = 0; 386 rom->client_monitors_config.heads[0].top = 0; 387 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres); 388 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres); 389 rom->client_monitors_config_crc = qxl_crc32( 390 (const uint8_t *)&rom->client_monitors_config, 391 sizeof(rom->client_monitors_config)); 392 } 393 394 d->shadow_rom = *rom; 395 d->rom = rom; 396 d->modes = modes; 397 } 398 399 static void init_qxl_ram(PCIQXLDevice *d) 400 { 401 uint8_t *buf; 402 uint32_t prod; 403 QXLReleaseRing *ring; 404 405 buf = d->vga.vram_ptr; 406 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 407 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 408 d->ram->int_pending = cpu_to_le32(0); 409 d->ram->int_mask = cpu_to_le32(0); 410 d->ram->update_surface = 0; 411 d->ram->monitors_config = 0; 412 SPICE_RING_INIT(&d->ram->cmd_ring); 413 SPICE_RING_INIT(&d->ram->cursor_ring); 414 SPICE_RING_INIT(&d->ram->release_ring); 415 416 ring = &d->ram->release_ring; 417 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); 418 assert(prod < ARRAY_SIZE(ring->items)); 419 ring->items[prod].el = 0; 420 421 qxl_ring_set_dirty(d); 422 } 423 424 /* can be called from spice server thread context */ 425 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 426 { 427 memory_region_set_dirty(mr, addr, end - addr); 428 } 429 430 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 431 { 432 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 433 } 434 435 /* called from spice server thread context only */ 436 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 437 { 438 void *base = qxl->vga.vram_ptr; 439 intptr_t offset; 440 441 offset = ptr - base; 442 assert(offset < qxl->vga.vram_size); 443 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 444 } 445 446 /* can be called from spice server thread context */ 447 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 448 { 449 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 450 ram_addr_t end = qxl->vga.vram_size; 451 qxl_set_dirty(&qxl->vga.vram, addr, end); 452 } 453 454 /* 455 * keep track of some command state, for savevm/loadvm. 456 * called from spice server thread context only 457 */ 458 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 459 { 460 switch (le32_to_cpu(ext->cmd.type)) { 461 case QXL_CMD_SURFACE: 462 { 463 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 464 465 if (!cmd) { 466 return 1; 467 } 468 uint32_t id = le32_to_cpu(cmd->surface_id); 469 470 if (id >= qxl->ssd.num_surfaces) { 471 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 472 qxl->ssd.num_surfaces); 473 return 1; 474 } 475 if (cmd->type == QXL_SURFACE_CMD_CREATE && 476 (cmd->u.surface_create.stride & 0x03) != 0) { 477 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 478 cmd->u.surface_create.stride); 479 return 1; 480 } 481 WITH_QEMU_LOCK_GUARD(&qxl->track_lock) { 482 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 483 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 484 qxl->guest_surfaces.count++; 485 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) { 486 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 487 } 488 } 489 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 490 qxl->guest_surfaces.cmds[id] = 0; 491 qxl->guest_surfaces.count--; 492 } 493 } 494 break; 495 } 496 case QXL_CMD_CURSOR: 497 { 498 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 499 500 if (!cmd) { 501 return 1; 502 } 503 if (cmd->type == QXL_CURSOR_SET) { 504 qemu_mutex_lock(&qxl->track_lock); 505 qxl->guest_cursor = ext->cmd.data; 506 qemu_mutex_unlock(&qxl->track_lock); 507 } 508 if (cmd->type == QXL_CURSOR_HIDE) { 509 qemu_mutex_lock(&qxl->track_lock); 510 qxl->guest_cursor = 0; 511 qemu_mutex_unlock(&qxl->track_lock); 512 } 513 break; 514 } 515 } 516 return 0; 517 } 518 519 /* spice display interface callbacks */ 520 521 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 522 { 523 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 524 525 trace_qxl_interface_attach_worker(qxl->id); 526 } 527 528 static void interface_set_compression_level(QXLInstance *sin, int level) 529 { 530 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 531 532 trace_qxl_interface_set_compression_level(qxl->id, level); 533 qxl->shadow_rom.compression_level = cpu_to_le32(level); 534 qxl->rom->compression_level = cpu_to_le32(level); 535 qxl_rom_set_dirty(qxl); 536 } 537 538 #if SPICE_NEEDS_SET_MM_TIME 539 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 540 { 541 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 542 543 if (!qemu_spice_display_is_running(&qxl->ssd)) { 544 return; 545 } 546 547 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 548 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 549 qxl->rom->mm_clock = cpu_to_le32(mm_time); 550 qxl_rom_set_dirty(qxl); 551 } 552 #endif 553 554 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 555 { 556 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 557 558 trace_qxl_interface_get_init_info(qxl->id); 559 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 560 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 561 info->num_memslots = NUM_MEMSLOTS; 562 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 563 info->internal_groupslot_id = 0; 564 info->qxl_ram_size = 565 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 566 info->n_surfaces = qxl->ssd.num_surfaces; 567 } 568 569 static const char *qxl_mode_to_string(int mode) 570 { 571 switch (mode) { 572 case QXL_MODE_COMPAT: 573 return "compat"; 574 case QXL_MODE_NATIVE: 575 return "native"; 576 case QXL_MODE_UNDEFINED: 577 return "undefined"; 578 case QXL_MODE_VGA: 579 return "vga"; 580 } 581 return "INVALID"; 582 } 583 584 static const char *io_port_to_string(uint32_t io_port) 585 { 586 if (io_port >= QXL_IO_RANGE_SIZE) { 587 return "out of range"; 588 } 589 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 590 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 591 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 592 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 593 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 594 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 595 [QXL_IO_RESET] = "QXL_IO_RESET", 596 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 597 [QXL_IO_LOG] = "QXL_IO_LOG", 598 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 599 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 600 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 601 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 602 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 603 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 604 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 605 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 606 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 607 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 608 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 609 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 610 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 611 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 612 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 613 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 614 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 615 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 616 }; 617 return io_port_to_string[io_port]; 618 } 619 620 /* called from spice server thread context only */ 621 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 622 { 623 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 624 SimpleSpiceUpdate *update; 625 QXLCommandRing *ring; 626 QXLCommand *cmd; 627 int notify, ret; 628 629 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 630 631 switch (qxl->mode) { 632 case QXL_MODE_VGA: 633 ret = false; 634 qemu_mutex_lock(&qxl->ssd.lock); 635 update = QTAILQ_FIRST(&qxl->ssd.updates); 636 if (update != NULL) { 637 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 638 *ext = update->ext; 639 ret = true; 640 } 641 qemu_mutex_unlock(&qxl->ssd.lock); 642 if (ret) { 643 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 644 qxl_log_command(qxl, "vga", ext); 645 } 646 return ret; 647 case QXL_MODE_COMPAT: 648 case QXL_MODE_NATIVE: 649 case QXL_MODE_UNDEFINED: 650 ring = &qxl->ram->cmd_ring; 651 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 652 return false; 653 } 654 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 655 if (!cmd) { 656 return false; 657 } 658 ext->cmd = *cmd; 659 ext->group_id = MEMSLOT_GROUP_GUEST; 660 ext->flags = qxl->cmdflags; 661 SPICE_RING_POP(ring, notify); 662 qxl_ring_set_dirty(qxl); 663 if (notify) { 664 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 665 } 666 qxl->guest_primary.commands++; 667 qxl_track_command(qxl, ext); 668 qxl_log_command(qxl, "cmd", ext); 669 { 670 /* 671 * Windows 8 drivers place qxl commands in the vram 672 * (instead of the ram) bar. We can't live migrate such a 673 * guest, so add a migration blocker in case we detect 674 * this, to avoid triggering the assert in pre_save(). 675 * 676 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa 677 */ 678 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 679 if (msg != NULL && ( 680 msg < (void *)qxl->vga.vram_ptr || 681 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) { 682 if (!qxl->migration_blocker) { 683 Error *local_err = NULL; 684 error_setg(&qxl->migration_blocker, 685 "qxl: guest bug: command not in ram bar"); 686 migrate_add_blocker(qxl->migration_blocker, &local_err); 687 if (local_err) { 688 error_report_err(local_err); 689 } 690 } 691 } 692 } 693 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 694 return true; 695 default: 696 return false; 697 } 698 } 699 700 /* called from spice server thread context only */ 701 static int interface_req_cmd_notification(QXLInstance *sin) 702 { 703 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 704 int wait = 1; 705 706 trace_qxl_ring_command_req_notification(qxl->id); 707 switch (qxl->mode) { 708 case QXL_MODE_COMPAT: 709 case QXL_MODE_NATIVE: 710 case QXL_MODE_UNDEFINED: 711 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 712 qxl_ring_set_dirty(qxl); 713 break; 714 default: 715 /* nothing */ 716 break; 717 } 718 return wait; 719 } 720 721 /* called from spice server thread context only */ 722 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 723 { 724 QXLReleaseRing *ring = &d->ram->release_ring; 725 uint32_t prod; 726 int notify; 727 728 #define QXL_FREE_BUNCH_SIZE 32 729 730 if (ring->prod - ring->cons + 1 == ring->num_items) { 731 /* ring full -- can't push */ 732 return; 733 } 734 if (!flush && d->oom_running) { 735 /* collect everything from oom handler before pushing */ 736 return; 737 } 738 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 739 /* collect a bit more before pushing */ 740 return; 741 } 742 743 SPICE_RING_PUSH(ring, notify); 744 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 745 d->guest_surfaces.count, d->num_free_res, 746 d->last_release, notify ? "yes" : "no"); 747 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 748 ring->num_items, ring->prod, ring->cons); 749 if (notify) { 750 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 751 } 752 753 ring = &d->ram->release_ring; 754 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); 755 if (prod >= ARRAY_SIZE(ring->items)) { 756 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch " 757 "%u >= %zu", prod, ARRAY_SIZE(ring->items)); 758 return; 759 } 760 ring->items[prod].el = 0; 761 d->num_free_res = 0; 762 d->last_release = NULL; 763 qxl_ring_set_dirty(d); 764 } 765 766 /* called from spice server thread context only */ 767 static void interface_release_resource(QXLInstance *sin, 768 QXLReleaseInfoExt ext) 769 { 770 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 771 QXLReleaseRing *ring; 772 uint32_t prod; 773 uint64_t id; 774 775 if (!ext.info) { 776 return; 777 } 778 if (ext.group_id == MEMSLOT_GROUP_HOST) { 779 /* host group -> vga mode update request */ 780 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 781 SimpleSpiceUpdate *update; 782 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 783 update = container_of(cmdext, SimpleSpiceUpdate, ext); 784 qemu_spice_destroy_update(&qxl->ssd, update); 785 return; 786 } 787 788 /* 789 * ext->info points into guest-visible memory 790 * pci bar 0, $command.release_info 791 */ 792 ring = &qxl->ram->release_ring; 793 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); 794 if (prod >= ARRAY_SIZE(ring->items)) { 795 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " 796 "%u >= %zu", prod, ARRAY_SIZE(ring->items)); 797 return; 798 } 799 if (ring->items[prod].el == 0) { 800 /* stick head into the ring */ 801 id = ext.info->id; 802 ext.info->next = 0; 803 qxl_ram_set_dirty(qxl, &ext.info->next); 804 ring->items[prod].el = id; 805 qxl_ring_set_dirty(qxl); 806 } else { 807 /* append item to the list */ 808 qxl->last_release->next = ext.info->id; 809 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 810 ext.info->next = 0; 811 qxl_ram_set_dirty(qxl, &ext.info->next); 812 } 813 qxl->last_release = ext.info; 814 qxl->num_free_res++; 815 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 816 qxl_push_free_res(qxl, 0); 817 } 818 819 /* called from spice server thread context only */ 820 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 821 { 822 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 823 QXLCursorRing *ring; 824 QXLCommand *cmd; 825 int notify; 826 827 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 828 829 switch (qxl->mode) { 830 case QXL_MODE_COMPAT: 831 case QXL_MODE_NATIVE: 832 case QXL_MODE_UNDEFINED: 833 ring = &qxl->ram->cursor_ring; 834 if (SPICE_RING_IS_EMPTY(ring)) { 835 return false; 836 } 837 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 838 if (!cmd) { 839 return false; 840 } 841 ext->cmd = *cmd; 842 ext->group_id = MEMSLOT_GROUP_GUEST; 843 ext->flags = qxl->cmdflags; 844 SPICE_RING_POP(ring, notify); 845 qxl_ring_set_dirty(qxl); 846 if (notify) { 847 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 848 } 849 qxl->guest_primary.commands++; 850 qxl_track_command(qxl, ext); 851 qxl_log_command(qxl, "csr", ext); 852 if (qxl->have_vga) { 853 qxl_render_cursor(qxl, ext); 854 } 855 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 856 return true; 857 default: 858 return false; 859 } 860 } 861 862 /* called from spice server thread context only */ 863 static int interface_req_cursor_notification(QXLInstance *sin) 864 { 865 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 866 int wait = 1; 867 868 trace_qxl_ring_cursor_req_notification(qxl->id); 869 switch (qxl->mode) { 870 case QXL_MODE_COMPAT: 871 case QXL_MODE_NATIVE: 872 case QXL_MODE_UNDEFINED: 873 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 874 qxl_ring_set_dirty(qxl); 875 break; 876 default: 877 /* nothing */ 878 break; 879 } 880 return wait; 881 } 882 883 /* called from spice server thread context */ 884 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 885 { 886 /* 887 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 888 * use by xf86-video-qxl and is defined out in the qxl windows driver. 889 * Probably was at some earlier version that is prior to git start (2009), 890 * and is still guest trigerrable. 891 */ 892 fprintf(stderr, "%s: deprecated\n", __func__); 893 } 894 895 /* called from spice server thread context only */ 896 static int interface_flush_resources(QXLInstance *sin) 897 { 898 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 899 int ret; 900 901 ret = qxl->num_free_res; 902 if (ret) { 903 qxl_push_free_res(qxl, 1); 904 } 905 return ret; 906 } 907 908 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 909 910 /* called from spice server thread context only */ 911 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 912 { 913 uint32_t current_async; 914 915 qemu_mutex_lock(&qxl->async_lock); 916 current_async = qxl->current_async; 917 qxl->current_async = QXL_UNDEFINED_IO; 918 qemu_mutex_unlock(&qxl->async_lock); 919 920 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 921 if (!cookie) { 922 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 923 return; 924 } 925 if (cookie && current_async != cookie->io) { 926 fprintf(stderr, 927 "qxl: %s: error: current_async = %d != %" 928 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 929 } 930 switch (current_async) { 931 case QXL_IO_MEMSLOT_ADD_ASYNC: 932 case QXL_IO_DESTROY_PRIMARY_ASYNC: 933 case QXL_IO_UPDATE_AREA_ASYNC: 934 case QXL_IO_FLUSH_SURFACES_ASYNC: 935 case QXL_IO_MONITORS_CONFIG_ASYNC: 936 break; 937 case QXL_IO_CREATE_PRIMARY_ASYNC: 938 qxl_create_guest_primary_complete(qxl); 939 break; 940 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 941 qxl_spice_destroy_surfaces_complete(qxl); 942 break; 943 case QXL_IO_DESTROY_SURFACE_ASYNC: 944 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 945 break; 946 default: 947 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 948 current_async); 949 } 950 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 951 } 952 953 /* called from spice server thread context only */ 954 static void interface_update_area_complete(QXLInstance *sin, 955 uint32_t surface_id, 956 QXLRect *dirty, uint32_t num_updated_rects) 957 { 958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 959 int i; 960 int qxl_i; 961 962 QEMU_LOCK_GUARD(&qxl->ssd.lock); 963 if (surface_id != 0 || !num_updated_rects || 964 !qxl->render_update_cookie_num) { 965 return; 966 } 967 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 968 dirty->right, dirty->top, dirty->bottom); 969 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 970 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 971 /* 972 * overflow - treat this as a full update. Not expected to be common. 973 */ 974 trace_qxl_interface_update_area_complete_overflow(qxl->id, 975 QXL_NUM_DIRTY_RECTS); 976 qxl->guest_primary.resized = 1; 977 } 978 if (qxl->guest_primary.resized) { 979 /* 980 * Don't bother copying or scheduling the bh since we will flip 981 * the whole area anyway on completion of the update_area async call 982 */ 983 return; 984 } 985 qxl_i = qxl->num_dirty_rects; 986 for (i = 0; i < num_updated_rects; i++) { 987 qxl->dirty[qxl_i++] = dirty[i]; 988 } 989 qxl->num_dirty_rects += num_updated_rects; 990 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 991 qxl->num_dirty_rects); 992 qemu_bh_schedule(qxl->update_area_bh); 993 } 994 995 /* called from spice server thread context only */ 996 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 997 { 998 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 999 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 1000 1001 switch (cookie->type) { 1002 case QXL_COOKIE_TYPE_IO: 1003 interface_async_complete_io(qxl, cookie); 1004 g_free(cookie); 1005 break; 1006 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 1007 qxl_render_update_area_done(qxl, cookie); 1008 break; 1009 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 1010 break; 1011 default: 1012 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 1013 __func__, cookie->type); 1014 g_free(cookie); 1015 } 1016 } 1017 1018 /* called from spice server thread context only */ 1019 static void interface_set_client_capabilities(QXLInstance *sin, 1020 uint8_t client_present, 1021 uint8_t caps[58]) 1022 { 1023 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1024 1025 if (qxl->revision < 4) { 1026 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 1027 qxl->revision); 1028 return; 1029 } 1030 1031 if (runstate_check(RUN_STATE_INMIGRATE) || 1032 runstate_check(RUN_STATE_POSTMIGRATE)) { 1033 return; 1034 } 1035 1036 qxl->shadow_rom.client_present = client_present; 1037 memcpy(qxl->shadow_rom.client_capabilities, caps, 1038 sizeof(qxl->shadow_rom.client_capabilities)); 1039 qxl->rom->client_present = client_present; 1040 memcpy(qxl->rom->client_capabilities, caps, 1041 sizeof(qxl->rom->client_capabilities)); 1042 qxl_rom_set_dirty(qxl); 1043 1044 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 1045 } 1046 1047 static bool qxl_rom_monitors_config_changed(QXLRom *rom, 1048 VDAgentMonitorsConfig *monitors_config, 1049 unsigned int max_outputs) 1050 { 1051 int i; 1052 unsigned int monitors_count; 1053 1054 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs); 1055 1056 if (rom->client_monitors_config.count != monitors_count) { 1057 return true; 1058 } 1059 1060 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1061 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1062 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1063 /* monitor->depth ignored */ 1064 if ((rect->left != monitor->x) || 1065 (rect->top != monitor->y) || 1066 (rect->right != monitor->x + monitor->width) || 1067 (rect->bottom != monitor->y + monitor->height)) { 1068 return true; 1069 } 1070 } 1071 1072 return false; 1073 } 1074 1075 /* called from main context only */ 1076 static int interface_client_monitors_config(QXLInstance *sin, 1077 VDAgentMonitorsConfig *monitors_config) 1078 { 1079 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1080 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 1081 int i; 1082 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads); 1083 bool config_changed = false; 1084 1085 if (qxl->revision < 4) { 1086 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 1087 qxl->revision); 1088 return 0; 1089 } 1090 /* 1091 * Older windows drivers set int_mask to 0 when their ISR is called, 1092 * then later set it to ~0. So it doesn't relate to the actual interrupts 1093 * handled. However, they are old, so clearly they don't support this 1094 * interrupt 1095 */ 1096 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1097 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1098 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1099 qxl->ram->int_mask, 1100 monitors_config); 1101 return 0; 1102 } 1103 if (!monitors_config) { 1104 return 1; 1105 } 1106 1107 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 1108 /* limit number of outputs based on setting limit */ 1109 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) { 1110 max_outputs = qxl->max_outputs; 1111 } 1112 #endif 1113 1114 config_changed = qxl_rom_monitors_config_changed(rom, 1115 monitors_config, 1116 max_outputs); 1117 1118 memset(&rom->client_monitors_config, 0, 1119 sizeof(rom->client_monitors_config)); 1120 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1121 /* monitors_config->flags ignored */ 1122 if (rom->client_monitors_config.count >= max_outputs) { 1123 trace_qxl_client_monitors_config_capped(qxl->id, 1124 monitors_config->num_of_monitors, 1125 max_outputs); 1126 rom->client_monitors_config.count = max_outputs; 1127 } 1128 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1129 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1130 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1131 /* monitor->depth ignored */ 1132 rect->left = monitor->x; 1133 rect->top = monitor->y; 1134 rect->right = monitor->x + monitor->width; 1135 rect->bottom = monitor->y + monitor->height; 1136 } 1137 rom->client_monitors_config_crc = qxl_crc32( 1138 (const uint8_t *)&rom->client_monitors_config, 1139 sizeof(rom->client_monitors_config)); 1140 trace_qxl_client_monitors_config_crc(qxl->id, 1141 sizeof(rom->client_monitors_config), 1142 rom->client_monitors_config_crc); 1143 1144 trace_qxl_interrupt_client_monitors_config(qxl->id, 1145 rom->client_monitors_config.count, 1146 rom->client_monitors_config.heads); 1147 if (config_changed) { 1148 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1149 } 1150 return 1; 1151 } 1152 1153 static const QXLInterface qxl_interface = { 1154 .base.type = SPICE_INTERFACE_QXL, 1155 .base.description = "qxl gpu", 1156 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1157 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1158 1159 .attache_worker = interface_attach_worker, 1160 .set_compression_level = interface_set_compression_level, 1161 #if SPICE_NEEDS_SET_MM_TIME 1162 .set_mm_time = interface_set_mm_time, 1163 #endif 1164 .get_init_info = interface_get_init_info, 1165 1166 /* the callbacks below are called from spice server thread context */ 1167 .get_command = interface_get_command, 1168 .req_cmd_notification = interface_req_cmd_notification, 1169 .release_resource = interface_release_resource, 1170 .get_cursor_command = interface_get_cursor_command, 1171 .req_cursor_notification = interface_req_cursor_notification, 1172 .notify_update = interface_notify_update, 1173 .flush_resources = interface_flush_resources, 1174 .async_complete = interface_async_complete, 1175 .update_area_complete = interface_update_area_complete, 1176 .set_client_capabilities = interface_set_client_capabilities, 1177 .client_monitors_config = interface_client_monitors_config, 1178 }; 1179 1180 static const GraphicHwOps qxl_ops = { 1181 .gfx_update = qxl_hw_update, 1182 .gfx_update_async = true, 1183 }; 1184 1185 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1186 { 1187 if (d->mode == QXL_MODE_VGA) { 1188 return; 1189 } 1190 trace_qxl_enter_vga_mode(d->id); 1191 spice_qxl_driver_unload(&d->ssd.qxl); 1192 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); 1193 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); 1194 qemu_spice_create_host_primary(&d->ssd); 1195 d->mode = QXL_MODE_VGA; 1196 qemu_spice_display_switch(&d->ssd, d->ssd.ds); 1197 vga_dirty_log_start(&d->vga); 1198 graphic_hw_update(d->vga.con); 1199 } 1200 1201 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1202 { 1203 if (d->mode != QXL_MODE_VGA) { 1204 return; 1205 } 1206 trace_qxl_exit_vga_mode(d->id); 1207 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); 1208 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1209 vga_dirty_log_stop(&d->vga); 1210 qxl_destroy_primary(d, QXL_SYNC); 1211 } 1212 1213 static void qxl_update_irq(PCIQXLDevice *d) 1214 { 1215 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1216 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1217 int level = !!(pending & mask); 1218 pci_set_irq(&d->pci, level); 1219 qxl_ring_set_dirty(d); 1220 } 1221 1222 static void qxl_check_state(PCIQXLDevice *d) 1223 { 1224 QXLRam *ram = d->ram; 1225 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1226 1227 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1228 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1229 } 1230 1231 static void qxl_reset_state(PCIQXLDevice *d) 1232 { 1233 QXLRom *rom = d->rom; 1234 1235 qxl_check_state(d); 1236 d->shadow_rom.update_id = cpu_to_le32(0); 1237 *rom = d->shadow_rom; 1238 qxl_rom_set_dirty(d); 1239 init_qxl_ram(d); 1240 d->num_free_res = 0; 1241 d->last_release = NULL; 1242 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1243 qxl_update_irq(d); 1244 } 1245 1246 static void qxl_soft_reset(PCIQXLDevice *d) 1247 { 1248 trace_qxl_soft_reset(d->id); 1249 qxl_check_state(d); 1250 qxl_clear_guest_bug(d); 1251 qemu_mutex_lock(&d->async_lock); 1252 d->current_async = QXL_UNDEFINED_IO; 1253 qemu_mutex_unlock(&d->async_lock); 1254 1255 if (d->have_vga) { 1256 qxl_enter_vga_mode(d); 1257 } else { 1258 d->mode = QXL_MODE_UNDEFINED; 1259 } 1260 } 1261 1262 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1263 { 1264 bool startstop = qemu_spice_display_is_running(&d->ssd); 1265 1266 trace_qxl_hard_reset(d->id, loadvm); 1267 1268 if (startstop) { 1269 qemu_spice_display_stop(); 1270 } 1271 1272 qxl_spice_reset_cursor(d); 1273 qxl_spice_reset_image_cache(d); 1274 qxl_reset_surfaces(d); 1275 qxl_reset_memslots(d); 1276 1277 /* pre loadvm reset must not touch QXLRam. This lives in 1278 * device memory, is migrated together with RAM and thus 1279 * already loaded at this point */ 1280 if (!loadvm) { 1281 qxl_reset_state(d); 1282 } 1283 qemu_spice_create_host_memslot(&d->ssd); 1284 qxl_soft_reset(d); 1285 1286 if (d->migration_blocker) { 1287 migrate_del_blocker(d->migration_blocker); 1288 error_free(d->migration_blocker); 1289 d->migration_blocker = NULL; 1290 } 1291 1292 if (startstop) { 1293 qemu_spice_display_start(); 1294 } 1295 } 1296 1297 static void qxl_reset_handler(DeviceState *dev) 1298 { 1299 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev)); 1300 1301 qxl_hard_reset(d, 0); 1302 } 1303 1304 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1305 { 1306 VGACommonState *vga = opaque; 1307 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1308 1309 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1310 if (qxl->mode != QXL_MODE_VGA && 1311 qxl->revision <= QXL_REVISION_STABLE_V12) { 1312 qxl_destroy_primary(qxl, QXL_SYNC); 1313 qxl_soft_reset(qxl); 1314 } 1315 vga_ioport_write(opaque, addr, val); 1316 } 1317 1318 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1319 { 0x04, 2, 1, .read = vga_ioport_read, 1320 .write = qxl_vga_ioport_write }, /* 3b4 */ 1321 { 0x0a, 1, 1, .read = vga_ioport_read, 1322 .write = qxl_vga_ioport_write }, /* 3ba */ 1323 { 0x10, 16, 1, .read = vga_ioport_read, 1324 .write = qxl_vga_ioport_write }, /* 3c0 */ 1325 { 0x24, 2, 1, .read = vga_ioport_read, 1326 .write = qxl_vga_ioport_write }, /* 3d4 */ 1327 { 0x2a, 1, 1, .read = vga_ioport_read, 1328 .write = qxl_vga_ioport_write }, /* 3da */ 1329 PORTIO_END_OF_LIST(), 1330 }; 1331 1332 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1333 qxl_async_io async) 1334 { 1335 static const int regions[] = { 1336 QXL_RAM_RANGE_INDEX, 1337 QXL_VRAM_RANGE_INDEX, 1338 QXL_VRAM64_RANGE_INDEX, 1339 }; 1340 uint64_t guest_start; 1341 uint64_t guest_end; 1342 int pci_region; 1343 pcibus_t pci_start; 1344 pcibus_t pci_end; 1345 MemoryRegion *mr; 1346 intptr_t virt_start; 1347 QXLDevMemSlot memslot; 1348 int i; 1349 1350 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1351 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1352 1353 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1354 1355 if (slot_id >= NUM_MEMSLOTS) { 1356 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1357 slot_id, NUM_MEMSLOTS); 1358 return 1; 1359 } 1360 if (guest_start > guest_end) { 1361 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1362 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1363 return 1; 1364 } 1365 1366 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1367 pci_region = regions[i]; 1368 pci_start = d->pci.io_regions[pci_region].addr; 1369 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1370 /* mapped? */ 1371 if (pci_start == -1) { 1372 continue; 1373 } 1374 /* start address in range ? */ 1375 if (guest_start < pci_start || guest_start > pci_end) { 1376 continue; 1377 } 1378 /* end address in range ? */ 1379 if (guest_end > pci_end) { 1380 continue; 1381 } 1382 /* passed */ 1383 break; 1384 } 1385 if (i == ARRAY_SIZE(regions)) { 1386 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1387 return 1; 1388 } 1389 1390 switch (pci_region) { 1391 case QXL_RAM_RANGE_INDEX: 1392 mr = &d->vga.vram; 1393 break; 1394 case QXL_VRAM_RANGE_INDEX: 1395 case 4 /* vram 64bit */: 1396 mr = &d->vram_bar; 1397 break; 1398 default: 1399 /* should not happen */ 1400 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1401 return 1; 1402 } 1403 1404 virt_start = (intptr_t)memory_region_get_ram_ptr(mr); 1405 memslot.slot_id = slot_id; 1406 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1407 memslot.virt_start = virt_start + (guest_start - pci_start); 1408 memslot.virt_end = virt_start + (guest_end - pci_start); 1409 memslot.addr_delta = memslot.virt_start - delta; 1410 memslot.generation = d->rom->slot_generation = 0; 1411 qxl_rom_set_dirty(d); 1412 1413 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1414 d->guest_slots[slot_id].mr = mr; 1415 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start; 1416 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1417 d->guest_slots[slot_id].delta = delta; 1418 d->guest_slots[slot_id].active = 1; 1419 return 0; 1420 } 1421 1422 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1423 { 1424 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1425 d->guest_slots[slot_id].active = 0; 1426 } 1427 1428 static void qxl_reset_memslots(PCIQXLDevice *d) 1429 { 1430 qxl_spice_reset_memslots(d); 1431 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1432 } 1433 1434 static void qxl_reset_surfaces(PCIQXLDevice *d) 1435 { 1436 trace_qxl_reset_surfaces(d->id); 1437 d->mode = QXL_MODE_UNDEFINED; 1438 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1439 } 1440 1441 /* can be also called from spice server thread context */ 1442 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1443 uint32_t *s, uint64_t *o) 1444 { 1445 uint64_t phys = le64_to_cpu(pqxl); 1446 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1447 uint64_t offset = phys & 0xffffffffffff; 1448 1449 if (slot >= NUM_MEMSLOTS) { 1450 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1451 NUM_MEMSLOTS); 1452 return false; 1453 } 1454 if (!qxl->guest_slots[slot].active) { 1455 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1456 return false; 1457 } 1458 if (offset < qxl->guest_slots[slot].delta) { 1459 qxl_set_guest_bug(qxl, 1460 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1461 slot, offset, qxl->guest_slots[slot].delta); 1462 return false; 1463 } 1464 offset -= qxl->guest_slots[slot].delta; 1465 if (offset > qxl->guest_slots[slot].size) { 1466 qxl_set_guest_bug(qxl, 1467 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1468 slot, offset, qxl->guest_slots[slot].size); 1469 return false; 1470 } 1471 1472 *s = slot; 1473 *o = offset; 1474 return true; 1475 } 1476 1477 /* can be also called from spice server thread context */ 1478 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1479 { 1480 uint64_t offset; 1481 uint32_t slot; 1482 void *ptr; 1483 1484 switch (group_id) { 1485 case MEMSLOT_GROUP_HOST: 1486 offset = le64_to_cpu(pqxl) & 0xffffffffffff; 1487 return (void *)(intptr_t)offset; 1488 case MEMSLOT_GROUP_GUEST: 1489 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) { 1490 return NULL; 1491 } 1492 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr); 1493 ptr += qxl->guest_slots[slot].offset; 1494 ptr += offset; 1495 return ptr; 1496 } 1497 return NULL; 1498 } 1499 1500 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1501 { 1502 /* for local rendering */ 1503 qxl_render_resize(qxl); 1504 } 1505 1506 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1507 qxl_async_io async) 1508 { 1509 QXLDevSurfaceCreate surface; 1510 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1511 uint32_t requested_height = le32_to_cpu(sc->height); 1512 int requested_stride = le32_to_cpu(sc->stride); 1513 1514 if (requested_stride == INT32_MIN || 1515 abs(requested_stride) * (uint64_t)requested_height 1516 > qxl->vgamem_size) { 1517 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1518 " stride %d x height %" PRIu32 " > %" PRIu32, 1519 __func__, requested_stride, requested_height, 1520 qxl->vgamem_size); 1521 return; 1522 } 1523 1524 if (qxl->mode == QXL_MODE_NATIVE) { 1525 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1526 __func__); 1527 } 1528 qxl_exit_vga_mode(qxl); 1529 1530 surface.format = le32_to_cpu(sc->format); 1531 surface.height = le32_to_cpu(sc->height); 1532 surface.mem = le64_to_cpu(sc->mem); 1533 surface.position = le32_to_cpu(sc->position); 1534 surface.stride = le32_to_cpu(sc->stride); 1535 surface.width = le32_to_cpu(sc->width); 1536 surface.type = le32_to_cpu(sc->type); 1537 surface.flags = le32_to_cpu(sc->flags); 1538 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1539 sc->format, sc->position); 1540 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1541 sc->flags); 1542 1543 if ((surface.stride & 0x3) != 0) { 1544 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1545 surface.stride); 1546 return; 1547 } 1548 1549 surface.mouse_mode = true; 1550 surface.group_id = MEMSLOT_GROUP_GUEST; 1551 if (loadvm) { 1552 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1553 } 1554 1555 qxl->mode = QXL_MODE_NATIVE; 1556 qxl->cmdflags = 0; 1557 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1558 1559 if (async == QXL_SYNC) { 1560 qxl_create_guest_primary_complete(qxl); 1561 } 1562 } 1563 1564 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1565 * done (in QXL_SYNC case), 0 otherwise. */ 1566 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1567 { 1568 if (d->mode == QXL_MODE_UNDEFINED) { 1569 return 0; 1570 } 1571 trace_qxl_destroy_primary(d->id); 1572 d->mode = QXL_MODE_UNDEFINED; 1573 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1574 qxl_spice_reset_cursor(d); 1575 return 1; 1576 } 1577 1578 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1579 { 1580 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1581 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1582 QXLMode *mode = d->modes->modes + modenr; 1583 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1584 QXLMemSlot slot = { 1585 .mem_start = start, 1586 .mem_end = end 1587 }; 1588 1589 if (modenr >= d->modes->n_modes) { 1590 qxl_set_guest_bug(d, "mode number out of range"); 1591 return; 1592 } 1593 1594 QXLSurfaceCreate surface = { 1595 .width = mode->x_res, 1596 .height = mode->y_res, 1597 .stride = -mode->x_res * 4, 1598 .format = SPICE_SURFACE_FMT_32_xRGB, 1599 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1600 .mouse_mode = true, 1601 .mem = devmem + d->shadow_rom.draw_area_offset, 1602 }; 1603 1604 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1605 devmem); 1606 if (!loadvm) { 1607 qxl_hard_reset(d, 0); 1608 } 1609 1610 d->guest_slots[0].slot = slot; 1611 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1612 1613 d->guest_primary.surface = surface; 1614 qxl_create_guest_primary(d, 0, QXL_SYNC); 1615 1616 d->mode = QXL_MODE_COMPAT; 1617 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1618 if (mode->bits == 16) { 1619 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1620 } 1621 d->shadow_rom.mode = cpu_to_le32(modenr); 1622 d->rom->mode = cpu_to_le32(modenr); 1623 qxl_rom_set_dirty(d); 1624 } 1625 1626 static void ioport_write(void *opaque, hwaddr addr, 1627 uint64_t val, unsigned size) 1628 { 1629 PCIQXLDevice *d = opaque; 1630 uint32_t io_port = addr; 1631 qxl_async_io async = QXL_SYNC; 1632 uint32_t orig_io_port; 1633 1634 if (d->guest_bug && io_port != QXL_IO_RESET) { 1635 return; 1636 } 1637 1638 if (d->revision <= QXL_REVISION_STABLE_V10 && 1639 io_port > QXL_IO_FLUSH_RELEASE) { 1640 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1641 io_port, d->revision); 1642 return; 1643 } 1644 1645 switch (io_port) { 1646 case QXL_IO_RESET: 1647 case QXL_IO_SET_MODE: 1648 case QXL_IO_MEMSLOT_ADD: 1649 case QXL_IO_MEMSLOT_DEL: 1650 case QXL_IO_CREATE_PRIMARY: 1651 case QXL_IO_UPDATE_IRQ: 1652 case QXL_IO_LOG: 1653 case QXL_IO_MEMSLOT_ADD_ASYNC: 1654 case QXL_IO_CREATE_PRIMARY_ASYNC: 1655 break; 1656 default: 1657 if (d->mode != QXL_MODE_VGA) { 1658 break; 1659 } 1660 trace_qxl_io_unexpected_vga_mode(d->id, 1661 addr, val, io_port_to_string(io_port)); 1662 /* be nice to buggy guest drivers */ 1663 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1664 io_port < QXL_IO_RANGE_SIZE) { 1665 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1666 } 1667 return; 1668 } 1669 1670 /* we change the io_port to avoid ifdeffery in the main switch */ 1671 orig_io_port = io_port; 1672 switch (io_port) { 1673 case QXL_IO_UPDATE_AREA_ASYNC: 1674 io_port = QXL_IO_UPDATE_AREA; 1675 goto async_common; 1676 case QXL_IO_MEMSLOT_ADD_ASYNC: 1677 io_port = QXL_IO_MEMSLOT_ADD; 1678 goto async_common; 1679 case QXL_IO_CREATE_PRIMARY_ASYNC: 1680 io_port = QXL_IO_CREATE_PRIMARY; 1681 goto async_common; 1682 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1683 io_port = QXL_IO_DESTROY_PRIMARY; 1684 goto async_common; 1685 case QXL_IO_DESTROY_SURFACE_ASYNC: 1686 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1687 goto async_common; 1688 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1689 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1690 goto async_common; 1691 case QXL_IO_FLUSH_SURFACES_ASYNC: 1692 case QXL_IO_MONITORS_CONFIG_ASYNC: 1693 async_common: 1694 async = QXL_ASYNC; 1695 WITH_QEMU_LOCK_GUARD(&d->async_lock) { 1696 if (d->current_async != QXL_UNDEFINED_IO) { 1697 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1698 io_port, d->current_async); 1699 return; 1700 } 1701 d->current_async = orig_io_port; 1702 } 1703 break; 1704 default: 1705 break; 1706 } 1707 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1708 addr, io_port_to_string(addr), 1709 val, size, async); 1710 1711 switch (io_port) { 1712 case QXL_IO_UPDATE_AREA: 1713 { 1714 QXLCookie *cookie = NULL; 1715 QXLRect update = d->ram->update_area; 1716 1717 if (d->ram->update_surface > d->ssd.num_surfaces) { 1718 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1719 d->ram->update_surface); 1720 break; 1721 } 1722 if (update.left >= update.right || update.top >= update.bottom || 1723 update.left < 0 || update.top < 0) { 1724 qxl_set_guest_bug(d, 1725 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1726 update.left, update.top, update.right, update.bottom); 1727 if (update.left == update.right || update.top == update.bottom) { 1728 /* old drivers may provide empty area, keep going */ 1729 qxl_clear_guest_bug(d); 1730 goto cancel_async; 1731 } 1732 break; 1733 } 1734 if (async == QXL_ASYNC) { 1735 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1736 QXL_IO_UPDATE_AREA_ASYNC); 1737 cookie->u.area = update; 1738 } 1739 qxl_spice_update_area(d, d->ram->update_surface, 1740 cookie ? &cookie->u.area : &update, 1741 NULL, 0, 0, async, cookie); 1742 break; 1743 } 1744 case QXL_IO_NOTIFY_CMD: 1745 qemu_spice_wakeup(&d->ssd); 1746 break; 1747 case QXL_IO_NOTIFY_CURSOR: 1748 qemu_spice_wakeup(&d->ssd); 1749 break; 1750 case QXL_IO_UPDATE_IRQ: 1751 qxl_update_irq(d); 1752 break; 1753 case QXL_IO_NOTIFY_OOM: 1754 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1755 break; 1756 } 1757 d->oom_running = 1; 1758 qxl_spice_oom(d); 1759 d->oom_running = 0; 1760 break; 1761 case QXL_IO_SET_MODE: 1762 qxl_set_mode(d, val, 0); 1763 break; 1764 case QXL_IO_LOG: 1765 if (trace_event_get_state_backends(TRACE_QXL_IO_LOG) || d->guestdebug) { 1766 /* We cannot trust the guest to NUL terminate d->ram->log_buf */ 1767 char *log_buf = g_strndup((const char *)d->ram->log_buf, 1768 sizeof(d->ram->log_buf)); 1769 trace_qxl_io_log(d->id, log_buf); 1770 if (d->guestdebug) { 1771 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1772 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf); 1773 } 1774 g_free(log_buf); 1775 } 1776 break; 1777 case QXL_IO_RESET: 1778 qxl_hard_reset(d, 0); 1779 break; 1780 case QXL_IO_MEMSLOT_ADD: 1781 if (val >= NUM_MEMSLOTS) { 1782 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1783 break; 1784 } 1785 if (d->guest_slots[val].active) { 1786 qxl_set_guest_bug(d, 1787 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1788 break; 1789 } 1790 d->guest_slots[val].slot = d->ram->mem_slot; 1791 qxl_add_memslot(d, val, 0, async); 1792 break; 1793 case QXL_IO_MEMSLOT_DEL: 1794 if (val >= NUM_MEMSLOTS) { 1795 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1796 break; 1797 } 1798 qxl_del_memslot(d, val); 1799 break; 1800 case QXL_IO_CREATE_PRIMARY: 1801 if (val != 0) { 1802 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1803 async); 1804 goto cancel_async; 1805 } 1806 d->guest_primary.surface = d->ram->create_surface; 1807 qxl_create_guest_primary(d, 0, async); 1808 break; 1809 case QXL_IO_DESTROY_PRIMARY: 1810 if (val != 0) { 1811 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1812 async); 1813 goto cancel_async; 1814 } 1815 if (!qxl_destroy_primary(d, async)) { 1816 trace_qxl_io_destroy_primary_ignored(d->id, 1817 qxl_mode_to_string(d->mode)); 1818 goto cancel_async; 1819 } 1820 break; 1821 case QXL_IO_DESTROY_SURFACE_WAIT: 1822 if (val >= d->ssd.num_surfaces) { 1823 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1824 "%" PRIu64 " >= NUM_SURFACES", async, val); 1825 goto cancel_async; 1826 } 1827 qxl_spice_destroy_surface_wait(d, val, async); 1828 break; 1829 case QXL_IO_FLUSH_RELEASE: { 1830 QXLReleaseRing *ring = &d->ram->release_ring; 1831 if (ring->prod - ring->cons + 1 == ring->num_items) { 1832 fprintf(stderr, 1833 "ERROR: no flush, full release ring [p%d,%dc]\n", 1834 ring->prod, ring->cons); 1835 } 1836 qxl_push_free_res(d, 1 /* flush */); 1837 break; 1838 } 1839 case QXL_IO_FLUSH_SURFACES_ASYNC: 1840 qxl_spice_flush_surfaces_async(d); 1841 break; 1842 case QXL_IO_DESTROY_ALL_SURFACES: 1843 d->mode = QXL_MODE_UNDEFINED; 1844 qxl_spice_destroy_surfaces(d, async); 1845 break; 1846 case QXL_IO_MONITORS_CONFIG_ASYNC: 1847 qxl_spice_monitors_config_async(d, 0); 1848 break; 1849 default: 1850 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1851 } 1852 return; 1853 cancel_async: 1854 if (async) { 1855 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1856 qemu_mutex_lock(&d->async_lock); 1857 d->current_async = QXL_UNDEFINED_IO; 1858 qemu_mutex_unlock(&d->async_lock); 1859 } 1860 } 1861 1862 static uint64_t ioport_read(void *opaque, hwaddr addr, 1863 unsigned size) 1864 { 1865 PCIQXLDevice *qxl = opaque; 1866 1867 trace_qxl_io_read_unexpected(qxl->id); 1868 return 0xff; 1869 } 1870 1871 static const MemoryRegionOps qxl_io_ops = { 1872 .read = ioport_read, 1873 .write = ioport_write, 1874 .valid = { 1875 .min_access_size = 1, 1876 .max_access_size = 1, 1877 }, 1878 }; 1879 1880 static void qxl_update_irq_bh(void *opaque) 1881 { 1882 PCIQXLDevice *d = opaque; 1883 qxl_update_irq(d); 1884 } 1885 1886 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1887 { 1888 uint32_t old_pending; 1889 uint32_t le_events = cpu_to_le32(events); 1890 1891 trace_qxl_send_events(d->id, events); 1892 if (!qemu_spice_display_is_running(&d->ssd)) { 1893 /* spice-server tracks guest running state and should not do this */ 1894 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1895 __func__); 1896 trace_qxl_send_events_vm_stopped(d->id, events); 1897 return; 1898 } 1899 /* 1900 * Older versions of Spice forgot to define the QXLRam struct 1901 * with the '__aligned__(4)' attribute. clang 7 and newer will 1902 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...) 1903 * might be a misaligned atomic access, and will generate an 1904 * out-of-line call for it, which results in a link error since 1905 * we don't currently link against libatomic. 1906 * 1907 * In fact we set up d->ram in init_qxl_ram() so it always starts 1908 * at a 4K boundary, so we know that &d->ram->int_pending is 1909 * naturally aligned for a uint32_t. Newer Spice versions 1910 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) 1911 * will fix the bug directly. To deal with older versions, 1912 * we tell the compiler to assume the address really is aligned. 1913 * Any compiler which cares about the misalignment will have 1914 * __builtin_assume_aligned. 1915 */ 1916 #ifdef HAS_ASSUME_ALIGNED 1917 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4)) 1918 #else 1919 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P) 1920 #endif 1921 1922 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending), 1923 le_events); 1924 if ((old_pending & le_events) == le_events) { 1925 return; 1926 } 1927 qemu_bh_schedule(d->update_irq); 1928 } 1929 1930 /* graphics console */ 1931 1932 static void qxl_hw_update(void *opaque) 1933 { 1934 PCIQXLDevice *qxl = opaque; 1935 1936 qxl_render_update(qxl); 1937 } 1938 1939 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1940 uint32_t height, int32_t stride) 1941 { 1942 uint64_t offset, size; 1943 uint32_t slot; 1944 bool rc; 1945 1946 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset); 1947 assert(rc == true); 1948 size = (uint64_t)height * abs(stride); 1949 trace_qxl_surfaces_dirty(qxl->id, offset, size); 1950 qxl_set_dirty(qxl->guest_slots[slot].mr, 1951 qxl->guest_slots[slot].offset + offset, 1952 qxl->guest_slots[slot].offset + offset + size); 1953 } 1954 1955 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1956 { 1957 int i; 1958 1959 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1960 return; 1961 } 1962 1963 /* dirty the primary surface */ 1964 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem, 1965 qxl->guest_primary.surface.height, 1966 qxl->guest_primary.surface.stride); 1967 1968 /* dirty the off-screen surfaces */ 1969 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1970 QXLSurfaceCmd *cmd; 1971 1972 if (qxl->guest_surfaces.cmds[i] == 0) { 1973 continue; 1974 } 1975 1976 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1977 MEMSLOT_GROUP_GUEST); 1978 assert(cmd); 1979 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1980 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data, 1981 cmd->u.surface_create.height, 1982 cmd->u.surface_create.stride); 1983 } 1984 } 1985 1986 static void qxl_vm_change_state_handler(void *opaque, int running, 1987 RunState state) 1988 { 1989 PCIQXLDevice *qxl = opaque; 1990 1991 if (running) { 1992 /* 1993 * if qxl_send_events was called from spice server context before 1994 * migration ended, qxl_update_irq for these events might not have been 1995 * called 1996 */ 1997 qxl_update_irq(qxl); 1998 } else { 1999 /* make sure surfaces are saved before migration */ 2000 qxl_dirty_surfaces(qxl); 2001 } 2002 } 2003 2004 /* display change listener */ 2005 2006 static void display_update(DisplayChangeListener *dcl, 2007 int x, int y, int w, int h) 2008 { 2009 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2010 2011 if (qxl->mode == QXL_MODE_VGA) { 2012 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 2013 } 2014 } 2015 2016 static void display_switch(DisplayChangeListener *dcl, 2017 struct DisplaySurface *surface) 2018 { 2019 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2020 2021 qxl->ssd.ds = surface; 2022 if (qxl->mode == QXL_MODE_VGA) { 2023 qemu_spice_display_switch(&qxl->ssd, surface); 2024 } 2025 } 2026 2027 static void display_refresh(DisplayChangeListener *dcl) 2028 { 2029 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2030 2031 if (qxl->mode == QXL_MODE_VGA) { 2032 qemu_spice_display_refresh(&qxl->ssd); 2033 } 2034 } 2035 2036 static DisplayChangeListenerOps display_listener_ops = { 2037 .dpy_name = "spice/qxl", 2038 .dpy_gfx_update = display_update, 2039 .dpy_gfx_switch = display_switch, 2040 .dpy_refresh = display_refresh, 2041 }; 2042 2043 static void qxl_init_ramsize(PCIQXLDevice *qxl) 2044 { 2045 /* vga mode framebuffer / primary surface (bar 0, first part) */ 2046 if (qxl->vgamem_size_mb < 8) { 2047 qxl->vgamem_size_mb = 8; 2048 } 2049 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be 2050 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now). 2051 */ 2052 if (qxl->vgamem_size_mb > 256) { 2053 qxl->vgamem_size_mb = 256; 2054 } 2055 qxl->vgamem_size = qxl->vgamem_size_mb * MiB; 2056 2057 /* vga ram (bar 0, total) */ 2058 if (qxl->ram_size_mb != -1) { 2059 qxl->vga.vram_size = qxl->ram_size_mb * MiB; 2060 } 2061 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 2062 qxl->vga.vram_size = qxl->vgamem_size * 2; 2063 } 2064 2065 /* vram32 (surfaces, 32bit, bar 1) */ 2066 if (qxl->vram32_size_mb != -1) { 2067 qxl->vram32_size = qxl->vram32_size_mb * MiB; 2068 } 2069 if (qxl->vram32_size < 4096) { 2070 qxl->vram32_size = 4096; 2071 } 2072 2073 /* vram (surfaces, 64bit, bar 4+5) */ 2074 if (qxl->vram_size_mb != -1) { 2075 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB; 2076 } 2077 if (qxl->vram_size < qxl->vram32_size) { 2078 qxl->vram_size = qxl->vram32_size; 2079 } 2080 2081 if (qxl->revision == 1) { 2082 qxl->vram32_size = 4096; 2083 qxl->vram_size = 4096; 2084 } 2085 qxl->vgamem_size = pow2ceil(qxl->vgamem_size); 2086 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size); 2087 qxl->vram32_size = pow2ceil(qxl->vram32_size); 2088 qxl->vram_size = pow2ceil(qxl->vram_size); 2089 } 2090 2091 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) 2092 { 2093 uint8_t* config = qxl->pci.config; 2094 uint32_t pci_device_rev; 2095 uint32_t io_size; 2096 2097 qemu_spice_display_init_common(&qxl->ssd); 2098 qxl->mode = QXL_MODE_UNDEFINED; 2099 qxl->num_memslots = NUM_MEMSLOTS; 2100 qemu_mutex_init(&qxl->track_lock); 2101 qemu_mutex_init(&qxl->async_lock); 2102 qxl->current_async = QXL_UNDEFINED_IO; 2103 qxl->guest_bug = 0; 2104 2105 switch (qxl->revision) { 2106 case 1: /* spice 0.4 -- qxl-1 */ 2107 pci_device_rev = QXL_REVISION_STABLE_V04; 2108 io_size = 8; 2109 break; 2110 case 2: /* spice 0.6 -- qxl-2 */ 2111 pci_device_rev = QXL_REVISION_STABLE_V06; 2112 io_size = 16; 2113 break; 2114 case 3: /* qxl-3 */ 2115 pci_device_rev = QXL_REVISION_STABLE_V10; 2116 io_size = 32; /* PCI region size must be pow2 */ 2117 break; 2118 case 4: /* qxl-4 */ 2119 pci_device_rev = QXL_REVISION_STABLE_V12; 2120 io_size = pow2ceil(QXL_IO_RANGE_SIZE); 2121 break; 2122 case 5: /* qxl-5 */ 2123 pci_device_rev = QXL_REVISION_STABLE_V12 + 1; 2124 io_size = pow2ceil(QXL_IO_RANGE_SIZE); 2125 break; 2126 default: 2127 error_setg(errp, "Invalid revision %d for qxl device (max %d)", 2128 qxl->revision, QXL_DEFAULT_REVISION); 2129 return; 2130 } 2131 2132 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 2133 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 2134 2135 qxl->rom_size = qxl_rom_size(); 2136 memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 2137 qxl->rom_size, &error_fatal); 2138 init_qxl_rom(qxl); 2139 init_qxl_ram(qxl); 2140 2141 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 2142 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 2143 qxl->vram_size, &error_fatal); 2144 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 2145 &qxl->vram_bar, 0, qxl->vram32_size); 2146 2147 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 2148 "qxl-ioports", io_size); 2149 if (qxl->have_vga) { 2150 vga_dirty_log_start(&qxl->vga); 2151 } 2152 memory_region_set_flush_coalesced(&qxl->io_bar); 2153 2154 2155 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2156 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2157 2158 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2159 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2160 2161 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2162 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2163 2164 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2165 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2166 2167 if (qxl->vram32_size < qxl->vram_size) { 2168 /* 2169 * Make the 64bit vram bar show up only in case it is 2170 * configured to be larger than the 32bit vram bar. 2171 */ 2172 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2173 PCI_BASE_ADDRESS_SPACE_MEMORY | 2174 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2175 PCI_BASE_ADDRESS_MEM_PREFETCH, 2176 &qxl->vram_bar); 2177 } 2178 2179 /* print pci bar details */ 2180 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n", 2181 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB); 2182 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n", 2183 qxl->vram32_size / MiB); 2184 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n", 2185 qxl->vram_size / MiB, 2186 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2187 2188 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2189 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2190 error_setg(errp, "qxl interface %d.%d not supported by spice-server", 2191 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2192 return; 2193 } 2194 2195 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */ 2196 char device_address[256] = ""; 2197 if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) { 2198 spice_qxl_set_device_info(&qxl->ssd.qxl, 2199 device_address, 2200 0, 2201 qxl->max_outputs); 2202 } 2203 #endif 2204 2205 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2206 2207 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2208 qxl_reset_state(qxl); 2209 2210 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2211 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd); 2212 } 2213 2214 static void qxl_realize_primary(PCIDevice *dev, Error **errp) 2215 { 2216 PCIQXLDevice *qxl = PCI_QXL(dev); 2217 VGACommonState *vga = &qxl->vga; 2218 Error *local_err = NULL; 2219 2220 qxl_init_ramsize(qxl); 2221 vga->vbe_size = qxl->vgamem_size; 2222 vga->vram_size_mb = qxl->vga.vram_size / MiB; 2223 vga_common_init(vga, OBJECT(dev)); 2224 vga_init(vga, OBJECT(dev), 2225 pci_address_space(dev), pci_address_space_io(dev), false); 2226 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2227 vga, "vga"); 2228 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2229 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2230 qxl->have_vga = true; 2231 2232 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2233 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */ 2234 if (qxl->id != 0) { 2235 error_setg(errp, "primary qxl-vga device must be console 0 " 2236 "(first display device on the command line)"); 2237 return; 2238 } 2239 2240 qxl_realize_common(qxl, &local_err); 2241 if (local_err) { 2242 error_propagate(errp, local_err); 2243 return; 2244 } 2245 2246 qxl->ssd.dcl.ops = &display_listener_ops; 2247 qxl->ssd.dcl.con = vga->con; 2248 register_displaychangelistener(&qxl->ssd.dcl); 2249 } 2250 2251 static void qxl_realize_secondary(PCIDevice *dev, Error **errp) 2252 { 2253 PCIQXLDevice *qxl = PCI_QXL(dev); 2254 2255 qxl_init_ramsize(qxl); 2256 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2257 qxl->vga.vram_size, &error_fatal); 2258 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2259 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2260 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */ 2261 2262 qxl_realize_common(qxl, errp); 2263 } 2264 2265 static int qxl_pre_save(void *opaque) 2266 { 2267 PCIQXLDevice* d = opaque; 2268 uint8_t *ram_start = d->vga.vram_ptr; 2269 2270 trace_qxl_pre_save(d->id); 2271 if (d->last_release == NULL) { 2272 d->last_release_offset = 0; 2273 } else { 2274 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2275 } 2276 assert(d->last_release_offset < d->vga.vram_size); 2277 2278 return 0; 2279 } 2280 2281 static int qxl_pre_load(void *opaque) 2282 { 2283 PCIQXLDevice* d = opaque; 2284 2285 trace_qxl_pre_load(d->id); 2286 qxl_hard_reset(d, 1); 2287 qxl_exit_vga_mode(d); 2288 return 0; 2289 } 2290 2291 static void qxl_create_memslots(PCIQXLDevice *d) 2292 { 2293 int i; 2294 2295 for (i = 0; i < NUM_MEMSLOTS; i++) { 2296 if (!d->guest_slots[i].active) { 2297 continue; 2298 } 2299 qxl_add_memslot(d, i, 0, QXL_SYNC); 2300 } 2301 } 2302 2303 static int qxl_post_load(void *opaque, int version) 2304 { 2305 PCIQXLDevice* d = opaque; 2306 uint8_t *ram_start = d->vga.vram_ptr; 2307 QXLCommandExt *cmds; 2308 int in, out, newmode; 2309 2310 assert(d->last_release_offset < d->vga.vram_size); 2311 if (d->last_release_offset == 0) { 2312 d->last_release = NULL; 2313 } else { 2314 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2315 } 2316 2317 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2318 2319 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2320 newmode = d->mode; 2321 d->mode = QXL_MODE_UNDEFINED; 2322 2323 switch (newmode) { 2324 case QXL_MODE_UNDEFINED: 2325 qxl_create_memslots(d); 2326 break; 2327 case QXL_MODE_VGA: 2328 qxl_create_memslots(d); 2329 qxl_enter_vga_mode(d); 2330 break; 2331 case QXL_MODE_NATIVE: 2332 qxl_create_memslots(d); 2333 qxl_create_guest_primary(d, 1, QXL_SYNC); 2334 2335 /* replay surface-create and cursor-set commands */ 2336 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1); 2337 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2338 if (d->guest_surfaces.cmds[in] == 0) { 2339 continue; 2340 } 2341 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2342 cmds[out].cmd.type = QXL_CMD_SURFACE; 2343 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2344 out++; 2345 } 2346 if (d->guest_cursor) { 2347 cmds[out].cmd.data = d->guest_cursor; 2348 cmds[out].cmd.type = QXL_CMD_CURSOR; 2349 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2350 out++; 2351 } 2352 qxl_spice_loadvm_commands(d, cmds, out); 2353 g_free(cmds); 2354 if (d->guest_monitors_config) { 2355 qxl_spice_monitors_config_async(d, 1); 2356 } 2357 break; 2358 case QXL_MODE_COMPAT: 2359 /* note: no need to call qxl_create_memslots, qxl_set_mode 2360 * creates the mem slot. */ 2361 qxl_set_mode(d, d->shadow_rom.mode, 1); 2362 break; 2363 } 2364 return 0; 2365 } 2366 2367 #define QXL_SAVE_VERSION 21 2368 2369 static bool qxl_monitors_config_needed(void *opaque) 2370 { 2371 PCIQXLDevice *qxl = opaque; 2372 2373 return qxl->guest_monitors_config != 0; 2374 } 2375 2376 2377 static VMStateDescription qxl_memslot = { 2378 .name = "qxl-memslot", 2379 .version_id = QXL_SAVE_VERSION, 2380 .minimum_version_id = QXL_SAVE_VERSION, 2381 .fields = (VMStateField[]) { 2382 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2383 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2384 VMSTATE_UINT32(active, struct guest_slots), 2385 VMSTATE_END_OF_LIST() 2386 } 2387 }; 2388 2389 static VMStateDescription qxl_surface = { 2390 .name = "qxl-surface", 2391 .version_id = QXL_SAVE_VERSION, 2392 .minimum_version_id = QXL_SAVE_VERSION, 2393 .fields = (VMStateField[]) { 2394 VMSTATE_UINT32(width, QXLSurfaceCreate), 2395 VMSTATE_UINT32(height, QXLSurfaceCreate), 2396 VMSTATE_INT32(stride, QXLSurfaceCreate), 2397 VMSTATE_UINT32(format, QXLSurfaceCreate), 2398 VMSTATE_UINT32(position, QXLSurfaceCreate), 2399 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2400 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2401 VMSTATE_UINT32(type, QXLSurfaceCreate), 2402 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2403 VMSTATE_END_OF_LIST() 2404 } 2405 }; 2406 2407 static VMStateDescription qxl_vmstate_monitors_config = { 2408 .name = "qxl/monitors-config", 2409 .version_id = 1, 2410 .minimum_version_id = 1, 2411 .needed = qxl_monitors_config_needed, 2412 .fields = (VMStateField[]) { 2413 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2414 VMSTATE_END_OF_LIST() 2415 }, 2416 }; 2417 2418 static VMStateDescription qxl_vmstate = { 2419 .name = "qxl", 2420 .version_id = QXL_SAVE_VERSION, 2421 .minimum_version_id = QXL_SAVE_VERSION, 2422 .pre_save = qxl_pre_save, 2423 .pre_load = qxl_pre_load, 2424 .post_load = qxl_post_load, 2425 .fields = (VMStateField[]) { 2426 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2427 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2428 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2429 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2430 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2431 VMSTATE_UINT32(mode, PCIQXLDevice), 2432 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2433 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL), 2434 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2435 qxl_memslot, struct guest_slots), 2436 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2437 qxl_surface, QXLSurfaceCreate), 2438 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL), 2439 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2440 ssd.num_surfaces, 0, 2441 vmstate_info_uint64, uint64_t), 2442 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2443 VMSTATE_END_OF_LIST() 2444 }, 2445 .subsections = (const VMStateDescription*[]) { 2446 &qxl_vmstate_monitors_config, 2447 NULL 2448 } 2449 }; 2450 2451 static Property qxl_properties[] = { 2452 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB), 2453 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB), 2454 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2455 QXL_DEFAULT_REVISION), 2456 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2457 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2458 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2459 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2460 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2461 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2462 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2463 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2464 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 2465 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0), 2466 #endif 2467 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0), 2468 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0), 2469 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false), 2470 DEFINE_PROP_END_OF_LIST(), 2471 }; 2472 2473 static void qxl_pci_class_init(ObjectClass *klass, void *data) 2474 { 2475 DeviceClass *dc = DEVICE_CLASS(klass); 2476 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2477 2478 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2479 k->device_id = QXL_DEVICE_ID_STABLE; 2480 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2481 dc->reset = qxl_reset_handler; 2482 dc->vmsd = &qxl_vmstate; 2483 device_class_set_props(dc, qxl_properties); 2484 } 2485 2486 static const TypeInfo qxl_pci_type_info = { 2487 .name = TYPE_PCI_QXL, 2488 .parent = TYPE_PCI_DEVICE, 2489 .instance_size = sizeof(PCIQXLDevice), 2490 .abstract = true, 2491 .class_init = qxl_pci_class_init, 2492 .interfaces = (InterfaceInfo[]) { 2493 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2494 { }, 2495 }, 2496 }; 2497 2498 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2499 { 2500 DeviceClass *dc = DEVICE_CLASS(klass); 2501 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2502 2503 k->realize = qxl_realize_primary; 2504 k->romfile = "vgabios-qxl.bin"; 2505 k->class_id = PCI_CLASS_DISPLAY_VGA; 2506 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2507 dc->hotpluggable = false; 2508 } 2509 2510 static const TypeInfo qxl_primary_info = { 2511 .name = "qxl-vga", 2512 .parent = TYPE_PCI_QXL, 2513 .class_init = qxl_primary_class_init, 2514 }; 2515 2516 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2517 { 2518 DeviceClass *dc = DEVICE_CLASS(klass); 2519 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2520 2521 k->realize = qxl_realize_secondary; 2522 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2523 dc->desc = "Spice QXL GPU (secondary)"; 2524 } 2525 2526 static const TypeInfo qxl_secondary_info = { 2527 .name = "qxl", 2528 .parent = TYPE_PCI_QXL, 2529 .class_init = qxl_secondary_class_init, 2530 }; 2531 2532 static void qxl_register_types(void) 2533 { 2534 type_register_static(&qxl_pci_type_info); 2535 type_register_static(&qxl_primary_info); 2536 type_register_static(&qxl_secondary_info); 2537 } 2538 2539 type_init(qxl_register_types) 2540