1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann 5 * maintained by Gerd Hoffmann <kraxel@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include <zlib.h> 24 25 #include "qapi/error.h" 26 #include "qemu/timer.h" 27 #include "qemu/queue.h" 28 #include "qemu/atomic.h" 29 #include "qemu/module.h" 30 #include "sysemu/sysemu.h" 31 #include "migration/blocker.h" 32 #include "trace.h" 33 34 #include "qxl.h" 35 36 #undef SPICE_RING_CONS_ITEM 37 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ 38 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ 39 if (cons >= ARRAY_SIZE((r)->items)) { \ 40 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ 41 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \ 42 ret = NULL; \ 43 } else { \ 44 ret = &(r)->items[cons].el; \ 45 } \ 46 } 47 48 #undef ALIGN 49 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) 50 51 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 52 53 #define QXL_MODE(_x, _y, _b, _o) \ 54 { .x_res = _x, \ 55 .y_res = _y, \ 56 .bits = _b, \ 57 .stride = (_x) * (_b) / 8, \ 58 .x_mili = PIXEL_SIZE * (_x), \ 59 .y_mili = PIXEL_SIZE * (_y), \ 60 .orientation = _o, \ 61 } 62 63 #define QXL_MODE_16_32(x_res, y_res, orientation) \ 64 QXL_MODE(x_res, y_res, 16, orientation), \ 65 QXL_MODE(x_res, y_res, 32, orientation) 66 67 #define QXL_MODE_EX(x_res, y_res) \ 68 QXL_MODE_16_32(x_res, y_res, 0), \ 69 QXL_MODE_16_32(x_res, y_res, 1) 70 71 static QXLMode qxl_modes[] = { 72 QXL_MODE_EX(640, 480), 73 QXL_MODE_EX(800, 480), 74 QXL_MODE_EX(800, 600), 75 QXL_MODE_EX(832, 624), 76 QXL_MODE_EX(960, 640), 77 QXL_MODE_EX(1024, 600), 78 QXL_MODE_EX(1024, 768), 79 QXL_MODE_EX(1152, 864), 80 QXL_MODE_EX(1152, 870), 81 QXL_MODE_EX(1280, 720), 82 QXL_MODE_EX(1280, 760), 83 QXL_MODE_EX(1280, 768), 84 QXL_MODE_EX(1280, 800), 85 QXL_MODE_EX(1280, 960), 86 QXL_MODE_EX(1280, 1024), 87 QXL_MODE_EX(1360, 768), 88 QXL_MODE_EX(1366, 768), 89 QXL_MODE_EX(1400, 1050), 90 QXL_MODE_EX(1440, 900), 91 QXL_MODE_EX(1600, 900), 92 QXL_MODE_EX(1600, 1200), 93 QXL_MODE_EX(1680, 1050), 94 QXL_MODE_EX(1920, 1080), 95 /* these modes need more than 8 MB video memory */ 96 QXL_MODE_EX(1920, 1200), 97 QXL_MODE_EX(1920, 1440), 98 QXL_MODE_EX(2000, 2000), 99 QXL_MODE_EX(2048, 1536), 100 QXL_MODE_EX(2048, 2048), 101 QXL_MODE_EX(2560, 1440), 102 QXL_MODE_EX(2560, 1600), 103 /* these modes need more than 16 MB video memory */ 104 QXL_MODE_EX(2560, 2048), 105 QXL_MODE_EX(2800, 2100), 106 QXL_MODE_EX(3200, 2400), 107 /* these modes need more than 32 MB video memory */ 108 QXL_MODE_EX(3840, 2160), /* 4k mainstream */ 109 QXL_MODE_EX(4096, 2160), /* 4k */ 110 /* these modes need more than 64 MB video memory */ 111 QXL_MODE_EX(7680, 4320), /* 8k mainstream */ 112 /* these modes need more than 128 MB video memory */ 113 QXL_MODE_EX(8192, 4320), /* 8k */ 114 }; 115 116 static void qxl_send_events(PCIQXLDevice *d, uint32_t events); 117 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); 118 static void qxl_reset_memslots(PCIQXLDevice *d); 119 static void qxl_reset_surfaces(PCIQXLDevice *d); 120 static void qxl_ring_set_dirty(PCIQXLDevice *qxl); 121 122 static void qxl_hw_update(void *opaque); 123 124 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) 125 { 126 trace_qxl_set_guest_bug(qxl->id); 127 qxl_send_events(qxl, QXL_INTERRUPT_ERROR); 128 qxl->guest_bug = 1; 129 if (qxl->guestdebug) { 130 va_list ap; 131 va_start(ap, msg); 132 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); 133 vfprintf(stderr, msg, ap); 134 fprintf(stderr, "\n"); 135 va_end(ap); 136 } 137 } 138 139 static void qxl_clear_guest_bug(PCIQXLDevice *qxl) 140 { 141 qxl->guest_bug = 0; 142 } 143 144 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, 145 struct QXLRect *area, struct QXLRect *dirty_rects, 146 uint32_t num_dirty_rects, 147 uint32_t clear_dirty_region, 148 qxl_async_io async, struct QXLCookie *cookie) 149 { 150 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, 151 area->top, area->bottom); 152 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, 153 clear_dirty_region); 154 if (async == QXL_SYNC) { 155 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, 156 dirty_rects, num_dirty_rects, clear_dirty_region); 157 } else { 158 assert(cookie != NULL); 159 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, 160 clear_dirty_region, (uintptr_t)cookie); 161 } 162 } 163 164 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, 165 uint32_t id) 166 { 167 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); 168 qemu_mutex_lock(&qxl->track_lock); 169 qxl->guest_surfaces.cmds[id] = 0; 170 qxl->guest_surfaces.count--; 171 qemu_mutex_unlock(&qxl->track_lock); 172 } 173 174 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, 175 qxl_async_io async) 176 { 177 QXLCookie *cookie; 178 179 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); 180 if (async) { 181 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 182 QXL_IO_DESTROY_SURFACE_ASYNC); 183 cookie->u.surface_id = id; 184 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); 185 } else { 186 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); 187 qxl_spice_destroy_surface_wait_complete(qxl, id); 188 } 189 } 190 191 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) 192 { 193 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, 194 qxl->num_free_res); 195 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 196 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 197 QXL_IO_FLUSH_SURFACES_ASYNC)); 198 } 199 200 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, 201 uint32_t count) 202 { 203 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); 204 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); 205 } 206 207 void qxl_spice_oom(PCIQXLDevice *qxl) 208 { 209 trace_qxl_spice_oom(qxl->id); 210 spice_qxl_oom(&qxl->ssd.qxl); 211 } 212 213 void qxl_spice_reset_memslots(PCIQXLDevice *qxl) 214 { 215 trace_qxl_spice_reset_memslots(qxl->id); 216 spice_qxl_reset_memslots(&qxl->ssd.qxl); 217 } 218 219 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) 220 { 221 trace_qxl_spice_destroy_surfaces_complete(qxl->id); 222 qemu_mutex_lock(&qxl->track_lock); 223 memset(qxl->guest_surfaces.cmds, 0, 224 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); 225 qxl->guest_surfaces.count = 0; 226 qemu_mutex_unlock(&qxl->track_lock); 227 } 228 229 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) 230 { 231 trace_qxl_spice_destroy_surfaces(qxl->id, async); 232 if (async) { 233 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 234 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 235 QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); 236 } else { 237 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); 238 qxl_spice_destroy_surfaces_complete(qxl); 239 } 240 } 241 242 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay) 243 { 244 QXLMonitorsConfig *cfg; 245 246 trace_qxl_spice_monitors_config(qxl->id); 247 if (replay) { 248 /* 249 * don't use QXL_COOKIE_TYPE_IO: 250 * - we are not running yet (post_load), we will assert 251 * in send_events 252 * - this is not a guest io, but a reply, so async_io isn't set. 253 */ 254 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 255 qxl->guest_monitors_config, 256 MEMSLOT_GROUP_GUEST, 257 (uintptr_t)qxl_cookie_new( 258 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG, 259 0)); 260 } else { 261 /* >= release 0.12.6, < release 0.14.2 */ 262 #if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02 263 if (qxl->max_outputs) { 264 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs); 265 } 266 #endif 267 qxl->guest_monitors_config = qxl->ram->monitors_config; 268 spice_qxl_monitors_config_async(&qxl->ssd.qxl, 269 qxl->ram->monitors_config, 270 MEMSLOT_GROUP_GUEST, 271 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, 272 QXL_IO_MONITORS_CONFIG_ASYNC)); 273 } 274 275 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST); 276 if (cfg != NULL && cfg->count == 1) { 277 qxl->guest_primary.resized = 1; 278 qxl->guest_head0_width = cfg->heads[0].width; 279 qxl->guest_head0_height = cfg->heads[0].height; 280 } else { 281 qxl->guest_head0_width = 0; 282 qxl->guest_head0_height = 0; 283 } 284 } 285 286 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) 287 { 288 trace_qxl_spice_reset_image_cache(qxl->id); 289 spice_qxl_reset_image_cache(&qxl->ssd.qxl); 290 } 291 292 void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 293 { 294 trace_qxl_spice_reset_cursor(qxl->id); 295 spice_qxl_reset_cursor(&qxl->ssd.qxl); 296 qemu_mutex_lock(&qxl->track_lock); 297 qxl->guest_cursor = 0; 298 qemu_mutex_unlock(&qxl->track_lock); 299 if (qxl->ssd.cursor) { 300 cursor_put(qxl->ssd.cursor); 301 } 302 qxl->ssd.cursor = cursor_builtin_hidden(); 303 } 304 305 static uint32_t qxl_crc32(const uint8_t *p, unsigned len) 306 { 307 /* 308 * zlib xors the seed with 0xffffffff, and xors the result 309 * again with 0xffffffff; Both are not done with linux's crc32, 310 * which we want to be compatible with, so undo that. 311 */ 312 return crc32(0xffffffff, p, len) ^ 0xffffffff; 313 } 314 315 static ram_addr_t qxl_rom_size(void) 316 { 317 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes)) 318 #define QXL_ROM_SZ 8192 319 320 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ); 321 return QXL_ROM_SZ; 322 } 323 324 static void init_qxl_rom(PCIQXLDevice *d) 325 { 326 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); 327 QXLModes *modes = (QXLModes *)(rom + 1); 328 uint32_t ram_header_size; 329 uint32_t surface0_area_size; 330 uint32_t num_pages; 331 uint32_t fb; 332 int i, n; 333 334 memset(rom, 0, d->rom_size); 335 336 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); 337 rom->id = cpu_to_le32(d->id); 338 rom->log_level = cpu_to_le32(d->guestdebug); 339 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); 340 341 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; 342 rom->slot_id_bits = MEMSLOT_SLOT_BITS; 343 rom->slots_start = 1; 344 rom->slots_end = NUM_MEMSLOTS - 1; 345 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); 346 347 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) { 348 fb = qxl_modes[i].y_res * qxl_modes[i].stride; 349 if (fb > d->vgamem_size) { 350 continue; 351 } 352 modes->modes[n].id = cpu_to_le32(i); 353 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); 354 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); 355 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); 356 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); 357 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); 358 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); 359 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); 360 n++; 361 } 362 modes->n_modes = cpu_to_le32(n); 363 364 ram_header_size = ALIGN(sizeof(QXLRam), 4096); 365 surface0_area_size = ALIGN(d->vgamem_size, 4096); 366 num_pages = d->vga.vram_size; 367 num_pages -= ram_header_size; 368 num_pages -= surface0_area_size; 369 num_pages = num_pages / QXL_PAGE_SIZE; 370 371 assert(ram_header_size + surface0_area_size <= d->vga.vram_size); 372 373 rom->draw_area_offset = cpu_to_le32(0); 374 rom->surface0_area_size = cpu_to_le32(surface0_area_size); 375 rom->pages_offset = cpu_to_le32(surface0_area_size); 376 rom->num_pages = cpu_to_le32(num_pages); 377 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); 378 379 if (d->xres && d->yres) { 380 /* needs linux kernel 4.12+ to work */ 381 rom->client_monitors_config.count = 1; 382 rom->client_monitors_config.heads[0].left = 0; 383 rom->client_monitors_config.heads[0].top = 0; 384 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres); 385 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres); 386 rom->client_monitors_config_crc = qxl_crc32( 387 (const uint8_t *)&rom->client_monitors_config, 388 sizeof(rom->client_monitors_config)); 389 } 390 391 d->shadow_rom = *rom; 392 d->rom = rom; 393 d->modes = modes; 394 } 395 396 static void init_qxl_ram(PCIQXLDevice *d) 397 { 398 uint8_t *buf; 399 uint32_t prod; 400 QXLReleaseRing *ring; 401 402 buf = d->vga.vram_ptr; 403 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); 404 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); 405 d->ram->int_pending = cpu_to_le32(0); 406 d->ram->int_mask = cpu_to_le32(0); 407 d->ram->update_surface = 0; 408 d->ram->monitors_config = 0; 409 SPICE_RING_INIT(&d->ram->cmd_ring); 410 SPICE_RING_INIT(&d->ram->cursor_ring); 411 SPICE_RING_INIT(&d->ram->release_ring); 412 413 ring = &d->ram->release_ring; 414 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); 415 assert(prod < ARRAY_SIZE(ring->items)); 416 ring->items[prod].el = 0; 417 418 qxl_ring_set_dirty(d); 419 } 420 421 /* can be called from spice server thread context */ 422 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) 423 { 424 memory_region_set_dirty(mr, addr, end - addr); 425 } 426 427 static void qxl_rom_set_dirty(PCIQXLDevice *qxl) 428 { 429 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); 430 } 431 432 /* called from spice server thread context only */ 433 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) 434 { 435 void *base = qxl->vga.vram_ptr; 436 intptr_t offset; 437 438 offset = ptr - base; 439 assert(offset < qxl->vga.vram_size); 440 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); 441 } 442 443 /* can be called from spice server thread context */ 444 static void qxl_ring_set_dirty(PCIQXLDevice *qxl) 445 { 446 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; 447 ram_addr_t end = qxl->vga.vram_size; 448 qxl_set_dirty(&qxl->vga.vram, addr, end); 449 } 450 451 /* 452 * keep track of some command state, for savevm/loadvm. 453 * called from spice server thread context only 454 */ 455 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) 456 { 457 switch (le32_to_cpu(ext->cmd.type)) { 458 case QXL_CMD_SURFACE: 459 { 460 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 461 462 if (!cmd) { 463 return 1; 464 } 465 uint32_t id = le32_to_cpu(cmd->surface_id); 466 467 if (id >= qxl->ssd.num_surfaces) { 468 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, 469 qxl->ssd.num_surfaces); 470 return 1; 471 } 472 if (cmd->type == QXL_SURFACE_CMD_CREATE && 473 (cmd->u.surface_create.stride & 0x03) != 0) { 474 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n", 475 cmd->u.surface_create.stride); 476 return 1; 477 } 478 qemu_mutex_lock(&qxl->track_lock); 479 if (cmd->type == QXL_SURFACE_CMD_CREATE) { 480 qxl->guest_surfaces.cmds[id] = ext->cmd.data; 481 qxl->guest_surfaces.count++; 482 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) 483 qxl->guest_surfaces.max = qxl->guest_surfaces.count; 484 } 485 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { 486 qxl->guest_surfaces.cmds[id] = 0; 487 qxl->guest_surfaces.count--; 488 } 489 qemu_mutex_unlock(&qxl->track_lock); 490 break; 491 } 492 case QXL_CMD_CURSOR: 493 { 494 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 495 496 if (!cmd) { 497 return 1; 498 } 499 if (cmd->type == QXL_CURSOR_SET) { 500 qemu_mutex_lock(&qxl->track_lock); 501 qxl->guest_cursor = ext->cmd.data; 502 qemu_mutex_unlock(&qxl->track_lock); 503 } 504 if (cmd->type == QXL_CURSOR_HIDE) { 505 qemu_mutex_lock(&qxl->track_lock); 506 qxl->guest_cursor = 0; 507 qemu_mutex_unlock(&qxl->track_lock); 508 } 509 break; 510 } 511 } 512 return 0; 513 } 514 515 /* spice display interface callbacks */ 516 517 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) 518 { 519 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 520 521 trace_qxl_interface_attach_worker(qxl->id); 522 } 523 524 static void interface_set_compression_level(QXLInstance *sin, int level) 525 { 526 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 527 528 trace_qxl_interface_set_compression_level(qxl->id, level); 529 qxl->shadow_rom.compression_level = cpu_to_le32(level); 530 qxl->rom->compression_level = cpu_to_le32(level); 531 qxl_rom_set_dirty(qxl); 532 } 533 534 #if SPICE_NEEDS_SET_MM_TIME 535 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) 536 { 537 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 538 539 if (!qemu_spice_display_is_running(&qxl->ssd)) { 540 return; 541 } 542 543 trace_qxl_interface_set_mm_time(qxl->id, mm_time); 544 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); 545 qxl->rom->mm_clock = cpu_to_le32(mm_time); 546 qxl_rom_set_dirty(qxl); 547 } 548 #endif 549 550 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) 551 { 552 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 553 554 trace_qxl_interface_get_init_info(qxl->id); 555 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; 556 info->memslot_id_bits = MEMSLOT_SLOT_BITS; 557 info->num_memslots = NUM_MEMSLOTS; 558 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; 559 info->internal_groupslot_id = 0; 560 info->qxl_ram_size = 561 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; 562 info->n_surfaces = qxl->ssd.num_surfaces; 563 } 564 565 static const char *qxl_mode_to_string(int mode) 566 { 567 switch (mode) { 568 case QXL_MODE_COMPAT: 569 return "compat"; 570 case QXL_MODE_NATIVE: 571 return "native"; 572 case QXL_MODE_UNDEFINED: 573 return "undefined"; 574 case QXL_MODE_VGA: 575 return "vga"; 576 } 577 return "INVALID"; 578 } 579 580 static const char *io_port_to_string(uint32_t io_port) 581 { 582 if (io_port >= QXL_IO_RANGE_SIZE) { 583 return "out of range"; 584 } 585 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { 586 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", 587 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", 588 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", 589 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", 590 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", 591 [QXL_IO_RESET] = "QXL_IO_RESET", 592 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", 593 [QXL_IO_LOG] = "QXL_IO_LOG", 594 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", 595 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", 596 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", 597 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", 598 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", 599 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", 600 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", 601 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", 602 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", 603 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", 604 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", 605 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", 606 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", 607 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] 608 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", 609 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", 610 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", 611 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC", 612 }; 613 return io_port_to_string[io_port]; 614 } 615 616 /* called from spice server thread context only */ 617 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) 618 { 619 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 620 SimpleSpiceUpdate *update; 621 QXLCommandRing *ring; 622 QXLCommand *cmd; 623 int notify, ret; 624 625 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); 626 627 switch (qxl->mode) { 628 case QXL_MODE_VGA: 629 ret = false; 630 qemu_mutex_lock(&qxl->ssd.lock); 631 update = QTAILQ_FIRST(&qxl->ssd.updates); 632 if (update != NULL) { 633 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); 634 *ext = update->ext; 635 ret = true; 636 } 637 qemu_mutex_unlock(&qxl->ssd.lock); 638 if (ret) { 639 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 640 qxl_log_command(qxl, "vga", ext); 641 } 642 return ret; 643 case QXL_MODE_COMPAT: 644 case QXL_MODE_NATIVE: 645 case QXL_MODE_UNDEFINED: 646 ring = &qxl->ram->cmd_ring; 647 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { 648 return false; 649 } 650 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 651 if (!cmd) { 652 return false; 653 } 654 ext->cmd = *cmd; 655 ext->group_id = MEMSLOT_GROUP_GUEST; 656 ext->flags = qxl->cmdflags; 657 SPICE_RING_POP(ring, notify); 658 qxl_ring_set_dirty(qxl); 659 if (notify) { 660 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); 661 } 662 qxl->guest_primary.commands++; 663 qxl_track_command(qxl, ext); 664 qxl_log_command(qxl, "cmd", ext); 665 { 666 /* 667 * Windows 8 drivers place qxl commands in the vram 668 * (instead of the ram) bar. We can't live migrate such a 669 * guest, so add a migration blocker in case we detect 670 * this, to avoid triggering the assert in pre_save(). 671 * 672 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa 673 */ 674 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); 675 if (msg != NULL && ( 676 msg < (void *)qxl->vga.vram_ptr || 677 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) { 678 if (!qxl->migration_blocker) { 679 Error *local_err = NULL; 680 error_setg(&qxl->migration_blocker, 681 "qxl: guest bug: command not in ram bar"); 682 migrate_add_blocker(qxl->migration_blocker, &local_err); 683 if (local_err) { 684 error_report_err(local_err); 685 } 686 } 687 } 688 } 689 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); 690 return true; 691 default: 692 return false; 693 } 694 } 695 696 /* called from spice server thread context only */ 697 static int interface_req_cmd_notification(QXLInstance *sin) 698 { 699 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 700 int wait = 1; 701 702 trace_qxl_ring_command_req_notification(qxl->id); 703 switch (qxl->mode) { 704 case QXL_MODE_COMPAT: 705 case QXL_MODE_NATIVE: 706 case QXL_MODE_UNDEFINED: 707 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); 708 qxl_ring_set_dirty(qxl); 709 break; 710 default: 711 /* nothing */ 712 break; 713 } 714 return wait; 715 } 716 717 /* called from spice server thread context only */ 718 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) 719 { 720 QXLReleaseRing *ring = &d->ram->release_ring; 721 uint32_t prod; 722 int notify; 723 724 #define QXL_FREE_BUNCH_SIZE 32 725 726 if (ring->prod - ring->cons + 1 == ring->num_items) { 727 /* ring full -- can't push */ 728 return; 729 } 730 if (!flush && d->oom_running) { 731 /* collect everything from oom handler before pushing */ 732 return; 733 } 734 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { 735 /* collect a bit more before pushing */ 736 return; 737 } 738 739 SPICE_RING_PUSH(ring, notify); 740 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), 741 d->guest_surfaces.count, d->num_free_res, 742 d->last_release, notify ? "yes" : "no"); 743 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, 744 ring->num_items, ring->prod, ring->cons); 745 if (notify) { 746 qxl_send_events(d, QXL_INTERRUPT_DISPLAY); 747 } 748 749 ring = &d->ram->release_ring; 750 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); 751 if (prod >= ARRAY_SIZE(ring->items)) { 752 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch " 753 "%u >= %zu", prod, ARRAY_SIZE(ring->items)); 754 return; 755 } 756 ring->items[prod].el = 0; 757 d->num_free_res = 0; 758 d->last_release = NULL; 759 qxl_ring_set_dirty(d); 760 } 761 762 /* called from spice server thread context only */ 763 static void interface_release_resource(QXLInstance *sin, 764 QXLReleaseInfoExt ext) 765 { 766 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 767 QXLReleaseRing *ring; 768 uint32_t prod; 769 uint64_t id; 770 771 if (!ext.info) { 772 return; 773 } 774 if (ext.group_id == MEMSLOT_GROUP_HOST) { 775 /* host group -> vga mode update request */ 776 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); 777 SimpleSpiceUpdate *update; 778 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); 779 update = container_of(cmdext, SimpleSpiceUpdate, ext); 780 qemu_spice_destroy_update(&qxl->ssd, update); 781 return; 782 } 783 784 /* 785 * ext->info points into guest-visible memory 786 * pci bar 0, $command.release_info 787 */ 788 ring = &qxl->ram->release_ring; 789 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); 790 if (prod >= ARRAY_SIZE(ring->items)) { 791 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " 792 "%u >= %zu", prod, ARRAY_SIZE(ring->items)); 793 return; 794 } 795 if (ring->items[prod].el == 0) { 796 /* stick head into the ring */ 797 id = ext.info->id; 798 ext.info->next = 0; 799 qxl_ram_set_dirty(qxl, &ext.info->next); 800 ring->items[prod].el = id; 801 qxl_ring_set_dirty(qxl); 802 } else { 803 /* append item to the list */ 804 qxl->last_release->next = ext.info->id; 805 qxl_ram_set_dirty(qxl, &qxl->last_release->next); 806 ext.info->next = 0; 807 qxl_ram_set_dirty(qxl, &ext.info->next); 808 } 809 qxl->last_release = ext.info; 810 qxl->num_free_res++; 811 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); 812 qxl_push_free_res(qxl, 0); 813 } 814 815 /* called from spice server thread context only */ 816 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) 817 { 818 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 819 QXLCursorRing *ring; 820 QXLCommand *cmd; 821 int notify; 822 823 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); 824 825 switch (qxl->mode) { 826 case QXL_MODE_COMPAT: 827 case QXL_MODE_NATIVE: 828 case QXL_MODE_UNDEFINED: 829 ring = &qxl->ram->cursor_ring; 830 if (SPICE_RING_IS_EMPTY(ring)) { 831 return false; 832 } 833 SPICE_RING_CONS_ITEM(qxl, ring, cmd); 834 if (!cmd) { 835 return false; 836 } 837 ext->cmd = *cmd; 838 ext->group_id = MEMSLOT_GROUP_GUEST; 839 ext->flags = qxl->cmdflags; 840 SPICE_RING_POP(ring, notify); 841 qxl_ring_set_dirty(qxl); 842 if (notify) { 843 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); 844 } 845 qxl->guest_primary.commands++; 846 qxl_track_command(qxl, ext); 847 qxl_log_command(qxl, "csr", ext); 848 if (qxl->have_vga) { 849 qxl_render_cursor(qxl, ext); 850 } 851 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); 852 return true; 853 default: 854 return false; 855 } 856 } 857 858 /* called from spice server thread context only */ 859 static int interface_req_cursor_notification(QXLInstance *sin) 860 { 861 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 862 int wait = 1; 863 864 trace_qxl_ring_cursor_req_notification(qxl->id); 865 switch (qxl->mode) { 866 case QXL_MODE_COMPAT: 867 case QXL_MODE_NATIVE: 868 case QXL_MODE_UNDEFINED: 869 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); 870 qxl_ring_set_dirty(qxl); 871 break; 872 default: 873 /* nothing */ 874 break; 875 } 876 return wait; 877 } 878 879 /* called from spice server thread context */ 880 static void interface_notify_update(QXLInstance *sin, uint32_t update_id) 881 { 882 /* 883 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in 884 * use by xf86-video-qxl and is defined out in the qxl windows driver. 885 * Probably was at some earlier version that is prior to git start (2009), 886 * and is still guest trigerrable. 887 */ 888 fprintf(stderr, "%s: deprecated\n", __func__); 889 } 890 891 /* called from spice server thread context only */ 892 static int interface_flush_resources(QXLInstance *sin) 893 { 894 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 895 int ret; 896 897 ret = qxl->num_free_res; 898 if (ret) { 899 qxl_push_free_res(qxl, 1); 900 } 901 return ret; 902 } 903 904 static void qxl_create_guest_primary_complete(PCIQXLDevice *d); 905 906 /* called from spice server thread context only */ 907 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) 908 { 909 uint32_t current_async; 910 911 qemu_mutex_lock(&qxl->async_lock); 912 current_async = qxl->current_async; 913 qxl->current_async = QXL_UNDEFINED_IO; 914 qemu_mutex_unlock(&qxl->async_lock); 915 916 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); 917 if (!cookie) { 918 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); 919 return; 920 } 921 if (cookie && current_async != cookie->io) { 922 fprintf(stderr, 923 "qxl: %s: error: current_async = %d != %" 924 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); 925 } 926 switch (current_async) { 927 case QXL_IO_MEMSLOT_ADD_ASYNC: 928 case QXL_IO_DESTROY_PRIMARY_ASYNC: 929 case QXL_IO_UPDATE_AREA_ASYNC: 930 case QXL_IO_FLUSH_SURFACES_ASYNC: 931 case QXL_IO_MONITORS_CONFIG_ASYNC: 932 break; 933 case QXL_IO_CREATE_PRIMARY_ASYNC: 934 qxl_create_guest_primary_complete(qxl); 935 break; 936 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 937 qxl_spice_destroy_surfaces_complete(qxl); 938 break; 939 case QXL_IO_DESTROY_SURFACE_ASYNC: 940 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); 941 break; 942 default: 943 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, 944 current_async); 945 } 946 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); 947 } 948 949 /* called from spice server thread context only */ 950 static void interface_update_area_complete(QXLInstance *sin, 951 uint32_t surface_id, 952 QXLRect *dirty, uint32_t num_updated_rects) 953 { 954 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 955 int i; 956 int qxl_i; 957 958 qemu_mutex_lock(&qxl->ssd.lock); 959 if (surface_id != 0 || !num_updated_rects || 960 !qxl->render_update_cookie_num) { 961 qemu_mutex_unlock(&qxl->ssd.lock); 962 return; 963 } 964 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, 965 dirty->right, dirty->top, dirty->bottom); 966 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); 967 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { 968 /* 969 * overflow - treat this as a full update. Not expected to be common. 970 */ 971 trace_qxl_interface_update_area_complete_overflow(qxl->id, 972 QXL_NUM_DIRTY_RECTS); 973 qxl->guest_primary.resized = 1; 974 } 975 if (qxl->guest_primary.resized) { 976 /* 977 * Don't bother copying or scheduling the bh since we will flip 978 * the whole area anyway on completion of the update_area async call 979 */ 980 qemu_mutex_unlock(&qxl->ssd.lock); 981 return; 982 } 983 qxl_i = qxl->num_dirty_rects; 984 for (i = 0; i < num_updated_rects; i++) { 985 qxl->dirty[qxl_i++] = dirty[i]; 986 } 987 qxl->num_dirty_rects += num_updated_rects; 988 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, 989 qxl->num_dirty_rects); 990 qemu_bh_schedule(qxl->update_area_bh); 991 qemu_mutex_unlock(&qxl->ssd.lock); 992 } 993 994 /* called from spice server thread context only */ 995 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) 996 { 997 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 998 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; 999 1000 switch (cookie->type) { 1001 case QXL_COOKIE_TYPE_IO: 1002 interface_async_complete_io(qxl, cookie); 1003 g_free(cookie); 1004 break; 1005 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: 1006 qxl_render_update_area_done(qxl, cookie); 1007 break; 1008 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG: 1009 break; 1010 default: 1011 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", 1012 __func__, cookie->type); 1013 g_free(cookie); 1014 } 1015 } 1016 1017 /* called from spice server thread context only */ 1018 static void interface_set_client_capabilities(QXLInstance *sin, 1019 uint8_t client_present, 1020 uint8_t caps[58]) 1021 { 1022 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1023 1024 if (qxl->revision < 4) { 1025 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, 1026 qxl->revision); 1027 return; 1028 } 1029 1030 if (runstate_check(RUN_STATE_INMIGRATE) || 1031 runstate_check(RUN_STATE_POSTMIGRATE)) { 1032 return; 1033 } 1034 1035 qxl->shadow_rom.client_present = client_present; 1036 memcpy(qxl->shadow_rom.client_capabilities, caps, 1037 sizeof(qxl->shadow_rom.client_capabilities)); 1038 qxl->rom->client_present = client_present; 1039 memcpy(qxl->rom->client_capabilities, caps, 1040 sizeof(qxl->rom->client_capabilities)); 1041 qxl_rom_set_dirty(qxl); 1042 1043 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT); 1044 } 1045 1046 static bool qxl_rom_monitors_config_changed(QXLRom *rom, 1047 VDAgentMonitorsConfig *monitors_config, 1048 unsigned int max_outputs) 1049 { 1050 int i; 1051 unsigned int monitors_count; 1052 1053 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs); 1054 1055 if (rom->client_monitors_config.count != monitors_count) { 1056 return true; 1057 } 1058 1059 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1060 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1061 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1062 /* monitor->depth ignored */ 1063 if ((rect->left != monitor->x) || 1064 (rect->top != monitor->y) || 1065 (rect->right != monitor->x + monitor->width) || 1066 (rect->bottom != monitor->y + monitor->height)) { 1067 return true; 1068 } 1069 } 1070 1071 return false; 1072 } 1073 1074 /* called from main context only */ 1075 static int interface_client_monitors_config(QXLInstance *sin, 1076 VDAgentMonitorsConfig *monitors_config) 1077 { 1078 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); 1079 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); 1080 int i; 1081 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads); 1082 bool config_changed = false; 1083 1084 if (qxl->revision < 4) { 1085 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, 1086 qxl->revision); 1087 return 0; 1088 } 1089 /* 1090 * Older windows drivers set int_mask to 0 when their ISR is called, 1091 * then later set it to ~0. So it doesn't relate to the actual interrupts 1092 * handled. However, they are old, so clearly they don't support this 1093 * interrupt 1094 */ 1095 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || 1096 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { 1097 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, 1098 qxl->ram->int_mask, 1099 monitors_config); 1100 return 0; 1101 } 1102 if (!monitors_config) { 1103 return 1; 1104 } 1105 1106 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 1107 /* limit number of outputs based on setting limit */ 1108 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) { 1109 max_outputs = qxl->max_outputs; 1110 } 1111 #endif 1112 1113 config_changed = qxl_rom_monitors_config_changed(rom, 1114 monitors_config, 1115 max_outputs); 1116 1117 memset(&rom->client_monitors_config, 0, 1118 sizeof(rom->client_monitors_config)); 1119 rom->client_monitors_config.count = monitors_config->num_of_monitors; 1120 /* monitors_config->flags ignored */ 1121 if (rom->client_monitors_config.count >= max_outputs) { 1122 trace_qxl_client_monitors_config_capped(qxl->id, 1123 monitors_config->num_of_monitors, 1124 max_outputs); 1125 rom->client_monitors_config.count = max_outputs; 1126 } 1127 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { 1128 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; 1129 QXLURect *rect = &rom->client_monitors_config.heads[i]; 1130 /* monitor->depth ignored */ 1131 rect->left = monitor->x; 1132 rect->top = monitor->y; 1133 rect->right = monitor->x + monitor->width; 1134 rect->bottom = monitor->y + monitor->height; 1135 } 1136 rom->client_monitors_config_crc = qxl_crc32( 1137 (const uint8_t *)&rom->client_monitors_config, 1138 sizeof(rom->client_monitors_config)); 1139 trace_qxl_client_monitors_config_crc(qxl->id, 1140 sizeof(rom->client_monitors_config), 1141 rom->client_monitors_config_crc); 1142 1143 trace_qxl_interrupt_client_monitors_config(qxl->id, 1144 rom->client_monitors_config.count, 1145 rom->client_monitors_config.heads); 1146 if (config_changed) { 1147 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG); 1148 } 1149 return 1; 1150 } 1151 1152 static const QXLInterface qxl_interface = { 1153 .base.type = SPICE_INTERFACE_QXL, 1154 .base.description = "qxl gpu", 1155 .base.major_version = SPICE_INTERFACE_QXL_MAJOR, 1156 .base.minor_version = SPICE_INTERFACE_QXL_MINOR, 1157 1158 .attache_worker = interface_attach_worker, 1159 .set_compression_level = interface_set_compression_level, 1160 #if SPICE_NEEDS_SET_MM_TIME 1161 .set_mm_time = interface_set_mm_time, 1162 #endif 1163 .get_init_info = interface_get_init_info, 1164 1165 /* the callbacks below are called from spice server thread context */ 1166 .get_command = interface_get_command, 1167 .req_cmd_notification = interface_req_cmd_notification, 1168 .release_resource = interface_release_resource, 1169 .get_cursor_command = interface_get_cursor_command, 1170 .req_cursor_notification = interface_req_cursor_notification, 1171 .notify_update = interface_notify_update, 1172 .flush_resources = interface_flush_resources, 1173 .async_complete = interface_async_complete, 1174 .update_area_complete = interface_update_area_complete, 1175 .set_client_capabilities = interface_set_client_capabilities, 1176 .client_monitors_config = interface_client_monitors_config, 1177 }; 1178 1179 static const GraphicHwOps qxl_ops = { 1180 .gfx_update = qxl_hw_update, 1181 }; 1182 1183 static void qxl_enter_vga_mode(PCIQXLDevice *d) 1184 { 1185 if (d->mode == QXL_MODE_VGA) { 1186 return; 1187 } 1188 trace_qxl_enter_vga_mode(d->id); 1189 spice_qxl_driver_unload(&d->ssd.qxl); 1190 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); 1191 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); 1192 qemu_spice_create_host_primary(&d->ssd); 1193 d->mode = QXL_MODE_VGA; 1194 qemu_spice_display_switch(&d->ssd, d->ssd.ds); 1195 vga_dirty_log_start(&d->vga); 1196 graphic_hw_update(d->vga.con); 1197 } 1198 1199 static void qxl_exit_vga_mode(PCIQXLDevice *d) 1200 { 1201 if (d->mode != QXL_MODE_VGA) { 1202 return; 1203 } 1204 trace_qxl_exit_vga_mode(d->id); 1205 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); 1206 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); 1207 vga_dirty_log_stop(&d->vga); 1208 qxl_destroy_primary(d, QXL_SYNC); 1209 } 1210 1211 static void qxl_update_irq(PCIQXLDevice *d) 1212 { 1213 uint32_t pending = le32_to_cpu(d->ram->int_pending); 1214 uint32_t mask = le32_to_cpu(d->ram->int_mask); 1215 int level = !!(pending & mask); 1216 pci_set_irq(&d->pci, level); 1217 qxl_ring_set_dirty(d); 1218 } 1219 1220 static void qxl_check_state(PCIQXLDevice *d) 1221 { 1222 QXLRam *ram = d->ram; 1223 int spice_display_running = qemu_spice_display_is_running(&d->ssd); 1224 1225 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); 1226 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); 1227 } 1228 1229 static void qxl_reset_state(PCIQXLDevice *d) 1230 { 1231 QXLRom *rom = d->rom; 1232 1233 qxl_check_state(d); 1234 d->shadow_rom.update_id = cpu_to_le32(0); 1235 *rom = d->shadow_rom; 1236 qxl_rom_set_dirty(d); 1237 init_qxl_ram(d); 1238 d->num_free_res = 0; 1239 d->last_release = NULL; 1240 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); 1241 qxl_update_irq(d); 1242 } 1243 1244 static void qxl_soft_reset(PCIQXLDevice *d) 1245 { 1246 trace_qxl_soft_reset(d->id); 1247 qxl_check_state(d); 1248 qxl_clear_guest_bug(d); 1249 qemu_mutex_lock(&d->async_lock); 1250 d->current_async = QXL_UNDEFINED_IO; 1251 qemu_mutex_unlock(&d->async_lock); 1252 1253 if (d->have_vga) { 1254 qxl_enter_vga_mode(d); 1255 } else { 1256 d->mode = QXL_MODE_UNDEFINED; 1257 } 1258 } 1259 1260 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) 1261 { 1262 bool startstop = qemu_spice_display_is_running(&d->ssd); 1263 1264 trace_qxl_hard_reset(d->id, loadvm); 1265 1266 if (startstop) { 1267 qemu_spice_display_stop(); 1268 } 1269 1270 qxl_spice_reset_cursor(d); 1271 qxl_spice_reset_image_cache(d); 1272 qxl_reset_surfaces(d); 1273 qxl_reset_memslots(d); 1274 1275 /* pre loadvm reset must not touch QXLRam. This lives in 1276 * device memory, is migrated together with RAM and thus 1277 * already loaded at this point */ 1278 if (!loadvm) { 1279 qxl_reset_state(d); 1280 } 1281 qemu_spice_create_host_memslot(&d->ssd); 1282 qxl_soft_reset(d); 1283 1284 if (d->migration_blocker) { 1285 migrate_del_blocker(d->migration_blocker); 1286 error_free(d->migration_blocker); 1287 d->migration_blocker = NULL; 1288 } 1289 1290 if (startstop) { 1291 qemu_spice_display_start(); 1292 } 1293 } 1294 1295 static void qxl_reset_handler(DeviceState *dev) 1296 { 1297 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev)); 1298 1299 qxl_hard_reset(d, 0); 1300 } 1301 1302 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1303 { 1304 VGACommonState *vga = opaque; 1305 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); 1306 1307 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); 1308 if (qxl->mode != QXL_MODE_VGA) { 1309 qxl_destroy_primary(qxl, QXL_SYNC); 1310 qxl_soft_reset(qxl); 1311 } 1312 vga_ioport_write(opaque, addr, val); 1313 } 1314 1315 static const MemoryRegionPortio qxl_vga_portio_list[] = { 1316 { 0x04, 2, 1, .read = vga_ioport_read, 1317 .write = qxl_vga_ioport_write }, /* 3b4 */ 1318 { 0x0a, 1, 1, .read = vga_ioport_read, 1319 .write = qxl_vga_ioport_write }, /* 3ba */ 1320 { 0x10, 16, 1, .read = vga_ioport_read, 1321 .write = qxl_vga_ioport_write }, /* 3c0 */ 1322 { 0x24, 2, 1, .read = vga_ioport_read, 1323 .write = qxl_vga_ioport_write }, /* 3d4 */ 1324 { 0x2a, 1, 1, .read = vga_ioport_read, 1325 .write = qxl_vga_ioport_write }, /* 3da */ 1326 PORTIO_END_OF_LIST(), 1327 }; 1328 1329 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, 1330 qxl_async_io async) 1331 { 1332 static const int regions[] = { 1333 QXL_RAM_RANGE_INDEX, 1334 QXL_VRAM_RANGE_INDEX, 1335 QXL_VRAM64_RANGE_INDEX, 1336 }; 1337 uint64_t guest_start; 1338 uint64_t guest_end; 1339 int pci_region; 1340 pcibus_t pci_start; 1341 pcibus_t pci_end; 1342 MemoryRegion *mr; 1343 intptr_t virt_start; 1344 QXLDevMemSlot memslot; 1345 int i; 1346 1347 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); 1348 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); 1349 1350 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); 1351 1352 if (slot_id >= NUM_MEMSLOTS) { 1353 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, 1354 slot_id, NUM_MEMSLOTS); 1355 return 1; 1356 } 1357 if (guest_start > guest_end) { 1358 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 1359 " > 0x%" PRIx64, __func__, guest_start, guest_end); 1360 return 1; 1361 } 1362 1363 for (i = 0; i < ARRAY_SIZE(regions); i++) { 1364 pci_region = regions[i]; 1365 pci_start = d->pci.io_regions[pci_region].addr; 1366 pci_end = pci_start + d->pci.io_regions[pci_region].size; 1367 /* mapped? */ 1368 if (pci_start == -1) { 1369 continue; 1370 } 1371 /* start address in range ? */ 1372 if (guest_start < pci_start || guest_start > pci_end) { 1373 continue; 1374 } 1375 /* end address in range ? */ 1376 if (guest_end > pci_end) { 1377 continue; 1378 } 1379 /* passed */ 1380 break; 1381 } 1382 if (i == ARRAY_SIZE(regions)) { 1383 qxl_set_guest_bug(d, "%s: finished loop without match", __func__); 1384 return 1; 1385 } 1386 1387 switch (pci_region) { 1388 case QXL_RAM_RANGE_INDEX: 1389 mr = &d->vga.vram; 1390 break; 1391 case QXL_VRAM_RANGE_INDEX: 1392 case 4 /* vram 64bit */: 1393 mr = &d->vram_bar; 1394 break; 1395 default: 1396 /* should not happen */ 1397 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); 1398 return 1; 1399 } 1400 1401 virt_start = (intptr_t)memory_region_get_ram_ptr(mr); 1402 memslot.slot_id = slot_id; 1403 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ 1404 memslot.virt_start = virt_start + (guest_start - pci_start); 1405 memslot.virt_end = virt_start + (guest_end - pci_start); 1406 memslot.addr_delta = memslot.virt_start - delta; 1407 memslot.generation = d->rom->slot_generation = 0; 1408 qxl_rom_set_dirty(d); 1409 1410 qemu_spice_add_memslot(&d->ssd, &memslot, async); 1411 d->guest_slots[slot_id].mr = mr; 1412 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start; 1413 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; 1414 d->guest_slots[slot_id].delta = delta; 1415 d->guest_slots[slot_id].active = 1; 1416 return 0; 1417 } 1418 1419 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) 1420 { 1421 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); 1422 d->guest_slots[slot_id].active = 0; 1423 } 1424 1425 static void qxl_reset_memslots(PCIQXLDevice *d) 1426 { 1427 qxl_spice_reset_memslots(d); 1428 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); 1429 } 1430 1431 static void qxl_reset_surfaces(PCIQXLDevice *d) 1432 { 1433 trace_qxl_reset_surfaces(d->id); 1434 d->mode = QXL_MODE_UNDEFINED; 1435 qxl_spice_destroy_surfaces(d, QXL_SYNC); 1436 } 1437 1438 /* can be also called from spice server thread context */ 1439 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1440 uint32_t *s, uint64_t *o) 1441 { 1442 uint64_t phys = le64_to_cpu(pqxl); 1443 uint32_t slot = (phys >> (64 - 8)) & 0xff; 1444 uint64_t offset = phys & 0xffffffffffff; 1445 1446 if (slot >= NUM_MEMSLOTS) { 1447 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, 1448 NUM_MEMSLOTS); 1449 return false; 1450 } 1451 if (!qxl->guest_slots[slot].active) { 1452 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); 1453 return false; 1454 } 1455 if (offset < qxl->guest_slots[slot].delta) { 1456 qxl_set_guest_bug(qxl, 1457 "slot %d offset %"PRIu64" < delta %"PRIu64"\n", 1458 slot, offset, qxl->guest_slots[slot].delta); 1459 return false; 1460 } 1461 offset -= qxl->guest_slots[slot].delta; 1462 if (offset > qxl->guest_slots[slot].size) { 1463 qxl_set_guest_bug(qxl, 1464 "slot %d offset %"PRIu64" > size %"PRIu64"\n", 1465 slot, offset, qxl->guest_slots[slot].size); 1466 return false; 1467 } 1468 1469 *s = slot; 1470 *o = offset; 1471 return true; 1472 } 1473 1474 /* can be also called from spice server thread context */ 1475 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) 1476 { 1477 uint64_t offset; 1478 uint32_t slot; 1479 void *ptr; 1480 1481 switch (group_id) { 1482 case MEMSLOT_GROUP_HOST: 1483 offset = le64_to_cpu(pqxl) & 0xffffffffffff; 1484 return (void *)(intptr_t)offset; 1485 case MEMSLOT_GROUP_GUEST: 1486 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) { 1487 return NULL; 1488 } 1489 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr); 1490 ptr += qxl->guest_slots[slot].offset; 1491 ptr += offset; 1492 return ptr; 1493 } 1494 return NULL; 1495 } 1496 1497 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) 1498 { 1499 /* for local rendering */ 1500 qxl_render_resize(qxl); 1501 } 1502 1503 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, 1504 qxl_async_io async) 1505 { 1506 QXLDevSurfaceCreate surface; 1507 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; 1508 uint32_t requested_height = le32_to_cpu(sc->height); 1509 int requested_stride = le32_to_cpu(sc->stride); 1510 1511 if (requested_stride == INT32_MIN || 1512 abs(requested_stride) * (uint64_t)requested_height 1513 > qxl->vgamem_size) { 1514 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer" 1515 " stride %d x height %" PRIu32 " > %" PRIu32, 1516 __func__, requested_stride, requested_height, 1517 qxl->vgamem_size); 1518 return; 1519 } 1520 1521 if (qxl->mode == QXL_MODE_NATIVE) { 1522 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", 1523 __func__); 1524 } 1525 qxl_exit_vga_mode(qxl); 1526 1527 surface.format = le32_to_cpu(sc->format); 1528 surface.height = le32_to_cpu(sc->height); 1529 surface.mem = le64_to_cpu(sc->mem); 1530 surface.position = le32_to_cpu(sc->position); 1531 surface.stride = le32_to_cpu(sc->stride); 1532 surface.width = le32_to_cpu(sc->width); 1533 surface.type = le32_to_cpu(sc->type); 1534 surface.flags = le32_to_cpu(sc->flags); 1535 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, 1536 sc->format, sc->position); 1537 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, 1538 sc->flags); 1539 1540 if ((surface.stride & 0x3) != 0) { 1541 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0", 1542 surface.stride); 1543 return; 1544 } 1545 1546 surface.mouse_mode = true; 1547 surface.group_id = MEMSLOT_GROUP_GUEST; 1548 if (loadvm) { 1549 surface.flags |= QXL_SURF_FLAG_KEEP_DATA; 1550 } 1551 1552 qxl->mode = QXL_MODE_NATIVE; 1553 qxl->cmdflags = 0; 1554 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); 1555 1556 if (async == QXL_SYNC) { 1557 qxl_create_guest_primary_complete(qxl); 1558 } 1559 } 1560 1561 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or 1562 * done (in QXL_SYNC case), 0 otherwise. */ 1563 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) 1564 { 1565 if (d->mode == QXL_MODE_UNDEFINED) { 1566 return 0; 1567 } 1568 trace_qxl_destroy_primary(d->id); 1569 d->mode = QXL_MODE_UNDEFINED; 1570 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); 1571 qxl_spice_reset_cursor(d); 1572 return 1; 1573 } 1574 1575 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm) 1576 { 1577 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1578 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; 1579 QXLMode *mode = d->modes->modes + modenr; 1580 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; 1581 QXLMemSlot slot = { 1582 .mem_start = start, 1583 .mem_end = end 1584 }; 1585 1586 if (modenr >= d->modes->n_modes) { 1587 qxl_set_guest_bug(d, "mode number out of range"); 1588 return; 1589 } 1590 1591 QXLSurfaceCreate surface = { 1592 .width = mode->x_res, 1593 .height = mode->y_res, 1594 .stride = -mode->x_res * 4, 1595 .format = SPICE_SURFACE_FMT_32_xRGB, 1596 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, 1597 .mouse_mode = true, 1598 .mem = devmem + d->shadow_rom.draw_area_offset, 1599 }; 1600 1601 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, 1602 devmem); 1603 if (!loadvm) { 1604 qxl_hard_reset(d, 0); 1605 } 1606 1607 d->guest_slots[0].slot = slot; 1608 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); 1609 1610 d->guest_primary.surface = surface; 1611 qxl_create_guest_primary(d, 0, QXL_SYNC); 1612 1613 d->mode = QXL_MODE_COMPAT; 1614 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; 1615 if (mode->bits == 16) { 1616 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; 1617 } 1618 d->shadow_rom.mode = cpu_to_le32(modenr); 1619 d->rom->mode = cpu_to_le32(modenr); 1620 qxl_rom_set_dirty(d); 1621 } 1622 1623 static void ioport_write(void *opaque, hwaddr addr, 1624 uint64_t val, unsigned size) 1625 { 1626 PCIQXLDevice *d = opaque; 1627 uint32_t io_port = addr; 1628 qxl_async_io async = QXL_SYNC; 1629 uint32_t orig_io_port = io_port; 1630 1631 if (d->guest_bug && io_port != QXL_IO_RESET) { 1632 return; 1633 } 1634 1635 if (d->revision <= QXL_REVISION_STABLE_V10 && 1636 io_port > QXL_IO_FLUSH_RELEASE) { 1637 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n", 1638 io_port, d->revision); 1639 return; 1640 } 1641 1642 switch (io_port) { 1643 case QXL_IO_RESET: 1644 case QXL_IO_SET_MODE: 1645 case QXL_IO_MEMSLOT_ADD: 1646 case QXL_IO_MEMSLOT_DEL: 1647 case QXL_IO_CREATE_PRIMARY: 1648 case QXL_IO_UPDATE_IRQ: 1649 case QXL_IO_LOG: 1650 case QXL_IO_MEMSLOT_ADD_ASYNC: 1651 case QXL_IO_CREATE_PRIMARY_ASYNC: 1652 break; 1653 default: 1654 if (d->mode != QXL_MODE_VGA) { 1655 break; 1656 } 1657 trace_qxl_io_unexpected_vga_mode(d->id, 1658 addr, val, io_port_to_string(io_port)); 1659 /* be nice to buggy guest drivers */ 1660 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && 1661 io_port < QXL_IO_RANGE_SIZE) { 1662 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1663 } 1664 return; 1665 } 1666 1667 /* we change the io_port to avoid ifdeffery in the main switch */ 1668 orig_io_port = io_port; 1669 switch (io_port) { 1670 case QXL_IO_UPDATE_AREA_ASYNC: 1671 io_port = QXL_IO_UPDATE_AREA; 1672 goto async_common; 1673 case QXL_IO_MEMSLOT_ADD_ASYNC: 1674 io_port = QXL_IO_MEMSLOT_ADD; 1675 goto async_common; 1676 case QXL_IO_CREATE_PRIMARY_ASYNC: 1677 io_port = QXL_IO_CREATE_PRIMARY; 1678 goto async_common; 1679 case QXL_IO_DESTROY_PRIMARY_ASYNC: 1680 io_port = QXL_IO_DESTROY_PRIMARY; 1681 goto async_common; 1682 case QXL_IO_DESTROY_SURFACE_ASYNC: 1683 io_port = QXL_IO_DESTROY_SURFACE_WAIT; 1684 goto async_common; 1685 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: 1686 io_port = QXL_IO_DESTROY_ALL_SURFACES; 1687 goto async_common; 1688 case QXL_IO_FLUSH_SURFACES_ASYNC: 1689 case QXL_IO_MONITORS_CONFIG_ASYNC: 1690 async_common: 1691 async = QXL_ASYNC; 1692 qemu_mutex_lock(&d->async_lock); 1693 if (d->current_async != QXL_UNDEFINED_IO) { 1694 qxl_set_guest_bug(d, "%d async started before last (%d) complete", 1695 io_port, d->current_async); 1696 qemu_mutex_unlock(&d->async_lock); 1697 return; 1698 } 1699 d->current_async = orig_io_port; 1700 qemu_mutex_unlock(&d->async_lock); 1701 break; 1702 default: 1703 break; 1704 } 1705 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), 1706 addr, io_port_to_string(addr), 1707 val, size, async); 1708 1709 switch (io_port) { 1710 case QXL_IO_UPDATE_AREA: 1711 { 1712 QXLCookie *cookie = NULL; 1713 QXLRect update = d->ram->update_area; 1714 1715 if (d->ram->update_surface > d->ssd.num_surfaces) { 1716 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n", 1717 d->ram->update_surface); 1718 break; 1719 } 1720 if (update.left >= update.right || update.top >= update.bottom || 1721 update.left < 0 || update.top < 0) { 1722 qxl_set_guest_bug(d, 1723 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n", 1724 update.left, update.top, update.right, update.bottom); 1725 if (update.left == update.right || update.top == update.bottom) { 1726 /* old drivers may provide empty area, keep going */ 1727 qxl_clear_guest_bug(d); 1728 goto cancel_async; 1729 } 1730 break; 1731 } 1732 if (async == QXL_ASYNC) { 1733 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, 1734 QXL_IO_UPDATE_AREA_ASYNC); 1735 cookie->u.area = update; 1736 } 1737 qxl_spice_update_area(d, d->ram->update_surface, 1738 cookie ? &cookie->u.area : &update, 1739 NULL, 0, 0, async, cookie); 1740 break; 1741 } 1742 case QXL_IO_NOTIFY_CMD: 1743 qemu_spice_wakeup(&d->ssd); 1744 break; 1745 case QXL_IO_NOTIFY_CURSOR: 1746 qemu_spice_wakeup(&d->ssd); 1747 break; 1748 case QXL_IO_UPDATE_IRQ: 1749 qxl_update_irq(d); 1750 break; 1751 case QXL_IO_NOTIFY_OOM: 1752 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { 1753 break; 1754 } 1755 d->oom_running = 1; 1756 qxl_spice_oom(d); 1757 d->oom_running = 0; 1758 break; 1759 case QXL_IO_SET_MODE: 1760 qxl_set_mode(d, val, 0); 1761 break; 1762 case QXL_IO_LOG: 1763 if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) { 1764 /* We cannot trust the guest to NUL terminate d->ram->log_buf */ 1765 char *log_buf = g_strndup((const char *)d->ram->log_buf, 1766 sizeof(d->ram->log_buf)); 1767 trace_qxl_io_log(d->id, log_buf); 1768 if (d->guestdebug) { 1769 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, 1770 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf); 1771 } 1772 g_free(log_buf); 1773 } 1774 break; 1775 case QXL_IO_RESET: 1776 qxl_hard_reset(d, 0); 1777 break; 1778 case QXL_IO_MEMSLOT_ADD: 1779 if (val >= NUM_MEMSLOTS) { 1780 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); 1781 break; 1782 } 1783 if (d->guest_slots[val].active) { 1784 qxl_set_guest_bug(d, 1785 "QXL_IO_MEMSLOT_ADD: memory slot already active"); 1786 break; 1787 } 1788 d->guest_slots[val].slot = d->ram->mem_slot; 1789 qxl_add_memslot(d, val, 0, async); 1790 break; 1791 case QXL_IO_MEMSLOT_DEL: 1792 if (val >= NUM_MEMSLOTS) { 1793 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); 1794 break; 1795 } 1796 qxl_del_memslot(d, val); 1797 break; 1798 case QXL_IO_CREATE_PRIMARY: 1799 if (val != 0) { 1800 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", 1801 async); 1802 goto cancel_async; 1803 } 1804 d->guest_primary.surface = d->ram->create_surface; 1805 qxl_create_guest_primary(d, 0, async); 1806 break; 1807 case QXL_IO_DESTROY_PRIMARY: 1808 if (val != 0) { 1809 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", 1810 async); 1811 goto cancel_async; 1812 } 1813 if (!qxl_destroy_primary(d, async)) { 1814 trace_qxl_io_destroy_primary_ignored(d->id, 1815 qxl_mode_to_string(d->mode)); 1816 goto cancel_async; 1817 } 1818 break; 1819 case QXL_IO_DESTROY_SURFACE_WAIT: 1820 if (val >= d->ssd.num_surfaces) { 1821 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" 1822 "%" PRIu64 " >= NUM_SURFACES", async, val); 1823 goto cancel_async; 1824 } 1825 qxl_spice_destroy_surface_wait(d, val, async); 1826 break; 1827 case QXL_IO_FLUSH_RELEASE: { 1828 QXLReleaseRing *ring = &d->ram->release_ring; 1829 if (ring->prod - ring->cons + 1 == ring->num_items) { 1830 fprintf(stderr, 1831 "ERROR: no flush, full release ring [p%d,%dc]\n", 1832 ring->prod, ring->cons); 1833 } 1834 qxl_push_free_res(d, 1 /* flush */); 1835 break; 1836 } 1837 case QXL_IO_FLUSH_SURFACES_ASYNC: 1838 qxl_spice_flush_surfaces_async(d); 1839 break; 1840 case QXL_IO_DESTROY_ALL_SURFACES: 1841 d->mode = QXL_MODE_UNDEFINED; 1842 qxl_spice_destroy_surfaces(d, async); 1843 break; 1844 case QXL_IO_MONITORS_CONFIG_ASYNC: 1845 qxl_spice_monitors_config_async(d, 0); 1846 break; 1847 default: 1848 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); 1849 } 1850 return; 1851 cancel_async: 1852 if (async) { 1853 qxl_send_events(d, QXL_INTERRUPT_IO_CMD); 1854 qemu_mutex_lock(&d->async_lock); 1855 d->current_async = QXL_UNDEFINED_IO; 1856 qemu_mutex_unlock(&d->async_lock); 1857 } 1858 } 1859 1860 static uint64_t ioport_read(void *opaque, hwaddr addr, 1861 unsigned size) 1862 { 1863 PCIQXLDevice *qxl = opaque; 1864 1865 trace_qxl_io_read_unexpected(qxl->id); 1866 return 0xff; 1867 } 1868 1869 static const MemoryRegionOps qxl_io_ops = { 1870 .read = ioport_read, 1871 .write = ioport_write, 1872 .valid = { 1873 .min_access_size = 1, 1874 .max_access_size = 1, 1875 }, 1876 }; 1877 1878 static void qxl_update_irq_bh(void *opaque) 1879 { 1880 PCIQXLDevice *d = opaque; 1881 qxl_update_irq(d); 1882 } 1883 1884 static void qxl_send_events(PCIQXLDevice *d, uint32_t events) 1885 { 1886 uint32_t old_pending; 1887 uint32_t le_events = cpu_to_le32(events); 1888 1889 trace_qxl_send_events(d->id, events); 1890 if (!qemu_spice_display_is_running(&d->ssd)) { 1891 /* spice-server tracks guest running state and should not do this */ 1892 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n", 1893 __func__); 1894 trace_qxl_send_events_vm_stopped(d->id, events); 1895 return; 1896 } 1897 /* 1898 * Older versions of Spice forgot to define the QXLRam struct 1899 * with the '__aligned__(4)' attribute. clang 7 and newer will 1900 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...) 1901 * might be a misaligned atomic access, and will generate an 1902 * out-of-line call for it, which results in a link error since 1903 * we don't currently link against libatomic. 1904 * 1905 * In fact we set up d->ram in init_qxl_ram() so it always starts 1906 * at a 4K boundary, so we know that &d->ram->int_pending is 1907 * naturally aligned for a uint32_t. Newer Spice versions 1908 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) 1909 * will fix the bug directly. To deal with older versions, 1910 * we tell the compiler to assume the address really is aligned. 1911 * Any compiler which cares about the misalignment will have 1912 * __builtin_assume_aligned. 1913 */ 1914 #ifdef HAS_ASSUME_ALIGNED 1915 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4)) 1916 #else 1917 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P) 1918 #endif 1919 1920 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending), 1921 le_events); 1922 if ((old_pending & le_events) == le_events) { 1923 return; 1924 } 1925 qemu_bh_schedule(d->update_irq); 1926 } 1927 1928 /* graphics console */ 1929 1930 static void qxl_hw_update(void *opaque) 1931 { 1932 PCIQXLDevice *qxl = opaque; 1933 1934 qxl_render_update(qxl); 1935 } 1936 1937 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, 1938 uint32_t height, int32_t stride) 1939 { 1940 uint64_t offset, size; 1941 uint32_t slot; 1942 bool rc; 1943 1944 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset); 1945 assert(rc == true); 1946 size = (uint64_t)height * abs(stride); 1947 trace_qxl_surfaces_dirty(qxl->id, offset, size); 1948 qxl_set_dirty(qxl->guest_slots[slot].mr, 1949 qxl->guest_slots[slot].offset + offset, 1950 qxl->guest_slots[slot].offset + offset + size); 1951 } 1952 1953 static void qxl_dirty_surfaces(PCIQXLDevice *qxl) 1954 { 1955 int i; 1956 1957 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { 1958 return; 1959 } 1960 1961 /* dirty the primary surface */ 1962 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem, 1963 qxl->guest_primary.surface.height, 1964 qxl->guest_primary.surface.stride); 1965 1966 /* dirty the off-screen surfaces */ 1967 for (i = 0; i < qxl->ssd.num_surfaces; i++) { 1968 QXLSurfaceCmd *cmd; 1969 1970 if (qxl->guest_surfaces.cmds[i] == 0) { 1971 continue; 1972 } 1973 1974 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], 1975 MEMSLOT_GROUP_GUEST); 1976 assert(cmd); 1977 assert(cmd->type == QXL_SURFACE_CMD_CREATE); 1978 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data, 1979 cmd->u.surface_create.height, 1980 cmd->u.surface_create.stride); 1981 } 1982 } 1983 1984 static void qxl_vm_change_state_handler(void *opaque, int running, 1985 RunState state) 1986 { 1987 PCIQXLDevice *qxl = opaque; 1988 1989 if (running) { 1990 /* 1991 * if qxl_send_events was called from spice server context before 1992 * migration ended, qxl_update_irq for these events might not have been 1993 * called 1994 */ 1995 qxl_update_irq(qxl); 1996 } else { 1997 /* make sure surfaces are saved before migration */ 1998 qxl_dirty_surfaces(qxl); 1999 } 2000 } 2001 2002 /* display change listener */ 2003 2004 static void display_update(DisplayChangeListener *dcl, 2005 int x, int y, int w, int h) 2006 { 2007 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2008 2009 if (qxl->mode == QXL_MODE_VGA) { 2010 qemu_spice_display_update(&qxl->ssd, x, y, w, h); 2011 } 2012 } 2013 2014 static void display_switch(DisplayChangeListener *dcl, 2015 struct DisplaySurface *surface) 2016 { 2017 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2018 2019 qxl->ssd.ds = surface; 2020 if (qxl->mode == QXL_MODE_VGA) { 2021 qemu_spice_display_switch(&qxl->ssd, surface); 2022 } 2023 } 2024 2025 static void display_refresh(DisplayChangeListener *dcl) 2026 { 2027 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl); 2028 2029 if (qxl->mode == QXL_MODE_VGA) { 2030 qemu_spice_display_refresh(&qxl->ssd); 2031 } 2032 } 2033 2034 static DisplayChangeListenerOps display_listener_ops = { 2035 .dpy_name = "spice/qxl", 2036 .dpy_gfx_update = display_update, 2037 .dpy_gfx_switch = display_switch, 2038 .dpy_refresh = display_refresh, 2039 }; 2040 2041 static void qxl_init_ramsize(PCIQXLDevice *qxl) 2042 { 2043 /* vga mode framebuffer / primary surface (bar 0, first part) */ 2044 if (qxl->vgamem_size_mb < 8) { 2045 qxl->vgamem_size_mb = 8; 2046 } 2047 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be 2048 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now). 2049 */ 2050 if (qxl->vgamem_size_mb > 256) { 2051 qxl->vgamem_size_mb = 256; 2052 } 2053 qxl->vgamem_size = qxl->vgamem_size_mb * MiB; 2054 2055 /* vga ram (bar 0, total) */ 2056 if (qxl->ram_size_mb != -1) { 2057 qxl->vga.vram_size = qxl->ram_size_mb * MiB; 2058 } 2059 if (qxl->vga.vram_size < qxl->vgamem_size * 2) { 2060 qxl->vga.vram_size = qxl->vgamem_size * 2; 2061 } 2062 2063 /* vram32 (surfaces, 32bit, bar 1) */ 2064 if (qxl->vram32_size_mb != -1) { 2065 qxl->vram32_size = qxl->vram32_size_mb * MiB; 2066 } 2067 if (qxl->vram32_size < 4096) { 2068 qxl->vram32_size = 4096; 2069 } 2070 2071 /* vram (surfaces, 64bit, bar 4+5) */ 2072 if (qxl->vram_size_mb != -1) { 2073 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB; 2074 } 2075 if (qxl->vram_size < qxl->vram32_size) { 2076 qxl->vram_size = qxl->vram32_size; 2077 } 2078 2079 if (qxl->revision == 1) { 2080 qxl->vram32_size = 4096; 2081 qxl->vram_size = 4096; 2082 } 2083 qxl->vgamem_size = pow2ceil(qxl->vgamem_size); 2084 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size); 2085 qxl->vram32_size = pow2ceil(qxl->vram32_size); 2086 qxl->vram_size = pow2ceil(qxl->vram_size); 2087 } 2088 2089 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) 2090 { 2091 uint8_t* config = qxl->pci.config; 2092 uint32_t pci_device_rev; 2093 uint32_t io_size; 2094 2095 qemu_spice_display_init_common(&qxl->ssd); 2096 qxl->mode = QXL_MODE_UNDEFINED; 2097 qxl->num_memslots = NUM_MEMSLOTS; 2098 qemu_mutex_init(&qxl->track_lock); 2099 qemu_mutex_init(&qxl->async_lock); 2100 qxl->current_async = QXL_UNDEFINED_IO; 2101 qxl->guest_bug = 0; 2102 2103 switch (qxl->revision) { 2104 case 1: /* spice 0.4 -- qxl-1 */ 2105 pci_device_rev = QXL_REVISION_STABLE_V04; 2106 io_size = 8; 2107 break; 2108 case 2: /* spice 0.6 -- qxl-2 */ 2109 pci_device_rev = QXL_REVISION_STABLE_V06; 2110 io_size = 16; 2111 break; 2112 case 3: /* qxl-3 */ 2113 pci_device_rev = QXL_REVISION_STABLE_V10; 2114 io_size = 32; /* PCI region size must be pow2 */ 2115 break; 2116 case 4: /* qxl-4 */ 2117 pci_device_rev = QXL_REVISION_STABLE_V12; 2118 io_size = pow2ceil(QXL_IO_RANGE_SIZE); 2119 break; 2120 default: 2121 error_setg(errp, "Invalid revision %d for qxl device (max %d)", 2122 qxl->revision, QXL_DEFAULT_REVISION); 2123 return; 2124 } 2125 2126 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); 2127 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); 2128 2129 qxl->rom_size = qxl_rom_size(); 2130 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", 2131 qxl->rom_size, &error_fatal); 2132 init_qxl_rom(qxl); 2133 init_qxl_ram(qxl); 2134 2135 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); 2136 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", 2137 qxl->vram_size, &error_fatal); 2138 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", 2139 &qxl->vram_bar, 0, qxl->vram32_size); 2140 2141 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl, 2142 "qxl-ioports", io_size); 2143 if (qxl->have_vga) { 2144 vga_dirty_log_start(&qxl->vga); 2145 } 2146 memory_region_set_flush_coalesced(&qxl->io_bar); 2147 2148 2149 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, 2150 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); 2151 2152 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, 2153 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); 2154 2155 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, 2156 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); 2157 2158 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, 2159 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); 2160 2161 if (qxl->vram32_size < qxl->vram_size) { 2162 /* 2163 * Make the 64bit vram bar show up only in case it is 2164 * configured to be larger than the 32bit vram bar. 2165 */ 2166 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, 2167 PCI_BASE_ADDRESS_SPACE_MEMORY | 2168 PCI_BASE_ADDRESS_MEM_TYPE_64 | 2169 PCI_BASE_ADDRESS_MEM_PREFETCH, 2170 &qxl->vram_bar); 2171 } 2172 2173 /* print pci bar details */ 2174 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n", 2175 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB); 2176 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n", 2177 qxl->vram32_size / MiB); 2178 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n", 2179 qxl->vram_size / MiB, 2180 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); 2181 2182 qxl->ssd.qxl.base.sif = &qxl_interface.base; 2183 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) { 2184 error_setg(errp, "qxl interface %d.%d not supported by spice-server", 2185 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR); 2186 return; 2187 } 2188 2189 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */ 2190 char device_address[256] = ""; 2191 if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) { 2192 spice_qxl_set_device_info(&qxl->ssd.qxl, 2193 device_address, 2194 0, 2195 qxl->max_outputs); 2196 } 2197 #endif 2198 2199 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); 2200 2201 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); 2202 qxl_reset_state(qxl); 2203 2204 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); 2205 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd); 2206 } 2207 2208 static void qxl_realize_primary(PCIDevice *dev, Error **errp) 2209 { 2210 PCIQXLDevice *qxl = PCI_QXL(dev); 2211 VGACommonState *vga = &qxl->vga; 2212 Error *local_err = NULL; 2213 2214 qxl_init_ramsize(qxl); 2215 vga->vbe_size = qxl->vgamem_size; 2216 vga->vram_size_mb = qxl->vga.vram_size / MiB; 2217 vga_common_init(vga, OBJECT(dev)); 2218 vga_init(vga, OBJECT(dev), 2219 pci_address_space(dev), pci_address_space_io(dev), false); 2220 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list, 2221 vga, "vga"); 2222 portio_list_set_flush_coalesced(&qxl->vga_port_list); 2223 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0); 2224 qxl->have_vga = true; 2225 2226 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2227 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */ 2228 if (qxl->id != 0) { 2229 error_setg(errp, "primary qxl-vga device must be console 0 " 2230 "(first display device on the command line)"); 2231 return; 2232 } 2233 2234 qxl_realize_common(qxl, &local_err); 2235 if (local_err) { 2236 error_propagate(errp, local_err); 2237 return; 2238 } 2239 2240 qxl->ssd.dcl.ops = &display_listener_ops; 2241 qxl->ssd.dcl.con = vga->con; 2242 register_displaychangelistener(&qxl->ssd.dcl); 2243 } 2244 2245 static void qxl_realize_secondary(PCIDevice *dev, Error **errp) 2246 { 2247 PCIQXLDevice *qxl = PCI_QXL(dev); 2248 2249 qxl_init_ramsize(qxl); 2250 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", 2251 qxl->vga.vram_size, &error_fatal); 2252 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); 2253 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); 2254 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */ 2255 2256 qxl_realize_common(qxl, errp); 2257 } 2258 2259 static int qxl_pre_save(void *opaque) 2260 { 2261 PCIQXLDevice* d = opaque; 2262 uint8_t *ram_start = d->vga.vram_ptr; 2263 2264 trace_qxl_pre_save(d->id); 2265 if (d->last_release == NULL) { 2266 d->last_release_offset = 0; 2267 } else { 2268 d->last_release_offset = (uint8_t *)d->last_release - ram_start; 2269 } 2270 assert(d->last_release_offset < d->vga.vram_size); 2271 2272 return 0; 2273 } 2274 2275 static int qxl_pre_load(void *opaque) 2276 { 2277 PCIQXLDevice* d = opaque; 2278 2279 trace_qxl_pre_load(d->id); 2280 qxl_hard_reset(d, 1); 2281 qxl_exit_vga_mode(d); 2282 return 0; 2283 } 2284 2285 static void qxl_create_memslots(PCIQXLDevice *d) 2286 { 2287 int i; 2288 2289 for (i = 0; i < NUM_MEMSLOTS; i++) { 2290 if (!d->guest_slots[i].active) { 2291 continue; 2292 } 2293 qxl_add_memslot(d, i, 0, QXL_SYNC); 2294 } 2295 } 2296 2297 static int qxl_post_load(void *opaque, int version) 2298 { 2299 PCIQXLDevice* d = opaque; 2300 uint8_t *ram_start = d->vga.vram_ptr; 2301 QXLCommandExt *cmds; 2302 int in, out, newmode; 2303 2304 assert(d->last_release_offset < d->vga.vram_size); 2305 if (d->last_release_offset == 0) { 2306 d->last_release = NULL; 2307 } else { 2308 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); 2309 } 2310 2311 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); 2312 2313 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); 2314 newmode = d->mode; 2315 d->mode = QXL_MODE_UNDEFINED; 2316 2317 switch (newmode) { 2318 case QXL_MODE_UNDEFINED: 2319 qxl_create_memslots(d); 2320 break; 2321 case QXL_MODE_VGA: 2322 qxl_create_memslots(d); 2323 qxl_enter_vga_mode(d); 2324 break; 2325 case QXL_MODE_NATIVE: 2326 qxl_create_memslots(d); 2327 qxl_create_guest_primary(d, 1, QXL_SYNC); 2328 2329 /* replay surface-create and cursor-set commands */ 2330 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1); 2331 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) { 2332 if (d->guest_surfaces.cmds[in] == 0) { 2333 continue; 2334 } 2335 cmds[out].cmd.data = d->guest_surfaces.cmds[in]; 2336 cmds[out].cmd.type = QXL_CMD_SURFACE; 2337 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2338 out++; 2339 } 2340 if (d->guest_cursor) { 2341 cmds[out].cmd.data = d->guest_cursor; 2342 cmds[out].cmd.type = QXL_CMD_CURSOR; 2343 cmds[out].group_id = MEMSLOT_GROUP_GUEST; 2344 out++; 2345 } 2346 qxl_spice_loadvm_commands(d, cmds, out); 2347 g_free(cmds); 2348 if (d->guest_monitors_config) { 2349 qxl_spice_monitors_config_async(d, 1); 2350 } 2351 break; 2352 case QXL_MODE_COMPAT: 2353 /* note: no need to call qxl_create_memslots, qxl_set_mode 2354 * creates the mem slot. */ 2355 qxl_set_mode(d, d->shadow_rom.mode, 1); 2356 break; 2357 } 2358 return 0; 2359 } 2360 2361 #define QXL_SAVE_VERSION 21 2362 2363 static bool qxl_monitors_config_needed(void *opaque) 2364 { 2365 PCIQXLDevice *qxl = opaque; 2366 2367 return qxl->guest_monitors_config != 0; 2368 } 2369 2370 2371 static VMStateDescription qxl_memslot = { 2372 .name = "qxl-memslot", 2373 .version_id = QXL_SAVE_VERSION, 2374 .minimum_version_id = QXL_SAVE_VERSION, 2375 .fields = (VMStateField[]) { 2376 VMSTATE_UINT64(slot.mem_start, struct guest_slots), 2377 VMSTATE_UINT64(slot.mem_end, struct guest_slots), 2378 VMSTATE_UINT32(active, struct guest_slots), 2379 VMSTATE_END_OF_LIST() 2380 } 2381 }; 2382 2383 static VMStateDescription qxl_surface = { 2384 .name = "qxl-surface", 2385 .version_id = QXL_SAVE_VERSION, 2386 .minimum_version_id = QXL_SAVE_VERSION, 2387 .fields = (VMStateField[]) { 2388 VMSTATE_UINT32(width, QXLSurfaceCreate), 2389 VMSTATE_UINT32(height, QXLSurfaceCreate), 2390 VMSTATE_INT32(stride, QXLSurfaceCreate), 2391 VMSTATE_UINT32(format, QXLSurfaceCreate), 2392 VMSTATE_UINT32(position, QXLSurfaceCreate), 2393 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), 2394 VMSTATE_UINT32(flags, QXLSurfaceCreate), 2395 VMSTATE_UINT32(type, QXLSurfaceCreate), 2396 VMSTATE_UINT64(mem, QXLSurfaceCreate), 2397 VMSTATE_END_OF_LIST() 2398 } 2399 }; 2400 2401 static VMStateDescription qxl_vmstate_monitors_config = { 2402 .name = "qxl/monitors-config", 2403 .version_id = 1, 2404 .minimum_version_id = 1, 2405 .needed = qxl_monitors_config_needed, 2406 .fields = (VMStateField[]) { 2407 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice), 2408 VMSTATE_END_OF_LIST() 2409 }, 2410 }; 2411 2412 static VMStateDescription qxl_vmstate = { 2413 .name = "qxl", 2414 .version_id = QXL_SAVE_VERSION, 2415 .minimum_version_id = QXL_SAVE_VERSION, 2416 .pre_save = qxl_pre_save, 2417 .pre_load = qxl_pre_load, 2418 .post_load = qxl_post_load, 2419 .fields = (VMStateField[]) { 2420 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), 2421 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), 2422 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), 2423 VMSTATE_UINT32(num_free_res, PCIQXLDevice), 2424 VMSTATE_UINT32(last_release_offset, PCIQXLDevice), 2425 VMSTATE_UINT32(mode, PCIQXLDevice), 2426 VMSTATE_UINT32(ssd.unique, PCIQXLDevice), 2427 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL), 2428 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, 2429 qxl_memslot, struct guest_slots), 2430 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, 2431 qxl_surface, QXLSurfaceCreate), 2432 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL), 2433 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice, 2434 ssd.num_surfaces, 0, 2435 vmstate_info_uint64, uint64_t), 2436 VMSTATE_UINT64(guest_cursor, PCIQXLDevice), 2437 VMSTATE_END_OF_LIST() 2438 }, 2439 .subsections = (const VMStateDescription*[]) { 2440 &qxl_vmstate_monitors_config, 2441 NULL 2442 } 2443 }; 2444 2445 static Property qxl_properties[] = { 2446 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB), 2447 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB), 2448 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2449 QXL_DEFAULT_REVISION), 2450 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), 2451 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), 2452 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), 2453 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), 2454 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), 2455 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), 2456 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16), 2457 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024), 2458 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */ 2459 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0), 2460 #endif 2461 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0), 2462 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0), 2463 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false), 2464 DEFINE_PROP_END_OF_LIST(), 2465 }; 2466 2467 static void qxl_pci_class_init(ObjectClass *klass, void *data) 2468 { 2469 DeviceClass *dc = DEVICE_CLASS(klass); 2470 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2471 2472 k->vendor_id = REDHAT_PCI_VENDOR_ID; 2473 k->device_id = QXL_DEVICE_ID_STABLE; 2474 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2475 dc->reset = qxl_reset_handler; 2476 dc->vmsd = &qxl_vmstate; 2477 dc->props = qxl_properties; 2478 } 2479 2480 static const TypeInfo qxl_pci_type_info = { 2481 .name = TYPE_PCI_QXL, 2482 .parent = TYPE_PCI_DEVICE, 2483 .instance_size = sizeof(PCIQXLDevice), 2484 .abstract = true, 2485 .class_init = qxl_pci_class_init, 2486 .interfaces = (InterfaceInfo[]) { 2487 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2488 { }, 2489 }, 2490 }; 2491 2492 static void qxl_primary_class_init(ObjectClass *klass, void *data) 2493 { 2494 DeviceClass *dc = DEVICE_CLASS(klass); 2495 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2496 2497 k->realize = qxl_realize_primary; 2498 k->romfile = "vgabios-qxl.bin"; 2499 k->class_id = PCI_CLASS_DISPLAY_VGA; 2500 dc->desc = "Spice QXL GPU (primary, vga compatible)"; 2501 dc->hotpluggable = false; 2502 } 2503 2504 static const TypeInfo qxl_primary_info = { 2505 .name = "qxl-vga", 2506 .parent = TYPE_PCI_QXL, 2507 .class_init = qxl_primary_class_init, 2508 }; 2509 2510 static void qxl_secondary_class_init(ObjectClass *klass, void *data) 2511 { 2512 DeviceClass *dc = DEVICE_CLASS(klass); 2513 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2514 2515 k->realize = qxl_realize_secondary; 2516 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2517 dc->desc = "Spice QXL GPU (secondary)"; 2518 } 2519 2520 static const TypeInfo qxl_secondary_info = { 2521 .name = "qxl", 2522 .parent = TYPE_PCI_QXL, 2523 .class_init = qxl_secondary_class_init, 2524 }; 2525 2526 static void qxl_register_types(void) 2527 { 2528 type_register_static(&qxl_pci_type_info); 2529 type_register_static(&qxl_primary_info); 2530 type_register_static(&qxl_secondary_info); 2531 } 2532 2533 type_init(qxl_register_types) 2534