1 /* 2 * Toshiba TC6393XB I/O Controller. 3 * Found in Sharp Zaurus SL-6000 (tosa) or some 4 * Toshiba e-Series PDAs. 5 * 6 * Most features are currently unsupported!!! 7 * 8 * This code is licensed under the GNU GPL v2. 9 * 10 * Contributions after 2012-01-13 are licensed under the terms of the 11 * GNU GPL, version 2 or (at your option) any later version. 12 */ 13 #include "qemu/osdep.h" 14 #include "hw/hw.h" 15 #include "hw/devices.h" 16 #include "hw/block/flash.h" 17 #include "ui/console.h" 18 #include "ui/pixel_ops.h" 19 #include "sysemu/block-backend.h" 20 #include "sysemu/blockdev.h" 21 22 #define IRQ_TC6393_NAND 0 23 #define IRQ_TC6393_MMC 1 24 #define IRQ_TC6393_OHCI 2 25 #define IRQ_TC6393_SERIAL 3 26 #define IRQ_TC6393_FB 4 27 28 #define TC6393XB_NR_IRQS 8 29 30 #define TC6393XB_GPIOS 16 31 32 #define SCR_REVID 0x08 /* b Revision ID */ 33 #define SCR_ISR 0x50 /* b Interrupt Status */ 34 #define SCR_IMR 0x52 /* b Interrupt Mask */ 35 #define SCR_IRR 0x54 /* b Interrupt Routing */ 36 #define SCR_GPER 0x60 /* w GP Enable */ 37 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ 38 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ 39 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ 40 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ 41 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ 42 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ 43 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ 44 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ 45 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ 46 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ 47 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ 48 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ 49 #define SCR_CCR 0x98 /* w Clock Control */ 50 #define SCR_PLL2CR 0x9a /* w PLL2 Control */ 51 #define SCR_PLL1CR 0x9c /* l PLL1 Control */ 52 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ 53 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ 54 #define SCR_FER 0xe0 /* b Function Enable */ 55 #define SCR_MCR 0xe4 /* w Mode Control */ 56 #define SCR_CONFIG 0xfc /* b Configuration Control */ 57 #define SCR_DEBUG 0xff /* b Debug */ 58 59 #define NAND_CFG_COMMAND 0x04 /* w Command */ 60 #define NAND_CFG_BASE 0x10 /* l Control Base Address */ 61 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ 62 #define NAND_CFG_INTE 0x48 /* b Int Enable */ 63 #define NAND_CFG_EC 0x4a /* b Event Control */ 64 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ 65 #define NAND_CFG_ECCC 0x5b /* b ECC Control */ 66 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ 67 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ 68 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ 69 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ 70 71 #define NAND_DATA 0x00 /* l Data */ 72 #define NAND_MODE 0x04 /* b Mode */ 73 #define NAND_STATUS 0x05 /* b Status */ 74 #define NAND_ISR 0x06 /* b Interrupt Status */ 75 #define NAND_IMR 0x07 /* b Interrupt Mask */ 76 77 #define NAND_MODE_WP 0x80 78 #define NAND_MODE_CE 0x10 79 #define NAND_MODE_ALE 0x02 80 #define NAND_MODE_CLE 0x01 81 #define NAND_MODE_ECC_MASK 0x60 82 #define NAND_MODE_ECC_EN 0x20 83 #define NAND_MODE_ECC_READ 0x40 84 #define NAND_MODE_ECC_RST 0x60 85 86 struct TC6393xbState { 87 MemoryRegion iomem; 88 qemu_irq irq; 89 qemu_irq *sub_irqs; 90 struct { 91 uint8_t ISR; 92 uint8_t IMR; 93 uint8_t IRR; 94 uint16_t GPER; 95 uint8_t GPI_SR[3]; 96 uint8_t GPI_IMR[3]; 97 uint8_t GPI_EDER[3]; 98 uint8_t GPI_LIR[3]; 99 uint8_t GP_IARCR[3]; 100 uint8_t GP_IARLCR[3]; 101 uint8_t GPI_BCR[3]; 102 uint16_t GPA_IARCR; 103 uint16_t GPA_IARLCR; 104 uint16_t CCR; 105 uint16_t PLL2CR; 106 uint32_t PLL1CR; 107 uint8_t DIARCR; 108 uint8_t DBOCR; 109 uint8_t FER; 110 uint16_t MCR; 111 uint8_t CONFIG; 112 uint8_t DEBUG; 113 } scr; 114 uint32_t gpio_dir; 115 uint32_t gpio_level; 116 uint32_t prev_level; 117 qemu_irq handler[TC6393XB_GPIOS]; 118 qemu_irq *gpio_in; 119 120 struct { 121 uint8_t mode; 122 uint8_t isr; 123 uint8_t imr; 124 } nand; 125 int nand_enable; 126 uint32_t nand_phys; 127 DeviceState *flash; 128 ECCState ecc; 129 130 QemuConsole *con; 131 MemoryRegion vram; 132 uint16_t *vram_ptr; 133 uint32_t scr_width, scr_height; /* in pixels */ 134 qemu_irq l3v; 135 unsigned blank : 1, 136 blanked : 1; 137 }; 138 139 qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) 140 { 141 return s->gpio_in; 142 } 143 144 static void tc6393xb_gpio_set(void *opaque, int line, int level) 145 { 146 // TC6393xbState *s = opaque; 147 148 if (line > TC6393XB_GPIOS) { 149 printf("%s: No GPIO pin %i\n", __FUNCTION__, line); 150 return; 151 } 152 153 // FIXME: how does the chip reflect the GPIO input level change? 154 } 155 156 void tc6393xb_gpio_out_set(TC6393xbState *s, int line, 157 qemu_irq handler) 158 { 159 if (line >= TC6393XB_GPIOS) { 160 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line); 161 return; 162 } 163 164 s->handler[line] = handler; 165 } 166 167 static void tc6393xb_gpio_handler_update(TC6393xbState *s) 168 { 169 uint32_t level, diff; 170 int bit; 171 172 level = s->gpio_level & s->gpio_dir; 173 174 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 175 bit = ctz32(diff); 176 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 177 } 178 179 s->prev_level = level; 180 } 181 182 qemu_irq tc6393xb_l3v_get(TC6393xbState *s) 183 { 184 return s->l3v; 185 } 186 187 static void tc6393xb_l3v(void *opaque, int line, int level) 188 { 189 TC6393xbState *s = opaque; 190 s->blank = !level; 191 fprintf(stderr, "L3V: %d\n", level); 192 } 193 194 static void tc6393xb_sub_irq(void *opaque, int line, int level) { 195 TC6393xbState *s = opaque; 196 uint8_t isr = s->scr.ISR; 197 if (level) 198 isr |= 1 << line; 199 else 200 isr &= ~(1 << line); 201 s->scr.ISR = isr; 202 qemu_set_irq(s->irq, isr & s->scr.IMR); 203 } 204 205 #define SCR_REG_B(N) \ 206 case SCR_ ##N: return s->scr.N 207 #define SCR_REG_W(N) \ 208 case SCR_ ##N: return s->scr.N; \ 209 case SCR_ ##N + 1: return s->scr.N >> 8; 210 #define SCR_REG_L(N) \ 211 case SCR_ ##N: return s->scr.N; \ 212 case SCR_ ##N + 1: return s->scr.N >> 8; \ 213 case SCR_ ##N + 2: return s->scr.N >> 16; \ 214 case SCR_ ##N + 3: return s->scr.N >> 24; 215 #define SCR_REG_A(N) \ 216 case SCR_ ##N(0): return s->scr.N[0]; \ 217 case SCR_ ##N(1): return s->scr.N[1]; \ 218 case SCR_ ##N(2): return s->scr.N[2] 219 220 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr) 221 { 222 switch (addr) { 223 case SCR_REVID: 224 return 3; 225 case SCR_REVID+1: 226 return 0; 227 SCR_REG_B(ISR); 228 SCR_REG_B(IMR); 229 SCR_REG_B(IRR); 230 SCR_REG_W(GPER); 231 SCR_REG_A(GPI_SR); 232 SCR_REG_A(GPI_IMR); 233 SCR_REG_A(GPI_EDER); 234 SCR_REG_A(GPI_LIR); 235 case SCR_GPO_DSR(0): 236 case SCR_GPO_DSR(1): 237 case SCR_GPO_DSR(2): 238 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; 239 case SCR_GPO_DOECR(0): 240 case SCR_GPO_DOECR(1): 241 case SCR_GPO_DOECR(2): 242 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; 243 SCR_REG_A(GP_IARCR); 244 SCR_REG_A(GP_IARLCR); 245 SCR_REG_A(GPI_BCR); 246 SCR_REG_W(GPA_IARCR); 247 SCR_REG_W(GPA_IARLCR); 248 SCR_REG_W(CCR); 249 SCR_REG_W(PLL2CR); 250 SCR_REG_L(PLL1CR); 251 SCR_REG_B(DIARCR); 252 SCR_REG_B(DBOCR); 253 SCR_REG_B(FER); 254 SCR_REG_W(MCR); 255 SCR_REG_B(CONFIG); 256 SCR_REG_B(DEBUG); 257 } 258 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr); 259 return 0; 260 } 261 #undef SCR_REG_B 262 #undef SCR_REG_W 263 #undef SCR_REG_L 264 #undef SCR_REG_A 265 266 #define SCR_REG_B(N) \ 267 case SCR_ ##N: s->scr.N = value; return; 268 #define SCR_REG_W(N) \ 269 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 270 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return 271 #define SCR_REG_L(N) \ 272 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ 273 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ 274 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ 275 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; 276 #define SCR_REG_A(N) \ 277 case SCR_ ##N(0): s->scr.N[0] = value; return; \ 278 case SCR_ ##N(1): s->scr.N[1] = value; return; \ 279 case SCR_ ##N(2): s->scr.N[2] = value; return 280 281 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) 282 { 283 switch (addr) { 284 SCR_REG_B(ISR); 285 SCR_REG_B(IMR); 286 SCR_REG_B(IRR); 287 SCR_REG_W(GPER); 288 SCR_REG_A(GPI_SR); 289 SCR_REG_A(GPI_IMR); 290 SCR_REG_A(GPI_EDER); 291 SCR_REG_A(GPI_LIR); 292 case SCR_GPO_DSR(0): 293 case SCR_GPO_DSR(1): 294 case SCR_GPO_DSR(2): 295 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); 296 tc6393xb_gpio_handler_update(s); 297 return; 298 case SCR_GPO_DOECR(0): 299 case SCR_GPO_DOECR(1): 300 case SCR_GPO_DOECR(2): 301 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); 302 tc6393xb_gpio_handler_update(s); 303 return; 304 SCR_REG_A(GP_IARCR); 305 SCR_REG_A(GP_IARLCR); 306 SCR_REG_A(GPI_BCR); 307 SCR_REG_W(GPA_IARCR); 308 SCR_REG_W(GPA_IARLCR); 309 SCR_REG_W(CCR); 310 SCR_REG_W(PLL2CR); 311 SCR_REG_L(PLL1CR); 312 SCR_REG_B(DIARCR); 313 SCR_REG_B(DBOCR); 314 SCR_REG_B(FER); 315 SCR_REG_W(MCR); 316 SCR_REG_B(CONFIG); 317 SCR_REG_B(DEBUG); 318 } 319 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n", 320 (uint32_t) addr, value & 0xff); 321 } 322 #undef SCR_REG_B 323 #undef SCR_REG_W 324 #undef SCR_REG_L 325 #undef SCR_REG_A 326 327 static void tc6393xb_nand_irq(TC6393xbState *s) { 328 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], 329 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); 330 } 331 332 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) { 333 switch (addr) { 334 case NAND_CFG_COMMAND: 335 return s->nand_enable ? 2 : 0; 336 case NAND_CFG_BASE: 337 case NAND_CFG_BASE + 1: 338 case NAND_CFG_BASE + 2: 339 case NAND_CFG_BASE + 3: 340 return s->nand_phys >> (addr - NAND_CFG_BASE); 341 } 342 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); 343 return 0; 344 } 345 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 346 switch (addr) { 347 case NAND_CFG_COMMAND: 348 s->nand_enable = (value & 0x2); 349 return; 350 case NAND_CFG_BASE: 351 case NAND_CFG_BASE + 1: 352 case NAND_CFG_BASE + 2: 353 case NAND_CFG_BASE + 3: 354 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); 355 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); 356 return; 357 } 358 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n", 359 (uint32_t) addr, value & 0xff); 360 } 361 362 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) { 363 switch (addr) { 364 case NAND_DATA + 0: 365 case NAND_DATA + 1: 366 case NAND_DATA + 2: 367 case NAND_DATA + 3: 368 return nand_getio(s->flash); 369 case NAND_MODE: 370 return s->nand.mode; 371 case NAND_STATUS: 372 return 0x14; 373 case NAND_ISR: 374 return s->nand.isr; 375 case NAND_IMR: 376 return s->nand.imr; 377 } 378 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); 379 return 0; 380 } 381 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) { 382 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", 383 // (uint32_t) addr, value & 0xff); 384 switch (addr) { 385 case NAND_DATA + 0: 386 case NAND_DATA + 1: 387 case NAND_DATA + 2: 388 case NAND_DATA + 3: 389 nand_setio(s->flash, value); 390 s->nand.isr |= 1; 391 tc6393xb_nand_irq(s); 392 return; 393 case NAND_MODE: 394 s->nand.mode = value; 395 nand_setpins(s->flash, 396 value & NAND_MODE_CLE, 397 value & NAND_MODE_ALE, 398 !(value & NAND_MODE_CE), 399 value & NAND_MODE_WP, 400 0); // FIXME: gnd 401 switch (value & NAND_MODE_ECC_MASK) { 402 case NAND_MODE_ECC_RST: 403 ecc_reset(&s->ecc); 404 break; 405 case NAND_MODE_ECC_READ: 406 // FIXME 407 break; 408 case NAND_MODE_ECC_EN: 409 ecc_reset(&s->ecc); 410 } 411 return; 412 case NAND_ISR: 413 s->nand.isr = value; 414 tc6393xb_nand_irq(s); 415 return; 416 case NAND_IMR: 417 s->nand.imr = value; 418 tc6393xb_nand_irq(s); 419 return; 420 } 421 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n", 422 (uint32_t) addr, value & 0xff); 423 } 424 425 #define BITS 8 426 #include "tc6393xb_template.h" 427 #define BITS 15 428 #include "tc6393xb_template.h" 429 #define BITS 16 430 #include "tc6393xb_template.h" 431 #define BITS 24 432 #include "tc6393xb_template.h" 433 #define BITS 32 434 #include "tc6393xb_template.h" 435 436 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) 437 { 438 DisplaySurface *surface = qemu_console_surface(s->con); 439 440 switch (surface_bits_per_pixel(surface)) { 441 case 8: 442 tc6393xb_draw_graphic8(s); 443 break; 444 case 15: 445 tc6393xb_draw_graphic15(s); 446 break; 447 case 16: 448 tc6393xb_draw_graphic16(s); 449 break; 450 case 24: 451 tc6393xb_draw_graphic24(s); 452 break; 453 case 32: 454 tc6393xb_draw_graphic32(s); 455 break; 456 default: 457 printf("tc6393xb: unknown depth %d\n", 458 surface_bits_per_pixel(surface)); 459 return; 460 } 461 462 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 463 } 464 465 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) 466 { 467 DisplaySurface *surface = qemu_console_surface(s->con); 468 int i, w; 469 uint8_t *d; 470 471 if (!full_update) 472 return; 473 474 w = s->scr_width * surface_bytes_per_pixel(surface); 475 d = surface_data(surface); 476 for(i = 0; i < s->scr_height; i++) { 477 memset(d, 0, w); 478 d += surface_stride(surface); 479 } 480 481 dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height); 482 } 483 484 static void tc6393xb_update_display(void *opaque) 485 { 486 TC6393xbState *s = opaque; 487 DisplaySurface *surface = qemu_console_surface(s->con); 488 int full_update; 489 490 if (s->scr_width == 0 || s->scr_height == 0) 491 return; 492 493 full_update = 0; 494 if (s->blanked != s->blank) { 495 s->blanked = s->blank; 496 full_update = 1; 497 } 498 if (s->scr_width != surface_width(surface) || 499 s->scr_height != surface_height(surface)) { 500 qemu_console_resize(s->con, s->scr_width, s->scr_height); 501 full_update = 1; 502 } 503 if (s->blanked) 504 tc6393xb_draw_blank(s, full_update); 505 else 506 tc6393xb_draw_graphic(s, full_update); 507 } 508 509 510 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr, 511 unsigned size) 512 { 513 TC6393xbState *s = opaque; 514 515 switch (addr >> 8) { 516 case 0: 517 return tc6393xb_scr_readb(s, addr & 0xff); 518 case 1: 519 return tc6393xb_nand_cfg_readb(s, addr & 0xff); 520 }; 521 522 if ((addr &~0xff) == s->nand_phys && s->nand_enable) { 523 // return tc6393xb_nand_readb(s, addr & 0xff); 524 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff); 525 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d); 526 return d; 527 } 528 529 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr); 530 return 0; 531 } 532 533 static void tc6393xb_writeb(void *opaque, hwaddr addr, 534 uint64_t value, unsigned size) { 535 TC6393xbState *s = opaque; 536 537 switch (addr >> 8) { 538 case 0: 539 tc6393xb_scr_writeb(s, addr & 0xff, value); 540 return; 541 case 1: 542 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value); 543 return; 544 }; 545 546 if ((addr &~0xff) == s->nand_phys && s->nand_enable) 547 tc6393xb_nand_writeb(s, addr & 0xff, value); 548 else 549 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", 550 (uint32_t) addr, (int)value & 0xff); 551 } 552 553 static const GraphicHwOps tc6393xb_gfx_ops = { 554 .gfx_update = tc6393xb_update_display, 555 }; 556 557 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) 558 { 559 TC6393xbState *s; 560 DriveInfo *nand; 561 static const MemoryRegionOps tc6393xb_ops = { 562 .read = tc6393xb_readb, 563 .write = tc6393xb_writeb, 564 .endianness = DEVICE_NATIVE_ENDIAN, 565 .impl = { 566 .min_access_size = 1, 567 .max_access_size = 1, 568 }, 569 }; 570 571 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState)); 572 s->irq = irq; 573 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); 574 575 s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0); 576 s->blanked = 1; 577 578 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); 579 580 nand = drive_get(IF_MTD, 0, 0); 581 s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL, 582 NAND_MFR_TOSHIBA, 0x76); 583 584 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000); 585 memory_region_add_subregion(sysmem, base, &s->iomem); 586 587 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000, 588 &error_fatal); 589 vmstate_register_ram_global(&s->vram); 590 s->vram_ptr = memory_region_get_ram_ptr(&s->vram); 591 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); 592 s->scr_width = 480; 593 s->scr_height = 640; 594 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s); 595 596 return s; 597 } 598