1 /* 2 * QEMU TCX Frame buffer 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu-common.h" 26 #include "ui/console.h" 27 #include "ui/pixel_ops.h" 28 #include "hw/loader.h" 29 #include "hw/sysbus.h" 30 31 #define TCX_ROM_FILE "QEMU,tcx.bin" 32 #define FCODE_MAX_ROM_SIZE 0x10000 33 34 #define MAXX 1024 35 #define MAXY 768 36 #define TCX_DAC_NREGS 16 37 #define TCX_THC_NREGS 0x1000 38 #define TCX_DHC_NREGS 0x4000 39 #define TCX_TEC_NREGS 0x1000 40 #define TCX_ALT_NREGS 0x8000 41 #define TCX_STIP_NREGS 0x800000 42 #define TCX_BLIT_NREGS 0x800000 43 #define TCX_RSTIP_NREGS 0x800000 44 #define TCX_RBLIT_NREGS 0x800000 45 46 #define TCX_THC_MISC 0x818 47 #define TCX_THC_CURSXY 0x8fc 48 #define TCX_THC_CURSMASK 0x900 49 #define TCX_THC_CURSBITS 0x980 50 51 #define TYPE_TCX "SUNW,tcx" 52 #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX) 53 54 typedef struct TCXState { 55 SysBusDevice parent_obj; 56 57 QemuConsole *con; 58 qemu_irq irq; 59 uint8_t *vram; 60 uint32_t *vram24, *cplane; 61 hwaddr prom_addr; 62 MemoryRegion rom; 63 MemoryRegion vram_mem; 64 MemoryRegion vram_8bit; 65 MemoryRegion vram_24bit; 66 MemoryRegion stip; 67 MemoryRegion blit; 68 MemoryRegion vram_cplane; 69 MemoryRegion rstip; 70 MemoryRegion rblit; 71 MemoryRegion tec; 72 MemoryRegion dac; 73 MemoryRegion thc; 74 MemoryRegion dhc; 75 MemoryRegion alt; 76 MemoryRegion thc24; 77 78 ram_addr_t vram24_offset, cplane_offset; 79 uint32_t tmpblit; 80 uint32_t vram_size; 81 uint32_t palette[260]; 82 uint8_t r[260], g[260], b[260]; 83 uint16_t width, height, depth; 84 uint8_t dac_index, dac_state; 85 uint32_t thcmisc; 86 uint32_t cursmask[32]; 87 uint32_t cursbits[32]; 88 uint16_t cursx; 89 uint16_t cursy; 90 } TCXState; 91 92 static void tcx_set_dirty(TCXState *s) 93 { 94 memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY); 95 } 96 97 static inline int tcx24_check_dirty(TCXState *s, ram_addr_t page, 98 ram_addr_t page24, ram_addr_t cpage) 99 { 100 int ret; 101 102 ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE, 103 DIRTY_MEMORY_VGA); 104 ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4, 105 DIRTY_MEMORY_VGA); 106 ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4, 107 DIRTY_MEMORY_VGA); 108 return ret; 109 } 110 111 static inline void tcx24_reset_dirty(TCXState *ts, ram_addr_t page_min, 112 ram_addr_t page_max, ram_addr_t page24, 113 ram_addr_t cpage) 114 { 115 memory_region_reset_dirty(&ts->vram_mem, 116 page_min, 117 (page_max - page_min) + TARGET_PAGE_SIZE, 118 DIRTY_MEMORY_VGA); 119 memory_region_reset_dirty(&ts->vram_mem, 120 page24 + page_min * 4, 121 (page_max - page_min) * 4 + TARGET_PAGE_SIZE, 122 DIRTY_MEMORY_VGA); 123 memory_region_reset_dirty(&ts->vram_mem, 124 cpage + page_min * 4, 125 (page_max - page_min) * 4 + TARGET_PAGE_SIZE, 126 DIRTY_MEMORY_VGA); 127 } 128 129 static void update_palette_entries(TCXState *s, int start, int end) 130 { 131 DisplaySurface *surface = qemu_console_surface(s->con); 132 int i; 133 134 for (i = start; i < end; i++) { 135 switch (surface_bits_per_pixel(surface)) { 136 default: 137 case 8: 138 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); 139 break; 140 case 15: 141 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); 142 break; 143 case 16: 144 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); 145 break; 146 case 32: 147 if (is_surface_bgr(surface)) { 148 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); 149 } else { 150 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); 151 } 152 break; 153 } 154 } 155 tcx_set_dirty(s); 156 } 157 158 static void tcx_draw_line32(TCXState *s1, uint8_t *d, 159 const uint8_t *s, int width) 160 { 161 int x; 162 uint8_t val; 163 uint32_t *p = (uint32_t *)d; 164 165 for (x = 0; x < width; x++) { 166 val = *s++; 167 *p++ = s1->palette[val]; 168 } 169 } 170 171 static void tcx_draw_line16(TCXState *s1, uint8_t *d, 172 const uint8_t *s, int width) 173 { 174 int x; 175 uint8_t val; 176 uint16_t *p = (uint16_t *)d; 177 178 for (x = 0; x < width; x++) { 179 val = *s++; 180 *p++ = s1->palette[val]; 181 } 182 } 183 184 static void tcx_draw_line8(TCXState *s1, uint8_t *d, 185 const uint8_t *s, int width) 186 { 187 int x; 188 uint8_t val; 189 190 for(x = 0; x < width; x++) { 191 val = *s++; 192 *d++ = s1->palette[val]; 193 } 194 } 195 196 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, 197 int y, int width) 198 { 199 int x, len; 200 uint32_t mask, bits; 201 uint32_t *p = (uint32_t *)d; 202 203 y = y - s1->cursy; 204 mask = s1->cursmask[y]; 205 bits = s1->cursbits[y]; 206 len = MIN(width - s1->cursx, 32); 207 p = &p[s1->cursx]; 208 for (x = 0; x < len; x++) { 209 if (mask & 0x80000000) { 210 if (bits & 0x80000000) { 211 *p = s1->palette[259]; 212 } else { 213 *p = s1->palette[258]; 214 } 215 } 216 p++; 217 mask <<= 1; 218 bits <<= 1; 219 } 220 } 221 222 static void tcx_draw_cursor16(TCXState *s1, uint8_t *d, 223 int y, int width) 224 { 225 int x, len; 226 uint32_t mask, bits; 227 uint16_t *p = (uint16_t *)d; 228 229 y = y - s1->cursy; 230 mask = s1->cursmask[y]; 231 bits = s1->cursbits[y]; 232 len = MIN(width - s1->cursx, 32); 233 p = &p[s1->cursx]; 234 for (x = 0; x < len; x++) { 235 if (mask & 0x80000000) { 236 if (bits & 0x80000000) { 237 *p = s1->palette[259]; 238 } else { 239 *p = s1->palette[258]; 240 } 241 } 242 p++; 243 mask <<= 1; 244 bits <<= 1; 245 } 246 } 247 248 static void tcx_draw_cursor8(TCXState *s1, uint8_t *d, 249 int y, int width) 250 { 251 int x, len; 252 uint32_t mask, bits; 253 254 y = y - s1->cursy; 255 mask = s1->cursmask[y]; 256 bits = s1->cursbits[y]; 257 len = MIN(width - s1->cursx, 32); 258 d = &d[s1->cursx]; 259 for (x = 0; x < len; x++) { 260 if (mask & 0x80000000) { 261 if (bits & 0x80000000) { 262 *d = s1->palette[259]; 263 } else { 264 *d = s1->palette[258]; 265 } 266 } 267 d++; 268 mask <<= 1; 269 bits <<= 1; 270 } 271 } 272 273 /* 274 XXX Could be much more optimal: 275 * detect if line/page/whole screen is in 24 bit mode 276 * if destination is also BGR, use memcpy 277 */ 278 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, 279 const uint8_t *s, int width, 280 const uint32_t *cplane, 281 const uint32_t *s24) 282 { 283 DisplaySurface *surface = qemu_console_surface(s1->con); 284 int x, bgr, r, g, b; 285 uint8_t val, *p8; 286 uint32_t *p = (uint32_t *)d; 287 uint32_t dval; 288 bgr = is_surface_bgr(surface); 289 for(x = 0; x < width; x++, s++, s24++) { 290 if (be32_to_cpu(*cplane) & 0x03000000) { 291 /* 24-bit direct, BGR order */ 292 p8 = (uint8_t *)s24; 293 p8++; 294 b = *p8++; 295 g = *p8++; 296 r = *p8; 297 if (bgr) 298 dval = rgb_to_pixel32bgr(r, g, b); 299 else 300 dval = rgb_to_pixel32(r, g, b); 301 } else { 302 /* 8-bit pseudocolor */ 303 val = *s; 304 dval = s1->palette[val]; 305 } 306 *p++ = dval; 307 cplane++; 308 } 309 } 310 311 /* Fixed line length 1024 allows us to do nice tricks not possible on 312 VGA... */ 313 314 static void tcx_update_display(void *opaque) 315 { 316 TCXState *ts = opaque; 317 DisplaySurface *surface = qemu_console_surface(ts->con); 318 ram_addr_t page, page_min, page_max; 319 int y, y_start, dd, ds; 320 uint8_t *d, *s; 321 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); 322 void (*fc)(TCXState *s1, uint8_t *dst, int y, int width); 323 324 if (surface_bits_per_pixel(surface) == 0) { 325 return; 326 } 327 328 page = 0; 329 y_start = -1; 330 page_min = -1; 331 page_max = 0; 332 d = surface_data(surface); 333 s = ts->vram; 334 dd = surface_stride(surface); 335 ds = 1024; 336 337 switch (surface_bits_per_pixel(surface)) { 338 case 32: 339 f = tcx_draw_line32; 340 fc = tcx_draw_cursor32; 341 break; 342 case 15: 343 case 16: 344 f = tcx_draw_line16; 345 fc = tcx_draw_cursor16; 346 break; 347 default: 348 case 8: 349 f = tcx_draw_line8; 350 fc = tcx_draw_cursor8; 351 break; 352 case 0: 353 return; 354 } 355 356 memory_region_sync_dirty_bitmap(&ts->vram_mem); 357 for (y = 0; y < ts->height; page += TARGET_PAGE_SIZE) { 358 if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE, 359 DIRTY_MEMORY_VGA)) { 360 if (y_start < 0) 361 y_start = y; 362 if (page < page_min) 363 page_min = page; 364 if (page > page_max) 365 page_max = page; 366 367 f(ts, d, s, ts->width); 368 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 369 fc(ts, d, y, ts->width); 370 } 371 d += dd; 372 s += ds; 373 y++; 374 375 f(ts, d, s, ts->width); 376 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 377 fc(ts, d, y, ts->width); 378 } 379 d += dd; 380 s += ds; 381 y++; 382 383 f(ts, d, s, ts->width); 384 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 385 fc(ts, d, y, ts->width); 386 } 387 d += dd; 388 s += ds; 389 y++; 390 391 f(ts, d, s, ts->width); 392 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 393 fc(ts, d, y, ts->width); 394 } 395 d += dd; 396 s += ds; 397 y++; 398 } else { 399 if (y_start >= 0) { 400 /* flush to display */ 401 dpy_gfx_update(ts->con, 0, y_start, 402 ts->width, y - y_start); 403 y_start = -1; 404 } 405 d += dd * 4; 406 s += ds * 4; 407 y += 4; 408 } 409 } 410 if (y_start >= 0) { 411 /* flush to display */ 412 dpy_gfx_update(ts->con, 0, y_start, 413 ts->width, y - y_start); 414 } 415 /* reset modified pages */ 416 if (page_max >= page_min) { 417 memory_region_reset_dirty(&ts->vram_mem, 418 page_min, 419 (page_max - page_min) + TARGET_PAGE_SIZE, 420 DIRTY_MEMORY_VGA); 421 } 422 } 423 424 static void tcx24_update_display(void *opaque) 425 { 426 TCXState *ts = opaque; 427 DisplaySurface *surface = qemu_console_surface(ts->con); 428 ram_addr_t page, page_min, page_max, cpage, page24; 429 int y, y_start, dd, ds; 430 uint8_t *d, *s; 431 uint32_t *cptr, *s24; 432 433 if (surface_bits_per_pixel(surface) != 32) { 434 return; 435 } 436 437 page = 0; 438 page24 = ts->vram24_offset; 439 cpage = ts->cplane_offset; 440 y_start = -1; 441 page_min = -1; 442 page_max = 0; 443 d = surface_data(surface); 444 s = ts->vram; 445 s24 = ts->vram24; 446 cptr = ts->cplane; 447 dd = surface_stride(surface); 448 ds = 1024; 449 450 memory_region_sync_dirty_bitmap(&ts->vram_mem); 451 for (y = 0; y < ts->height; page += TARGET_PAGE_SIZE, 452 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { 453 if (tcx24_check_dirty(ts, page, page24, cpage)) { 454 if (y_start < 0) 455 y_start = y; 456 if (page < page_min) 457 page_min = page; 458 if (page > page_max) 459 page_max = page; 460 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 461 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 462 tcx_draw_cursor32(ts, d, y, ts->width); 463 } 464 d += dd; 465 s += ds; 466 cptr += ds; 467 s24 += ds; 468 y++; 469 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 470 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 471 tcx_draw_cursor32(ts, d, y, ts->width); 472 } 473 d += dd; 474 s += ds; 475 cptr += ds; 476 s24 += ds; 477 y++; 478 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 479 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 480 tcx_draw_cursor32(ts, d, y, ts->width); 481 } 482 d += dd; 483 s += ds; 484 cptr += ds; 485 s24 += ds; 486 y++; 487 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 488 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 489 tcx_draw_cursor32(ts, d, y, ts->width); 490 } 491 d += dd; 492 s += ds; 493 cptr += ds; 494 s24 += ds; 495 y++; 496 } else { 497 if (y_start >= 0) { 498 /* flush to display */ 499 dpy_gfx_update(ts->con, 0, y_start, 500 ts->width, y - y_start); 501 y_start = -1; 502 } 503 d += dd * 4; 504 s += ds * 4; 505 cptr += ds * 4; 506 s24 += ds * 4; 507 y += 4; 508 } 509 } 510 if (y_start >= 0) { 511 /* flush to display */ 512 dpy_gfx_update(ts->con, 0, y_start, 513 ts->width, y - y_start); 514 } 515 /* reset modified pages */ 516 if (page_max >= page_min) { 517 tcx24_reset_dirty(ts, page_min, page_max, page24, cpage); 518 } 519 } 520 521 static void tcx_invalidate_display(void *opaque) 522 { 523 TCXState *s = opaque; 524 525 tcx_set_dirty(s); 526 qemu_console_resize(s->con, s->width, s->height); 527 } 528 529 static void tcx24_invalidate_display(void *opaque) 530 { 531 TCXState *s = opaque; 532 533 tcx_set_dirty(s); 534 qemu_console_resize(s->con, s->width, s->height); 535 } 536 537 static int vmstate_tcx_post_load(void *opaque, int version_id) 538 { 539 TCXState *s = opaque; 540 541 update_palette_entries(s, 0, 256); 542 tcx_set_dirty(s); 543 return 0; 544 } 545 546 static const VMStateDescription vmstate_tcx = { 547 .name ="tcx", 548 .version_id = 4, 549 .minimum_version_id = 4, 550 .post_load = vmstate_tcx_post_load, 551 .fields = (VMStateField[]) { 552 VMSTATE_UINT16(height, TCXState), 553 VMSTATE_UINT16(width, TCXState), 554 VMSTATE_UINT16(depth, TCXState), 555 VMSTATE_BUFFER(r, TCXState), 556 VMSTATE_BUFFER(g, TCXState), 557 VMSTATE_BUFFER(b, TCXState), 558 VMSTATE_UINT8(dac_index, TCXState), 559 VMSTATE_UINT8(dac_state, TCXState), 560 VMSTATE_END_OF_LIST() 561 } 562 }; 563 564 static void tcx_reset(DeviceState *d) 565 { 566 TCXState *s = TCX(d); 567 568 /* Initialize palette */ 569 memset(s->r, 0, 260); 570 memset(s->g, 0, 260); 571 memset(s->b, 0, 260); 572 s->r[255] = s->g[255] = s->b[255] = 255; 573 s->r[256] = s->g[256] = s->b[256] = 255; 574 s->r[258] = s->g[258] = s->b[258] = 255; 575 update_palette_entries(s, 0, 260); 576 memset(s->vram, 0, MAXX*MAXY); 577 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), 578 DIRTY_MEMORY_VGA); 579 s->dac_index = 0; 580 s->dac_state = 0; 581 s->cursx = 0xf000; /* Put cursor off screen */ 582 s->cursy = 0xf000; 583 } 584 585 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, 586 unsigned size) 587 { 588 TCXState *s = opaque; 589 uint32_t val = 0; 590 591 switch (s->dac_state) { 592 case 0: 593 val = s->r[s->dac_index] << 24; 594 s->dac_state++; 595 break; 596 case 1: 597 val = s->g[s->dac_index] << 24; 598 s->dac_state++; 599 break; 600 case 2: 601 val = s->b[s->dac_index] << 24; 602 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 603 default: 604 s->dac_state = 0; 605 break; 606 } 607 608 return val; 609 } 610 611 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, 612 unsigned size) 613 { 614 TCXState *s = opaque; 615 unsigned index; 616 617 switch (addr) { 618 case 0: /* Address */ 619 s->dac_index = val >> 24; 620 s->dac_state = 0; 621 break; 622 case 4: /* Pixel colours */ 623 case 12: /* Overlay (cursor) colours */ 624 if (addr & 8) { 625 index = (s->dac_index & 3) + 256; 626 } else { 627 index = s->dac_index; 628 } 629 switch (s->dac_state) { 630 case 0: 631 s->r[index] = val >> 24; 632 update_palette_entries(s, index, index + 1); 633 s->dac_state++; 634 break; 635 case 1: 636 s->g[index] = val >> 24; 637 update_palette_entries(s, index, index + 1); 638 s->dac_state++; 639 break; 640 case 2: 641 s->b[index] = val >> 24; 642 update_palette_entries(s, index, index + 1); 643 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 644 default: 645 s->dac_state = 0; 646 break; 647 } 648 break; 649 default: /* Control registers */ 650 break; 651 } 652 } 653 654 static const MemoryRegionOps tcx_dac_ops = { 655 .read = tcx_dac_readl, 656 .write = tcx_dac_writel, 657 .endianness = DEVICE_NATIVE_ENDIAN, 658 .valid = { 659 .min_access_size = 4, 660 .max_access_size = 4, 661 }, 662 }; 663 664 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr, 665 unsigned size) 666 { 667 return 0; 668 } 669 670 static void tcx_stip_writel(void *opaque, hwaddr addr, 671 uint64_t val, unsigned size) 672 { 673 TCXState *s = opaque; 674 int i; 675 uint32_t col; 676 677 if (!(addr & 4)) { 678 s->tmpblit = val; 679 } else { 680 addr = (addr >> 3) & 0xfffff; 681 col = cpu_to_be32(s->tmpblit); 682 if (s->depth == 24) { 683 for (i = 0; i < 32; i++) { 684 if (val & 0x80000000) { 685 s->vram[addr + i] = s->tmpblit; 686 s->vram24[addr + i] = col; 687 } 688 val <<= 1; 689 } 690 } else { 691 for (i = 0; i < 32; i++) { 692 if (val & 0x80000000) { 693 s->vram[addr + i] = s->tmpblit; 694 } 695 val <<= 1; 696 } 697 } 698 memory_region_set_dirty(&s->vram_mem, addr, 32); 699 } 700 } 701 702 static void tcx_rstip_writel(void *opaque, hwaddr addr, 703 uint64_t val, unsigned size) 704 { 705 TCXState *s = opaque; 706 int i; 707 uint32_t col; 708 709 if (!(addr & 4)) { 710 s->tmpblit = val; 711 } else { 712 addr = (addr >> 3) & 0xfffff; 713 col = cpu_to_be32(s->tmpblit); 714 if (s->depth == 24) { 715 for (i = 0; i < 32; i++) { 716 if (val & 0x80000000) { 717 s->vram[addr + i] = s->tmpblit; 718 s->vram24[addr + i] = col; 719 s->cplane[addr + i] = col; 720 } 721 val <<= 1; 722 } 723 } else { 724 for (i = 0; i < 32; i++) { 725 if (val & 0x80000000) { 726 s->vram[addr + i] = s->tmpblit; 727 } 728 val <<= 1; 729 } 730 } 731 memory_region_set_dirty(&s->vram_mem, addr, 32); 732 } 733 } 734 735 static const MemoryRegionOps tcx_stip_ops = { 736 .read = tcx_stip_readl, 737 .write = tcx_stip_writel, 738 .endianness = DEVICE_NATIVE_ENDIAN, 739 .valid = { 740 .min_access_size = 4, 741 .max_access_size = 4, 742 }, 743 }; 744 745 static const MemoryRegionOps tcx_rstip_ops = { 746 .read = tcx_stip_readl, 747 .write = tcx_rstip_writel, 748 .endianness = DEVICE_NATIVE_ENDIAN, 749 .valid = { 750 .min_access_size = 4, 751 .max_access_size = 4, 752 }, 753 }; 754 755 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, 756 unsigned size) 757 { 758 return 0; 759 } 760 761 static void tcx_blit_writel(void *opaque, hwaddr addr, 762 uint64_t val, unsigned size) 763 { 764 TCXState *s = opaque; 765 uint32_t adsr, len; 766 int i; 767 768 if (!(addr & 4)) { 769 s->tmpblit = val; 770 } else { 771 addr = (addr >> 3) & 0xfffff; 772 adsr = val & 0xffffff; 773 len = ((val >> 24) & 0x1f) + 1; 774 if (adsr == 0xffffff) { 775 memset(&s->vram[addr], s->tmpblit, len); 776 if (s->depth == 24) { 777 val = s->tmpblit & 0xffffff; 778 val = cpu_to_be32(val); 779 for (i = 0; i < len; i++) { 780 s->vram24[addr + i] = val; 781 } 782 } 783 } else { 784 memcpy(&s->vram[addr], &s->vram[adsr], len); 785 if (s->depth == 24) { 786 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 787 } 788 } 789 memory_region_set_dirty(&s->vram_mem, addr, len); 790 } 791 } 792 793 static void tcx_rblit_writel(void *opaque, hwaddr addr, 794 uint64_t val, unsigned size) 795 { 796 TCXState *s = opaque; 797 uint32_t adsr, len; 798 int i; 799 800 if (!(addr & 4)) { 801 s->tmpblit = val; 802 } else { 803 addr = (addr >> 3) & 0xfffff; 804 adsr = val & 0xffffff; 805 len = ((val >> 24) & 0x1f) + 1; 806 if (adsr == 0xffffff) { 807 memset(&s->vram[addr], s->tmpblit, len); 808 if (s->depth == 24) { 809 val = s->tmpblit & 0xffffff; 810 val = cpu_to_be32(val); 811 for (i = 0; i < len; i++) { 812 s->vram24[addr + i] = val; 813 s->cplane[addr + i] = val; 814 } 815 } 816 } else { 817 memcpy(&s->vram[addr], &s->vram[adsr], len); 818 if (s->depth == 24) { 819 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 820 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4); 821 } 822 } 823 memory_region_set_dirty(&s->vram_mem, addr, len); 824 } 825 } 826 827 static const MemoryRegionOps tcx_blit_ops = { 828 .read = tcx_blit_readl, 829 .write = tcx_blit_writel, 830 .endianness = DEVICE_NATIVE_ENDIAN, 831 .valid = { 832 .min_access_size = 4, 833 .max_access_size = 4, 834 }, 835 }; 836 837 static const MemoryRegionOps tcx_rblit_ops = { 838 .read = tcx_blit_readl, 839 .write = tcx_rblit_writel, 840 .endianness = DEVICE_NATIVE_ENDIAN, 841 .valid = { 842 .min_access_size = 4, 843 .max_access_size = 4, 844 }, 845 }; 846 847 static void tcx_invalidate_cursor_position(TCXState *s) 848 { 849 int ymin, ymax, start, end; 850 851 /* invalidate only near the cursor */ 852 ymin = s->cursy; 853 if (ymin >= s->height) { 854 return; 855 } 856 ymax = MIN(s->height, ymin + 32); 857 start = ymin * 1024; 858 end = ymax * 1024; 859 860 memory_region_set_dirty(&s->vram_mem, start, end-start); 861 } 862 863 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr, 864 unsigned size) 865 { 866 TCXState *s = opaque; 867 uint64_t val; 868 869 if (addr == TCX_THC_MISC) { 870 val = s->thcmisc | 0x02000000; 871 } else { 872 val = 0; 873 } 874 return val; 875 } 876 877 static void tcx_thc_writel(void *opaque, hwaddr addr, 878 uint64_t val, unsigned size) 879 { 880 TCXState *s = opaque; 881 882 if (addr == TCX_THC_CURSXY) { 883 tcx_invalidate_cursor_position(s); 884 s->cursx = val >> 16; 885 s->cursy = val; 886 tcx_invalidate_cursor_position(s); 887 } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) { 888 s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val; 889 tcx_invalidate_cursor_position(s); 890 } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) { 891 s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val; 892 tcx_invalidate_cursor_position(s); 893 } else if (addr == TCX_THC_MISC) { 894 s->thcmisc = val; 895 } 896 897 } 898 899 static const MemoryRegionOps tcx_thc_ops = { 900 .read = tcx_thc_readl, 901 .write = tcx_thc_writel, 902 .endianness = DEVICE_NATIVE_ENDIAN, 903 .valid = { 904 .min_access_size = 4, 905 .max_access_size = 4, 906 }, 907 }; 908 909 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr, 910 unsigned size) 911 { 912 return 0; 913 } 914 915 static void tcx_dummy_writel(void *opaque, hwaddr addr, 916 uint64_t val, unsigned size) 917 { 918 return; 919 } 920 921 static const MemoryRegionOps tcx_dummy_ops = { 922 .read = tcx_dummy_readl, 923 .write = tcx_dummy_writel, 924 .endianness = DEVICE_NATIVE_ENDIAN, 925 .valid = { 926 .min_access_size = 4, 927 .max_access_size = 4, 928 }, 929 }; 930 931 static const GraphicHwOps tcx_ops = { 932 .invalidate = tcx_invalidate_display, 933 .gfx_update = tcx_update_display, 934 }; 935 936 static const GraphicHwOps tcx24_ops = { 937 .invalidate = tcx24_invalidate_display, 938 .gfx_update = tcx24_update_display, 939 }; 940 941 static void tcx_initfn(Object *obj) 942 { 943 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 944 TCXState *s = TCX(obj); 945 946 memory_region_init_ram(&s->rom, NULL, "tcx.prom", FCODE_MAX_ROM_SIZE, 947 &error_abort); 948 memory_region_set_readonly(&s->rom, true); 949 sysbus_init_mmio(sbd, &s->rom); 950 951 /* 2/STIP : Stippler */ 952 memory_region_init_io(&s->stip, OBJECT(s), &tcx_stip_ops, s, "tcx.stip", 953 TCX_STIP_NREGS); 954 sysbus_init_mmio(sbd, &s->stip); 955 956 /* 3/BLIT : Blitter */ 957 memory_region_init_io(&s->blit, OBJECT(s), &tcx_blit_ops, s, "tcx.blit", 958 TCX_BLIT_NREGS); 959 sysbus_init_mmio(sbd, &s->blit); 960 961 /* 5/RSTIP : Raw Stippler */ 962 memory_region_init_io(&s->rstip, OBJECT(s), &tcx_rstip_ops, s, "tcx.rstip", 963 TCX_RSTIP_NREGS); 964 sysbus_init_mmio(sbd, &s->rstip); 965 966 /* 6/RBLIT : Raw Blitter */ 967 memory_region_init_io(&s->rblit, OBJECT(s), &tcx_rblit_ops, s, "tcx.rblit", 968 TCX_RBLIT_NREGS); 969 sysbus_init_mmio(sbd, &s->rblit); 970 971 /* 7/TEC : ??? */ 972 memory_region_init_io(&s->tec, OBJECT(s), &tcx_dummy_ops, s, 973 "tcx.tec", TCX_TEC_NREGS); 974 sysbus_init_mmio(sbd, &s->tec); 975 976 /* 8/CMAP : DAC */ 977 memory_region_init_io(&s->dac, OBJECT(s), &tcx_dac_ops, s, 978 "tcx.dac", TCX_DAC_NREGS); 979 sysbus_init_mmio(sbd, &s->dac); 980 981 /* 9/THC : Cursor */ 982 memory_region_init_io(&s->thc, OBJECT(s), &tcx_thc_ops, s, "tcx.thc", 983 TCX_THC_NREGS); 984 sysbus_init_mmio(sbd, &s->thc); 985 986 /* 11/DHC : ??? */ 987 memory_region_init_io(&s->dhc, OBJECT(s), &tcx_dummy_ops, s, "tcx.dhc", 988 TCX_DHC_NREGS); 989 sysbus_init_mmio(sbd, &s->dhc); 990 991 /* 12/ALT : ??? */ 992 memory_region_init_io(&s->alt, OBJECT(s), &tcx_dummy_ops, s, "tcx.alt", 993 TCX_ALT_NREGS); 994 sysbus_init_mmio(sbd, &s->alt); 995 996 return; 997 } 998 999 static void tcx_realizefn(DeviceState *dev, Error **errp) 1000 { 1001 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1002 TCXState *s = TCX(dev); 1003 ram_addr_t vram_offset = 0; 1004 int size, ret; 1005 uint8_t *vram_base; 1006 char *fcode_filename; 1007 1008 memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram", 1009 s->vram_size * (1 + 4 + 4), &error_abort); 1010 vmstate_register_ram_global(&s->vram_mem); 1011 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 1012 vram_base = memory_region_get_ram_ptr(&s->vram_mem); 1013 1014 /* 10/ROM : FCode ROM */ 1015 vmstate_register_ram_global(&s->rom); 1016 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); 1017 if (fcode_filename) { 1018 ret = load_image_targphys(fcode_filename, s->prom_addr, 1019 FCODE_MAX_ROM_SIZE); 1020 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 1021 error_report("tcx: could not load prom '%s'", TCX_ROM_FILE); 1022 } 1023 } 1024 1025 /* 0/DFB8 : 8-bit plane */ 1026 s->vram = vram_base; 1027 size = s->vram_size; 1028 memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", 1029 &s->vram_mem, vram_offset, size); 1030 sysbus_init_mmio(sbd, &s->vram_8bit); 1031 vram_offset += size; 1032 vram_base += size; 1033 1034 /* 1/DFB24 : 24bit plane */ 1035 size = s->vram_size * 4; 1036 s->vram24 = (uint32_t *)vram_base; 1037 s->vram24_offset = vram_offset; 1038 memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", 1039 &s->vram_mem, vram_offset, size); 1040 sysbus_init_mmio(sbd, &s->vram_24bit); 1041 vram_offset += size; 1042 vram_base += size; 1043 1044 /* 4/RDFB32 : Raw Framebuffer */ 1045 size = s->vram_size * 4; 1046 s->cplane = (uint32_t *)vram_base; 1047 s->cplane_offset = vram_offset; 1048 memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", 1049 &s->vram_mem, vram_offset, size); 1050 sysbus_init_mmio(sbd, &s->vram_cplane); 1051 1052 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 1053 if (s->depth == 8) { 1054 memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s, 1055 "tcx.thc24", TCX_THC_NREGS); 1056 sysbus_init_mmio(sbd, &s->thc24); 1057 } 1058 1059 sysbus_init_irq(sbd, &s->irq); 1060 1061 if (s->depth == 8) { 1062 s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s); 1063 } else { 1064 s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s); 1065 } 1066 s->thcmisc = 0; 1067 1068 qemu_console_resize(s->con, s->width, s->height); 1069 } 1070 1071 static Property tcx_properties[] = { 1072 DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1), 1073 DEFINE_PROP_UINT16("width", TCXState, width, -1), 1074 DEFINE_PROP_UINT16("height", TCXState, height, -1), 1075 DEFINE_PROP_UINT16("depth", TCXState, depth, -1), 1076 DEFINE_PROP_UINT64("prom_addr", TCXState, prom_addr, -1), 1077 DEFINE_PROP_END_OF_LIST(), 1078 }; 1079 1080 static void tcx_class_init(ObjectClass *klass, void *data) 1081 { 1082 DeviceClass *dc = DEVICE_CLASS(klass); 1083 1084 dc->realize = tcx_realizefn; 1085 dc->reset = tcx_reset; 1086 dc->vmsd = &vmstate_tcx; 1087 dc->props = tcx_properties; 1088 } 1089 1090 static const TypeInfo tcx_info = { 1091 .name = TYPE_TCX, 1092 .parent = TYPE_SYS_BUS_DEVICE, 1093 .instance_size = sizeof(TCXState), 1094 .instance_init = tcx_initfn, 1095 .class_init = tcx_class_init, 1096 }; 1097 1098 static void tcx_register_types(void) 1099 { 1100 type_register_static(&tcx_info); 1101 } 1102 1103 type_init(tcx_register_types) 1104