xref: /qemu/hw/display/vga-mmio.c (revision 28cf3960)
13ac25236SPhilippe Mathieu-Daudé /*
23ac25236SPhilippe Mathieu-Daudé  * QEMU MMIO VGA Emulator.
33ac25236SPhilippe Mathieu-Daudé  *
43ac25236SPhilippe Mathieu-Daudé  * Copyright (c) 2003 Fabrice Bellard
53ac25236SPhilippe Mathieu-Daudé  *
63ac25236SPhilippe Mathieu-Daudé  * Permission is hereby granted, free of charge, to any person obtaining a copy
73ac25236SPhilippe Mathieu-Daudé  * of this software and associated documentation files (the "Software"), to deal
83ac25236SPhilippe Mathieu-Daudé  * in the Software without restriction, including without limitation the rights
93ac25236SPhilippe Mathieu-Daudé  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
103ac25236SPhilippe Mathieu-Daudé  * copies of the Software, and to permit persons to whom the Software is
113ac25236SPhilippe Mathieu-Daudé  * furnished to do so, subject to the following conditions:
123ac25236SPhilippe Mathieu-Daudé  *
133ac25236SPhilippe Mathieu-Daudé  * The above copyright notice and this permission notice shall be included in
143ac25236SPhilippe Mathieu-Daudé  * all copies or substantial portions of the Software.
153ac25236SPhilippe Mathieu-Daudé  *
163ac25236SPhilippe Mathieu-Daudé  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
173ac25236SPhilippe Mathieu-Daudé  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
183ac25236SPhilippe Mathieu-Daudé  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
193ac25236SPhilippe Mathieu-Daudé  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
203ac25236SPhilippe Mathieu-Daudé  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
213ac25236SPhilippe Mathieu-Daudé  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
223ac25236SPhilippe Mathieu-Daudé  * THE SOFTWARE.
233ac25236SPhilippe Mathieu-Daudé  */
243ac25236SPhilippe Mathieu-Daudé 
253ac25236SPhilippe Mathieu-Daudé #include "qemu/osdep.h"
2623f6e3b1SPhilippe Mathieu-Daudé #include "qapi/error.h"
2723f6e3b1SPhilippe Mathieu-Daudé #include "hw/sysbus.h"
2823f6e3b1SPhilippe Mathieu-Daudé #include "hw/display/vga.h"
2923f6e3b1SPhilippe Mathieu-Daudé #include "hw/qdev-properties.h"
3028cf3960SMichael S. Tsirkin #include "ui/console.h"
313ac25236SPhilippe Mathieu-Daudé #include "vga_int.h"
323ac25236SPhilippe Mathieu-Daudé 
3323f6e3b1SPhilippe Mathieu-Daudé /*
3423f6e3b1SPhilippe Mathieu-Daudé  * QEMU interface:
3523f6e3b1SPhilippe Mathieu-Daudé  *  + sysbus MMIO region 0: VGA I/O registers
3623f6e3b1SPhilippe Mathieu-Daudé  *  + sysbus MMIO region 1: VGA MMIO registers
3723f6e3b1SPhilippe Mathieu-Daudé  *  + sysbus MMIO region 2: VGA memory
3823f6e3b1SPhilippe Mathieu-Daudé  */
393ac25236SPhilippe Mathieu-Daudé 
4023f6e3b1SPhilippe Mathieu-Daudé OBJECT_DECLARE_SIMPLE_TYPE(VGAMmioState, VGA_MMIO)
4123f6e3b1SPhilippe Mathieu-Daudé 
4223f6e3b1SPhilippe Mathieu-Daudé struct VGAMmioState {
4323f6e3b1SPhilippe Mathieu-Daudé     /*< private >*/
4423f6e3b1SPhilippe Mathieu-Daudé     SysBusDevice parent_obj;
4523f6e3b1SPhilippe Mathieu-Daudé 
4623f6e3b1SPhilippe Mathieu-Daudé     /*< public >*/
473ac25236SPhilippe Mathieu-Daudé     VGACommonState vga;
4823f6e3b1SPhilippe Mathieu-Daudé     MemoryRegion iomem;
4923f6e3b1SPhilippe Mathieu-Daudé     MemoryRegion lowmem;
503ac25236SPhilippe Mathieu-Daudé 
5123f6e3b1SPhilippe Mathieu-Daudé     uint8_t it_shift;
5223f6e3b1SPhilippe Mathieu-Daudé };
5323f6e3b1SPhilippe Mathieu-Daudé 
vga_mm_read(void * opaque,hwaddr addr,unsigned size)543ac25236SPhilippe Mathieu-Daudé static uint64_t vga_mm_read(void *opaque, hwaddr addr, unsigned size)
553ac25236SPhilippe Mathieu-Daudé {
563ac25236SPhilippe Mathieu-Daudé     VGAMmioState *s = opaque;
573ac25236SPhilippe Mathieu-Daudé 
583ac25236SPhilippe Mathieu-Daudé     return vga_ioport_read(&s->vga, addr >> s->it_shift) &
593ac25236SPhilippe Mathieu-Daudé         MAKE_64BIT_MASK(0, size * 8);
603ac25236SPhilippe Mathieu-Daudé }
613ac25236SPhilippe Mathieu-Daudé 
vga_mm_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)623ac25236SPhilippe Mathieu-Daudé static void vga_mm_write(void *opaque, hwaddr addr, uint64_t value,
633ac25236SPhilippe Mathieu-Daudé                          unsigned size)
643ac25236SPhilippe Mathieu-Daudé {
653ac25236SPhilippe Mathieu-Daudé     VGAMmioState *s = opaque;
663ac25236SPhilippe Mathieu-Daudé 
673ac25236SPhilippe Mathieu-Daudé     vga_ioport_write(&s->vga, addr >> s->it_shift,
683ac25236SPhilippe Mathieu-Daudé                      value & MAKE_64BIT_MASK(0, size * 8));
693ac25236SPhilippe Mathieu-Daudé }
703ac25236SPhilippe Mathieu-Daudé 
713ac25236SPhilippe Mathieu-Daudé static const MemoryRegionOps vga_mm_ctrl_ops = {
723ac25236SPhilippe Mathieu-Daudé     .read = vga_mm_read,
733ac25236SPhilippe Mathieu-Daudé     .write = vga_mm_write,
743ac25236SPhilippe Mathieu-Daudé     .valid.min_access_size = 1,
753ac25236SPhilippe Mathieu-Daudé     .valid.max_access_size = 4,
763ac25236SPhilippe Mathieu-Daudé     .impl.min_access_size = 1,
773ac25236SPhilippe Mathieu-Daudé     .impl.max_access_size = 4,
783ac25236SPhilippe Mathieu-Daudé     .endianness = DEVICE_NATIVE_ENDIAN,
793ac25236SPhilippe Mathieu-Daudé };
803ac25236SPhilippe Mathieu-Daudé 
vga_mmio_reset(DeviceState * dev)8123f6e3b1SPhilippe Mathieu-Daudé static void vga_mmio_reset(DeviceState *dev)
8223f6e3b1SPhilippe Mathieu-Daudé {
8323f6e3b1SPhilippe Mathieu-Daudé     VGAMmioState *s = VGA_MMIO(dev);
8423f6e3b1SPhilippe Mathieu-Daudé 
8523f6e3b1SPhilippe Mathieu-Daudé     vga_common_reset(&s->vga);
8623f6e3b1SPhilippe Mathieu-Daudé }
8723f6e3b1SPhilippe Mathieu-Daudé 
vga_mmio_realizefn(DeviceState * dev,Error ** errp)8823f6e3b1SPhilippe Mathieu-Daudé static void vga_mmio_realizefn(DeviceState *dev, Error **errp)
8923f6e3b1SPhilippe Mathieu-Daudé {
9023f6e3b1SPhilippe Mathieu-Daudé     VGAMmioState *s = VGA_MMIO(dev);
9123f6e3b1SPhilippe Mathieu-Daudé     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
9223f6e3b1SPhilippe Mathieu-Daudé 
9323f6e3b1SPhilippe Mathieu-Daudé     memory_region_init_io(&s->iomem, OBJECT(dev), &vga_mm_ctrl_ops, s,
9423f6e3b1SPhilippe Mathieu-Daudé                           "vga-mmio", 0x100000);
9523f6e3b1SPhilippe Mathieu-Daudé     memory_region_set_flush_coalesced(&s->iomem);
9623f6e3b1SPhilippe Mathieu-Daudé     sysbus_init_mmio(sbd, &s->iomem);
9723f6e3b1SPhilippe Mathieu-Daudé 
9823f6e3b1SPhilippe Mathieu-Daudé     /* XXX: endianness? */
9923f6e3b1SPhilippe Mathieu-Daudé     memory_region_init_io(&s->lowmem, OBJECT(dev), &vga_mem_ops, &s->vga,
10023f6e3b1SPhilippe Mathieu-Daudé                           "vga-lowmem", 0x20000);
10123f6e3b1SPhilippe Mathieu-Daudé     memory_region_set_coalescing(&s->lowmem);
10223f6e3b1SPhilippe Mathieu-Daudé     sysbus_init_mmio(sbd, &s->lowmem);
10323f6e3b1SPhilippe Mathieu-Daudé 
10423f6e3b1SPhilippe Mathieu-Daudé     s->vga.bank_offset = 0;
10523f6e3b1SPhilippe Mathieu-Daudé     s->vga.global_vmstate = true;
1066832deb8SThomas Huth     if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
1076832deb8SThomas Huth         return;
1086832deb8SThomas Huth     }
1096832deb8SThomas Huth 
11023f6e3b1SPhilippe Mathieu-Daudé     sysbus_init_mmio(sbd, &s->vga.vram);
11123f6e3b1SPhilippe Mathieu-Daudé     s->vga.con = graphic_console_init(dev, 0, s->vga.hw_ops, &s->vga);
11223f6e3b1SPhilippe Mathieu-Daudé }
11323f6e3b1SPhilippe Mathieu-Daudé 
11423f6e3b1SPhilippe Mathieu-Daudé static Property vga_mmio_properties[] = {
11523f6e3b1SPhilippe Mathieu-Daudé     DEFINE_PROP_UINT8("it_shift", VGAMmioState, it_shift, 0),
11623f6e3b1SPhilippe Mathieu-Daudé     DEFINE_PROP_UINT32("vgamem_mb", VGAMmioState, vga.vram_size_mb, 8),
11723f6e3b1SPhilippe Mathieu-Daudé     DEFINE_PROP_END_OF_LIST(),
11823f6e3b1SPhilippe Mathieu-Daudé };
11923f6e3b1SPhilippe Mathieu-Daudé 
vga_mmio_class_initfn(ObjectClass * klass,void * data)12023f6e3b1SPhilippe Mathieu-Daudé static void vga_mmio_class_initfn(ObjectClass *klass, void *data)
12123f6e3b1SPhilippe Mathieu-Daudé {
12223f6e3b1SPhilippe Mathieu-Daudé     DeviceClass *dc = DEVICE_CLASS(klass);
12323f6e3b1SPhilippe Mathieu-Daudé 
12423f6e3b1SPhilippe Mathieu-Daudé     dc->realize = vga_mmio_realizefn;
12523f6e3b1SPhilippe Mathieu-Daudé     dc->reset = vga_mmio_reset;
12623f6e3b1SPhilippe Mathieu-Daudé     dc->vmsd = &vmstate_vga_common;
12723f6e3b1SPhilippe Mathieu-Daudé     device_class_set_props(dc, vga_mmio_properties);
12823f6e3b1SPhilippe Mathieu-Daudé     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
12923f6e3b1SPhilippe Mathieu-Daudé }
13023f6e3b1SPhilippe Mathieu-Daudé 
13123f6e3b1SPhilippe Mathieu-Daudé static const TypeInfo vga_mmio_info = {
13223f6e3b1SPhilippe Mathieu-Daudé     .name          = TYPE_VGA_MMIO,
13323f6e3b1SPhilippe Mathieu-Daudé     .parent        = TYPE_SYS_BUS_DEVICE,
13423f6e3b1SPhilippe Mathieu-Daudé     .instance_size = sizeof(VGAMmioState),
13523f6e3b1SPhilippe Mathieu-Daudé     .class_init    = vga_mmio_class_initfn,
13623f6e3b1SPhilippe Mathieu-Daudé };
13723f6e3b1SPhilippe Mathieu-Daudé 
vga_mmio_register_types(void)13823f6e3b1SPhilippe Mathieu-Daudé static void vga_mmio_register_types(void)
13923f6e3b1SPhilippe Mathieu-Daudé {
14023f6e3b1SPhilippe Mathieu-Daudé     type_register_static(&vga_mmio_info);
14123f6e3b1SPhilippe Mathieu-Daudé }
14223f6e3b1SPhilippe Mathieu-Daudé 
14323f6e3b1SPhilippe Mathieu-Daudé type_init(vga_mmio_register_types)
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