1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/error-report.h" 16 #include "qemu/iov.h" 17 #include "trace.h" 18 #include "hw/virtio/virtio.h" 19 #include "hw/virtio/virtio-gpu.h" 20 21 #include "ui/egl-helpers.h" 22 23 #include <virglrenderer.h> 24 25 #if VIRGL_RENDERER_CALLBACKS_VERSION >= 4 26 static void * 27 virgl_get_egl_display(G_GNUC_UNUSED void *cookie) 28 { 29 return qemu_egl_display; 30 } 31 #endif 32 33 static void virgl_cmd_create_resource_2d(VirtIOGPU *g, 34 struct virtio_gpu_ctrl_command *cmd) 35 { 36 struct virtio_gpu_resource_create_2d c2d; 37 struct virgl_renderer_resource_create_args args; 38 39 VIRTIO_GPU_FILL_CMD(c2d); 40 trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format, 41 c2d.width, c2d.height); 42 43 args.handle = c2d.resource_id; 44 args.target = 2; 45 args.format = c2d.format; 46 args.bind = (1 << 1); 47 args.width = c2d.width; 48 args.height = c2d.height; 49 args.depth = 1; 50 args.array_size = 1; 51 args.last_level = 0; 52 args.nr_samples = 0; 53 args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP; 54 virgl_renderer_resource_create(&args, NULL, 0); 55 } 56 57 static void virgl_cmd_create_resource_3d(VirtIOGPU *g, 58 struct virtio_gpu_ctrl_command *cmd) 59 { 60 struct virtio_gpu_resource_create_3d c3d; 61 struct virgl_renderer_resource_create_args args; 62 63 VIRTIO_GPU_FILL_CMD(c3d); 64 trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format, 65 c3d.width, c3d.height, c3d.depth); 66 67 args.handle = c3d.resource_id; 68 args.target = c3d.target; 69 args.format = c3d.format; 70 args.bind = c3d.bind; 71 args.width = c3d.width; 72 args.height = c3d.height; 73 args.depth = c3d.depth; 74 args.array_size = c3d.array_size; 75 args.last_level = c3d.last_level; 76 args.nr_samples = c3d.nr_samples; 77 args.flags = c3d.flags; 78 virgl_renderer_resource_create(&args, NULL, 0); 79 } 80 81 static void virgl_cmd_resource_unref(VirtIOGPU *g, 82 struct virtio_gpu_ctrl_command *cmd) 83 { 84 struct virtio_gpu_resource_unref unref; 85 struct iovec *res_iovs = NULL; 86 int num_iovs = 0; 87 88 VIRTIO_GPU_FILL_CMD(unref); 89 trace_virtio_gpu_cmd_res_unref(unref.resource_id); 90 91 virgl_renderer_resource_detach_iov(unref.resource_id, 92 &res_iovs, 93 &num_iovs); 94 if (res_iovs != NULL && num_iovs != 0) { 95 virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs); 96 } 97 virgl_renderer_resource_unref(unref.resource_id); 98 } 99 100 static void virgl_cmd_context_create(VirtIOGPU *g, 101 struct virtio_gpu_ctrl_command *cmd) 102 { 103 struct virtio_gpu_ctx_create cc; 104 105 VIRTIO_GPU_FILL_CMD(cc); 106 trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id, 107 cc.debug_name); 108 109 virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, 110 cc.debug_name); 111 } 112 113 static void virgl_cmd_context_destroy(VirtIOGPU *g, 114 struct virtio_gpu_ctrl_command *cmd) 115 { 116 struct virtio_gpu_ctx_destroy cd; 117 118 VIRTIO_GPU_FILL_CMD(cd); 119 trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id); 120 121 virgl_renderer_context_destroy(cd.hdr.ctx_id); 122 } 123 124 static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y, 125 int width, int height) 126 { 127 if (!g->parent_obj.scanout[idx].con) { 128 return; 129 } 130 131 dpy_gl_update(g->parent_obj.scanout[idx].con, x, y, width, height); 132 } 133 134 static void virgl_cmd_resource_flush(VirtIOGPU *g, 135 struct virtio_gpu_ctrl_command *cmd) 136 { 137 struct virtio_gpu_resource_flush rf; 138 int i; 139 140 VIRTIO_GPU_FILL_CMD(rf); 141 trace_virtio_gpu_cmd_res_flush(rf.resource_id, 142 rf.r.width, rf.r.height, rf.r.x, rf.r.y); 143 144 for (i = 0; i < g->parent_obj.conf.max_outputs; i++) { 145 if (g->parent_obj.scanout[i].resource_id != rf.resource_id) { 146 continue; 147 } 148 virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height); 149 } 150 } 151 152 static void virgl_cmd_set_scanout(VirtIOGPU *g, 153 struct virtio_gpu_ctrl_command *cmd) 154 { 155 struct virtio_gpu_set_scanout ss; 156 struct virgl_renderer_resource_info info; 157 void *d3d_tex2d = NULL; 158 int ret; 159 160 VIRTIO_GPU_FILL_CMD(ss); 161 trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id, 162 ss.r.width, ss.r.height, ss.r.x, ss.r.y); 163 164 if (ss.scanout_id >= g->parent_obj.conf.max_outputs) { 165 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d", 166 __func__, ss.scanout_id); 167 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID; 168 return; 169 } 170 g->parent_obj.enable = 1; 171 172 memset(&info, 0, sizeof(info)); 173 174 if (ss.resource_id && ss.r.width && ss.r.height) { 175 ret = virgl_renderer_resource_get_info(ss.resource_id, &info); 176 if (ret == -1) { 177 qemu_log_mask(LOG_GUEST_ERROR, 178 "%s: illegal resource specified %d\n", 179 __func__, ss.resource_id); 180 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; 181 return; 182 } 183 qemu_console_resize(g->parent_obj.scanout[ss.scanout_id].con, 184 ss.r.width, ss.r.height); 185 virgl_renderer_force_ctx_0(); 186 dpy_gl_scanout_texture( 187 g->parent_obj.scanout[ss.scanout_id].con, info.tex_id, 188 info.flags & VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP, 189 info.width, info.height, 190 ss.r.x, ss.r.y, ss.r.width, ss.r.height, 191 d3d_tex2d); 192 } else { 193 dpy_gfx_replace_surface( 194 g->parent_obj.scanout[ss.scanout_id].con, NULL); 195 dpy_gl_scanout_disable(g->parent_obj.scanout[ss.scanout_id].con); 196 } 197 g->parent_obj.scanout[ss.scanout_id].resource_id = ss.resource_id; 198 } 199 200 static void virgl_cmd_submit_3d(VirtIOGPU *g, 201 struct virtio_gpu_ctrl_command *cmd) 202 { 203 struct virtio_gpu_cmd_submit cs; 204 void *buf; 205 size_t s; 206 207 VIRTIO_GPU_FILL_CMD(cs); 208 trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size); 209 210 buf = g_malloc(cs.size); 211 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 212 sizeof(cs), buf, cs.size); 213 if (s != cs.size) { 214 qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)", 215 __func__, s, cs.size); 216 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; 217 goto out; 218 } 219 220 if (virtio_gpu_stats_enabled(g->parent_obj.conf)) { 221 g->stats.req_3d++; 222 g->stats.bytes_3d += cs.size; 223 } 224 225 virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4); 226 227 out: 228 g_free(buf); 229 } 230 231 static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g, 232 struct virtio_gpu_ctrl_command *cmd) 233 { 234 struct virtio_gpu_transfer_to_host_2d t2d; 235 struct virtio_gpu_box box; 236 237 VIRTIO_GPU_FILL_CMD(t2d); 238 trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id); 239 240 box.x = t2d.r.x; 241 box.y = t2d.r.y; 242 box.z = 0; 243 box.w = t2d.r.width; 244 box.h = t2d.r.height; 245 box.d = 1; 246 247 virgl_renderer_transfer_write_iov(t2d.resource_id, 248 0, 249 0, 250 0, 251 0, 252 (struct virgl_box *)&box, 253 t2d.offset, NULL, 0); 254 } 255 256 static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g, 257 struct virtio_gpu_ctrl_command *cmd) 258 { 259 struct virtio_gpu_transfer_host_3d t3d; 260 261 VIRTIO_GPU_FILL_CMD(t3d); 262 trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id); 263 264 virgl_renderer_transfer_write_iov(t3d.resource_id, 265 t3d.hdr.ctx_id, 266 t3d.level, 267 t3d.stride, 268 t3d.layer_stride, 269 (struct virgl_box *)&t3d.box, 270 t3d.offset, NULL, 0); 271 } 272 273 static void 274 virgl_cmd_transfer_from_host_3d(VirtIOGPU *g, 275 struct virtio_gpu_ctrl_command *cmd) 276 { 277 struct virtio_gpu_transfer_host_3d tf3d; 278 279 VIRTIO_GPU_FILL_CMD(tf3d); 280 trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id); 281 282 virgl_renderer_transfer_read_iov(tf3d.resource_id, 283 tf3d.hdr.ctx_id, 284 tf3d.level, 285 tf3d.stride, 286 tf3d.layer_stride, 287 (struct virgl_box *)&tf3d.box, 288 tf3d.offset, NULL, 0); 289 } 290 291 292 static void virgl_resource_attach_backing(VirtIOGPU *g, 293 struct virtio_gpu_ctrl_command *cmd) 294 { 295 struct virtio_gpu_resource_attach_backing att_rb; 296 struct iovec *res_iovs; 297 uint32_t res_niov; 298 int ret; 299 300 VIRTIO_GPU_FILL_CMD(att_rb); 301 trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id); 302 303 ret = virtio_gpu_create_mapping_iov(g, att_rb.nr_entries, sizeof(att_rb), 304 cmd, NULL, &res_iovs, &res_niov); 305 if (ret != 0) { 306 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; 307 return; 308 } 309 310 ret = virgl_renderer_resource_attach_iov(att_rb.resource_id, 311 res_iovs, res_niov); 312 313 if (ret != 0) 314 virtio_gpu_cleanup_mapping_iov(g, res_iovs, res_niov); 315 } 316 317 static void virgl_resource_detach_backing(VirtIOGPU *g, 318 struct virtio_gpu_ctrl_command *cmd) 319 { 320 struct virtio_gpu_resource_detach_backing detach_rb; 321 struct iovec *res_iovs = NULL; 322 int num_iovs = 0; 323 324 VIRTIO_GPU_FILL_CMD(detach_rb); 325 trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id); 326 327 virgl_renderer_resource_detach_iov(detach_rb.resource_id, 328 &res_iovs, 329 &num_iovs); 330 if (res_iovs == NULL || num_iovs == 0) { 331 return; 332 } 333 virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs); 334 } 335 336 337 static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g, 338 struct virtio_gpu_ctrl_command *cmd) 339 { 340 struct virtio_gpu_ctx_resource att_res; 341 342 VIRTIO_GPU_FILL_CMD(att_res); 343 trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id, 344 att_res.resource_id); 345 346 virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id); 347 } 348 349 static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g, 350 struct virtio_gpu_ctrl_command *cmd) 351 { 352 struct virtio_gpu_ctx_resource det_res; 353 354 VIRTIO_GPU_FILL_CMD(det_res); 355 trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id, 356 det_res.resource_id); 357 358 virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id); 359 } 360 361 static void virgl_cmd_get_capset_info(VirtIOGPU *g, 362 struct virtio_gpu_ctrl_command *cmd) 363 { 364 struct virtio_gpu_get_capset_info info; 365 struct virtio_gpu_resp_capset_info resp; 366 367 VIRTIO_GPU_FILL_CMD(info); 368 369 memset(&resp, 0, sizeof(resp)); 370 if (info.capset_index == 0) { 371 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL; 372 virgl_renderer_get_cap_set(resp.capset_id, 373 &resp.capset_max_version, 374 &resp.capset_max_size); 375 } else if (info.capset_index == 1) { 376 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2; 377 virgl_renderer_get_cap_set(resp.capset_id, 378 &resp.capset_max_version, 379 &resp.capset_max_size); 380 } else { 381 resp.capset_max_version = 0; 382 resp.capset_max_size = 0; 383 } 384 resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO; 385 virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); 386 } 387 388 static void virgl_cmd_get_capset(VirtIOGPU *g, 389 struct virtio_gpu_ctrl_command *cmd) 390 { 391 struct virtio_gpu_get_capset gc; 392 struct virtio_gpu_resp_capset *resp; 393 uint32_t max_ver, max_size; 394 VIRTIO_GPU_FILL_CMD(gc); 395 396 virgl_renderer_get_cap_set(gc.capset_id, &max_ver, 397 &max_size); 398 if (!max_size) { 399 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; 400 return; 401 } 402 403 resp = g_malloc0(sizeof(*resp) + max_size); 404 resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET; 405 virgl_renderer_fill_caps(gc.capset_id, 406 gc.capset_version, 407 (void *)resp->capset_data); 408 virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size); 409 g_free(resp); 410 } 411 412 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, 413 struct virtio_gpu_ctrl_command *cmd) 414 { 415 VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr); 416 417 virgl_renderer_force_ctx_0(); 418 switch (cmd->cmd_hdr.type) { 419 case VIRTIO_GPU_CMD_CTX_CREATE: 420 virgl_cmd_context_create(g, cmd); 421 break; 422 case VIRTIO_GPU_CMD_CTX_DESTROY: 423 virgl_cmd_context_destroy(g, cmd); 424 break; 425 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: 426 virgl_cmd_create_resource_2d(g, cmd); 427 break; 428 case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D: 429 virgl_cmd_create_resource_3d(g, cmd); 430 break; 431 case VIRTIO_GPU_CMD_SUBMIT_3D: 432 virgl_cmd_submit_3d(g, cmd); 433 break; 434 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: 435 virgl_cmd_transfer_to_host_2d(g, cmd); 436 break; 437 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D: 438 virgl_cmd_transfer_to_host_3d(g, cmd); 439 break; 440 case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D: 441 virgl_cmd_transfer_from_host_3d(g, cmd); 442 break; 443 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING: 444 virgl_resource_attach_backing(g, cmd); 445 break; 446 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: 447 virgl_resource_detach_backing(g, cmd); 448 break; 449 case VIRTIO_GPU_CMD_SET_SCANOUT: 450 virgl_cmd_set_scanout(g, cmd); 451 break; 452 case VIRTIO_GPU_CMD_RESOURCE_FLUSH: 453 virgl_cmd_resource_flush(g, cmd); 454 break; 455 case VIRTIO_GPU_CMD_RESOURCE_UNREF: 456 virgl_cmd_resource_unref(g, cmd); 457 break; 458 case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE: 459 /* TODO add security */ 460 virgl_cmd_ctx_attach_resource(g, cmd); 461 break; 462 case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE: 463 /* TODO add security */ 464 virgl_cmd_ctx_detach_resource(g, cmd); 465 break; 466 case VIRTIO_GPU_CMD_GET_CAPSET_INFO: 467 virgl_cmd_get_capset_info(g, cmd); 468 break; 469 case VIRTIO_GPU_CMD_GET_CAPSET: 470 virgl_cmd_get_capset(g, cmd); 471 break; 472 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO: 473 virtio_gpu_get_display_info(g, cmd); 474 break; 475 case VIRTIO_GPU_CMD_GET_EDID: 476 virtio_gpu_get_edid(g, cmd); 477 break; 478 default: 479 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; 480 break; 481 } 482 483 if (cmd->finished) { 484 return; 485 } 486 if (cmd->error) { 487 fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__, 488 cmd->cmd_hdr.type, cmd->error); 489 virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error); 490 return; 491 } 492 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { 493 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); 494 return; 495 } 496 497 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); 498 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); 499 } 500 501 static void virgl_write_fence(void *opaque, uint32_t fence) 502 { 503 VirtIOGPU *g = opaque; 504 struct virtio_gpu_ctrl_command *cmd, *tmp; 505 506 QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) { 507 /* 508 * the guest can end up emitting fences out of order 509 * so we should check all fenced cmds not just the first one. 510 */ 511 if (cmd->cmd_hdr.fence_id > fence) { 512 continue; 513 } 514 trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id); 515 virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); 516 QTAILQ_REMOVE(&g->fenceq, cmd, next); 517 g_free(cmd); 518 g->inflight--; 519 if (virtio_gpu_stats_enabled(g->parent_obj.conf)) { 520 fprintf(stderr, "inflight: %3d (-)\r", g->inflight); 521 } 522 } 523 } 524 525 static virgl_renderer_gl_context 526 virgl_create_context(void *opaque, int scanout_idx, 527 struct virgl_renderer_gl_ctx_param *params) 528 { 529 VirtIOGPU *g = opaque; 530 QEMUGLContext ctx; 531 QEMUGLParams qparams; 532 533 qparams.major_ver = params->major_ver; 534 qparams.minor_ver = params->minor_ver; 535 536 ctx = dpy_gl_ctx_create(g->parent_obj.scanout[scanout_idx].con, &qparams); 537 return (virgl_renderer_gl_context)ctx; 538 } 539 540 static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx) 541 { 542 VirtIOGPU *g = opaque; 543 QEMUGLContext qctx = (QEMUGLContext)ctx; 544 545 dpy_gl_ctx_destroy(g->parent_obj.scanout[0].con, qctx); 546 } 547 548 static int virgl_make_context_current(void *opaque, int scanout_idx, 549 virgl_renderer_gl_context ctx) 550 { 551 VirtIOGPU *g = opaque; 552 QEMUGLContext qctx = (QEMUGLContext)ctx; 553 554 return dpy_gl_ctx_make_current(g->parent_obj.scanout[scanout_idx].con, 555 qctx); 556 } 557 558 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = { 559 .version = 1, 560 .write_fence = virgl_write_fence, 561 .create_gl_context = virgl_create_context, 562 .destroy_gl_context = virgl_destroy_context, 563 .make_current = virgl_make_context_current, 564 }; 565 566 static void virtio_gpu_print_stats(void *opaque) 567 { 568 VirtIOGPU *g = opaque; 569 570 if (g->stats.requests) { 571 fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n", 572 g->stats.requests, 573 g->stats.max_inflight, 574 g->stats.req_3d, 575 g->stats.bytes_3d); 576 g->stats.requests = 0; 577 g->stats.max_inflight = 0; 578 g->stats.req_3d = 0; 579 g->stats.bytes_3d = 0; 580 } else { 581 fprintf(stderr, "stats: idle\r"); 582 } 583 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); 584 } 585 586 static void virtio_gpu_fence_poll(void *opaque) 587 { 588 VirtIOGPU *g = opaque; 589 590 virgl_renderer_poll(); 591 virtio_gpu_process_cmdq(g); 592 if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) { 593 timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10); 594 } 595 } 596 597 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g) 598 { 599 virtio_gpu_fence_poll(g); 600 } 601 602 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g) 603 { 604 int i; 605 606 for (i = 0; i < g->parent_obj.conf.max_outputs; i++) { 607 dpy_gfx_replace_surface(g->parent_obj.scanout[i].con, NULL); 608 dpy_gl_scanout_disable(g->parent_obj.scanout[i].con); 609 } 610 } 611 612 void virtio_gpu_virgl_reset(VirtIOGPU *g) 613 { 614 virgl_renderer_reset(); 615 } 616 617 int virtio_gpu_virgl_init(VirtIOGPU *g) 618 { 619 int ret; 620 621 #if VIRGL_RENDERER_CALLBACKS_VERSION >= 4 622 if (qemu_egl_display) { 623 virtio_gpu_3d_cbs.version = 4; 624 virtio_gpu_3d_cbs.get_egl_display = virgl_get_egl_display; 625 } 626 #endif 627 628 ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs); 629 if (ret != 0) { 630 error_report("virgl could not be initialized: %d", ret); 631 return ret; 632 } 633 634 g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL, 635 virtio_gpu_fence_poll, g); 636 637 if (virtio_gpu_stats_enabled(g->parent_obj.conf)) { 638 g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL, 639 virtio_gpu_print_stats, g); 640 timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); 641 } 642 return 0; 643 } 644 645 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g) 646 { 647 uint32_t capset2_max_ver, capset2_max_size; 648 virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2, 649 &capset2_max_ver, 650 &capset2_max_size); 651 652 return capset2_max_ver ? 2 : 1; 653 } 654